JP2014170881A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a silicon loss and desorption defectiveness associated with formation of an element isolation region in an annealing process.SOLUTION: A manufacturing method of a semiconductor device having on a semiconductor substrate, an active region surrounded by an element isolation region comprises: a process of forming on the semiconductor surface, a pattern of a mask nitride film corresponding to the active region; a process of etching the semiconductor substrate by using the mask nitride film as a mask to form an element isolation trench corresponding to the element isolation region; a process of forming a mobile silicon oxide film so as to bury the element isolation trench and locate its surface above a top face of the mask nitride film; a process of etching the mobile silicon oxide film from an upper limit of the element isolation trench to a predetermined depth; a process of forming an HDP (High Density Plasma) silicon oxide film so as to bury the etched element isolation trench; and a process of planarizing the HDP silicon oxide film by using the mask nitride film as a stop film.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In recent years, with the miniaturization of semiconductor elements, the size of transistors tends to be reduced. With regard to the semiconductor memory device, the difference between the element isolation region width in the memory cell region and the element isolation region width in the peripheral circuit region is increased due to the size reduction. Further, since the element isolation region width in the memory cell region has become narrower and it has become difficult to embed with an insulating film, a silicon oxide film (hereinafter referred to as a fluid silicon oxide film) by F-CVD (Flowable-Chemical Vapor Deposition) method is used. The method of embedding with an insulating film having fluidity such as) has been introduced. That is, of the element isolation region in the memory cell region and the element isolation region in the peripheral circuit region, those having a width of 80 nm or less are embedded with a fluid silicon oxide film, and the element isolation region in the peripheral circuit region having a width exceeding 80 nm is It is embedded in a composite structure of a fluid silicon oxide film and an HDP (High Density Plasma) -CVD silicon oxide film (hereinafter abbreviated as HDP silicon oxide film). Patent Document 1 describes a method for manufacturing a semiconductor device in which a groove is embedded using a fluid silicon oxide film.

JP2012-231007

  By the way, when the element isolation region is buried with a fluid silicon oxide film, annealing in the oxygen and nitrogen atmosphere (reforming treatment at a high temperature) is required to form the fluid silicon oxide film.

  Specifically, in order to improve the wet etch rate of the fluid silicon oxide film in the element isolation region, it is necessary to modify (Cure) the fluid silicon oxide film in the element isolation region by high-temperature heat treatment at a high oxygen concentration. is there. In this modification, as shown in FIG. 17, the inner walls of each of the memory cell shallow trench 201 formed in the semiconductor substrate 100, the peripheral shallow trench 202 having a width of 80 nm or less, and the large region isolation trench 203 having a width of more than 80 nm are formed. Is thermally oxidized to form a thermal oxide film 204, and then the memory cell shallow trench 201, the peripheral shallow trench 202, and the large region isolation trench 203 are embedded with a fluid silicon oxide film 205, and a high temperature annealing process is performed with a high oxygen concentration. Silicon loss D1 occurs, and the memory retention capability is reduced. Further, the upper part of the fluid silicon oxide film 205 is desorbed by the stress, and a desorption defect D2 is generated.

  A method for manufacturing a semiconductor device according to an aspect of the present invention includes forming a plurality of element isolation trenches so as to divide an element formation layer, and embedding element isolation insulating films in these trenches, thereby providing a plurality of element isolation regions. And a plurality of active regions insulated and isolated by the plurality of element isolation regions, in which the element isolation insulating film is formed without removing the mask nitride film and modified by annealing. Etching back 30% to 40% from above the thinnest element isolation trench, and backfilling with an element isolation insulating film that does not require modification.

  According to the first aspect of the present invention, in a method of manufacturing a semiconductor device having an active region surrounded by an element isolation region on a semiconductor substrate, a mask nitride film pattern corresponding to the active region is formed on the surface of the semiconductor substrate. A step of etching, using the mask nitride film as a mask, etching the semiconductor substrate to form an element isolation trench corresponding to the element isolation region; and embedding the element isolation trench and from above the mask nitride film Forming a fluid silicon oxide film so that the surface is located above, etching the fluid silicon oxide film from the upper end of the element isolation trench to a predetermined depth, and etching the element isolation Forming an HDP silicon oxide film so as to bury the trench, and using the mask nitride film as a stop film The method of manufacturing a semiconductor device which comprises the steps of flattening the DP silicon oxide film, is provided.

  According to the second aspect of the present invention, the semiconductor substrate is surrounded by the first active region surrounded by the first element isolation region in the memory cell region and the second element isolation region in the peripheral circuit region. Forming a mask nitride film pattern corresponding to the first active region and the second active region on a surface of the semiconductor substrate in a method of manufacturing a semiconductor device having a second active region; The mask is used as a mask to etch the semiconductor substrate so that the first element isolation trench corresponding to the first element isolation region has a groove width wider than the first element isolation trench corresponding to the second element isolation region. Forming a second element isolation trench, a region isolation trench corresponding to a width between the memory cell area and the peripheral circuit area and wider than the second element isolation trench; and The first element isolation trench and the second element isolation trench are embedded without completely burying the isolation trench, and the mask nitridation is performed in the first element isolation trench and the second element isolation trench. A step of forming a fluid silicon oxide film so that the surface is located above the upper surface of the film; and a first HDP silicon so as to fill a groove remaining in the region isolation trench without being buried by the fluid silicon oxide film A step of forming an oxide film, a step of planarizing the first HDP silicon oxide film using the mask nitride film as a stop film, and a predetermined depth from the upper end of the first element isolation trench, the second The element isolation trench is flush with the surface of the semiconductor substrate, and the region isolation trench is from the upper surface of the mask nitride film. Etching to a depth position of a predetermined proportion of the thickness, and embedding the etched first element isolation trench, the second element isolation trench and the region isolation trench and above the upper surface of the mask nitride film And a step of forming a second HDP silicon oxide film so that the surface thereof is located on the substrate, and a step of planarizing the second HDP silicon oxide film using the mask nitride film as a stop film. A method of manufacturing a device is provided.

  According to the method for manufacturing a semiconductor device according to the present invention, the mask nitride film remains at the time of annealing, and the surface of the semiconductor substrate becomes far from the atmosphere of high oxygen concentration. Etching back up to 30 to 40% from the top of the groove removes the upper part of the element isolation insulating film that is easily detached due to stress and the separated element isolation insulating film, so that it becomes difficult to cause a separation defect.

1 is a plan view schematically showing main parts of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing by line AA of FIG. It is a top view for demonstrating the manufacturing method of the semiconductor device by the 1st Embodiment of this invention in order of a process. It is sectional drawing by line BB of FIG. It is sectional drawing for demonstrating the manufacturing process following FIG. FIG. 6 is a cross-sectional view for explaining a manufacturing step subsequent to FIG. 5. FIG. 7 is a cross-sectional view for explaining a manufacturing step subsequent to FIG. 6. FIG. 8 is a cross-sectional view for explaining a manufacturing step subsequent to FIG. 7. It is sectional drawing for demonstrating the manufacturing process following FIG. FIG. 10 is a cross-sectional view for explaining a manufacturing step following FIG. 9. FIG. 11 is a cross-sectional view for explaining the semiconductor device manufacturing method according to the second embodiment of the present invention in the order of steps for the same portion as the portion shown in FIG. 2; FIG. 12 is a cross-sectional view for illustrating a manufacturing step following FIG. 11. It is sectional drawing for demonstrating the manufacturing process following FIG. It is sectional drawing for demonstrating the manufacturing process following FIG. It is sectional drawing for demonstrating the manufacturing process following FIG. It is sectional drawing for demonstrating the manufacturing process following FIG. FIG. 4 is a cross-sectional view showing the same portion as the cross-sectional portion taken along line BB in FIG. 3 in order to explain the problem of the related art of the present invention.

  Hereinafter, a semiconductor device manufacturing method and a semiconductor device embodiment to which the present invention is applied will be described in detail with reference to the drawings. In addition, in the drawings used in the following description, in order to make the features easy to understand, there are cases where the portions that become the features are enlarged for convenience, and the dimensional ratios of the respective components are the same as the actual ones. Not exclusively. In addition, the materials, dimensions, and the like exemplified in the following description are merely examples, and the present invention is not necessarily limited thereto, and can be appropriately modified and implemented without departing from the scope of the invention. .

[First Embodiment]
(Semiconductor device)
As a first embodiment of the present invention, an arrangement configuration of main parts of a semiconductor device 1 to which the present invention is applied will be described with reference to FIGS. FIG. 1 is a plan view showing an arrangement configuration of main parts up to the bit line of the semiconductor device 1. FIG. 2 is a view corresponding to the AA cross section of FIG. FIG. 1 shows the X direction, the Y direction perpendicular to the X direction, and the X ′ direction forming an angle in the X direction on the XY plane, and FIG. 2 shows a right angle to the X direction and the XY plane. Z direction is shown.

  The semiconductor device 1 finally functions as a DRAM (Dynamic Random Access Memory). In the plane of the semiconductor substrate 100, a memory cell region 2 and a peripheral circuit region 3 positioned around the memory cell region 2 are provided. (In FIG. 1, only the right side of the memory cell region is shown). Among these, the memory cell region 2 is a region in which a plurality of memory cells are arranged in a matrix. On the other hand, the peripheral circuit region 3 is a region where a circuit for controlling the operation of each memory cell is formed.

  A plurality of memory cell shallow trenches (first element isolation trenches) 201, a peripheral shallow trench (second element isolation trench) 202, and a large region isolation (region isolation trench) trench 203 are formed so as to divide the surface of the semiconductor substrate 100. Forming. By embedding element isolation insulating films in the plurality of trenches, a plurality of memory cell active regions 101 are arranged in the X direction and the Y direction in the memory cell region 2, and the peripheral circuit active region 102 is provided in the peripheral circuit region 3. Are arranged in the X and Y directions. Here, the element isolation insulating film includes a fluid silicon oxide film 205 and a first HDP silicon oxide film 206 which will be described later.

  A first interlayer insulating film 400 is provided on the surface of the semiconductor substrate 100 in the memory cell region 2, and a plurality of word lines 300 extending in the Y direction intersecting with the memory cell active region 101 are arranged in stripes. Is provided. The upper portions of these word lines 300 are sealed with a cap insulating film 314.

  In addition, a bit line contact plug 511 is provided so as to be connected to a central portion sandwiched between the word lines 300 of each memory cell active region 101. A bit line 501 extending in the X direction is provided so as to be connected to the upper surface of the bit line contact plug 511. A cover insulating film 504 is provided on the upper surface of the bit line 501.

  A peripheral gate 502 is provided on the central part of the plurality of peripheral circuit active regions 102 via a peripheral gate insulating film 503. A cover insulating film 504 is provided on the upper surface of the peripheral gate 502.

  A second interlayer insulating film 600 is provided so as to cover the bit line 501 and the peripheral gate 502. Capacitor contact plugs 700 are provided so as to connect to both ends of the memory cell active region 101 across the word line 300 through the second interlayer insulating film 600. A peripheral contact plug 750 is provided so as to be connected to both ends of the circuit active region 102 across the peripheral gate 502, and a peripheral wiring 770 is provided so as to be connected to the upper surface of the peripheral contact plug 750.

  Further, a stopper film 780 and a third interlayer insulating film 790 are provided so as to cover the upper surface of the capacitor contact plug 700 and the entire surface of the semiconductor substrate 100 including the peripheral wiring 770. A cylinder hole 810 is provided through the third interlayer insulating film 790 and the stopper film 780, and a capacitor 800 including a lower electrode 811, a capacitive insulating film 812, and an upper electrode 813 is provided using the inner surface of the cylinder hole 810. . The capacitor 800 is a cylinder type, but other types such as a crown type may be used. A fourth interlayer insulating film 910 is provided to cover the upper surface of capacitor 800. A wiring contact plug 900 is provided through the fourth interlayer insulating film 910, the third interlayer insulating film 790, and the stopper film 780 and connected to the peripheral wiring 770, and the wiring 920 is provided so as to connect to the upper surface of the wiring contact plug 900. It is done. A protective insulating film 930 is provided so as to cover the wiring 920.

(Method for Manufacturing Semiconductor Device of First Embodiment)
Next, a method for manufacturing the semiconductor device 1 according to the first embodiment will be described with reference to FIGS.

  FIG. 3 is a plan view showing a portion corresponding to FIG. 4-10 is sectional drawing which shows the part corresponding to FIG.

  First, FIG. 3 and FIG. 4 will be referred to. A plurality of memory cell shallow trenches 201 are formed so that a mat oxide film 208 and a mask nitride film 209 are formed on the surface of the semiconductor substrate 100, a resist 91 is applied to the entire surface, and the surface of the semiconductor substrate 100 is divided by lithography and dry etching. The peripheral shallow trench 202 and the large region isolation trench 203 are formed. As a result, a plurality of memory cell active regions 101 and a plurality of peripheral circuit active regions 102 are formed.

  Reference is now made to FIG. The resist 91 is removed, and a thin thermal oxide film 204 (for example, 5 nm) is formed on the inner surfaces of the memory cell shallow trench 201, the peripheral shallow trench 202, and the large region isolation trench 203 by thermal diffusion.

  Reference is now made to FIG. A memory cell shallow trench 201 and a peripheral shallow trench 202 having a width of 80 nm or less are embedded, and a flowable silicon oxide film 205 is formed so as to cover the inner surface of the large region isolation trench 203, and an oxidizing atmosphere, for example, a high oxygen concentration atmosphere is formed. The flowable silicon oxide film 205 is modified (Cure) by annealing. At this time, since the mask nitride film 209 remains, the distance between the atmosphere having a high oxygen concentration and the surface of the semiconductor substrate 100 is increased, and silicon loss as described with reference to FIG. 17 hardly occurs. Further, although stress is generated in the fluid silicon oxide film 205 above the memory cell shallow trench 201, it does not detach because the uppermost part of the fluid silicon oxide film 205 is connected.

  Reference is now made to FIG. The fluid silicon oxide film 205 is etched back by H1 by oxide film plasma dry etching or oxide film wet etching (HF). H1 is set to a depth of 30 to 40% of the entire trench from the upper end of the memory cell shallow trench 201. At this time, since the fluid silicon oxide film 205 is recessed in the large region isolation trench 203, the large region remaining trench 210 is formed so as to push the recess. Here, the fluid silicon oxide film 205 having the stress on the upper part of the memory cell shallow trench 201 is not etched, and even if it is detached, it is removed by etching, so that a desorption defect is less likely to occur.

  Reference is now made to FIG. The first HDP silicon oxide film 206 is formed thick so as to bury the etch back portion of the memory cell shallow trench 201 and the peripheral shallow trench 202 having a width of 80 nm or less and the large region remaining trench 210.

  Reference is now made to FIG. The first HDP silicon oxide film 206 is planarized by CMP (Chemical Mechanical Polishing) using the mask nitride film 209 as a stop film.

  Reference is now made to FIG. The first HDP silicon oxide film 206 is etched to be flush with the upper surface of the mat oxide film 208 by oxide film wet etching, and the mask nitride film 209 is removed by nitride film wet etching.

  Next, the peripheral gate insulating film 503, the first interlayer insulating film 400, the word line 300, the bit line 501, the peripheral gate 502, the second interlayer insulating film 600, and the capacitor contact plug 700 described in FIG. , Peripheral contact plug 750, peripheral wiring 770, stopper film 780, third interlayer insulating film 790, capacitor 800, fourth interlayer insulating film 910, wiring contact plug 900, wiring 920, and protective insulating film 930 are formed as shown in FIG. The semiconductor device 1 of FIG. 2 is completed.

[Second Embodiment]
(Semiconductor device)
In the first embodiment, the upper inner surfaces of the memory cell shallow trench 201, the peripheral shallow trench 202, and the large region isolation trench 203 are exposed when the first HDP silicon oxide film 206 is formed. HDP-CVD improves the coverage by performing sputtering simultaneously with deposition. Since the memory cell shallow trench 201 and the peripheral shallow trench 202 are narrow, there is no problem. However, since the large region isolation trench 203 is wide, there is a concern of silicon loss due to sputtering when the first HDP silicon oxide film 206 is formed. In order to solve this, the semiconductor device manufacturing method of the second embodiment has been devised.

(Method for Manufacturing Semiconductor Device of Second Embodiment)
A method for manufacturing the semiconductor device 1 according to the second embodiment will be described with reference to FIGS. FIGS. 11-16 is sectional drawing of the part corresponding to FIG. In the following description, the same portions as those in the method for manufacturing the semiconductor device of the first embodiment are not described, and the same reference numerals are given in the drawings.

  First, a flowable silicon oxide film 205 is formed so as to fill the memory cell shallow trench 201 and a peripheral shallow trench 202 having a width of 80 nm or less so as to cover the inner surface of the large region isolation trench 203, and anneal to flow in a high oxygen concentration atmosphere. Until the reactive silicon oxide film 205 is modified, the same steps as those in the method of manufacturing the semiconductor device of the first embodiment are performed (corresponding to FIG. 6). At this time, since the mask nitride film 209 remains, the distance between the atmosphere having a high oxygen concentration and the surface of the semiconductor substrate 100 becomes long, and silicon loss hardly occurs. Further, although stress is generated in the fluid silicon oxide film 205 above the memory cell shallow trench 201, it does not detach because the uppermost part of the fluid silicon oxide film 205 is connected.

  Reference is now made to FIG. A first HDP silicon oxide film 206 is formed on the entire surface of the semiconductor substrate 100 so as to completely fill the large region remaining trench 210 remaining after the flowable silicon oxide film 205 is formed so as to cover the inner surface of the large region isolation trench 203. .

  Reference is now made to FIG. The first HDP silicon oxide film 206 is planarized by CMP using the mask nitride film 209 as a stop film.

  Reference is now made to FIG. The first HDP silicon oxide film 206 and the fluid silicon oxide film 205 are mask-nitrided by H1 in the memory cell shallow trench 201, H2 in the peripheral shallow trench 202 having a width of 80 nm or less, and H3 in the large region isolation trench 203 by oxide film plasma dry etching. Etch back so as to descend from the film 209. H1 is a depth of 30 to 40% of the entire trench from the upper end of the memory cell shallow trench 201, H2 is a depth that is flush with the surface of the semiconductor substrate 100, and H3 is a film of the mask nitride film 209 from the upper surface of the mask nitride film 209. Adjust process conditions to be 50-70% deep. Such etching can be realized by using process conditions in which a reverse loading effect occurs. Here, the reverse loading effect refers to a phenomenon in which when etching is performed under process conditions with a large amount of Depo (etching product), the etching rate in a narrow pattern becomes larger than the etching rate in a wide pattern due to the influence of Depo. By this etching, the fluid silicon oxide film 205 having the stress on the upper part of the memory cell shallow trench 201 is not etched, and even if it is detached, it is removed by the etching, so that the defect is less likely to occur.

  Reference is now made to FIG. A second HDP silicon oxide film 207 is formed on the entire surface of the semiconductor substrate 100 so as to fill up the portion etched back in the above process. Since the side surface of the large region isolation trench 203 is not exposed when the second HDP silicon oxide film 207 is formed, silicon loss due to sputtering can be prevented.

  Reference is now made to FIG. The second HDP silicon oxide film 207 is planarized by CMP using the mask nitride film 209 as a stop film.

  Reference is now made to FIG. The second HDP silicon oxide film 207, the first HDP silicon oxide film 206, and the fluid silicon oxide film 205 are etched until they are flush with the top surface of the mat oxide film 208 by wet etching of the oxide film, and mask nitridation is performed by wet etching of the nitride film. The film 209 is removed.

  Thereafter, the same steps as those of the semiconductor device manufacturing method of the first embodiment are performed.

  With the above manufacturing method, the same effects as those of the first embodiment can be obtained in the second embodiment.

  Although the present invention has been described with reference to a plurality of embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the spirit and scope of the present invention described in the claims.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Memory cell area 3 Peripheral circuit area 91 Resist 100 Semiconductor substrate 101 Memory cell active area 102 Peripheral circuit active area 201 Memory cell shallow trench 202 Peripheral shallow trench 203 Large area isolation trench 204 Thermal oxide film 205 Fluid silicon oxide film 206 First HDP silicon oxide film 207 Second HDP silicon oxide film 208 Matt oxide film 209 Mask nitride film 210 Large region remaining trench 300 Word line 400 First interlayer insulating film 314 Cap insulating film 501 Bit line 502 Peripheral gate 503 Peripheral gate Insulating film 504 Cover insulating film 511 Bit line contact plug 600 Second interlayer insulating film 700 Capacitance contact plug 750 Peripheral contact plug 770 Peripheral wiring 780 Stopper film 790 Third layer Interlayer insulating film 800 Capacitor 810 Cylinder hole 811 Lower electrode 812 Capacitor insulating film 813 Upper electrode 900 Fourth interlayer insulating film 910 Wiring contact plug 920 Wiring 930 Protective insulating film

Claims (16)

In a method for manufacturing a semiconductor device having an active region surrounded by an element isolation region on a semiconductor substrate,
Forming a mask nitride film pattern corresponding to the active region on the semiconductor substrate surface;
Etching the semiconductor substrate using the mask nitride film as a mask to form an element isolation trench corresponding to the element isolation region;
Forming a flowable silicon oxide film so as to bury the element isolation trench and to have a surface located above the upper surface of the mask nitride film;
Etching the fluid silicon oxide film from the upper end of the element isolation trench to a predetermined depth;
Forming an HDP silicon oxide film so as to bury the etched element isolation trench;
Planarizing the HDP silicon oxide film using the mask nitride film as a stop film;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the predetermined depth is 30 to 40% of a depth of the entire trench from an upper end of the element isolation trench.   Forming the mask nitride film pattern includes forming a mat oxide film on the surface of the semiconductor substrate and forming a silicon nitride film as the mask nitride film; and etching the mat oxide film and the mask nitride film. The method for manufacturing a semiconductor device according to claim 1, further comprising a step.   The fluid silicon oxide film is modified by annealing between the step of forming the fluid silicon oxide film and the step of etching the fluid silicon oxide film from the upper end of the element isolation trench to a predetermined depth. The method for manufacturing a semiconductor device according to claim 1, further comprising a step.   5. The method of manufacturing a semiconductor device according to claim 1, wherein the HDP silicon oxide film is formed so that a surface thereof is located above an upper surface of the mask nitride film. 6.   After the step of planarizing the HDP silicon oxide film, the HDP silicon oxide film is etched to be flush with the upper surface of the mat oxide film by oxide wet etching, and then the mask nitride film is etched by nitride film wet etching. The method for manufacturing a semiconductor device according to claim 2, further comprising a step of removing.   The method includes forming a thermal oxide film on at least an inner surface of the element isolation trench between the step of forming the element isolation trench and the step of forming the fluid silicon oxide film. The manufacturing method of the semiconductor device of any one of 1-6.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the step of modifying by annealing is performed in an oxidizing atmosphere. Manufacturing of a semiconductor device having a first active region surrounded by a first element isolation region in a memory cell region and a second active region surrounded by a second element isolation region in a peripheral circuit region on a semiconductor substrate In the method
Forming a mask nitride film pattern corresponding to the first active region and the second active region on the semiconductor substrate surface;
Using the mask nitride film as a mask, the semiconductor substrate is etched, and a first element isolation trench corresponding to the first element isolation region and a first element isolation trench corresponding to the second element isolation region Forming a second element isolation trench having a wide groove width, a region isolation trench corresponding to a width between the memory cell region and the peripheral circuit region and having a groove width wider than that of the second element isolation trench;
The first element isolation trench and the second element isolation trench are embedded without completely burying the region isolation trench, and in the first element isolation trench and the second element isolation trench, Forming a flowable silicon oxide film such that the surface is positioned above the upper surface of the mask nitride film;
Forming a first HDP silicon oxide film so as to fill a groove remaining in the region isolation trench without being filled with the fluid silicon oxide film;
Planarizing the first HDP silicon oxide film using the mask nitride film as a stop film;
The first element isolation trench has a predetermined depth from the upper end, the second element isolation trench has the same level as the surface of the semiconductor substrate, and the region isolation trench has a film thickness from the upper surface of the mask nitride film. Etching to a predetermined percentage depth position;
The second HDP silicon oxide film is embedded so as to bury the etched first element isolation trench, the second element isolation trench, and the region isolation trench and to have a surface positioned above the upper surface of the mask nitride film. Forming, and
Planarizing the second HDP silicon oxide film using the mask nitride film as a stop film;
A method for manufacturing a semiconductor device, comprising:   The predetermined depth is 30 to 40% of a depth of the entire trench from an upper end of the first element isolation trench, and the predetermined ratio is 50 to 70%. Item 10. A method for manufacturing a semiconductor device according to Item 9.   11. The method of manufacturing a semiconductor device according to claim 9, wherein a groove width of the second element isolation trench is 80 nm or less.   Forming the mask nitride film pattern includes forming a mat oxide film on the surface of the semiconductor substrate and forming a silicon nitride film as the mask nitride film; and etching the mat oxide film and the mask nitride film. The method for manufacturing a semiconductor device according to claim 9, further comprising a step.   The step of modifying the fluid silicon oxide film by annealing is included between the step of forming the fluid silicon oxide film and the step of forming the first HDP silicon oxide film. The manufacturing method of the semiconductor device of any one of 9-12.   After the step of planarizing the second HDP silicon oxide film, the second HDP silicon oxide film, the first HDP silicon oxide film, and the fluid silicon oxide film are formed on an upper surface of the mat oxide film by wet etching of the oxide film. 13. The method of manufacturing a semiconductor device according to claim 12, further comprising a step of removing the mask nitride film by wet etching of a nitride film after etching until the surface becomes flush.   A step of forming a thermal oxide film on at least an inner surface of each trench between the step of forming the first and second element isolation trenches and the region isolation trench and the step of forming the fluid silicon oxide film. The method for manufacturing a semiconductor device according to claim 9, comprising:   14. The method of manufacturing a semiconductor device according to claim 13, wherein the step of modifying by annealing is performed in an oxidizing atmosphere.

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