JP2014170476A - Data processor and method for controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure data by data transfer to an external memory using an internal memory by achieving high speed transfer under the control of the direct output of data to the external memory.SOLUTION: A data processor is configured to control data transfer to a DRAM 110 as an internal memory for temporarily storing processed data and an external card 111 as an external memory. A DMA controller 105 monitors a data transfer state to the external card 111, and switches control in a first mode for transferring data via the DRAM 110 to the external card 111 and control in a second mode for transferring data to the external card 111 without using the DRAM 110. In the second mode, the data are directly transferred to the external memory such that transfer processing with a high throughput is executable. In the first mode, the data read from the internal memory are transferred to the external memory in accordance with the deterioration of the data transfer speed.

Description

  The present invention relates to a data processing apparatus and a control method therefor, and particularly relates to processing using a plurality of storage media.

  In conventional imaging devices such as digital cameras and video cameras, for example, imaging data is temporarily stored in a memory (hereinafter referred to as internal memory) inside the camera and then output to a removable recording medium (hereinafter referred to as external memory). The Japanese Patent Application Laid-Open No. 2004-228561 discloses a process of detecting whether or not an external memory is inserted and determining whether or not the external memory can be used and reflecting it in a subsequent photographing operation. When it is determined that writing is not possible by determining whether the external memory can be used, the imaging operation is prohibited.

  At the start of the camera operation, the state of the inserted recording medium is checked, but it is difficult to precisely define the data transfer speed of the recording medium. For this reason, data is stored in the internal memory and then transferred to the external memory. In general, the external memory is often slower than the internal memory, and data is transferred to the external memory via the internal memory in order to absorb the speed difference between the two. Even if the external memory has a sufficient data transfer rate, it is necessary to retransmit the data when an error occurs. For example, in the SD card (trademark), the minimum guaranteed speed is 10 megabytes / second in Class 10, but there is a CRC (error detection method during transfer) error caused by the transmission path between the camera body and the external memory. Can occur. In such a case, since it is difficult to guarantee the data transfer rate, the data to be output to the external memory needs to be temporarily stored in the internal memory.

  In the case of a system in which image data is temporarily stored in the internal memory, the number of continuous shots of the camera depends on the size of the internal memory that can be stored. For example, if the average data size per image is 5 megabytes and the internal memory capacity is 50 megabytes, the number of images that can be continuously shot is 10. In a system that cannot execute data transfer to the internal memory and data output to the external memory at the same time, it is necessary to output the data to the external memory after the data transfer to the internal memory is completed. Therefore, when the maximum number of continuous shots, that is, the maximum number (10) that can be continuously shot by the camera is exceeded, the user waits until the next shooting.

  On the other hand, in the case of a system that can output image data already stored in the internal memory to the external memory simultaneously with the data transfer to the internal memory, the maximum number of continuous shots can be increased. For example, if it is possible to output data for five images to the external memory during a period in which data transfer to the internal memory is performed for ten images, the maximum number of continuous shots is about 15. In both systems, there is a limit to the number of images that can be shot continuously. Since the external memory is generally slower than the data transfer rate to the internal memory, the maximum number of consecutive shots depends on the storage amount (buffer amount) in the internal memory.

Japanese Patent Laid-Open No. 06-006665

Incidentally, card-type storage devices used for the external memory have been increased in data transfer speed, and image data captured by a camera can be directly written. In this case, the maximum number of continuous shots can be increased to the maximum size that can be output to the external memory, regardless of the data storage capacity of the internal memory. However, even if the external memory has a sufficiently high data transfer rate, it is necessary to guarantee data when a CRC error occurs and data writing fails.
An object of the present invention is to realize high-speed transfer by controlling data output directly to an external memory and to guarantee data by data transfer to an external memory using an internal memory.

  In order to solve the above-described problems, an apparatus according to the present invention transfers input data to the first storage medium and the second storage medium and stores the data input by the input means and the input means. And means for transferring the data stored in the first storage medium to the second storage medium for storage, wherein the data is transferred from the first storage medium to the second storage medium. Control means for switching between a first mode for storing and a second mode for transferring and storing data from the input means to the second storage medium. The control means switches between the first mode and the second mode depending on whether data can be transferred from the input means to the second storage medium and stored.

  According to the present invention, high-speed transfer is realized by the control of directly outputting data to the second storage medium, and the data is guaranteed by the control of transferring to the second storage medium via the first storage medium. Can do.

It is a figure which shows the structural example of an apparatus in order to demonstrate 1st Embodiment of this invention combined with FIG. 2 thru | or FIG. It is a figure for demonstrating in detail the switching control of the data path of a DMA controller and a card controller. It is a flowchart explaining the example of a data transfer process. FIG. 6 is a conceptual diagram illustrating the flow of data transfer together with FIG. 5 and shows transfer states (A) to (D). FIG. 5 is a diagram illustrating transfer states (E) to (G) following FIG. 4. It is a figure which shows the structural example of an apparatus in order to demonstrate 2nd Embodiment of this invention with FIG. 7 and FIG. It is a figure which shows the time chart (A) for demonstrating the example of a process, and the data arrangement example (B) of DRAM. It is a flowchart explaining the example of a data transfer process.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In each embodiment, a digital camera is exemplified as the electronic device, but the present invention can be widely applied to imaging devices such as a digital video camera and a camera-equipped mobile phone.

[First Embodiment]
FIG. 1 is a block diagram illustrating a system configuration example of a digital camera according to the first embodiment of the present invention.

The imaging optical system 100 includes an imaging lens, a shutter, a diaphragm, and the like. The imaging unit 101 includes an imaging element that photoelectrically converts light from a subject via the imaging optical system 100 to generate an imaging signal, and a correlated double sampling unit (not shown) that removes reset noise included in the imaging signal. . In addition, the imaging unit 101 includes a variable gain amplification unit that amplifies the level of the imaging signal in a variable gain, and an A / D conversion unit that quantizes analog data into digital data. The imaging unit 101 outputs imaging data to a DMA (Direct Memory Access) controller 105 described later. In FIG. 1, as data processing means for processing imaging data output from the imaging unit 101, a signal processing unit 102 that performs imaging data development processing and the like, and an image compression / decompression unit 103 that performs image data compression processing and decompression processing are provided. Illustrate.
The signal processing unit 102 performs appropriate digital signal processing on the digital image data obtained by the imaging unit 101 based on an evaluation value by an image evaluation processing unit (not shown). The image compression / decompression unit 103 performs compression processing on the image data processed by the signal processing unit 102 to generate, for example, JPEG (Joint Photographic Experts Group) data. The image compression / decompression unit 103 performs decompression processing on the compressed JPEG image data, and generates image data to be displayed on a display device or the like.

A CPU (Central Processing Unit) 104 executes a control program to control each unit. The DMA controller 105 is a first control unit that controls data transmitted and received between the imaging unit 101, the signal processing unit 102, and the image compression / decompression unit 103. The display controller 106 transmits display image data acquired via the system bus 112 to the display device 109. The display device 109 displays an image on the screen according to the display image data.
A DRAM (Dynamic Random Access Memory) controller 107 controls data access to the DRAM 110. The DRAM 110 is an internal memory (first storage medium) for temporarily saving processed data. The card controller 108 is second control means for controlling data access to the external card (mainly flash memory) 111. The external card 111 is an external memory (second storage medium) that can be attached to and detached from the imaging apparatus, and various card-type storage devices, recording devices using magnetic recording media, and the like can be used.

  The CPU 104 and each controller are connected to the system bus 112. Each unit is connected to the system bus 112 with the CPU 104 and the DMA controller 105 as a bus master, and the display controller 106, DRAM controller 107, and card controller 108 as a bus slave. The card direct path 113 directly transfers data from the DMA controller 105 to the card controller 108 as a data path independent of the system bus 112. The flow control signal line 114 is a signal line for performing data flow control of writing to the external card 111.

  Next, a configuration example centering on the DMA controller 105 and the card controller 108 will be described with reference to FIG. The first selector 105-1 in the DMA controller 105 is a first data selection unit that selects one of the data of the imaging unit 101, the signal processing unit 102, and the image compression / decompression unit 103 as a plurality of input data. The signal selection in the first selector 105-1 is controlled by the CPU 104.

  A data FIFO memory (hereinafter simply referred to as FIFO) 105-2 is a data buffer that temporarily holds and outputs data, accumulates data selected by the first selector 105-1, and sequentially outputs the data. FIFO is an abbreviation for “First-In First-Out”. The data path 112-3 is a connection line of the DMA controller 105 at the time of write access to the system bus 112. The card direct path 113 indicates a path for transferring data from the FIFO 105-2 to the card controller 108.

The second selector 108-1 in the card controller 108 is second data selection means for selecting either input data from the system bus 112 or input data from the DMA controller 105. The second selector 108-1 has a function of selecting the output data of the FIFO 105-2 and the data read from the DRAM 110 as the internal memory as data to be written to the external card 111. The signal selection in the second selector 108-1 is controlled by the CPU 104. A data path 112-4 connecting the system bus 112 and the card controller 108 is used for data transfer when writing to the external card 111.
The data path 112-1 connects the system bus 112 and the CPU 104, and the data path 112-2 connects the system bus 112 and the DRAM controller 107.

  Next, a processing example in the case where image data input from the imaging unit 101 is directly written to the external card 111 will be described with reference to FIGS. 3, 4, and 5. FIG. 3 is a flowchart for explaining the flow of processing, and FIGS. 4 and 5 are conceptual diagrams for explaining data transfer examples.

  When the external card 111 is inserted into the card slot of the camera, the CPU 104 checks the attribute of the external card 111. At this time, the data reading speed and writing speed can be determined. The processing of FIG. 3 starts, and in S301, the CPU 104 directly writes the data output by the imaging unit 101 to the external card 111 via the DMA controller 105 based on the data transfer speed checked at the time of card insertion (card direct processing). Whether or not is possible is determined. In the case where the card direct processing is impossible, for example, when the data transfer speed of the external card 111 is slower than the data transfer speed of the imaging unit 101, the process proceeds to S309 and the first mode is set. Hereinafter, the first mode in which image data read from the internal memory (DRAM 110) is transferred to the external memory (card 111) and recorded is referred to as an “internal buffer mode”. In the internal buffer mode, output data of the imaging unit 101 is temporarily stored in the DRAM 110 and then transferred from the DRAM 110 to the external card 111 to execute a writing process. That is, when the external memory is a low-speed recording medium, the processed data is transferred from the FIFO 105-2 to the DRAM 110, temporarily stored, and then transferred to the card 111.

  On the other hand, when the card direct processing is possible, for example, when it is determined that the data transfer speed of the card 111 inserted into the card slot is a speed sufficient to directly write the output data of the imaging unit 101, The process proceeds to S302. In S302, the second mode is set. Hereinafter, the second mode in which image data is transferred to and recorded on the card 111 without going through the DRAM 110 is referred to as “card direct mode”. In this case, the CPU 104 performs setting processing so that the first selector 105-1 selects an input from the imaging unit 101 and the second selector 108-1 selects an input from the card direct path 113. The CPU 104 starts transfer of image data by the DMA controller 105. Also in the card direct mode, the image data is transferred to the DRAM controller 107 in parallel with the transfer of the image data to the card controller 108. In the next S303, the imaging operation is started, the image data acquisition by the imaging optical system 100 and the imaging unit 101 is started, and the image data is input to the FIFO 105-2 in the DMA controller 105.

  Here, the flow of data input to the FIFO 105-2, the DRAM 110, and the external card 111 will be described with reference to FIGS. In the present embodiment, it is assumed that the total capacity of the FIFO 105-2 is 2048 bytes and this is used by being divided into four. That is, the data amount per block is 512 bytes. The image data output from the imaging unit 101 is transferred to the DRAM 110 and the external card 111 when data for one block is accumulated in the FIFO 105-2.

  FIG. 4A conceptually shows the amount of data stored in each part. The FIFO 105-2 is composed of four blocks, and one block is 512 bytes. The DRAM 110 and the external card 111 are also shown as being divided in units of blocks. A first pointer (FIFO write pointer) in the figure indicates a position where imaging data is written to the FIFO 105-2. Further, the second pointer (card write pointer) indicates a position where image data is written from the FIFO 105-2 to the external card 111. The third pointer (DRAM write pointer) indicates a position where the imaging data is written from the FIFO 105-2 to the DRAM 110. These pointers point to the same position at the time of S303 in FIG. 3, and this position is the position of the FIFO write pointer (this reference position is set to zero).

  FIG. 4B illustrates a state where time has elapsed after the start of imaging. In the figure, the imaging data for each block is distinguished by a number shown in a circle, and each data is expressed as D (X) in the specification. X represents a natural number variable. In the state shown in FIG. 4B, data is stored in the FIFO 105-2 from D (1) to D (3) as shown by the FIFO write pointer, and D (4) is being written. . In the DRAM 110, as indicated by the DRAM write pointer, the writing of D (1) and D (2) is completed, and the data of D (3) is being transferred. At this time, if an error occurs in the external card 111, a retransmission process is executed, and therefore a delay occurs in the data transfer process. As indicated by the card write pointer, the data of D (1) is being transferred to the external card 111.

  In the state shown in FIG. 4C, the card write pointer points to the beginning of D (2), and the data of D (2) is currently transferred to the external card 111. The FIFO write pointer points to the beginning of D (5), and D (5) is being written. That is, since the data of D (1) has already been transferred, D (5) can be written in the area where D (1) previously existed.

  When writing of D (5) is completed in the FIFO 105-2 and the next D (6) is transferred from the imaging unit 101 to the FIFO 105-2, the transfer to the external card 111 at the present time is performed. D (2) May be overwritten. Therefore, at this time, the CPU 104 is notified that the FIFO 105-2 is not allowed to write any more data (Full). The full state can be determined, for example, based on whether or not the data accumulation amount of the FIFO 105-2 exceeds a threshold value. In S304 of FIG. 3, a Full state determination process related to the FIFO 105-2 is shown. If it is determined that the FIFO 105-2 is in the full state, the process proceeds to step S305. If it is determined that the FIFO 105-2 is not in the full state, the process proceeds to step S307. When the DMA controller 105 accepts the data of the imaging unit 101, real-time processing relating to imaging data at a specific frame rate is required. When this imaging data is written to the external memory by card direct processing, the waiting time for the writing processing cannot be taken. For this reason, it is necessary to constantly monitor the data accumulation amount in the FIFO 105-2.

  In step S305, the CPU 104 performs an internal buffer mode setting process. As a result, the second selector 108-1 switches to a state of selecting a data input from the data path 112-4. That is, a process of writing data input from the DRAM 110 to the card controller 108 via the system bus 112 to the external card 111 is executed. At this time, since the data D (1) on the DRAM 110 shown in FIG. 4C has already been transferred to the external card 111, the area storing the D (1) Freed for no need. An area indicated by hatching in FIG. 4 indicates a releasable area, that is, an area that can be used for data writing again. Of the data on the DRAM 110, an area for storing data that has been written to the external card 111 is in a state in which the next data can be written to the area upon release.

  FIG. 4D shows a state in which the mode is switched to the internal buffer mode, and the card write pointer points to the head of D (2) on the DRAM 110. D (2) on the DRAM 110 is transferred to the external card 111. In the state of FIG. 5E, the internal buffer mode is continuing, and D (4) on the DRAM 110 is being transferred to the external card 111. The FIFO write pointer at this time points to the head of D (6), and D (6) is written from the imaging unit 101. The difference between the write position pointed to by the FIFO write pointer and the position pointed to by the card write pointer is two blocks or more. At this time, the determination result of S304 in FIG. 3 indicates that the FIFO 105-2 is not in the Full state. That is, the Full state is released. In this case, the process proceeds to S307, the card direct mode is set, and the second selector 108-1 selects the input of the card direct path 113. At this time, the transfer to the external card 111 has already been completed for the areas in the DRAM 110 that store D (1) to D (3). Therefore, these areas can be released.

  In FIG. 5F, the card direct mode is set, and the card write pointer points to the beginning of D (4) of the FIFO 105-2. Since the difference between the position pointed to by the FIFO write pointer and the position pointed to by the card write pointer is two blocks or more, the card direct mode is being continued. FIG. 5G shows a state further advanced from FIG. 5F, and the card write pointer indicates the beginning of D (5), but the FIFO write pointer indicates the beginning of D (7). ing. Since the position indicated by these pointers is two blocks or more away, the card direct mode can be continued. In addition, as for D (5) on the DRAM 110, writing is performed in an area that has already been released and that holds D (1).

  As described above, in this embodiment, the first pointer used when writing data from the imaging unit 101 to the FIFO 105-2 and the second pointer used when writing data from the FIFO 105-2 to the external memory are monitored. In order to determine whether the position pointed to by the first pointer exceeds the position pointed to by the second pointer, a difference in pointer position is calculated and compared with a threshold value. If the calculated difference is greater than or equal to the threshold value, there is room in processing, so that it is possible to continue the control of transferring the imaging data to the external memory and writing it directly. On the other hand, if the calculated difference is less than the threshold value, it is determined that the position pointed to by the first pointer may possibly overtake the position pointed to by the second pointer. In this case, the control of transferring the imaging data to the external memory and directly writing it is stopped, and the control of reading the imaging data already saved in the internal memory, transferring it to the external memory and writing it is performed. In other words, the mode switching criterion for changing the data transfer path is based on the result of comparing the difference amount between the positions indicated by the first pointer and the second pointer with the threshold value, and the mode switching is performed dynamically. become.

When the process moves to S306 after S305 in FIG. 3, the CPU 104 determines whether or not to end the imaging operation. If the imaging operation is continued, the process returns to S304. Similarly, if the process moves from S307 to S308 and it is determined that the shooting operation is to be continued, the process returns to S304. If the process moves from S309 to S310 and it is determined that the photographing operation is to be continued, the process returns to S309. When it is determined in S306, S308, and S310 that the photographing operation has been completed, the series of processing illustrated in FIG. 3 ends.
As described above, dynamic switching control between the internal buffer mode and the card direct mode is performed until the data transfer to the external card 111 is completed while monitoring the first pointer and the second pointer.

  According to the first embodiment, the first storage medium (internal memory) having the minimum necessary capacity for data guarantee is used directly to the second storage medium (external memory) mounted on the imaging apparatus. Data can be output and stored. At that time, the transfer state (transfer speed, etc.) of the external memory is monitored, and the amount of data stored in the FIFO of the DMA controller is ascertained, and control is performed to directly write data to the external memory according to the monitoring result. Generally, it is difficult to strictly determine the data transfer rate of the external memory, but when it is determined that the data transfer rate is sufficient, direct processing to the external memory is executed. In this case, data transfer with high throughput is possible as compared with the method of transferring data saved in the internal memory to the external memory.

  In addition, for data to be stored in the internal memory at the same time as data transfer to the external memory, the storage area to be secured on the internal memory is minimized by sequentially releasing from the area where the transfer to the external memory has been completed. Can do. When the data transfer rate decreases due to an external memory transfer error or the like, the process switches to the process of writing the data saved in the internal memory to the external memory, so that the data to be transferred can be guaranteed. In addition, by changing the criteria for determining whether direct processing to the external memory is possible or not according to the processing in the imaging apparatus, optimal data transfer processing can be realized according to each processing.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. In the second embodiment, a description will be given of a process of performing signal processing on data output from an imaging unit and storing JPEG data that has undergone image compression directly in an external memory. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those used in the first embodiment, and detailed description thereof is omitted. Hereinafter, differences will be mainly described.

FIG. 6 is a diagram illustrating a configuration example of a system that outputs JPEG image data after image compression to the external card 111.
When the specified time elapses, the hardware timer 120 notifies the CPU 104 of the elapse of time via the timer interrupt signal line 121. The flow control signal line 122 of the DMA controller 105 transmits a signal to the image compression / decompression unit 103 to stop data input to the DMA controller 105 when detecting a state where all the data of the FIFO 105-2 is accumulated. In the case of the first embodiment, data input from the imaging unit 101 cannot be stopped halfway. On the other hand, in the case of the second embodiment, regarding the data input of the processing system that performs signal processing and image compression, if data reading from the DRAM 110 is interrupted, the processing can be stopped halfway.

  Next, with reference to FIG. 7, processing for generating JPEG data by performing signal processing on imaging data from the imaging unit 101 will be described. FIG. 7A is a schematic diagram for explaining the flow of processing, and shows four periods T1, T2, T3, and T4 divided in the time axis direction. Each period corresponds to the processing time per frame during continuous shooting. For example, assuming that 10 frames are continuously shot per second, the time lengths of the periods T1, T2, T3, and T4 are each 100 milliseconds. That is, 1000/10 = 100 milliseconds per frame. The imaging data, the development data, and the JPEG data in each period are distinguished by the numbers in the circles in the figure. In the specification, these are expressed as D (X). X is a natural number variable, and D (X) represents image data of the Xth frame. As imaging data, D (1) to D (4) are shown in periods T1 to T4, respectively. As development data, D (1) to D (3) are shown in periods T2 to T4, respectively, and as JPEG data, D (1) and D (2) are shown in periods T3 and T4, respectively.

The state of access to the DRAM 110 when attention is paid to the period T4 will be described with reference to FIG. FIG. 7B illustrates the arrangement of image data on the DRAM 110 in the period T4 within a rectangular frame. On the left side of the rectangular frame, the write pointers by the imaging unit 101 and the development processing unit in the signal processing unit 102 are shown, and on the right side of the rectangular frame, the read pointers by the development processing unit and the image compression / decompression unit 103 are shown.
In the period T4, the imaging data D (4) from the imaging unit 101 is written in the DRAM 110. As for the development data, the imaging data D (3) that has already completed the imaging process in the period T3 is read, and the development processing unit performs the development process of D (3) and writes it in the DRAM 110. For JPEG data, development data D (2) that has already undergone development processing in period T3 is read. The data D (2) is compressed by the image compression / decompression unit 103, transferred from the DMA controller 105 to the card controller 108 via the card direct path 113, and output to the external card 111.

  At this time, if a series of processes related to imaging data, development data, and JPEG data cannot be completed within 1000 milliseconds, continuous shooting of 10 frames cannot be continued per second. Therefore, if the transfer speed of image data to the DRAM 110, which is the internal memory of the camera, is strictly guaranteed, the time required for the card direct processing of JPEG data must not exceed a predetermined time. This predetermined time is 1000 milliseconds in this example, and is hereinafter referred to as 1V processing time. In other words, when reading and writing of imaging data to the internal memory and reading and writing of development data are possible within 1V processing time, it is guaranteed that the time for transferring compressed data to the external memory does not exceed 1V processing time. There is a need to.

Next, with reference to FIG. 8, a sequence for ensuring that the time required for card direct processing of JPEG data does not exceed 1V processing time will be described.
Similar to the flowchart of FIG. 3 of the first embodiment, when the external card 111 is inserted into the card slot of the camera, the attribute of the card is checked. If it is determined in S701 that card direct processing is not possible, the process proceeds to S710, and the internal buffer mode is set. That is, the JPEG data output from the image compression / decompression unit 103 is temporarily stored in the DRAM 110 via the system bus 112 and the DRAM controller 107, read out, and stored in the external card 111. If it is determined in S711 that the shooting has ended, the process ends, but the internal buffer mode remains set while the imaging operation continues.

  On the other hand, if it is determined in S701 that card direct processing is possible, the process proceeds to S702. In S702, if the user is operating the release switch, it is determined that continuous shooting (so-called continuous shooting) is continued, and the process proceeds to S703. At the end of continuous shooting, the current frame processing is completed. In S703, it is determined whether JPEG data output for the previous frame is completed. For example, during the continuous shooting operation, whether or not the process of writing the JPEG data D (1) of the period T3 to the external card 111 is completed before the process of the period T4 shown in FIG. Is determined. If the processing of data D (1) has not been completed, the process proceeds to S708. If the processing of data D (1) has been completed, the process proceeds to S704. In step S <b> 708, the internal buffer mode is set, and the JPEG data is once written to the DRAM 110 and then read and stored in the external card 111.

  In S704, the card direct mode is set, and imaging processing, development processing, and JPEG compression processing start all at once. For example, in the period T4 shown in FIG. 7A, the reading and writing of the data D (4) and D (3) are guaranteed to be reliably completed within 1V processing time as described above. ing. However, in the case of writing JPEG data by card direct processing, completion of processing within 1 V processing time is not necessarily guaranteed. For example, when a write error occurs in the external card 111, retransmission processing is necessary, and the transfer rate to the external card 111 may be slow. For this reason, the JPEG data D (2) shown in FIG. 7B may not be stored in the external card 111 within the 1V processing time. Therefore, a timer monitoring function is used to detect that the data transfer rate of the external card 111 has become slower than the threshold rate. In other words, the hardware timer 120 is activated at the start of processing in the period T4, and for example, when 500 milliseconds have elapsed, the CPU 104 is interrupted, and the CPU 104 measures the amount of JPEG data written to the external card 111. Execute the process to check. The time threshold value 500 milliseconds set here is a half of the time when the 1V processing time is 1000 milliseconds. For example, the progress of the read process is checked by monitoring the read address of the development data (see D (2) in FIG. 7B) for generating JPEG data. Whether the write processing to the external card 111 is performed without any problem or the write processing is delayed by comparing the measured amount of data with the planned data amount (threshold) to be processed within the time threshold Can be judged. In S705, it is determined whether or not a timer interrupt has occurred. If a timer interrupt occurs after 500 milliseconds have elapsed, the process proceeds to S706. In S706, a check is made as to whether or not the writing process of JPEG data to the external card 111 is proceeding without any problem. Here, if the output amount of JPEG data is less than the specified value, that is, the writing speed to the external card 111 is slow, and if it is determined that the card direct processing will not be in time for the end of the 1V processing time, S708 is performed. Move on. In step S708, the internal buffer mode is set, and JPEG data writing processing is guaranteed. If the output amount of JPEG data is greater than or equal to the specified value in S706, the process proceeds to S707.

  In S707, it is determined whether or not the output of the JPEG data of the current frame has been completed. If it is confirmed in the card direct process that the process for the current frame (see the frame in the period T4 in FIG. 7) has been completed, the process returns to S702, and if not completed, the process returns to S705. Similarly, when the process proceeds from S708 to S709, it is determined whether or not the output of the JPEG data of the current frame is completed in the internal buffer mode. When the process for the current piece is completed, the process returns to S702. When the process is not completed, the determination process of S709 is repeated. When the continuous shooting operation is finished in S702, the sequence is finished.

According to the second embodiment, the processed data can be transferred and stored in the external memory while performing a series of processing such as imaging processing, development processing, and data compression processing within a specified time. In data compression processing, when data is transferred from the internal memory to the external memory, it is possible to wait for the processing according to the writing speed, but the processing time per frame is specified as in continuous shooting. In the case of processing, it is necessary to monitor the specified time. Data transfer control is performed based on the measurement amount while monitoring the time by the hardware timer 120 and measuring the progress of the processing data in the middle of the specified time. As a result, it is selected whether to continue the control of transferring the output data subjected to the data compression processing to the external memory and directly writing it, or to change the control to transfer the data stored in the internal memory and writing to the external memory.
The DMA controller 105 monitors the address pointer of the FIFO 105-2 when data from the imaging unit 101 is selected, and the CPU 104 monitors the processing time when data is from the image compression / decompression unit 103. In this way, the monitoring process can be appropriately switched according to the processing content.

104 CPU
105 DMA controller 110 DRAM (first storage medium)
111 External card (second storage medium)

Claims (10)

An input means for inputting data;
The data input by the input means is transferred to and stored in the first storage medium and the second storage medium, and the data stored in the first storage medium is transferred to the second storage medium. A first mode for transferring and storing data from the first storage medium to the second storage medium, and transferring data from the input means to the second storage medium Control means for switching between the second mode to be stored and
The control means switches between the first mode and the second mode depending on whether or not data can be transferred from the input means to the second storage medium and stored. A data processing device.   2. The data processing apparatus according to claim 1, wherein the control unit sets the first mode when a data transfer rate to the second storage medium is less than a threshold value.   The data processing apparatus according to claim 1, wherein the control unit sets the second mode when the amount of data written from the input unit to the second storage medium is equal to or greater than a threshold value.   In the second mode, the control means performs data transfer from the input means to the first storage medium in parallel with data transfer from the input means to the second storage medium. The data processing device according to claim 1, wherein the data processing device is a data processing device.   The control means has storage means for storing data input by the input means, and is not stored in the second storage medium among the data stored in the storage means in the second mode. The data processing apparatus according to claim 4, wherein when the amount of data exceeds a threshold value, the second mode is changed to the first mode.   The control means changes the second mode to the first mode, and then, among the data stored in the first storage medium, the control means starts from the data not stored in the second storage medium. 6. The data processing apparatus according to claim 5, wherein transfer to the second storage medium is started.   In the second mode, the control means is responsive to the same data stored in the first storage medium as being stored in the second storage medium. The data processing apparatus according to claim 4, wherein data is written in an area where the same data is stored.   The data processing apparatus according to claim 1, wherein the input unit selects and inputs one data from a plurality of data.   The data processing apparatus according to claim 1, wherein the input unit includes an imaging unit. A first storage medium that temporarily stores processed data, and a data processing device that controls data transfer with respect to the second storage medium that stores the data and data transferred from the first storage medium A control method executed in
When transferring and storing the data in the first storage medium and the second storage medium, monitoring a transfer state of the data to the second storage medium;
According to the monitoring result in the step, the control in the first mode for transferring the data to the second storage medium via the first storage medium, and without passing through the first storage medium A method for controlling a data processing apparatus, comprising: switching a control in a second mode for transferring data to the second storage medium.

Images