JP2014168106A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves enhancement of breakdown resistance and a low loss (low on-resistance and low saturation voltage).SOLUTION: A semiconductor device includes: a first high-resistance base layer 2 of a first conductivity type; a collector layer 14 of a second conductivity type; a second base layer 16 of the second conductivity type; an emitter layer 13 of the first conductivity type; a gate electrode 8 which extends in a first direction and is formed through a gate insulating film 6 in a trench that passes through the emitter layer and the second base layer and reaches the halfway depth of the first base layer; a collector electrode 20; and an emitter electrode 24 provided in the emitter layer and the second base layer. The emitter layer includes: a first emitter layer 13-1 arranged along the trench in a first direction; and a second emitter layer 13-2 arranged in a second direction so that the first emitter layers are connected to each other in a ladder shape. A base contact layer 4 having impurity density higher than that of the second base layer of the second conductivity type is arranged so as to surround the second emitter layer.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to breakdown in a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT). The present invention relates to a semiconductor device characterized by a structure in which an improvement in withstand capability and a low loss (low on-resistance, low saturation voltage) are compatible, and also a high switching speed for IGBT, and a manufacturing method thereof.

  As a semiconductor device having a trench structure, a vertical MOSFET and a vertical IGBT have been proposed. Since the trench side wall is used as the channel region, it is easy to shorten the channel, and since the channel region can be formed at a high density, a high current density is expected.

  The reduction of the on-voltage of the vertical IGBT having a trench structure has already been disclosed (for example, see Patent Document 1). In Patent Document 1, a p-type drain layer, a high-resistance n-type base layer provided on the p-type drain layer, a p-type base layer formed on the surface of the n-type base layer, A plurality of n-type source layers formed on the surface of the n-type base layer, and a gate oxide film in a plurality of trenches that penetrate the n-type source layer and the p-type base layer and reach a depth in the middle of the n-type base layer In an IGBT having a gate electrode formed through a p-type base layer and a p-type contact layer formed in contact with the n-type source layer on the surface of the p-type base layer, the interval between the trenches can be set to 1.5 μm or less. It is disclosed.

Japanese Patent Laid-Open No. 11-274484 (page 9-10, FIG. 1)

  FIG. 7 shows a schematic perspective view of a conventional IGBT.

  As shown in FIG. 7, the conventional IGBT has a first base layer 2 having a high resistance and a first conductivity type, a collector layer 14 having a second conductivity type provided on the first base layer 2, and a first base layer. The second conductivity type second base layer 16 formed on the surface of the second base layer 16, the first conductivity type emitter layer 13 formed on the surface of the second base layer 16, and the emitter layer extending in the first direction. 13 and the second base layer 16, and a gate electrode 8 formed through a gate insulating film 6 in a plurality of trenches reaching a depth in the middle of the first base layer 2. An emitter is formed on the surface of the second base layer 16. A base contact layer 4 formed in contact with the layer 13 and extending in a first direction and having a higher impurity density than the second base layer of the second conductivity type is provided.

  In FIG. 7, the collector electrode provided in the collector layer 14, the emitter layer 13, and the emitter electrode provided in the base contact layer 4 are not shown.

In the conventional IGBT, in order to increase the breakdown tolerance, a base contact layer 4 made of a p ⁺ diffusion layer is usually formed in a portion of the second base layer 16 made of a p region, as shown in FIG. However, in this structure, the channel portion of the second base layer 16 made of the p region is narrowed, and the channel is not sufficiently opened when conducting a large current, and the on-resistance (saturation voltage) is increased.

  An object of the present invention is to achieve both improvement in breakdown resistance and low loss (low on-resistance, low saturation voltage) in a semiconductor device composed of MOSFET and IGBT, and further increase the switching speed for IGBT. Another object of the present invention is to provide a semiconductor device having a feature in the structure to be manufactured and a method for manufacturing the same.

  In order to achieve the above object, a semiconductor device according to claim 1 of the present invention is a high-resistance first conductive type first base layer, and a second conductive type collector layer provided on the first base layer; A second conductivity type second base layer formed on the surface of the first base layer; a first conductivity type emitter layer formed on the surface of the second base layer; and extending in a first direction. A gate electrode formed through a gate insulating film in a plurality of trenches that penetrates the emitter layer and the second base layer and reaches a depth in the middle of the first base layer, and a collector provided in the collector layer An emitter electrode provided on the emitter layer and the second base layer, wherein the emitter layer is disposed in the first direction along the trench; and the first emitter Connect layers to a ladder And a second emitter layer disposed in a second direction orthogonal to the first direction, wherein a base contact layer having a higher impurity density than the second conductivity type second base layer is formed as the second emitter layer. It is arranged to wrap the layers.

  According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein an interlayer insulating film is disposed on the gate insulating film and the gate electrode forming the trench. To do.

  According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the emitter electrode is formed on the surfaces of the emitter layer and the second base layer via the interlayer insulating film. It is characterized by that.

  A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the second aspect, wherein the emitter electrode is formed of the emitter layer, the second base layer, and the base contact layer through the interlayer insulating film. It is formed on the surface.

  A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to any one of the first to fourth aspects, wherein the area ratio of the emitter layer formed on the surface of the second base layer is 10%. It is characterized by being 70% or less.

  According to a sixth aspect of the present invention, there is provided a semiconductor device having a high resistance and a first conductivity type first base layer, a second conductivity type collector layer provided on the first base layer, and the first base layer. A buffer layer having a first conductivity type formed on the surface and having a higher impurity density than the first base layer; a second base layer of a second conductivity type formed on the surface of the buffer layer; A first conductivity type emitter layer formed on the surface of the base layer, and a plurality of trenches extending in a first direction and penetrating through the emitter layer and the second base layer to reach a depth in the middle of the buffer layer. A gate electrode formed through a gate insulating film, a collector electrode provided in the collector layer, and an emitter electrode provided in the emitter layer and the second base layer, Along the trench And a second emitter layer disposed in a second direction orthogonal to the first direction so as to connect the first emitter layers to each other in a ladder shape. A base contact layer having a higher impurity density than the two-conductivity type second base layer is disposed so as to surround the second emitter layer.

  According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, an interlayer insulating film is disposed on the gate insulating film and the gate electrode forming the trench. .

  According to an eighth aspect of the present invention, in the semiconductor device according to the sixth aspect, the emitter electrode is formed on the surface of the emitter layer and the second base layer via the interlayer insulating film. It is characterized by that.

  According to a ninth aspect of the present invention, in the semiconductor device according to the sixth aspect, the emitter electrode includes the emitter layer, the second base layer, and the base contact layer through the interlayer insulating film. It is formed on the surface.

  A semiconductor device according to a tenth aspect of the present invention is the semiconductor device according to any one of the sixth to ninth aspects, wherein the area ratio of the emitter layer formed on the surface of the second base layer is 10%. It is characterized by being 70% or less.

  According to an eleventh aspect of the present invention, there is provided a semiconductor device having a high resistance and a first conductivity type first base layer, a first conductivity type drain layer provided on the first base layer, and the first base layer. A second conductivity type second base layer formed on the surface; a first conductivity type source layer formed on the surface of the second base layer; and extending in a first direction, the source layer and the first A gate electrode formed through a gate insulating film in a plurality of trenches that penetrates through the two base layers and reaches the middle depth of the first base layer, a drain electrode provided in the drain layer, the source layer, A source electrode provided on the second base layer, wherein the source layer is disposed along the trench in a first direction, and the first source layer is disposed in the first direction. The first layer is connected so that the source layers are connected in a ladder shape. A base contact layer having a higher impurity density than that of the second conductivity type second base layer is disposed so as to wrap around the second source layer. It is characterized by that.

  A semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to the eleventh aspect, wherein an interlayer insulating film is disposed on the gate insulating film and the gate electrode forming the trench. .

  According to a thirteenth aspect of the present invention, in the semiconductor device according to the eleventh aspect, the source electrode is formed on the surface of the source layer and the second base layer via the interlayer insulating film. It is characterized by that.

  A semiconductor device according to a fourteenth aspect of the present invention is the semiconductor device according to the eleventh aspect, wherein the source electrode includes the source layer, the second base layer, and the base contact layer via the interlayer insulating film. It is formed on the surface.

  According to a fifteenth aspect of the present invention, there is provided a semiconductor device according to a fifteenth aspect of the present invention, wherein the first resistance type first base layer, the first conductivity type drain layer provided on the first base layer, and the first base layer are formed. A buffer layer having a first conductivity type formed on the surface and having a higher impurity density than the first base layer; a second base layer of a second conductivity type formed on the surface of the buffer layer; A source layer of a first conductivity type formed on the surface of the base layer, and a plurality of trenches extending in a first direction and extending through the source layer and the second base layer to a depth in the middle of the buffer layer A gate electrode formed through a gate insulating film, a drain electrode provided in the drain layer, and a source electrode provided in the source layer and the second base layer, Along the trench, the first direction A first source layer to be disposed; and a second source layer disposed in a second direction orthogonal to the first direction so as to connect the first source layers to each other in a ladder shape. A base contact layer having an impurity density higher than that of the second base layer is disposed so as to surround the second source layer.

  According to a sixteenth aspect of the present invention, in the semiconductor device according to the fifteenth aspect, an interlayer insulating film is disposed on the gate insulating film and the gate electrode forming the trench. .

  According to a seventeenth aspect of the present invention, in the semiconductor device according to the fifteenth aspect, the source electrode is formed on the surface of the source layer and the second base layer via the interlayer insulating film. It is characterized by that.

  A semiconductor device according to an eighteenth aspect of the present invention is the semiconductor device according to the fifteenth aspect, wherein the source electrode includes the source layer, the second base layer, and the base contact layer through the interlayer insulating film. It is formed on the surface.

  According to a nineteenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: preparing a first conductive type high-resistance semiconductor substrate to be a first base layer; and a second conductive type collector on a back surface of the first base layer. A step of forming a layer, a step of forming a second base layer on the surface of the first base layer, and a base contact layer at a predetermined position on the surface of the second base layer. Forming an emitter layer from the surface of the second base layer in a first direction along the formation position of the base contact layer on the surface of the second base layer and the region where the trench is to be formed After forming a trench groove in the first direction, forming a gate insulating film in the trench groove, forming a gate electrode in the trench groove, the second base layer, and the base Contact layer and Forming an interlayer insulating film on a surface of the emitter layer, patterning the interlayer insulating film so as to cover a trench portion on the gate insulating film and the gate electrode, and a semiconductor through the interlayer insulating film Forming an emitter electrode over the entire surface of the device.

  According to a twentieth aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a first conductive type high-resistance semiconductor substrate to be a first base layer; and a second conductive type collector on a back surface of the first base layer. Forming a layer, forming a buffer layer on the surface of the first base layer, forming a second base layer on the surface of the buffer layer, and a predetermined surface on the surface of the second base layer Forming a base contact layer at a position from the surface of the first base layer, and in a first direction along a region where the base contact layer is formed and a trench formation planned region on the surface of the second base layer. Forming an emitter layer from the surface of the second base layer, forming a trench groove in the first direction and then forming a gate insulating film in the trench groove, and forming a gate electrode in the trench groove Form Then, an interlayer insulating film is formed on the surfaces of the second base layer, the base contact layer, and the emitter layer, and the interlayer insulating film is formed on the gate insulating film and the gate electrode so as to cover the trench portion. And a step of patterning, and a step of forming an emitter electrode on the entire surface of the semiconductor device through the interlayer insulating film.

  According to a twenty-first aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a first conductive type high-resistance semiconductor substrate to be a first base layer; and a first conductive type drain on the back surface of the first base layer. A step of forming a layer, a step of forming a second base layer on the surface of the first base layer, and a base contact layer at a predetermined position on the surface of the second base layer. Forming from the surface, and forming a source layer from the surface of the second base layer in a first direction along the region where the base contact layer is formed on the surface of the second base layer and the region where the trench is to be formed After forming a trench groove in the first direction, forming a gate insulating film in the trench groove, forming a gate electrode in the trench groove, the second base layer, and the base Contact layer and Forming an interlayer insulating film on the surface of the source layer, patterning the interlayer insulating film so as to cover a trench portion on the gate insulating film and the gate electrode, and a semiconductor through the interlayer insulating film And a step of forming a source electrode over the entire surface of the device.

  According to a twenty-second aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a first conductive type high-resistance semiconductor substrate to be a first base layer; and a first conductive type drain on the back surface of the first base layer. Forming a layer, forming a buffer layer on the surface of the first base layer, forming a second base layer on the surface of the buffer layer, and a predetermined surface on the surface of the second base layer Forming a base contact layer at a position from the surface of the first base layer, and in a first direction along a region where the base contact layer is formed and a trench formation planned region on the surface of the second base layer. Forming a source layer from the surface of the second base layer, forming a trench groove in the first direction and then forming a gate insulating film in the trench groove, and forming a gate electrode in the trench groove Craft to form And forming an interlayer insulating film on the surfaces of the second base layer, the base contact layer and the source layer, and patterning the interlayer insulating film so as to cover the trench portion on the gate insulating film and the gate electrode. And a step of forming a source electrode over the entire surface of the semiconductor device through the interlayer insulating film.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which consists of MOSFET and IGBT which improved the breakdown tolerance, and low loss (low on-resistance, low saturation voltage), and its manufacturing method can be provided.

1 is a schematic perspective view of a semiconductor device according to a first embodiment of the present invention. FIG. 6 is a schematic perspective view of a semiconductor device according to a modification of the first embodiment of the present invention. The typical perspective view of the semiconductor device concerning a 2nd embodiment of the present invention. The typical perspective view of the semiconductor device concerning the modification of the 2nd Embodiment of the present invention. 6 is a characteristic example showing the relationship between the normalized on-resistance R _{CE (on) of the} semiconductor device according to the first embodiment of the present invention and the ratio of the n ⁺ emitter region. 6 is a characteristic example showing the relationship between the normalized latch-up current I _L and the ratio of the n ⁺ emitter region of the semiconductor device according to the first embodiment of the present invention. The typical perspective view of the conventional semiconductor device.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiment described below exemplifies an apparatus and a method for embodying the technical idea of the present invention. The technical idea of the present invention is the arrangement of each component as described below. It is not something specific. The technical idea of the present invention can be variously modified within the scope of the claims.

[First embodiment]
(Element structure)
FIG. 1 is a schematic perspective view of a semiconductor device according to the first embodiment of the present invention.

  The schematic configuration of the semiconductor device according to the first embodiment of the present invention is provided in the first base layer 2 and the first base layer 2 having a high resistance and the first conductivity type, as shown in FIG. The second conductivity type collector layer 14, the second conductivity type second base layer 16 formed on the surface of the first base layer 2, and the first conductivity type emitter formed on the surface of the second base layer 16. Layer 13 and a plurality of trenches extending in the first direction and penetrating through the emitter layer 13 and the second base layer 16 to reach the middle depth of the first base layer 2, and are formed via the gate insulating film 6. A gate electrode 8, a collector electrode 20 provided on the collector layer 14, and an emitter electrode 24 provided on the emitter layer 13 and the second base layer 16 are provided.

  The emitter layer 13 includes a first emitter layer 13-1 disposed in the first direction along the trench, and a second orthogonal to the first direction so as to connect the first emitter layers in a ladder shape. The second emitter layer 13-2 is arranged in the direction.

  In the semiconductor device according to the first embodiment of the present invention, the base contact layer 4 having a higher impurity density than the second conductivity type second base layer 16 is disposed so as to surround the second emitter layer 13-2. It is characterized by that.

  The semiconductor device according to the first embodiment of the present invention is characterized in that an interlayer insulating film 10 is disposed on the gate insulating film 6 and the gate electrode 8 forming the trench.

  In the semiconductor device according to the first embodiment of the present invention, the emitter electrode 24 is formed on the surfaces of the emitter layer 13 and the second base layer 16 with the interlayer insulating film 10 interposed therebetween. To do.

  In the semiconductor device according to the first embodiment of the present invention, the emitter electrode 24 is formed on the surface of the emitter layer 13 and the base contact layer 4 with the interlayer insulating film 10 interposed therebetween. To do.

(Production method)
A method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described below with reference to FIG.
(A) First, for example, an n-type silicon substrate having an impurity density of about 10 ¹² to 10 ¹⁵ cm ⁻³ is prepared as the first base layer 2 of high resistance and first conductivity type. Atoms to be p-type impurities such as boron (B) are added from the back surface of the substrate by ion implantation or diffusion process to form a thickness of about 1 μm to 10 μm and an impurity density of about 10 ¹⁸ to 10 ²⁰ cm ⁻³ ; A collector layer 14 of the second conductivity type is formed.
(B) Next, an impurity which is a p-type impurity such as boron (B) is added from the surface of the first base layer 2 by an ion implantation or diffusion process, for example, a thickness of about 1 μm to 5 μm, an impurity density of about The second base layer 16 is formed to a thickness of about 10 ¹⁵ to 10 ¹⁷ cm ⁻³ .
(C) Next, atoms that become p-type impurities such as boron (B) from the surface of the first base layer 2 to a predetermined position on the surface of the second base layer 16 by a lithography process. Are formed by adding impurities by ion implantation or diffusion process. As shown in FIG. 1, the base contact layer 4 is formed to have the same thickness as the second base layer 16 or thicker than the second base layer 16. The impurity density of the base contact layer 4 is higher than the impurity density of the second base layer 16 and is, for example, about 10 ¹⁶ to 10 ²⁰ cm ⁻³ .
(D) Next, the emitter layer 13 is formed in the first direction along the formation position of the base contact layer 4 on the surface of the second base layer 16 and along the trench formation scheduled region by a lithography process. An n-type impurity atom such as phosphorus (P), arsenic (As), or the like is added from the surface of the substrate by an impurity implantation or diffusion process. As shown in FIG. 1, the emitter layer 13 is formed to be sufficiently thinner than the base contact layer 4 and has a thickness of about 0.5 μm to about 2 μm, for example, and the impurity density is about 10 μm, for example. It is about ¹⁸ to 10 ²¹ cm ⁻³ .
(E) Next, as shown in FIG. 1, after forming the trench groove in the first direction by an etching process such as reactive ion etching (RIE), the gate insulating film 6 in the trench groove is heated. It is formed by an oxidation process. The depth of the trench groove reaches the middle depth of the first base layer 2 through the emitter layer 13 and the second base layer 16 and is, for example, about 2 μm to 7 μm. The thickness of the gate insulating film 6 is, for example, about 40 nm to 200 nm.
(F) Next, the trench groove is filled with, for example, polysilicon, and the gate electrode 8 is formed.
(G) Next, an interlayer insulating film 10 is formed on the surfaces of the second base layer 16, the base contact layer 4 and the emitter layer 13, and a trench portion is formed on the gate insulating film 6 and the gate electrode 8 by an etching process. The interlayer insulating film 10 is patterned and disposed so as to cover it.
(H) Next, the emitter electrode 24 is formed of aluminum (Al) or the like over the entire surface of the semiconductor device via the interlayer insulating film 10, and at the same time, the collector electrode 20 is formed over the entire back surface of the semiconductor device with aluminum. (Al) or the like.

(Example of characteristics)
FIG. 5 is a characteristic example showing the relationship between the normalized on-resistance R _{CE (on)} of the IGBT and the ratio of the n ⁺ emitter region in the semiconductor device according to the first embodiment of the present invention.

The ratio of the n ⁺ emitter region is the total area of the second base layer 16 made of the p region, the base contact layer 4 made of the p ⁺ region, and the emitter layer 13 made of the n ⁺ layer on the surface of the second base layer 16. Is defined by a ratio occupied by the emitter layer 13 with respect to.

The normalized on-resistance R _{CE (on)} is a value obtained by standardizing the on-resistance R _{CE (on)} in the ON state between the collector and the emitter in the IGBT.

As apparent from FIG. 5, the semiconductor device according to the first embodiment of the present invention constitutes an IGBT, and the normalized on-resistance R _{CE (on)} in the ON state between the collector and the emitter is n ⁺ It varies depending on the ratio of the emitter region and has a value of 1 to 2.5, especially at about 10% to about 70%. The normalized on-resistance R _{CE (on)} in the ON state between the collector and the emitter should be a desirable value of about 1 to 1.2 when the ratio of the n ⁺ emitter region is about 10% to about 40%. I understand.

FIG. 6 shows a characteristic example representing the relationship between the normalized latch-up current I _L of the IGBT and the ratio of the n ⁺ emitter region in the semiconductor device according to the first embodiment of the present invention.

The normalized latch-up current I _L, in IGBT, in which the latch-up current that can be expressed by normalizing. with increasing ratio of n ⁺ emitter region, since the latch-up can be a current value decreases, normalized latch-up current I _L, an increase both in the ratio of n ⁺ emitter region, decreases.

As is apparent from FIG. 6, in the semiconductor device according to the first embodiment of the present invention, the normalized latch-up current I _L increases as the ratio of the n ⁺ emitter region changes from about 10% to about 70%. , Varying from about 2.7 to about 1.0.

As is apparent from FIG. 6, in the semiconductor device according to the first embodiment of the present invention, the normalized latch-up current I _L has an n ⁺ emitter region ratio of about 10% to about 40%. It can be seen that a desirable value of 2.5 or more is obtained.

  Therefore, in the semiconductor device according to the first embodiment of the present invention, the area ratio of the emitter layer formed on the surface of the second base layer is about 10% to about 70%, Preferably, it is about 10% or more and about 40% or less.

In the semiconductor device according to the first embodiment of the present invention, in the IGBT having a trench type stripe cell as a basic structure, the first emitter layer 13-1 composed of the n ⁺ region is formed as a trench extending in the first direction. Arrange along. Furthermore, in order to widen the contact to the first emitter layer 13-1 made of n ⁺ regions, the second emitter layer 13-2 made of a first emitter layer 13-1 between the n ⁺ region formed by connecting the ladder-like , And so as to extend in a second direction orthogonal to the first direction.

Furthermore, in the semiconductor device according to the first embodiment of the present invention, the base contact layer 4 made of the p ⁺ region is disposed so as to surround the second emitter layer 13-2 made of the n ⁺ region. As a result, in the semiconductor device according to the first embodiment of the present invention, the planar pattern of the emitter layer 13 including the first emitter layer 13-1 and the second emitter layer 13-2 and the base contact layer 4 is Become a ladder.

In the semiconductor device according to the first embodiment of the present invention, by disposing the base contact layer 4 made of the p ⁺ region so as to wrap around the second emitter layer 13-2 made of the n ⁺ region, The base resistance of the n ⁺ (13-2) p ⁺ (4) n ⁻ (2) parasitic bipolar transistor can be reduced. As a result, it is possible to increase the latching up tolerance in the IGBT operation. Therefore, the dv / dt resistance of the IGBT can be increased, and the breakdown resistance can be improved.

Further, in the semiconductor device according to the first embodiment of the present invention, the base contact layer 4 made of the p ⁺ region is locally disposed on the surface of the second base layer 16 so that the p ⁺ channel portion is formed. The occupied area can be minimized, and a low on-resistance can be achieved at the same time.

Further, in the semiconductor device according to the first embodiment of the present invention, the switching speed of the IGBT is higher than that of the emitter layer 13 made of n ⁺ region, and is the first made of the base contact layer 4 made of p ⁺ and the p region. By setting the area occupied by the two base layers 16 large, holes are easily removed when the base layer 16 is turned off, and the speed can be increased.

  Further, in the semiconductor device according to the first embodiment of the present invention, the first emitter layer 13-1 and the second emitter layer 2 in the first direction along the trench and the second direction orthogonal to the first direction. The repetition of the pattern composed of the emitter layer 13-2, the base contact layer 4 and the second base layer 16 can be set to an arbitrary value according to the target breakdown resistance characteristics and on-resistance characteristics.

Further, in the semiconductor device according to the first embodiment of the present invention, the second base layer 16 has a larger area than the occupied area of the first emitter layer 13-1 and the second emitter layer 13-2 made of the n ⁺ region. Lower on-resistance can be promoted by setting the occupation area wider.

(Modification)
FIG. 2 is a schematic perspective view of a semiconductor device according to a modification of the first embodiment of the present invention. As shown in FIG. 2, the semiconductor device according to the modification of the first embodiment of the present invention has a first base layer 2 having a high resistance and a first conductivity type, and a first base layer 2 provided on the first base layer 2. A two-conductivity type collector layer 14, a first conductivity type buffer layer 18 formed on the surface of the first base layer 2 and having a higher impurity density than the first base layer 2, and formed on the surface of the buffer layer 18. The second base layer 16 of the second conductivity type, the emitter layer 13 of the first conductivity type formed on the surface of the second base layer 16, and the emitter layer 13 and the second base layer extending in the first direction. A gate electrode 8 formed through a gate insulating film 6 in a plurality of trenches penetrating through the layer 16 and reaching the middle depth of the buffer layer 18; a collector electrode 20 provided on the collector layer 14; an emitter layer 13; Emitter electricity provided in the second base layer 16 Comprises a (not shown) and.

  The emitter layer 13 is orthogonal to the first direction so as to connect the first emitter layer 13-1 disposed in the first direction along the trench and the first emitter layer 13-1 in a ladder shape. The second emitter layer 13-2 is arranged in the second direction.

  In the semiconductor device according to the modification of the first embodiment of the present invention, the second conductivity type second base layer 16 also includes a base contact layer having a high impurity density so as to enclose the second emitter layer 13-2. It is arranged.

  The semiconductor device according to the modification of the first embodiment of the present invention is characterized in that an interlayer insulating film 10 is disposed on the gate insulating film 6 and the gate electrode 8 forming the trench.

  In the semiconductor device according to the modification of the first embodiment of the present invention, the emitter electrode is formed on the surfaces of the emitter layer 13 and the second base layer 16 via the interlayer insulating film 10. Features.

  In the semiconductor device according to the modification of the first embodiment of the present invention, the emitter electrode is disposed on the surfaces of the emitter layer 13, the second base layer 16, and the base contact layer 4 via the interlayer insulating film 10. It is formed.

(Production method)
A method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention will be described below with reference to FIG.
(A) First, for example, an n-type silicon substrate having an impurity density of about 10 ¹² to 10 ¹⁵ cm ⁻³ is prepared as the first base layer 2 of high resistance and first conductivity type. Atoms to be p-type impurities such as boron (B) are added from the back surface of the substrate by ion implantation or diffusion process to form a thickness of about 1 μm to 10 μm and an impurity density of about 10 ¹⁸ to 10 ²⁰ cm ⁻³ ; A collector layer 14 of the second conductivity type is formed.
(B) Next, an atom that becomes an n-type impurity such as phosphorus (P) is doped from the surface of the first base layer 2 by an ion implantation or diffusion process. The buffer layer 18 is formed to a thickness of about 10 ¹⁵ to 10 ¹⁷ cm ⁻³ .
(C) Next, an atom that becomes a p-type impurity such as boron (B) is added from the surface of the buffer layer 18 by ion implantation or diffusion process, for example, a thickness of about 1 μm to 5 μm, and an impurity density of about 10 ^15. formed of about to 10 ¹⁷ cm ^-3, forming the second base layer 16.
(D) Next, atoms that become p-type impurities such as boron (B) from the surface of the first base layer 2 are formed at predetermined positions on the surface of the second base layer 16 by a lithography process. Are formed by adding impurities by ion implantation or diffusion process. As shown in FIG. 2, the base contact layer 4 is formed to have the same thickness as the second base layer 16 or thicker than the second base layer 16. The impurity density of the base contact layer 4 is higher than the impurity density of the second base layer 16 and is, for example, about 10 ¹⁶ to 10 ²⁰ cm ⁻³ .
(E) Next, the emitter layer 13 is formed in the first direction along the formation position of the base contact layer 4 on the surface of the second base layer 16 and along the trench formation scheduled region by a lithography process. An n-type impurity atom such as phosphorus (P), arsenic (As), or the like is added from the surface of the substrate by an impurity implantation or diffusion process. As shown in FIG. 2, the emitter layer 13 is formed to be sufficiently thinner than the base contact layer 4, for example, about 0.5 μm to about 2 μm, and the impurity density is about 10 μm, for example. It is about ¹⁸ to 10 ²¹ cm ⁻³ .
(F) Next, as shown in FIG. 2, after forming the trench groove in the first direction by an etching process such as RIE, the gate insulating film 6 in the trench groove is formed by a thermal oxidation process. The depth of the trench groove reaches the middle depth of the first base layer 2 through the emitter layer 13 and the second base layer 16 and is, for example, about 2 μm to 7 μm. The thickness of the gate insulating film 6 is, for example, about 40 nm to 200 nm.
(G) Next, the trench groove is filled with, for example, polysilicon, and the gate electrode 8 is formed.
(H) Next, an interlayer insulating film 10 is formed on the surfaces of the second base layer 16, the base contact layer 4 and the emitter layer 13, and a trench portion is formed on the gate insulating film 6 and the gate electrode 8 by an etching process. The interlayer insulating film 10 is patterned and disposed so as to cover it.
(I) Next, the emitter electrode 24 is formed of aluminum (Al) or the like over the entire surface of the semiconductor device via the interlayer insulating film 10, and at the same time, the collector electrode 20 is formed over the entire surface of the back surface of the semiconductor device with aluminum. (Al) or the like.

(Example of characteristics)
Also in the semiconductor device according to the variant example of the first embodiment of the present invention, the characteristic example showing the relationship between the normalized on-resistance R _{CE (on) of the} IGBT and the ratio of the n ⁺ emitter region is the same as in FIG. Can be expressed as Further, a characteristic example showing the relationship between the normalized latch-up current I _L and the ratio of the n ⁺ emitter region can be expressed in the same manner as in FIG.

  Therefore, in the semiconductor device according to the modification of the first embodiment of the present invention, the area ratio of the emitter layer formed on the surface of the second base layer is about 10% or more and about 70% or less. Preferably, it is about 10% or more and about 40% or less.

Further, in the semiconductor device according to the modification of the first embodiment of the present invention, the buffer layer 18 formed of the n region is provided between the first base layer 2 and the second base layer 16 and between the first base layer 2 and the base. Since the n (13) p ⁺ (4) p (16) n (18) n ⁻ (2) p ⁺ (14) structure is formed by arranging between the contact layers 4, the emitter layer 13 and the collector are formed. Punching through between the layers 14 is suppressed, and as a result, it is possible to further increase the latching up tolerance in the IGBT operation. Therefore, the dv / dt resistance of the IGBT can be increased, and the breakdown resistance can be further improved.

  According to the semiconductor device according to the first embodiment of the present invention and the modification thereof, there is provided a semiconductor device made of IGBT having both improved breakdown resistance and low loss (low on-resistance, low saturation voltage) and a method for manufacturing the same. Can be provided. Furthermore, it is possible to provide a semiconductor device made of an IGBT and a method for manufacturing the same, which are compatible with an increase in switching speed.

[Second Embodiment]
(Element structure)
FIG. 3 is a schematic perspective view of a semiconductor device according to the second embodiment of the present invention.

  The schematic configuration of the semiconductor device according to the second embodiment of the present invention is provided on the first base layer 2 and the first base layer 2 of high resistance and first conductivity type, as shown in FIG. The first conductivity type drain layer 15, the second conductivity type second base layer 16 formed on the surface of the first base layer 2, and the first conductivity type source formed on the surface of the second base layer 16. Layer 12 and a plurality of trenches extending in the first direction and penetrating through source layer 12 and second base layer 16 to reach the middle depth of first base layer 2 are formed via gate insulating film 6 A gate electrode 8, a drain electrode 21 provided on the drain layer 15, and a source electrode 25 provided on the source layer 12 and the second base layer 16 are provided.

  The source layer 12 is connected to the first source layer 12-1 arranged in the first direction along the trench and the first source layers 12-1 arranged in the first direction in a ladder shape. And a second source layer 12-2 arranged in a second direction orthogonal to the first direction.

  The base contact layer 4 having a higher impurity density than the second conductivity type second base layer 16 is arranged so as to surround the second source layer 12-2.

  The semiconductor device according to the second embodiment of the present invention is characterized in that an interlayer insulating film 10 is disposed on the gate insulating film 6 and the gate electrode 8 forming the trench.

  The source electrode 25 is formed on the surface of the source layer 12 and the second base layer 16 with the interlayer insulating film 10 interposed therebetween.

  In the semiconductor device according to the second embodiment of the present invention, the source electrode 25 is formed on the surface of the source layer 12, the second base layer 16, and the base contact layer 4 via the interlayer insulating film 10. It is characterized by that.

(Production method)
A method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIG.
(A) First, for example, an n-type silicon substrate having an impurity density of about 10 ¹² to 10 ¹⁵ cm ⁻³ is prepared as the first base layer 2 of high resistance and first conductivity type. An n-type impurity atom such as phosphorus (P) or arsenic (As) is added from the back surface of the substrate by an ion implantation or diffusion process to have a thickness of about 1 μm to 10 μm and an impurity density of about 10 ¹⁸ to 10 ²¹ cm ^−3. The drain layer 15 of the first conductivity type is formed.
(B) Next, an impurity which is a p-type impurity such as boron (B) is added from the surface of the first base layer 2 by an ion implantation or diffusion process, for example, a thickness of about 1 μm to 5 μm, an impurity density of about The second base layer 16 is formed to a thickness of about 10 ¹⁵ to 10 ¹⁷ cm ⁻³ .
(C) Next, atoms that become p-type impurities such as boron (B) from the surface of the first base layer 2 to a predetermined position on the surface of the second base layer 16 by a lithography process. Are formed by adding impurities by ion implantation or diffusion process. As shown in FIG. 3, the base contact layer 4 is formed to have the same thickness as the second base layer 16 or thicker than the second base layer 16. The impurity density of the base contact layer 4 is higher than the impurity density of the second base layer 16 and is, for example, about 10 ¹⁶ to 10 ²⁰ cm ⁻³ .
(D) Next, the source layer 12 is moved to the second base layer 16 in the first direction along the formation position of the base contact layer 4 on the surface of the second base layer 16 and along the planned trench formation region by a lithography process. An n-type impurity atom such as phosphorus (P), arsenic (As), or the like is added from the surface of the substrate by an impurity implantation or diffusion process. As shown in FIG. 3, the thickness of the source layer 12 is sufficiently thinner than the thickness of the base contact layer 4, and is about 0.5 μm to about 2 μm, for example, and the impurity density is about 10 μm, for example. It is about ¹⁸ to 10 ²¹ cm ⁻³ .
(E) Next, as shown in FIG. 3, after forming the trench groove in the first direction by an etching process such as RIE, the gate insulating film 6 in the trench groove is formed by a thermal oxidation process. The depth of the trench groove reaches the middle depth of the first base layer 2 through the source layer 12 and the second base layer 16 and is, for example, about 2 μm to 7 μm. The thickness of the gate insulating film 6 is, for example, about 40 nm to 200 nm.
(F) Next, the trench groove is filled with, for example, polysilicon, and the gate electrode 8 is formed.
(G) Next, an interlayer insulating film 10 is formed on the surfaces of the second base layer 16, the base contact layer 4 and the source layer 12, and trench portions are formed on the gate insulating film 6 and the gate electrode 8 by an etching process. The interlayer insulating film 10 is patterned and disposed so as to cover it.
(H) Next, the source electrode 25 is formed of aluminum (Al) or the like over the entire surface of the semiconductor device via the interlayer insulating film 10, and at the same time, the drain electrode 21 is formed over the entire back surface of the semiconductor device with aluminum. (Al) or the like.

(Example of characteristics)
In the semiconductor device according to the second embodiment of the present invention, a characteristic example representing the relationship between the normalized on-resistance R _{DS (on)} of the MOSFET and the ratio of the n ⁺ source region can be expressed in the same manner as in FIG. .

The ratio of the n ⁺ source region is the total area of the second base layer 16 made of the p region, the base contact layer 4 made of the p ⁺ region, and the source layer 12 made of the n ⁺ layer on the surface of the second base layer 16. Defined by the ratio of the source layer 12 to

The normalized on-resistance R _{DS (on)} is a value expressed by standardizing the on-resistance R _{DS (on)} in the ON state between the source and the drain in the MOSFET.

The semiconductor device according to the second embodiment of the present invention constitutes a MOSFET, and the normalized on-resistance R _{DS (on)} in the ON state between the source and the drain varies depending on the ratio of the n ⁺ source region. In particular, at about 10% to about 70%, it has a value of 1 to 2.5. The normalized on-resistance R _{DS (on)} in the ON state between the source and the drain can be a desirable value of about 1 to 1.2, particularly when the ratio of the n ⁺ source region is about 10% to about 40%.

  Therefore, in the semiconductor device according to the second embodiment of the present invention, the area ratio of the source layer formed on the surface of the second base layer is about 10% to about 70%, Preferably, it is about 10% or more and about 40% or less.

In the semiconductor device according to the second embodiment of the present invention, in a MOSFET having a trench-type stripe cell as a basic structure, the first source layer 12-1 composed of an n ⁺ region is formed into a trench extending in the first direction. Arrange along. Furthermore, in order to widen the contact to the first source layer 12-1 made of n ⁺ regions, the second source layer 12-2 made to each other first source layer 12-1 ladder shape the connected n ⁺ region , And so as to extend in a second direction orthogonal to the first direction.

Further, in the semiconductor device according to the second embodiment of the present invention, the base contact layer 4 made of the p ⁺ region is disposed so as to surround the second source layer 12-2 made of the n ⁺ region. As a result, in the semiconductor device according to the second embodiment of the present invention, the planar pattern of the source layer 12 including the first source layer 12-1 and the second source layer 12-2 and the base contact layer 4 is Become a ladder.

In the semiconductor device according to the second embodiment of the present invention, the base contact layer 4 made of the p ⁺ region is disposed so as to wrap around the second source layer 12-2 made of the n ⁺ region, The base resistance of the n ⁺ (12-2) p ⁺ (4) n ⁻ (2) parasitic bipolar transistor can be reduced. As a result, the dv / dt resistance of the MOSFET can be increased, and the breakdown resistance can be improved.

Further, in the semiconductor device according to the second embodiment of the present invention, the base contact layer 4 composed of the p ⁺ region is locally disposed on the surface of the second base layer 16 so that the p ⁺ channel portion is formed. The occupied area can be minimized, and a low on-resistance can be achieved at the same time.

Further, in the semiconductor device according to the second embodiment of the present invention, the switching speed of the MOSFET is higher than that of the source layer 12 consisting of the n ⁺ region, and the base contact layer 4 consisting of p ⁺ and the first region consisting of the p region. By setting the area occupied by the two base layers 16 large, holes are easily removed when the base layer 16 is turned off, and the speed can be increased.

  In the semiconductor device according to the second embodiment of the present invention, the first source layer 12-1 and the second source layer 12-1 are arranged in the first direction along the trench and the second direction orthogonal to the first direction. The repetition of the pattern composed of the source layer 12-2, the base contact layer 4 and the second base layer 16 can be set to an arbitrary value according to the target breakdown resistance characteristics and on-resistance characteristics.

In the semiconductor device according to the second embodiment of the present invention, the second base layer 16 occupies more than the area occupied by the first source layer 12-1 and the second source layer 12-2 made of n ⁺ regions. Lowering the on-resistance can be promoted by setting the area wider.

(Modification)
FIG. 4 is a schematic perspective view of a semiconductor device according to a modification of the second embodiment of the present invention.

  As shown in FIG. 4, the semiconductor device according to the modification of the second embodiment of the present invention has a first base layer 2 having a high resistance and a first conductivity type, and a first base layer 2 provided on the first base layer 2. A first conductivity type drain layer 15, a first conductivity type formed on the surface of the first base layer 2, and having a higher impurity density than the first base layer 2; The formed second base layer 16 of the second conductivity type, the first conductivity type source layer 12 formed on the surface of the second base layer 16, and extending in the first direction, the source layer 12 and the second layer A gate electrode 8 formed through a gate insulating film 6 in a plurality of trenches that reach the intermediate depth of the buffer layer 18 through the base layer 16, a drain electrode 21 provided in the drain layer 15, and a source layer 12 And a source electrode provided on the second base layer 16 ( It provided with the shown omitted) and.

  The source layer 12 is orthogonal to the first direction so as to connect the first source layer 12-1 disposed in the first direction along the trench and the first source layer 12-1 in a ladder shape. The second source layer 12-2 is arranged in the second direction.

  The semiconductor device according to the modification of the second embodiment of the present invention includes the base contact layer 4 having a higher impurity density than the second conductivity type second base layer 16 and the second source layer 12-2. It is characterized by being arranged in such a way.

  Further, the semiconductor device according to the modification of the second embodiment of the present invention is characterized in that an interlayer insulating film 10 is disposed on the gate insulating film 6 and the gate electrode 8 forming the trench.

  Further, in the semiconductor device according to the modification of the second embodiment of the present invention, the source electrode is formed on the surface of the source layer 12 and the second base layer 16 via the interlayer insulating film 10. Features.

  Further, in the semiconductor device according to the modification of the second embodiment of the present invention, the source electrode is provided on the surface of the source layer 12, the second base layer 16, and the base contact layer 4 via the interlayer insulating film 10. It is formed.

(Production method)
A method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention will be described below with reference to FIG.
(A) First, for example, an n-type silicon substrate having an impurity density of about 10 ¹² to 10 ¹⁵ cm ⁻³ is prepared as the first base layer 2 of high resistance and first conductivity type. An n-type impurity atom such as phosphorus (P) or arsenic (As) is added from the back surface of the substrate by an ion implantation or diffusion process to have a thickness of about 1 μm to 10 μm and an impurity density of about 10 ¹⁸ to 10 ²¹ cm ^−3. The drain layer 15 of the first conductivity type is formed.
(B) Next, an atom that becomes an n-type impurity such as phosphorus (P) is doped from the surface of the first base layer 2 by an ion implantation or diffusion process. The buffer layer 18 is formed to a thickness of about 10 ¹⁵ to 10 ¹⁷ cm ⁻³ .
(C) Next, an atom that becomes a p-type impurity such as boron (B) is added from the surface of the buffer layer 18 by ion implantation or diffusion process, for example, a thickness of about 1 μm to 5 μm, and an impurity density of about 10 ^15. formed of about to 10 ¹⁷ cm ^-3, forming the second base layer 16.
(D) Next, atoms that become p-type impurities such as boron (B) from the surface of the first base layer 2 are formed at predetermined positions on the surface of the second base layer 16 by a lithography process. Are formed by adding impurities by ion implantation or diffusion process. As shown in FIG. 4, the base contact layer 4 is formed to have the same thickness as the second base layer 16 or thicker than the second base layer 16. The impurity density of the base contact layer 4 is higher than the impurity density of the second base layer 16 and is, for example, about 10 ¹⁶ to 10 ²⁰ cm ⁻³ .
(E) Next, the source layer 12 is moved to the second base layer 16 in a first direction along the formation position of the base contact layer 4 on the surface of the second base layer 16 and along the planned trench formation region by a lithography process. An n-type impurity atom such as phosphorus (P), arsenic (As), or the like is added from the surface of the substrate by an impurity implantation or diffusion process. As shown in FIG. 4, the source layer 12 is formed to be sufficiently thinner than the base contact layer 4. For example, the source layer 12 has a thickness of about 0.5 μm to about 2 μm. The impurity density is about 10 μm, for example. It is about ¹⁸ to 10 ²¹ cm ⁻³ .
(F) Next, as shown in FIG. 4, after the trench groove is formed in the first direction by an etching process such as RIE, the gate insulating film 6 in the trench groove is formed by a thermal oxidation process. The depth of the trench groove reaches the middle depth of the first base layer 2 through the source layer 12 and the second base layer 16 and is, for example, about 2 μm to 7 μm. The thickness of the gate insulating film 6 is, for example, about 40 nm to 200 nm.
(G) Next, the trench groove is filled with, for example, polysilicon, and the gate electrode 8 is formed.
(H) Next, an interlayer insulating film 10 is formed on the surfaces of the second base layer 16, the base contact layer 4 and the source layer 12, and trench portions are formed on the gate insulating film 6 and the gate electrode 8 by an etching process. The interlayer insulating film 10 is patterned and disposed so as to cover it.
(I) Next, the source electrode 25 is formed of aluminum (Al) or the like over the entire surface of the semiconductor device through the interlayer insulating film 10, and at the same time, the drain electrode 21 is formed over the entire surface of the back surface of the semiconductor device with aluminum. (Al) or the like.

(Example of characteristics)
Also in the semiconductor device according to the variant example of the second embodiment of the present invention, the characteristic example representing the relationship between the normalized on-resistance R _{DS (on) of the} MOSFET and the ratio of the n ⁺ source region is the same as in FIG. Can be expressed as

  Therefore, in the semiconductor device according to the modification of the second embodiment of the present invention, the area ratio of the source layer 12 formed on the surface of the second base layer 16 is about 10% or more and about 70% or less. Preferably, it is about 10% or more and about 40% or less.

In the semiconductor device according to the modification of the second embodiment of the present invention, the buffer layer 18 formed of the n region is provided between the first base layer 2 and the second base layer 16 and between the first base layer 2 and the base. Since the n (12) p ⁺ (4) p (16) n (18) n ⁻ (2) p ⁺ (15) structure is formed by being disposed between the contact layers 4, the source layer 12 and the drain are formed. Punching through between the layers 15 is suppressed, and as a result, the dv / dt resistance of the MOSFET can be further increased, and the breakdown resistance of the MOSFET can be further improved.

  According to the semiconductor device according to the second embodiment of the present invention and the modification thereof, there is provided a semiconductor device composed of a MOSFET that has both improved breakdown resistance and low loss (low on-resistance, low saturation voltage) and a method for manufacturing the same. Can be provided.

[Other embodiments]
As described above, the present invention has been described according to the first to second embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the semiconductor devices according to the first and second embodiments of the present invention, description of structural devices for increasing the breakdown voltage is omitted, but a guard ring structure and a field plate structure can be applied. It is clear that there is.

  In the method of manufacturing the semiconductor device according to the first or second embodiment of the present invention, the method of sequentially applying the diffusion process or the ion implantation process has been described. However, a wafer bonding process for bonding a plurality of wafers, etc. It is also possible to apply as appropriate.

  As described above, the present invention naturally includes various embodiments that are not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

  A semiconductor device according to an embodiment of the present invention includes various AC-AC, AC-DC, DC-DC, DC-AC power converters, etc., from low power to high power, such as a DC-DC converter and a PWM inverter. It is applicable to.

DESCRIPTION OF SYMBOLS 2 ... 1st base layer 4 ... Base contact layer 6 ... Gate insulating film 8 ... Gate electrode 10 ... Interlayer insulating film 12 ... Source layer 12-1 ... 1st source layer 12-2 ... 2nd source layer 13 ... Emitter layer 13 -1 ... first emitter layer 13-2 ... second emitter layer 14 ... collector layer 15 ... drain layer 16 ... second base layer 18 ... buffer layer 20 ... collector electrode 21 ... drain electrode 24 ... emitter electrode 25 ... source electrode

The present invention relates to a semiconductor device , and more particularly, in a metal-oxide-semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT) with improved breakdown resistance. The present invention relates to a semiconductor device characterized by a structure that achieves both low loss (low on-resistance and low saturation voltage), and also IGBTs that are compatible with high switching speed.

An object of the present invention is to achieve both improvement in breakdown resistance and low loss (low on-resistance, low saturation voltage) in a semiconductor device composed of MOSFET and IGBT, and further increase the switching speed for IGBT. Another object of the present invention is to provide a semiconductor device having a feature in the structure.

According to one aspect of the present invention, a first base layer of a first conductivity type high-resistance, and a second base layer of a second conductivity type formed on a surface of the first base layer, said second base layer A first semiconductor layer formed on the surface of the first semiconductor layer and a plurality of trenches extending in a first direction and penetrating through the first semiconductor layer and the second base layer and reaching a depth in the middle of the first base layer. a gate electrode formed through a gate insulating film, and a first main electrode provided on the first semiconductor layer and the second base layer, the first semiconductor layer along the trench, the A first region disposed in a direction of 1 and a second region disposed in a second direction orthogonal to the first direction so as to connect the first regions in a ladder shape, the second conductive than the second base layer of mold base contact layer having a high impurity concentration, said first The base layer is spaced apart in the first direction, and the second region is spaced apart in the first direction by alternately interposing the base contact layer and the second base layer. A semiconductor device is provided in which the base contact layer is continuously arranged over the entire lower portion of the second region.

ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which consists of MOSFET and IGBT which improved the destruction tolerance and low loss (low on-resistance, low saturation voltage) can be provided.

Claims (22)

A first base layer of high resistance and first conductivity type;
A collector layer of a second conductivity type provided on the first base layer;
A second base layer of a second conductivity type formed on the surface of the first base layer;
A first conductivity type emitter layer formed on a surface of the second base layer;
A gate electrode formed through a gate insulating film in a plurality of trenches extending in a first direction and penetrating through the emitter layer and the second base layer and reaching a middle depth of the first base layer;
A collector electrode provided in the collector layer;
An emitter electrode provided on the emitter layer and the second base layer,
The emitter layer includes a first emitter layer disposed in the first direction along the trench, and a second direction orthogonal to the first direction so as to connect the first emitter layers in a ladder shape. And a second emitter layer disposed on
A semiconductor device, wherein a base contact layer having a higher impurity density than the second conductivity type second base layer is disposed so as to surround the second emitter layer.   The semiconductor device according to claim 1, wherein an interlayer insulating film is disposed on the gate insulating film and the gate electrode forming the trench.   The semiconductor device according to claim 2, wherein the emitter electrode is formed on a surface of the emitter layer and the second base layer via the interlayer insulating film.   The semiconductor device according to claim 2, wherein the emitter electrode is formed on surfaces of the emitter layer, the second base layer, and the base contact layer via the interlayer insulating film.   5. The semiconductor device according to claim 1, wherein an area ratio of the emitter layer formed on the surface of the second base layer is not less than 10% and not more than 70%. A first base layer of high resistance and first conductivity type;
A collector layer of a second conductivity type provided on the first base layer;
A buffer layer of a first conductivity type formed on the surface of the first base layer and having a higher impurity density than the first base layer;
A second base layer of a second conductivity type formed on the surface of the buffer layer;
A first conductivity type emitter layer formed on a surface of the second base layer;
A gate electrode formed through a gate insulating film in a plurality of trenches extending in a first direction and penetrating through the emitter layer and the second base layer and reaching a middle depth of the buffer layer;
A collector electrode provided in the collector layer;
An emitter electrode provided on the emitter layer and the second base layer,
The emitter layer includes a first emitter layer disposed in the first direction along the trench, and a second direction orthogonal to the first direction so as to connect the first emitter layers in a ladder shape. And a second emitter layer disposed on
A semiconductor device, wherein a base contact layer having a higher impurity density than the second conductivity type second base layer is disposed so as to surround the second emitter layer.   The semiconductor device according to claim 6, wherein an interlayer insulating film is disposed on the gate insulating film and the gate electrode forming the trench.   The semiconductor device according to claim 6, wherein the emitter electrode is formed on a surface of the emitter layer and the second base layer via the interlayer insulating film.   The semiconductor device according to claim 6, wherein the emitter electrode is formed on a surface of the emitter layer, the second base layer, and the base contact layer via the interlayer insulating film.   10. The semiconductor device according to claim 6, wherein an area ratio of the emitter layer formed on the surface of the second base layer is not less than 10% and not more than 70%. A first base layer of high resistance and first conductivity type;
A drain layer of a first conductivity type provided in the first base layer;
A second base layer of a second conductivity type formed on the surface of the first base layer;
A source layer of a first conductivity type formed on the surface of the second base layer;
A gate electrode formed through a gate insulating film in a plurality of trenches extending in a first direction and penetrating through the source layer and the second base layer to reach a middle depth of the first base layer;
A drain electrode provided in the drain layer;
A source electrode provided on the source layer and the second base layer,
The source layer includes a first source layer disposed in a first direction along the trench, and a first source layer connected in a ladder shape to the first source layers disposed in the first direction. A second source layer disposed in a second direction orthogonal to the direction,
A semiconductor device, wherein a base contact layer having an impurity density higher than that of the second conductivity type second base layer is disposed so as to surround the second source layer.   The semiconductor device according to claim 11, wherein an interlayer insulating film is disposed on the gate insulating film and the gate electrode forming the trench.   The semiconductor device according to claim 11, wherein the source electrode is formed on a surface of the source layer and the second base layer via the interlayer insulating film.   The semiconductor device according to claim 11, wherein the source electrode is formed on a surface of the source layer, the second base layer, and the base contact layer via the interlayer insulating film. A first base layer of high resistance and first conductivity type;
A drain layer of a first conductivity type provided in the first base layer;
A buffer layer of a first conductivity type formed on the surface of the first base layer and having a higher impurity density than the first base layer;
A second base layer of a second conductivity type formed on the surface of the buffer layer;
A source layer of a first conductivity type formed on the surface of the second base layer;
A gate electrode formed through a gate insulating film in a plurality of trenches extending in a first direction and penetrating through the source layer and the second base layer and reaching a middle depth of the buffer layer;
A drain electrode provided in the drain layer;
A source electrode provided on the source layer and the second base layer,
The source layer has a first source layer disposed in the first direction along the trench, and a second direction orthogonal to the first direction so as to connect the first source layers in a ladder shape. And a second source layer disposed on
A semiconductor device, wherein a base contact layer having an impurity density higher than that of the second conductivity type second base layer is disposed so as to surround the second source layer.   The semiconductor device according to claim 15, wherein an interlayer insulating film is disposed on the gate insulating film and the gate electrode forming the trench.   The semiconductor device according to claim 15, wherein the source electrode is formed on a surface of the source layer and the second base layer via the interlayer insulating film.   The semiconductor device according to claim 15, wherein the source electrode is formed on a surface of the source layer, the second base layer, and the base contact layer via the interlayer insulating film. Preparing a first conductive type high-resistance semiconductor substrate to be a first base layer;
Forming a second conductivity type collector layer on the back surface of the first base layer;
Forming a second base layer on a surface of the first base layer;
Forming a base contact layer from a surface of the first base layer at a predetermined position on the surface of the second base layer;
Forming an emitter layer from the surface of the second base layer in a first direction along a region where the base contact layer is formed on the surface of the second base layer and along a region where a trench is to be formed;
Forming a gate insulating film in the trench groove after forming the trench groove in the first direction;
Forming a gate electrode in the trench groove;
Forming an interlayer insulating film on the surfaces of the second base layer, the base contact layer, and the emitter layer, and patterning the interlayer insulating film so as to cover a trench portion on the gate insulating film and the gate electrode; When,
And a step of forming an emitter electrode over the entire surface of the semiconductor device through the interlayer insulating film. Preparing a first conductive type high-resistance semiconductor substrate to be a first base layer;
Forming a second conductivity type collector layer on the back surface of the first base layer;
Forming a buffer layer on a surface of the first base layer;
Forming a second base layer on the surface of the buffer layer;
Forming a base contact layer from a surface of the first base layer at a predetermined position on the surface of the second base layer;
Forming an emitter layer from the surface of the second base layer in a first direction along a region where the base contact layer is formed on the surface of the second base layer and along a region where a trench is to be formed;
Forming a gate insulating film in the trench groove after forming the trench groove in the first direction;
Forming a gate electrode in the trench groove;
Forming an interlayer insulating film on the surfaces of the second base layer, the base contact layer, and the emitter layer, and patterning the interlayer insulating film so as to cover a trench portion on the gate insulating film and the gate electrode; When,
And a step of forming an emitter electrode over the entire surface of the semiconductor device through the interlayer insulating film. Preparing a first conductive type high-resistance semiconductor substrate to be a first base layer;
Forming a drain layer of a first conductivity type on the back surface of the first base layer;
Forming a second base layer on a surface of the first base layer;
Forming a base contact layer from a surface of the first base layer at a predetermined position on the surface of the second base layer;
Forming a source layer from the surface of the second base layer in a first direction along the formation position of the base contact layer on the surface of the second base layer and a trench formation scheduled region;
Forming a gate insulating film in the trench groove after forming the trench groove in the first direction;
Forming a gate electrode in the trench groove;
Forming an interlayer insulating film on the surfaces of the second base layer, the base contact layer, and the source layer, and patterning the interlayer insulating film so as to cover a trench portion on the gate insulating film and the gate electrode; When,
And a step of forming a source electrode over the entire surface of the semiconductor device with the interlayer insulating film interposed therebetween. Preparing a first conductive type high-resistance semiconductor substrate to be a first base layer;
Forming a drain layer of a first conductivity type on the back surface of the first base layer;
Forming a buffer layer on a surface of the first base layer;
Forming a second base layer on the surface of the buffer layer;
Forming a base contact layer from a surface of the first base layer at a predetermined position on the surface of the second base layer;
Forming a source layer from the surface of the second base layer in a first direction along the formation position of the base contact layer on the surface of the second base layer and a trench formation scheduled region;
Forming a gate insulating film in the trench groove after forming the trench groove in the first direction;
Forming a gate electrode in the trench groove;
Forming an interlayer insulating film on the surfaces of the second base layer, the base contact layer, and the source layer, and patterning the interlayer insulating film so as to cover a trench portion on the gate insulating film and the gate electrode; When,
And a step of forming a source electrode over the entire surface of the semiconductor device with the interlayer insulating film interposed therebetween.

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