JP2014160763A - Insulation substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an extra blazing material of a brazing material layer from penetrating upward to an upper surface of a metal layer in an insulation substrate where a lower surface of the metal layer for improving the solderability is brazed to an upper surface of an aluminum circuit layer laminated on an upper surface of an insulation layer through the brazing material layer.SOLUTION: An upper surface 2 of a metal layer 1 of an insulation substrate 30 has solderability better than an upper surface 11 of a circuit layer 10, and a heating body 22 is soldered onto the upper surface 2 of the metal layer 1. The upper surface 11 of the circuit layer 10 includes an exposed part 15 that is not covered by a lower surface 3 of the metal layer 1 and is exposed. The metal layer 1 includes a standing surface 7 which is disposed standing relative to the exposed part 15 of the upper surface 11 of the circuit layer 10. A corner part 8 between the exposed part 15 of the upper surface 11 of the circuit layer 10 and the standing surface 7 of the metal layer 1 is filled with an extra brazing material 9a of a brazing material layer 9.

Description

  The present invention relates to an insulating substrate having a surface to which a heating element (eg, semiconductor element) is soldered, a heat dissipation device including the insulating substrate, a semiconductor module including the insulating substrate, a method for manufacturing the insulating substrate, and a method for manufacturing the heat dissipation device. And a method of manufacturing a semiconductor module.

  Although the vertical direction of the insulating substrate according to the present invention is not limited, in the present specification and claims, a heating element in the insulating substrate is soldered for easy understanding of the configuration of the insulating substrate. The surface side is defined as the upper surface side, and the opposite side as the lower surface side. Further, in the present specification, the term “plate” is used to include “foil”.

  For example, an insulating substrate disposed between a semiconductor element and a radiator that emits heat of the semiconductor element as a heating element generally includes an electrical insulating layer, and a metal circuit layer is formed on the upper surface of the insulating layer. Are stacked. And a semiconductor element is soldered on the upper surface of a metal circuit layer (for example, refer patent documents 1-6).

  In recent years, an aluminum circuit layer formed of aluminum (including an alloy thereof) has been used as the metal circuit layer. The reason is that the aluminum circuit layer has excellent electrical and thermal characteristics and can reduce the manufacturing cost of the insulating substrate.

JP 2011-238892 A JP 2011-210947 A JP 2012-104539 A JP 2012-248697 A JP 2012-227356 A JP 2012-4534 A

  However, the upper surface of the aluminum circuit layer has poor solderability. Therefore, it is conceivable that a metal layer for improving solderability is disposed on the upper surface of the circuit layer in a laminated manner with respect to the circuit layer, and the lower surface of the metal layer is brazed to the upper surface of the circuit layer via a brazing material layer. .

  However, when brazing, the excess brazing material of the brazing material layer oozes up to the upper surface of the metal layer, and further, the brazing material pool is generated on the upper surface of the metal layer due to the surplus brazing material swelled to the upper surface of the metal layer. There was a thing. If it becomes like this, the problem that the solderability of the upper surface of a metal layer falls will generate | occur | produce.

  The present invention has been made in view of the above-described technical background, and its object is to provide a lower surface of a metal layer having an upper surface for improving solderability on an upper surface of an aluminum circuit layer laminated on an upper surface of an insulating layer. An object of the present invention is to provide an insulating substrate that is brazed via a material layer and that can maintain good solderability of the upper surface of a metal layer. Still another object of the present invention is to provide a heat dissipation device including the insulating substrate, a semiconductor module including the insulating substrate, a method for manufacturing the insulating substrate, a method for manufacturing the heat dissipation device, and a method for manufacturing the semiconductor module. It is in.

  The present invention provides the following means.

[1] The lower surface of the metal layer disposed in a laminated manner with respect to the circuit layer is brazed to the upper surface of the aluminum circuit layer laminated on the upper surface of the insulating layer via a brazing material layer,
The upper surface of the metal layer has better solderability than the upper surface of the circuit layer, and the heating element is soldered.
The upper surface of the circuit layer includes an exposed portion exposed without being concealed by the lower surface of the metal layer,
The metal layer includes a rising surface arranged in a rising manner with respect to the exposed portion of the upper surface of the circuit layer;
An insulating substrate, wherein an excess brazing material of the brazing material layer is filled in a corner portion between the exposed portion of the upper surface of the circuit layer and the rising surface of the metal layer.

[2] The rising surface of the metal layer includes an outer peripheral side surface of the metal layer,
The exposed portion of the upper surface of the circuit layer includes a first exposed portion exposed outside the outer peripheral side surface of the metal layer;
The excess brazing filler metal of the brazing filler metal layer is filled in the first corner between the first exposed portion on the upper surface of the circuit layer and the outer peripheral side surface of the metal layer as the corner. Insulating substrate.

  [3] With the outer peripheral edge of the lower surface of the metal layer partially aligned with the outer peripheral edge of the upper surface of the circuit layer, the lower surface of the metal layer passes through the brazing material layer on the upper surface of the circuit layer. 3. The insulating substrate according to 1 or 2 above, which is brazed.

[4] The outer peripheral shape of the upper surface of the circuit layer is a polygonal shape having a plurality of corners and a plurality of sides.
The outer peripheral edge shape of the lower surface of the metal layer corresponds to the outer peripheral edge shape of the upper surface of the circuit layer and is a shape in which at least one corner portion is removed among the plurality of corner portions,
The sides of the outer peripheral edge of the lower surface of the metal layer are aligned with the sides of the outer peripheral edge of the upper surface of the circuit layer, and the lower surface of the metal layer is on the upper surface of the circuit layer. Is brazed through,
3. The insulating substrate according to claim 2, wherein the first exposed portion on the upper surface of the circuit layer includes the region of the at least one corner portion on the upper surface of the circuit layer.

[5] The upper surface of the metal layer has a soldering scheduled part to which the heating element is soldered and a non-soldering scheduled part to which the heating element is not soldered.
The non-soldered portion on the upper surface of the metal layer is provided with a through hole penetrating to the lower surface side of the metal layer,
The rising surface of the metal layer includes an inner peripheral side surface of the through hole of the metal layer,
The exposed portion of the upper surface of the circuit layer includes a second exposed portion exposed inside the inner peripheral side surface of the through hole of the metal layer,
The excess brazing filler metal of the brazing filler metal layer is filled in the second corner between the second exposed portion on the upper surface of the circuit layer and the inner peripheral side surface of the through hole of the metal layer as the corner. 5. The insulating substrate according to any one of 1 to 4 above.

  [6] The insulating substrate according to any one of [1] to [5], wherein the metal layer includes a Ni layer, and an upper surface of the metal layer is formed on an upper surface of the Ni layer.

[7] The insulating substrate according to [6], wherein the metal layer includes an Al layer, and a lower surface of the metal layer is formed by a lower surface of the Al layer. [8] The metal layer includes the Ni layer and the Al layer. The insulating substrate according to item 7, wherein the Ni layer, the Ti layer, and the Al layer are joined and integrated in a laminated manner.

[9] The insulating substrate according to any one of 1 to 8 above,
And a radiator disposed on the lower surface side of the insulating substrate.

[10] The insulating substrate according to any one of 1 to 8 above,
A radiator disposed on the lower surface side of the insulating substrate;
And a semiconductor element as a heating element soldered to the upper surface of the metal layer of the insulating substrate.

[11] A brazing step of brazing the lower surface of the metal layer disposed on the upper surface of the aluminum circuit layer in a stacked manner with respect to the circuit layer via the brazing material layer,
The upper surface of the metal layer has better solderability than the upper surface of the circuit layer, and the heating element is soldered.
The upper surface of the circuit layer includes an exposed portion that is exposed without being hidden by the lower surface of the metal layer,
The metal layer includes a rising surface arranged in a rising manner with respect to the exposed portion of the upper surface of the circuit layer,
In the brazing step, the lower surface of the metal layer is brazed to the upper surface of the circuit layer via the brazing material layer, so that the exposed portion of the upper surface of the circuit layer and the rising surface of the metal layer are A method for manufacturing an insulating substrate, comprising: filling a surplus brazing material of the brazing material layer in the corners between them.

[12] The rising surface of the metal layer includes an outer peripheral side surface of the metal layer,
The exposed portion of the upper surface of the circuit layer includes a first exposed portion exposed outside the outer peripheral side surface of the metal layer;
In the brazing step, by brazing the lower surface of the metal layer to the upper surface of the circuit layer via the brazing material layer, the surplus brazing material of the brazing material layer is used as the corner portion of the circuit layer. 12. The method for manufacturing an insulating substrate according to 11 above, wherein a first corner between the first exposed portion on the upper surface and the outer peripheral side surface of the metal layer is filled.

  [13] In the brazing step, the lower peripheral surface of the metal layer is placed on the upper surface of the circuit layer with the outer peripheral edge of the lower surface of the metal layer partially aligned with the outer peripheral edge of the upper surface of the circuit layer. 13. The method for producing an insulating substrate according to 11 or 12 above, wherein the brazing is performed through the brazing material layer.

[14] The outer peripheral shape of the upper surface of the circuit layer is a polygonal shape having a plurality of corners and a plurality of sides.
The outer peripheral edge shape of the lower surface of the metal layer corresponds to the outer peripheral edge shape of the upper surface of the circuit layer and is a shape in which at least one corner portion is removed among the plurality of corner portions,
In the brazing step, the sides of the outer peripheral edge of the lower surface of the metal layer are aligned with the sides of the outer peripheral edge of the upper surface of the circuit layer, and the metal layer is formed on the upper surface of the circuit layer. The lower surface is brazed via the brazing material layer,
13. The method for manufacturing an insulating substrate according to item 12, wherein the first exposed portion on the upper surface of the circuit layer includes the region of the at least one corner portion on the upper surface of the circuit layer.

[15] The upper surface of the metal layer has a soldering scheduled part to which the heating element is soldered and a non-soldering scheduled part to which the heating element is not soldered,
The non-soldered portion on the upper surface of the metal layer is provided with a through hole penetrating to the lower surface side of the metal layer,
The rising surface of the metal layer includes an inner peripheral side surface of the through hole of the metal layer,
The exposed portion of the upper surface of the circuit layer includes a second exposed portion exposed inside the inner peripheral side surface of the through hole of the metal layer,
In the brazing step, by brazing the lower surface of the metal layer to the upper surface of the circuit layer via the brazing material layer, the surplus brazing material of the brazing material layer is used as the corner portion of the circuit layer. 15. The method for manufacturing an insulating substrate according to any one of the above items 11 to 14, wherein the second corner between the second exposed portion on the upper surface and the inner peripheral side surface of the through hole of the metal layer is filled.

  [16] The method for manufacturing an insulating substrate according to any one of [11] to [15], wherein the metal layer includes a Ni layer, and an upper surface of the metal layer is formed on an upper surface of the Ni layer.

  [17] The method for manufacturing an insulating substrate according to [16], wherein the metal layer includes an Al layer, and a lower surface of the metal layer is formed by a lower surface of the Al layer.

  [18] The metal layer includes a Ti layer disposed between the Ni layer and the Al layer, and the Ni layer, the Ti layer, and the Al layer are joined and integrated in a stacked manner. 18. The method for manufacturing an insulating substrate according to 17 above.

  [19] A method for manufacturing a heat dissipation device, comprising fixing a heatsink to the lower surface of the insulating substrate according to any one of items 1 to 8.

[20] While fixing the radiator to the lower surface of the insulating substrate according to any one of 1 to 8 above,
A method of manufacturing a semiconductor module, comprising: soldering a semiconductor element as a heating element to an upper surface of a metal layer of the insulating substrate.

  The present invention has the following effects.

  According to the insulating substrate of [1], the brazing filler metal surplus brazing material is filled in the corner between the exposed portion of the upper surface of the aluminum circuit layer and the rising surface of the metal layer. In addition, when the lower surface of the metal layer is brazed via the brazing material layer, it is possible to prevent the excess brazing material of the brazing material layer from oozing up to the upper surface of the metal layer. Thereby, the favorable solderability of the upper surface of a metal layer can be maintained, As a result, a heat generating body can be favorably soldered to the upper surface of a metal layer.

  In the preceding item [2], the exposed portion of the upper surface of the circuit layer includes a first exposed portion exposed outside the outer peripheral side surface of the metal layer, and the surplus brazing material of the brazing material layer is the first exposed portion of the upper surface of the circuit layer. The first corner between the exposed portion and the outer peripheral side surface of the metal layer is filled. Therefore, the corner filled with the excess brazing filler metal of the brazing filler metal layer can be easily formed.

  In the above [3], the outer peripheral edge of the lower surface of the metal layer is aligned with the outer peripheral edge of the upper surface of the circuit layer, and the lower surface of the metal layer is brazed with the brazing material layer on the upper surface of the circuit layer. It is attached. Therefore, when the lower surface of the metal layer is brazed to the upper surface of the circuit layer, the outer peripheral edge of the lower surface of the metal layer is partially aligned with the outer peripheral edge of the upper surface of the circuit layer so that the lower surface of the metal layer is connected to the circuit layer. By disposing on the upper surface, the position of the lower surface of the metal layer relative to the upper surface of the circuit layer can be determined. Therefore, the position of the lower surface of the metal layer can be easily determined.

  In the preceding item [4], the sides of the outer peripheral edge of the lower surface of the metal layer are aligned with the sides of the outer peripheral edge of the upper surface of the circuit layer, and the lower surface of the metal layer is brazed on the upper surface of the circuit layer. Brazed through layers. Therefore, when the lower surface of the metal layer is brazed to the upper surface of the circuit layer, the metal layer is placed in a state in which the sides of the outer peripheral edge of the lower surface of the metal layer are aligned with the sides of the outer peripheral edge of the upper surface of the circuit layer. By arranging the lower surface of the metal layer on the upper surface of the circuit layer, the position of the lower surface of the metal layer with respect to the upper surface of the circuit layer can be determined very accurately. Therefore, the position of the lower surface of the metal layer can be easily and very accurately determined.

  In the preceding item [5], by providing a through hole penetrating to the lower surface side of the metal layer in the non-soldered portion on the upper surface of the metal layer, the area of the exposed portion on the upper surface of the circuit layer can be increased. Thereby, the corner part with which the excess brazing filler metal of a brazing filler metal layer is filled can be increased, and, therefore, the excess brazing filler metal can be prevented reliably.

  Furthermore, by providing the through holes, it is possible to reduce the brazing area and promote the discharge of the brazing material layer to the corners of the surplus brazing material. Thereby, the lower surface of the metal layer can be satisfactorily brazed to the upper surface of the circuit layer.

  Moreover, since the through hole is provided in the non-soldered portion on the upper surface of the metal layer, the conduction of heat from the heating element to the circuit layer side is prevented by the through hole. can do. Thereby, the heat of the heating element can be conducted well to the circuit layer side, and as a result, the heat of the heating element can be quickly released.

  The preceding item [6] has the following effects. In general, Ni has better solderability than aluminum. Therefore, when the upper surface of the metal layer is formed from the upper surface of the Ni layer, the heating element can be satisfactorily soldered to the upper surface of the metal layer.

  In general, Ni reacts with Al to form an intermetallic compound. Therefore, if the metal layer includes a Ni layer, Ni in the Ni layer reacts with Al in the brazing material of the brazing material layer to form an intermetallic compound, thereby consuming excess brazing material in the brazing material layer. The As a result, it is possible to reliably prevent the excess brazing material from seeping up.

  In the preceding item [7], the lower surface of the metal layer is formed by the lower surface of the Al layer, whereby the lower surface of the metal layer can be firmly brazed to the upper surface of the circuit layer.

  The preceding item [8] has the following effects. In general, Ti reacts with Al to form an intermetallic compound. Therefore, when the metal layer includes a Ti layer, Ti in the Ti layer reacts with Al in the brazing material of the brazing material layer to form an intermetallic compound, thereby further consuming excess brazing material in the brazing material layer. Is done. Thereby, it is possible to more reliably prevent the excess brazing material from spreading.

  In addition, the Ti layer is disposed between the Ni layer and the Al layer, and the Ni layer, the Ti layer, and the Al layer are joined and integrated in a laminated manner, so that insulation having excellent strength and reliability is achieved. A substrate can be obtained. Therefore, it is possible to prevent the insulating substrate from being peeled off or cracked when a thermal cycle test is performed on the insulating substrate.

  In the preceding item [9], it is possible to provide a heat dissipation device including an insulating substrate that exhibits any one of the effects [1] to [8].

  In the preceding item [10], it is possible to provide a semiconductor module including an insulating substrate that exhibits any of the effects [1] to [8].

  In the previous items [11] to [18], it is possible to obtain an insulating substrate that exhibits any of the effects [1] to [8].

  In the previous item [19], it is possible to obtain a heat radiating device including an insulating substrate that exhibits any one of the effects [1] to [8].

  In the preceding item [20], a semiconductor module including an insulating substrate that exhibits any of the effects [1] to [8] can be obtained.

FIG. 1 is a cross-sectional view of a semiconductor module including an insulating substrate according to the first embodiment of the present invention. FIG. 2 is a plan view of an aluminum circuit layer used for the insulating substrate. FIG. 3 is a cross-sectional view showing a state where the lower surface of the metal layer is brazed to the upper surface of the aluminum circuit layer of the insulating substrate. FIG. 4 is a plan view of an aluminum circuit layer used for an insulating substrate according to the second embodiment of the present invention. FIG. 5 is a plan view of an aluminum circuit layer used for an insulating substrate according to the third embodiment of the present invention. FIG. 6 is a plan view of an aluminum circuit layer used for an insulating substrate according to the fourth embodiment of the present invention. FIG. 7 is a plan view of an aluminum circuit layer used in an insulating substrate according to the fifth embodiment of the present invention. FIG. 8 is a cross-sectional view of the vicinity of an aluminum circuit layer and a metal layer of a semiconductor module having an insulating substrate according to a sixth embodiment of the present invention. FIG. 9 is a plan view of an aluminum circuit layer used for the insulating substrate.

  Several embodiments of the present invention will be described below with reference to the drawings.

  1-3 is a figure explaining the structure of the insulated substrate and semiconductor module which concern on 1st Embodiment of this invention. FIG. 1 is a cross-sectional view of the semiconductor module corresponding to line XX in FIG.

  As shown in FIG. 1, the semiconductor module 32 of the first embodiment is, for example, a power module, and specifically, an IGBT module, a MOSFET module, a thyristor module, a diode module, or the like. The semiconductor module 32 includes the semiconductor element 22 as a heating element, the heat dissipation device 31 of the first embodiment, and the like.

  The semiconductor element 22 is an IGBT chip, a MOSFET chip, a thyristor chip, a diode chip, or the like.

  The heat dissipating device 31 includes the insulating substrate 30 and the heat radiator 20 of the first embodiment, and the heat of the semiconductor element 22 is conducted to the heat radiator 20 through the insulating substrate 30 to be released. 22 is for cooling.

  The insulating substrate 30 is disposed between the semiconductor element 22 and the radiator 20 and has an electrical insulating layer 17, an aluminum circuit layer 10, a metal layer 1, a first stress relaxation layer 18, and a second stress relaxation. Layer 19 is provided. In the present embodiment, these layers 17, 10, 1, 18, 19 are all in a plan view shape, and are arranged in a horizontal and stacked manner and are integrally joined.

The insulating layer 17 is made of, for example, ceramic, and more specifically, is formed of a ceramic plate. Ceramics include aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), alumina (Al ₂ O ₃ ), silicon carbide (SiC), yttrium oxide (Y ₂ O ₃ ), calcium oxide (CaO), boron nitride (BN), beryllium oxide (BeO), or the like is used. The thickness of the insulating layer 17 is set to 200 to 1200 μm, for example.

  The aluminum circuit layer 10 is made of aluminum (including its alloy), and more specifically, an aluminum plate. As the aluminum forming the circuit layer 10, for example, high-purity aluminum having a purity of 99.99% or more, or A1000 or A3000 aluminum is used. The circuit layer 10 is laminated on the upper surface of the insulating layer 17 and joined in a fixed state by brazing or the like. The thickness of the circuit layer 10 is set to 200 to 1000 μm, for example. Since the circuit layer 10 is made of aluminum, the upper surface 11 of the circuit layer 10 has poor solderability.

  The metal layer 1 is disposed on the upper surface 11 of the circuit layer 10 so as to be laminated with respect to the circuit layer 10, and the lower surface 3 of the metal layer 1 has a brazing filler metal layer 9 at a substantially central portion of the upper surface 11 of the circuit layer 10. It is brazed to a surface contact state via. The metal layer 1 is a layer for improving solderability, that is, the upper surface 2 of the metal layer 1 has better solderability than the upper surface 11 of the circuit layer 10. And the semiconductor element 22 is soldered to the approximate center part of the upper surface 2 of the metal layer 1 according to a conventional method. In this embodiment, the metal layer 1 is formed by joining and integrating a plurality of layers 1a, 1b, and 1c in a stacked manner, and details of the configuration will be described later.

  The brazing material layer 9 is a layer obtained by brazing the lower surface 3 of the metal layer 1 to the upper surface 11 of the circuit layer 10 and is formed of an Al-based brazing material (eg, Al—Si brazing material) or the like. The thickness of the brazing material layer 9 is set to, for example, 5 to 50 μm in a state where the lower surface 3 of the metal layer 1 is brazed to the upper surface 11 of the circuit layer 10. The melting point of the circuit layer 10 is set to be higher than the melting point of the brazing material of the brazing material layer 9. In the drawing, the brazing filler metal layer 9 and its surplus brazing filler metal 9a are shown by dot hatching for easy distinction from other layers.

  The first stress relieving layer 18 is a layer for relieving stress such as thermal stress generated in the insulating substrate 30, and is laminated on the lower surface of the insulating layer 17 and joined in a fixed state by brazing or the like. The first stress relaxation layer 18 is formed of a metal (eg, aluminum). More specifically, the first stress relaxation layer 18 is formed of a metal plate (eg, aluminum plate). As a metal for forming the first stress relaxation layer 18, for example, high-purity aluminum having a purity of 99.99% or more, or A1000 series or A3000 series aluminum is used. The thickness of the first stress relaxation layer 18 is set to 200 to 3000 μm, for example.

  The second stress relaxation layer 19 is a layer for relaxing stresses such as thermal stress generated in the insulating substrate 30, similar to the first stress relaxation layer 18, and is laminated on the lower surface of the first stress relaxation layer 18 and brazed. Etc. are joined in a fixed state. The second stress relaxation layer 19 is made of metal, and more specifically, is formed of a punching metal plate having a plurality of holes 19a. As a metal for forming the second stress relaxation layer 19, for example, high-purity aluminum having a purity of 99.99% or more, or A1000 series or A3000 series aluminum is used. The thickness of the second stress relaxation layer 19 is set to 200 to 3000 μm, for example.

  The radiator 20 is made of metal (for example, aluminum) disposed on the lower surface side of the insulating substrate 30, and emits heat conducted from the semiconductor element 22 through the insulating substrate 30. The heat dissipation method of the radiator 20 is a liquid cooling type (eg, water cooling type) or an air cooling type. In the present embodiment, the radiator 20 has a case formed by joining both side edges of the metal upper plate portion 20a and both side edges of the metal lower plate portion 20b to each other. Metal corrugated fins 20c that form a plurality of refrigerant passages 20d are arranged. The upper surface of the radiator 20 is bonded to the lower surface of the second stress relaxation layer 19 as the lower surface of the insulating substrate 30 by brazing or the like.

  Next, the configuration of the metal layer 1 will be described below.

  The metal layer 1 includes a Ni layer 1a, a Ti layer 1b, and an Al layer 1c. Then, the Ni layer 1a, the Ti layer 1b, and the Al layer 1c are arranged in order from the top, and are joined and integrated, whereby the metal layer 1 is formed. Therefore, the upper surface 2 of the metal layer 1 is formed by the upper surface of the Ni layer 1a, the lower surface 3 of the metal layer 1 is formed by the lower surface of the Al layer 1c, and the Ti layer 1b includes the Ni layer 1a and the Al layer 1c. Between the Ni layer 1a and the Al layer 1c. Since the upper surface 2 of the metal layer 1 is formed by the upper surface of the Ni layer 1a, it has better solderability than the upper surface 11 of the circuit layer 10.

  The Ni layer 1a of the metal layer 1 is formed of nickel (including an alloy thereof), and more specifically is formed of a nickel plate. In the present embodiment, the Ni layer 1a is formed of, for example, a pure nickel plate. The thickness of the Ni layer 1a is set to 5 to 100 μm, for example.

  The Ti layer 1b of the metal layer 1 is formed of titanium (including its titanium alloy), and more specifically, is formed of a titanium plate. In the present embodiment, the Ti layer 1b is formed of, for example, a pure titanium plate. The thickness of the Ti layer 1b is set to 2 to 100 μm, for example.

  The Al layer 1c of the metal layer is made of aluminum (including its alloy), and more specifically, is made of an aluminum plate. The aluminum for forming the Al layer 1c is not limited, and for example, high-purity aluminum having a purity of 99.99% or more or A1000 series or A3000 series aluminum is used, and in particular, A1000 series (example: A1050, A1100). ) Or A3000 series (e.g., A3003) aluminum is desirable because it can be brazed firmly to the upper surface 11 of the circuit layer 10. The thickness of the Al layer 1c is set to 20 to 1200 μm, for example. Furthermore, the melting point of the Al layer 1 c is set higher than the melting point of the brazing material of the brazing material layer 9.

  The Ni layer 1a and the Ti layer 1b are joined and integrated with each other by diffusion bonding or the like, and in this embodiment, they are joined and integrated with each other by clad rolling as diffusion bonding. As a result, as shown in FIG. 3, a Ni—Ti alloy layer 1d formed by alloying Ni in the Ni layer 1a and Ti in the Ti layer 1b is formed at the joint interface between the Ni layer 1a and the Ti layer 1b. ing. The thickness of the alloy layer 1d is not limited, but is particularly preferably 0.1 to 10 μm. The conditions for clad rolling are not limited, but it is particularly desirable that the clad temperature is 10 to 500 ° C. and the rolling reduction is 20 to 70%. By doing so, the Ni layer 1a and the Ti layer 1b can be firmly bonded.

  The Ti layer 1b and the Al layer 1c are joined and integrated with each other by diffusion bonding or the like, and in this embodiment, they are joined and integrated with each other by clad rolling as diffusion bonding. The conditions for clad rolling are not limited, but it is particularly desirable that the clad temperature is 10 to 500 ° C. and the rolling reduction is 20 to 70%. By doing so, the Ti layer 1b and the Al layer 1c can be firmly bonded.

  Thus, as shown in FIG. 1, the upper surface 11 of the circuit layer 10 includes an exposed portion 15 exposed without being hidden by the lower surface 3 of the metal layer 1. In addition, the metal layer 1 includes a rising surface 7 arranged in a rising shape substantially perpendicular to the exposed portion 15 of the upper surface 11 of the circuit layer 10. Further, the upper surface 2 of the metal layer 1 is composed of a soldering scheduled portion 2a to which the semiconductor element 22 is soldered and a non-soldering scheduled portion 2b to which the semiconductor element 22 is not soldered.

  In the first embodiment, the rising surface 7 of the metal layer 1 is the outer peripheral side surface 4 of the metal layer 1. The exposed portion 15 of the upper surface 11 of the circuit layer 10 is a portion of the upper surface 11 of the circuit layer 10 that is exposed outside the outer peripheral side surface 4 (that is, the rising surface 7) of the metal layer 1. It is referred to as “first exposed portion 15a”. Further, the corner portion 8 between the first exposed portion 15a of the upper surface 11 of the circuit layer 10 and the outer peripheral side surface 4 of the metal layer 1 is particularly referred to as a “first corner portion 8a”.

  Here, in FIG. 2, the metal layer 1 is illustrated by a two-dot chain line, and the semiconductor element 22 is illustrated by a one-dot chain line. Further, the exposed portion 15 of the upper surface 11 of the circuit layer 10 is illustrated by cross hatching.

  As shown in FIGS. 1 and 2, the soldered portion 2 a on the upper surface 2 of the metal layer 1 is a substantially central portion of the upper surface 2 of the metal layer 1. On the other hand, the non-soldering scheduled portion 2 b on the upper surface 2 of the metal layer 1 is a portion excluding the scheduled soldering portion 2 a on the upper surface 2 of the metal layer 1, that is, the outer peripheral portion of the upper surface 2 of the metal layer 1.

  The ratio of the area of the exposed portion 15 of the upper surface 11 of the circuit layer 10 to the area of the upper surface 11 of the circuit layer 10 is not limited, but in particular, the area of the exposed portion 15 of the upper surface 11 of the circuit layer 10 is It is desirable to set it to 1 to 50% with respect to the area of the upper surface 11 of the circuit layer 10.

  Next, the brazing state between the circuit layer 10 and the metal layer 1 will be described in detail below.

  As shown in FIG. 2, the shape of the outer peripheral edge 11a of the upper surface 11 of the circuit layer 10 is a rectangular shape (in detail, a square shape), and thus has four corners and four sides. Yes. The vertical and horizontal dimensions of the upper surface 11 of the circuit layer 10 are not limited, and are set to 5 to 50 mm, for example.

  The shape of the outer peripheral edge 3 a of the lower surface 3 of the metal layer 1 is similar to the shape of the outer peripheral edge 11 a of the upper surface 11 of the circuit layer 10 (that is, a square shape). Furthermore, the vertical and horizontal dimensions of the lower surface 3 of the metal layer 1 are set to be slightly smaller than the vertical and horizontal dimensions of the upper surface 11 of the circuit layer 10, respectively, and preferably the vertical and horizontal dimensions of the upper surface 11 of the circuit layer 10. It is good to set each 0.3 to 10% smaller than the horizontal dimension. As described above, the lower surface 3 of the metal layer 1 is brazed to the substantially central portion of the upper surface 11 of the circuit layer 10 via the brazing material layer 9. Therefore, in the first embodiment, the first exposed portion 15 a of the upper surface 11 of the circuit layer 10 is an outer peripheral portion of the outer peripheral side surface 4 of the metal layer 1 on the upper surface 11 of the circuit layer 10.

  Further, as shown in FIG. 1, an excess brazing material 9 a of the brazing material layer 9 is formed at the first corner portion 8 a between the first exposed portion 15 a of the upper surface 11 of the circuit layer 10 and the outer peripheral side surface 4 of the metal layer 1. As a fillet portion of the brazing filler metal layer 9, the entire outer peripheral side surface 4 of the metal layer 1 is filled.

  Furthermore, the semiconductor element 22 is soldered to the soldering scheduled portion 2 a on the upper surface 2 of the metal layer 1.

  Next, a method for manufacturing the insulating substrate 30 of the first embodiment will be described.

  As shown in FIG. 3, a metal layer 1 is prepared in which a Ni layer 1a, a Ti layer 1b, and an Al layer 1c are joined and integrated in a laminated form. Further, a brazing filler metal layer 9 is bonded in advance to the lower surface 3 of the metal layer 1 by clad rolling.

The lower surface 3 of the metal layer 1 is brazed on the upper surface 11 of the circuit layer 10 so that the first exposed portion 15a (exposed portion 15) of the upper surface 11 of the circuit layer 10 is exposed without being concealed by the lower surface 3 of the metal layer 1. Arranged via the material layer 9. In this state, the lower surface 3 of the metal layer 1 is brazed to the upper surface 11 of the circuit layer 10 via the brazing material layer 9. This process is called “brazing process”. The brazing means in this case is not limited, but vacuum brazing is particularly desirable. In this case, the brazing conditions are not limited, but the degree of vacuum is 1 × 10 ⁻³ to 1 × 10 ⁻⁵ Pa, the brazing temperature is 590 to 610 ° C., and the holding time is ³ to 60 min. Particularly desirable.

  By brazing in this way, the lower surface 3 of the metal layer 1 is brazed to the upper surface 11 of the circuit layer 10 via the brazing material layer 9, and at the same time, the upper surface 11 of the circuit layer 10 as shown in FIG. Excess brazing material 9a of the brazing material layer 9 is filled in the first corner 8a between the first exposed portion 15a and the outer peripheral side surface 4 of the metal layer 1 over the entire circumference of the outer peripheral side surface 4 of the metal layer 1. .

  In this brazing process, the lower surface 3 of the metal layer 1 is brazed to the upper surface 11 of the circuit layer 10, and at the same time, other layers (17, 18, 19) constituting the insulating substrate 30 are collectively processed. Brazing may be performed, and the radiator 20 may be brazed together.

  When manufacturing the heat dissipation device 31 using the insulating substrate 30 of the first embodiment, the upper surface of the radiator 20 is joined to the lower surface of the second stress relaxation layer 19 as the lower surface of the insulating substrate 30 by brazing or the like. The Thereby, the radiator 20 is fixed to the lower surface of the insulating substrate 30.

  When the semiconductor module 32 is manufactured using the insulating substrate 30 of the first embodiment, the semiconductor element 22 is soldered to the soldering scheduled portion 2a on the upper surface 2 of the metal layer 1 in accordance with a conventional method.

  The insulating substrate 30 and the manufacturing method thereof according to the first embodiment have the following advantages.

  The brazing filler metal layer 9 is formed on the first corner 8a (corner portion 8) between the first exposed portion 15a (exposed portion 15) of the upper surface 11 of the aluminum circuit layer 10 and the outer peripheral side surface 4 (rising surface 7) of the metal layer 1. Therefore, when the lower surface 3 of the metal layer 1 is brazed to the upper surface 11 of the circuit layer 10, the excess brazing material 9 a of the brazing material layer 9 oozes up to the upper surface 2 of the metal layer 1. In addition, it is possible to prevent the brazing material pool from being generated on the upper surface 2 of the metal layer 1 by the surplus brazing material 9a that has swelled on the upper surface 2 of the metal layer 1. Thereby, the favorable solderability of the upper surface 2 of the metal layer 1 can be maintained, and as a result, the semiconductor element 22 (heating element) can be soldered to the upper surface 2 of the metal layer 1 satisfactorily. Further, since the excess brazing filler metal 9a of the brazing filler metal layer 9 is filled in the first corner 8a as a fillet portion of the brazing filler metal layer 9, the brazing between the upper surface 11 of the circuit layer 10 and the lower surface 3 of the metal layer 1 is performed. The attachment strength is very high.

  Further, the corner portion 8 filled with the excess brazing material 9 a of the brazing material layer 9 is a first corner portion 8 a between the first exposed portion 15 a of the upper surface 11 of the circuit layer 10 and the outer peripheral side surface 4 of the metal layer 1. Therefore, the corner 8 can be easily formed.

  Furthermore, since the upper surface 2 of the metal layer 1 is formed by the upper surface (ie, Ni) of the Ni layer 1a, the semiconductor element 22 can be satisfactorily soldered to the upper surface 2 of the metal layer 1.

  In general, Ni reacts with Al to form an intermetallic compound. Accordingly, when the metal layer 1 includes the Ni layer 1a, Ni in the Ni layer 1a reacts with Al in the brazing material of the brazing material layer 9 to form an intermetallic compound, thereby surplus of the brazing material layer 9 The brazing material 9a is consumed. Thereby, it is possible to reliably prevent the excess brazing material 9a from spreading.

  Furthermore, the lower surface 3 of the metal layer 1 is formed by the lower surface of the Al layer 1 c, whereby the lower surface 3 of the metal layer 1 can be firmly brazed to the upper surface 11 of the circuit layer 10.

  In general, Ti reacts with Al to form an intermetallic compound. Therefore, if the metal layer 1 includes the Ti layer 1b, the Ti in the Ti layer 1b reacts with Al in the brazing material of the brazing material layer 9 to form an intermetallic compound, thereby surplus of the brazing material layer 9 The brazing material 9a is further consumed. Thereby, it is possible to more reliably prevent the excess brazing material 9a from spreading.

  In addition, the Ti layer 1b is disposed between the Ni layer 1a and the Al layer 1c, and the Ni layer 1a, the Ti layer 1b, and the Al layer 1c are joined and integrated in a laminated form. Therefore, the thermal strain generated in the insulating substrate 30 by the thermal cycle test or the like is alleviated by the difference in linear expansion coefficient between Ni, Ti and Al. Thereby, it is possible to prevent the insulating substrate 30 from being peeled off or cracked, and thus it is possible to obtain the insulating substrate 30 having excellent strength reliability.

  The present invention is not limited to the first embodiment and can be variously modified without departing from the gist of the present invention. Some modified embodiments are shown below.

  FIG. 4 is a plan view of the aluminum circuit layer 110 used in the insulating substrate 130 according to the second embodiment of the present invention. In the figure, constituent elements equivalent to the insulating substrate 30 of the first embodiment are given reference numerals obtained by adding 100 to the reference numerals. In FIG. 4, as in FIG. 2, the metal layer 101 is illustrated by a two-dot chain line, and the semiconductor element 122 is illustrated by a one-dot chain line. Further, the exposed portion 115 of the upper surface 111 of the circuit layer 110 is illustrated by cross hatching.

  As shown in FIG. 4, in the second embodiment, the one side portion of the outer peripheral edge 103 a on the lower surface of the metal layer 101 is aligned with the middle portion of one side portion of the outer peripheral edge 111 a of the upper surface 111 of the aluminum circuit layer 110. Thus, the lower surface of the metal layer 101 is brazed to the upper surface 111 of the circuit layer 110 via a brazing material layer. On the other hand, the other part of the outer peripheral edge 103 a on the lower surface of the metal layer 101 does not coincide with the outer peripheral edge 111 a of the upper surface 111 of the circuit layer 110.

  In the second embodiment, when brazing the lower surface of the metal layer 101 to the upper surface 111 of the circuit layer 110, one side of the outer peripheral edge 103 a of the lower surface of the metal layer 101 is one side of the outer peripheral edge 111 a of the upper surface 111 of the circuit layer 110. The lower surface of the metal layer 101 is disposed on the upper surface 111 of the circuit layer 110 so as to be aligned with the middle portion of the circuit portion. Thereby, the position of the lower surface of the metal layer 101 with respect to the upper surface 111 of the circuit layer 110 is determined. Therefore, the position of the lower surface of the metal layer 101 can be easily determined.

  FIG. 5 is a plan view of the aluminum circuit layer 210 used in the insulating substrate 230 according to the third embodiment of the present invention. In the figure, components equivalent to those of the insulating substrate 30 of the first embodiment are denoted by reference numerals obtained by adding 200 to the reference numerals. In FIG. 5, as in FIG. 2, the metal layer 201 is illustrated by a two-dot chain line, and the semiconductor element 222 is illustrated by a one-dot chain line. Further, the exposed portion 215 (first exposed portion 215a) of the upper surface 211 of the circuit layer 210 is illustrated by cross hatching.

  As shown in FIG. 5, in the third embodiment, the shape of the outer peripheral edge 203a of the lower surface of the metal layer 201 corresponds to the shape of the outer peripheral edge 211a of the upper surface 211 of the aluminum circuit layer 210, and each corner is removed. is there. More specifically, the vertical and horizontal dimensions of the lower surface of the metal layer 201 are set to be equal to the vertical and horizontal dimensions of the upper surface 211 of the circuit layer 210, and the radius of curvature of each corner of the lower surface of the metal layer 201 is set. Is set to be larger than the radius of curvature of each corner of the upper surface 211 of the circuit layer 210. Then, the sides of the outer peripheral edge 203 a on the lower surface of the metal layer 201 are aligned with the sides of the outer peripheral edge 211 a of the upper surface 211 of the circuit layer 210, and the metal layer 201 is placed on the upper surface 211 of the circuit layer 210. The lower surface is brazed via a brazing material layer. On the other hand, each corner of the outer peripheral edge 203 a on the lower surface of the metal layer 201 does not coincide with each corner of the outer peripheral edge 211 a of the upper surface 211 of the circuit layer 210. Therefore, each corner region 215aa on the upper surface 211 of the circuit layer 210 is exposed without being hidden by the lower surface of the metal layer 201. Accordingly, the first exposed portion 215a of the upper surface 211 of the circuit layer 210 is composed of four exposed corner regions 215aa on the upper surface 211 of the circuit layer 210.

  According to the third embodiment, when brazing the lower surface of the metal layer 201 to the upper surface 211 of the circuit layer 210, each side portion of the outer peripheral edge 203 a of the lower surface of the metal layer 201 is used as the outer peripheral edge of the upper surface 211 of the circuit layer 210. The lower surface of the metal layer 201 is disposed on the upper surface 211 of the circuit layer 210 so as to be aligned with the sides of the 211a. Thereby, the position of the lower surface of the metal layer 201 with respect to the upper surface 211 of the circuit layer 210 is determined very accurately. Therefore, the position of the lower surface of the metal layer 201 can be determined easily and very accurately.

  FIG. 6 is a plan view of an aluminum circuit layer 310 used in an insulating substrate 330 according to the fourth embodiment of the present invention. In the figure, components equivalent to those of the insulating substrate 30 of the first embodiment are denoted by reference numerals obtained by adding 300 to the reference numerals. In FIG. 6, as in FIG. 2, the metal layer 301 is illustrated by a two-dot chain line, and the semiconductor element 322 is illustrated by a one-dot chain line. Further, the exposed portion 315 of the upper surface 311 of the circuit layer 310 is illustrated by cross hatching.

  As shown in FIG. 6, in the fourth embodiment, the shape of the outer peripheral edge 303 a on the lower surface of the metal layer 301 is a shape that partially protrudes outward with respect to the outer peripheral edge 311 a of the upper surface 311 of the aluminum circuit layer 310. ing. In this case, only one side of the outer peripheral edge 303a of the lower surface of the metal layer 301 is aligned with the middle part of one side of the outer peripheral edge 311a of the upper surface 311 of the circuit layer 310, and the metal is applied to the upper surface 311 of the circuit layer 310. The lower surface of the layer 301 is brazed via a brazing material layer. The first exposed portion 315 a on the upper surface 311 of the circuit layer 310 includes two corner regions 315 aa on the upper surface 311 of the circuit layer 310.

  FIG. 7 is a plan view of the aluminum circuit layer 410 used in the insulating substrate 430 according to the fifth embodiment of the present invention. In the figure, components equivalent to those of the insulating substrate 30 of the first embodiment are denoted by reference numerals obtained by adding 400 to the reference numerals. In FIG. 7, as in FIG. 2, the metal layer 401 is illustrated by a two-dot chain line, and the semiconductor element 422 is illustrated by a one-dot chain line. Further, the exposed portion 415 of the upper surface 411 of the circuit layer 410 is illustrated by cross hatching.

  As shown in FIG. 7, in the fifth embodiment, the three sides of the outer peripheral edge 403a on the lower surface of the metal layer 401 are formed in a wavy shape, whereby the shape of the outer peripheral edge 403a on the lower surface of the metal layer 401 is The aluminum circuit layer 410 has a shape that partially protrudes outward from the outer peripheral edge 411a of the upper surface 411 and is partially recessed inward. In this case, only one side portion of the outer peripheral edge 403a on the lower surface of the metal layer 401 is aligned with the middle portion of one side portion of the outer peripheral edge 411a of the upper surface 411 of the circuit layer 410, and the metal is applied to the upper surface 411 of the circuit layer 410. The lower surface of the layer 401 is brazed via a brazing material layer. The first exposed portion 415a of the upper surface 411 of the circuit layer 410 includes two corner regions 415aa.

  8 and 9 are diagrams illustrating an insulating substrate 530 and a semiconductor module 532 according to the sixth embodiment of the present invention. In these figures, components equivalent to those of the insulating substrate 30 of the first embodiment are given reference numerals obtained by adding 500 to the reference numerals. 8 is a cross-sectional view of the main part of the semiconductor module corresponding to the YY line in FIG.

  In the sixth embodiment, as shown in FIG. 9, the outer peripheral edge 503a of the lower surface 503 of the metal layer 501 is shaped like the outer peripheral edge of the upper surface 511 of the aluminum circuit layer 510 as in the third embodiment shown in FIG. The shape corresponds to the 511a shape and each corner is removed. More specifically, the vertical and horizontal dimensions of the lower surface of the metal layer 501 are set to be equal to the vertical and horizontal dimensions of the upper surface 511 of the circuit layer 510, and the radius of curvature of each corner of the lower surface of the metal layer 501 is set. Is set larger than the radius of curvature of each corner of the upper surface 511 of the circuit layer 510.

  As shown in FIG. 8, two semiconductor elements 522 and 522 as a plurality of semiconductor elements are soldered to the upper surface 502 of the metal layer 501 of the insulating substrate 530 so as to be separated from each other. Therefore, the upper surface 502 of the metal layer 501 has two soldering portions 502a and 502a spaced apart from each other to which the two semiconductor elements 522 and 522 are soldered. These soldered portions 502a and 502a are located on both sides of the substantially central portion of the upper surface 502 of the metal layer 501 as shown in FIG. On the other hand, a substantially central portion of the upper surface 502 of the metal layer 501 constitutes a part of a non-soldered portion 502b where the two semiconductor elements 522 and 522 are not soldered, and the metal layer 501 has a substantially central portion. A through hole 505 having a substantially oval shape in plan view penetrating to the lower surface 503 side is formed. The through hole 505 is a hole for increasing the area of the exposed portion 515 on the upper surface 511 of the circuit layer 510.

  In the sixth embodiment, the top surface of the circuit layer 510 is set such that each side portion of the outer peripheral edge 503a of the lower surface 503 of the metal layer 501 coincides with and follows each side portion of the outer peripheral edge 511a of the upper surface 511 of the circuit layer 510. A lower surface 503 of the metal layer 501 is brazed to 511 via a brazing material layer 509. On the other hand, each corner of the outer peripheral edge 503 a of the lower surface 503 of the metal layer 501 does not coincide with each corner of the outer peripheral edge 511 a of the upper surface 511 of the circuit layer 510. Therefore, each corner region 515aa on the upper surface 511 of the circuit layer 510 is exposed without being hidden by the lower surface 503 of the metal layer 501. Accordingly, the first exposed portion 515a of the upper surface 511 of the circuit layer 510 is configured by the four corner regions 515aa exposed on the upper surface 511 of the circuit layer 510.

  Furthermore, the upper surface 502 of the metal layer 501 includes a second exposed portion 515b exposed as an exposed portion 515 inside the inner peripheral side surface 505a of the through hole 505 of the metal layer 501. An inner peripheral side surface 505a of the through hole 505 of the metal layer 501 is arranged to rise substantially perpendicular to the second exposed portion 515b. Therefore, the rising surface 507 of the metal layer 501 includes not only the outer peripheral side surface 504 of the metal layer 501 but also the inner peripheral side surface 505 a of the through hole 505 of the metal layer 501.

  Here, the corner portion 508 between the second exposed portion 515b of the upper surface 502 of the metal layer 501 and the inner peripheral side surface 505a of the through hole 505 of the metal layer 501 is particularly referred to as a “second corner portion 508b”.

  In a state where the lower surface 503 of the metal layer 501 is brazed to the upper surface 511 of the circuit layer 510 via the brazing material layer 509, the surplus brazing material 9 a of the brazing material layer 9 is exposed to the first exposed portion of the upper surface 511 of the circuit layer 510. 515a (ie, the corner region 515aa) is filled in the first corner 508a between the outer peripheral side surface 504 of the metal layer 501, and the surplus brazing material 9a is formed on the upper surface of the circuit layer 510 as shown in FIG. The second corner 508b between the second exposed portion 515b of 511 and the inner peripheral side surface 505a of the through hole 505 of the metal layer 501 is filled over the entire circumference of the inner peripheral side surface 505a.

  In the manufacturing method of the insulating substrate 530 of the sixth embodiment, the lower surface 503 of the metal layer 501 is brazed to the upper surface 511 of the circuit layer 510 via the brazing material layer 509 in the same procedure as in the first embodiment. Thereby, the lower surface 503 of the metal layer 501 is brazed to the upper surface 511 of the circuit layer 510 via the brazing material layer 509, and at the same time, the brazing material layer 509 is respectively attached to the first corner portion 508a and the second corner portion 508b. Excess brazing material 509a is filled.

  According to the sixth embodiment, the through hole 505 penetrating to the lower surface 503 side of the metal layer 501 is formed in the substantially central portion (non-soldered portion 502 b) of the upper surface 502 of the metal layer 501. The area of the exposed portion 515 on the upper surface 511 of the layer 510 can be increased. Thereby, the corner part 508 with which the excess brazing material 509a of the brazing material layer 509 is filled can be increased, so that the excess brazing material 509a can be reliably prevented from rising.

  Further, by forming the through hole 505, it is possible to reduce the brazing area and promote the discharge of the brazing material layer 509 to the corner 508 of the surplus brazing material 509a. Thereby, the lower surface 503 of the metal layer 501 can be satisfactorily brazed to the upper surface 511 of the circuit layer 510.

  Moreover, since the through-hole 505 is formed in the non-soldering scheduled portion 502b instead of the soldering planned portion 502a on the upper surface 502 of the metal layer 501, the conduction of the heat of the semiconductor element 522 to the circuit layer 510 side is a through-hole. Inhibition by 505 can be prevented. Thereby, the heat of the semiconductor element 522 can be conducted well to the circuit layer 510 side, and as a result, the heat of the semiconductor element 522 can be quickly released.

  Further, the respective sides of the outer peripheral edge 503 a of the lower surface 503 of the metal layer 501 are aligned with the respective sides of the outer peripheral edge 511 a of the upper surface 511 of the circuit layer 510, and the lower surface 503 of the metal layer 501 is aligned with the circuit layer 510. Since the upper surface 511 of the metal layer 501 is brazed, the position of the lower surface 503 of the metal layer 501 with respect to the upper surface 511 of the circuit layer 510 is determined very accurately during the brazing. Therefore, the position of the lower surface 503 of the metal layer 501 can be determined easily and very accurately.

  Although several embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications can be made without departing from the scope of the present invention.

  For example, in the present invention, the upper surface of the metal layer is particularly preferably formed of Ni as in the above embodiment, but may be formed of Cu or the like.

  Furthermore, the present invention may combine two or more technical ideas applied in the first to sixth embodiments.

  Next, specific examples and comparative examples of the present invention are shown below.

<Example>
In order to produce the insulating substrate 30 of the first embodiment shown in FIGS. 1 to 3, the following metal layer 1 and aluminum circuit layer 10 were prepared.

  The metal layer 1 is formed by joining and integrating a Ni layer 1a, a Ti layer 1b, and an Al layer 1c in a laminated manner. Further, a brazing filler metal layer 9 is formed on the lower surface 3 of the metal layer 1 by clad rolling. It is joined. The Ni layer 1a is formed of a JIS (Japanese Industrial Standard) type pure nickel plate, and the thickness of the Ni layer 1a is 30 μm. The Ti layer 1b is formed of a JIS type 1 pure titanium plate, and the thickness of the Ti layer 1b is 20 μm. The Al layer 1c is formed of an A3003 aluminum plate, and the thickness of the Al layer 1c is 100 μm. Therefore, the thickness of the metal layer 1 is 150 μm. The brazing material of the brazing material layer 9 is an Al—Si brazing material, and the thickness of the brazing material layer 9 is 20 μm. The vertical and horizontal dimensions of the lower surface 3 of the metal layer 1 are 29.5 mm, respectively.

  The aluminum circuit layer 10 is formed of a high-purity aluminum plate having a purity of 99.99%. The thickness of the circuit layer 10 is 600 μm. The vertical and horizontal dimensions of the upper surface 11 of the circuit layer 10 are each 30 mm.

Next, the lower surface 3 of the metal layer 1 was brazed by vacuum brazing through the brazing material layer 9 just to the center of the upper surface 11 of the circuit layer 10. The first exposed portion 15a on the upper surface 11 of the circuit layer 10 is a portion outside the entire circumference of the outer peripheral side surface 4 (rising surface 7) of the metal layer 1 on the upper surface 11 of the circuit layer 10, and its width is 0.25 mm. is there. The brazing conditions applied in this brazing step are a vacuum degree of 1 × 10 ⁻⁴ Pa, a brazing temperature of 600 ° C., and a holding time of 10 min.

  And the circuit layer 10 and the metal layer 1 were observed visually and with the microscope or the stereomicroscope. As a result, the surplus brazing filler metal 9a of the brazing filler metal layer 9 is formed on the entire circumference of the outer peripheral side surface 4 at the first corner 8a between the first exposed portion 15a of the upper surface 11 of the circuit layer 10 and the outer peripheral side surface 4 of the metal layer 1. It was filled over. Further, the surplus brazing material 9 a hardly oozes up to the upper surface 2 of the metal layer 1, and no brazing material pool was generated on the upper surface 2 of the metal layer 1. Therefore, it was confirmed that the upper surface 2 of the metal layer 1 maintained good solderability.

<Comparative example>
The outer peripheral shape of the lower surface of the metal layer is made the same shape as the outer peripheral shape of the upper surface of the aluminum circuit layer, and the vertical and horizontal dimensions of the lower surface of the metal layer are set to the vertical and horizontal dimensions of the upper surface of the circuit layer, respectively. Set equal. Then, the outer peripheral edge of the lower surface of the metal layer was made to coincide with the outer peripheral edge of the upper surface of the circuit layer, and the lower surface of the metal layer was brazed to the upper surface of the circuit layer by vacuum brazing via the brazing material layer. The brazing conditions at that time are the same as those in Example 1.

  And the circuit layer and the metal layer were observed visually and with a microscope or a stereomicroscope. As a result, surplus brazing material in the brazing material layer oozes up to the upper surface of the metal layer, and further, brazing material pooling occurs on the upper surface of the metal layer. Therefore, it was confirmed that the solderability of the upper surface of the metal layer was deteriorated.

  The present invention relates to an insulating substrate having a surface to which a heating element (eg, semiconductor element) is soldered, a heat dissipation device including the insulating substrate, a semiconductor module including the insulating substrate, a method for manufacturing the insulating substrate, and a method for manufacturing the heat dissipation device. And can be used in a method for manufacturing a semiconductor module.

1: metal layer 1a: Ni layer 1b: Ti layer 1c: Al layer 2: upper surface of metal layer 3: lower surface of metal layer 4: outer peripheral side surface of metal layer (rising surface of metal layer)
7: rising surface 8 of metal layer 8: corner 8a: first corner 8b: second corner 9: brazing material layer 9a: surplus brazing material 10: aluminum circuit layer 11: upper surface 15 of circuit layer: exposed portion 15a: First exposed portion 15b: second exposed portion 17: insulating layer 20: radiator 22: semiconductor element (heating element)
30: Insulating substrate 31: Heat dissipation device 32: Semiconductor module

Claims (20)

The upper surface of the aluminum circuit layer laminated on the upper surface of the insulating layer is brazed to the lower surface of the metal layer arranged in a laminated form with respect to the circuit layer via a brazing material layer,
The upper surface of the metal layer has better solderability than the upper surface of the circuit layer, and the heating element is soldered.
The upper surface of the circuit layer includes an exposed portion exposed without being concealed by the lower surface of the metal layer,
The metal layer includes a rising surface arranged in a rising manner with respect to the exposed portion of the upper surface of the circuit layer;
An insulating substrate, wherein an excess brazing material of the brazing material layer is filled in a corner portion between the exposed portion of the upper surface of the circuit layer and the rising surface of the metal layer. The rising surface of the metal layer includes an outer peripheral side surface of the metal layer;
The exposed portion of the upper surface of the circuit layer includes a first exposed portion exposed outside the outer peripheral side surface of the metal layer;
The surplus brazing filler metal of the brazing filler metal layer is filled in the first corner between the first exposed portion on the upper surface of the circuit layer and the outer peripheral side surface of the metal layer as the corner. The insulating substrate described.   With the outer peripheral edge of the lower surface of the metal layer partially aligned with the outer peripheral edge of the upper surface of the circuit layer, the lower surface of the metal layer is brazed to the upper surface of the circuit layer via the brazing material layer. The insulating substrate according to claim 1 or 2, wherein The outer peripheral edge shape of the upper surface of the circuit layer is a polygonal shape having a plurality of corners and a plurality of sides,
The outer peripheral edge shape of the lower surface of the metal layer corresponds to the outer peripheral edge shape of the upper surface of the circuit layer and is a shape in which at least one corner portion is removed among the plurality of corner portions,
The sides of the outer peripheral edge of the lower surface of the metal layer are aligned with the sides of the outer peripheral edge of the upper surface of the circuit layer, and the lower surface of the metal layer is on the upper surface of the circuit layer. Is brazed through,
The insulating substrate according to claim 2, wherein the first exposed portion on the upper surface of the circuit layer includes the region of the at least one corner portion on the upper surface of the circuit layer. The upper surface of the metal layer has a planned soldering part to which the heating element is soldered and a non-soldering scheduled part to which the heating element is not soldered,
The non-soldered portion on the upper surface of the metal layer is provided with a through hole penetrating to the lower surface side of the metal layer,
The rising surface of the metal layer includes an inner peripheral side surface of the through hole of the metal layer,
The exposed portion of the upper surface of the circuit layer includes a second exposed portion exposed inside the inner peripheral side surface of the through hole of the metal layer,
The excess brazing filler metal of the brazing filler metal layer is filled in the second corner between the second exposed portion on the upper surface of the circuit layer and the inner peripheral side surface of the through hole of the metal layer as the corner. The insulating substrate according to claim 1.   The insulating substrate according to claim 1, wherein the metal layer includes a Ni layer, and an upper surface of the metal layer is formed on an upper surface of the Ni layer.   The insulating substrate according to claim 6, wherein the metal layer includes an Al layer, and a lower surface of the metal layer is formed by a lower surface of the Al layer.   The metal layer includes a Ti layer disposed between the Ni layer and the Al layer, and the Ni layer, the Ti layer, and the Al layer are bonded and integrated in a stacked manner. Item 8. The insulating substrate according to Item 7. An insulating substrate according to any one of claims 1 to 8,
And a radiator disposed on the lower surface side of the insulating substrate. An insulating substrate according to any one of claims 1 to 8,
A radiator disposed on the lower surface side of the insulating substrate;
And a semiconductor element as a heating element soldered to the upper surface of the metal layer of the insulating substrate. A brazing step of brazing the lower surface of the metal layer disposed in a stacked manner with respect to the circuit layer on the upper surface of the aluminum circuit layer via a brazing material layer;
The upper surface of the metal layer has better solderability than the upper surface of the circuit layer, and the heating element is soldered.
The upper surface of the circuit layer includes an exposed portion that is exposed without being hidden by the lower surface of the metal layer,
The metal layer includes a rising surface arranged in a rising manner with respect to the exposed portion of the upper surface of the circuit layer,
In the brazing step, the lower surface of the metal layer is brazed to the upper surface of the circuit layer via the brazing material layer, so that the exposed portion of the upper surface of the circuit layer and the rising surface of the metal layer are A method for manufacturing an insulating substrate, comprising: filling a surplus brazing material of the brazing material layer in the corners between them. The rising surface of the metal layer includes an outer peripheral side surface of the metal layer;
The exposed portion of the upper surface of the circuit layer includes a first exposed portion exposed outside the outer peripheral side surface of the metal layer;
In the brazing step, by brazing the lower surface of the metal layer to the upper surface of the circuit layer via the brazing material layer, the surplus brazing material of the brazing material layer is used as the corner portion of the circuit layer. The method for manufacturing an insulating substrate according to claim 11, wherein a first corner portion between the first exposed portion on the upper surface and the outer peripheral side surface of the metal layer is filled.   In the brazing step, the outer peripheral edge of the lower surface of the metal layer is partially aligned with the outer peripheral edge of the upper surface of the circuit layer, and the lower surface of the metal layer is placed on the upper surface of the circuit layer. The manufacturing method of the insulated substrate of Claim 11 or 12 brazed via a layer. The outer peripheral edge shape of the upper surface of the circuit layer is a polygonal shape having a plurality of corners and a plurality of sides,
The outer peripheral edge shape of the lower surface of the metal layer corresponds to the outer peripheral edge shape of the upper surface of the circuit layer and is a shape in which at least one corner portion is removed among the plurality of corner portions,
In the brazing step, the sides of the outer peripheral edge of the lower surface of the metal layer are aligned with the sides of the outer peripheral edge of the upper surface of the circuit layer, and the metal layer is formed on the upper surface of the circuit layer. The lower surface is brazed via the brazing material layer,
13. The method for manufacturing an insulating substrate according to claim 12, wherein the first exposed portion on the upper surface of the circuit layer includes the region of the at least one corner portion on the upper surface of the circuit layer. The upper surface of the metal layer has a planned soldering part to which the heating element is soldered and a non-soldering scheduled part to which the heating element is not soldered,
The non-soldered portion on the upper surface of the metal layer is provided with a through hole penetrating to the lower surface side of the metal layer,
The rising surface of the metal layer includes an inner peripheral side surface of the through hole of the metal layer,
The exposed portion of the upper surface of the circuit layer includes a second exposed portion exposed inside the inner peripheral side surface of the through hole of the metal layer,
In the brazing step, by brazing the lower surface of the metal layer to the upper surface of the circuit layer via the brazing material layer, the surplus brazing material of the brazing material layer is used as the corner portion of the circuit layer. The method for manufacturing an insulating substrate according to claim 11, wherein the second corner between the second exposed portion on the upper surface and the inner peripheral side surface of the through hole of the metal layer is filled.   The method for manufacturing an insulating substrate according to claim 11, wherein the metal layer includes a Ni layer, and an upper surface of the metal layer is formed on an upper surface of the Ni layer.   The method for manufacturing an insulating substrate according to claim 16, wherein the metal layer includes an Al layer, and a lower surface of the metal layer is formed by a lower surface of the Al layer.   The metal layer includes a Ti layer disposed between the Ni layer and the Al layer, and the Ni layer, the Ti layer, and the Al layer are bonded and integrated in a stacked manner. Item 18. A method for manufacturing an insulating substrate according to Item 17.   A method for manufacturing a heat radiating device, comprising fixing a heat radiator to the lower surface of the insulating substrate according to claim 1. While fixing a radiator to the lower surface of the insulating substrate according to any one of claims 1 to 8,
A method of manufacturing a semiconductor module, comprising: soldering a semiconductor element as a heating element to an upper surface of a metal layer of the insulating substrate.

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