JP2014160335A - Memory management device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a block search time during parallel writing by efficiently searching an unused block in the case of performing parallel writing of continuously inputted data to a plurality of memories connected to the same bus.SOLUTION: A bit map information by block numbers storage part 107 stores bit map information by block numbers representing with a bit map whether blocks having a common block number are respectively used or unused in each different block number. An empty block management part 106 sequentially analyzes bit maps in each different block number of the bit map information by block numbers, and searches an unused block in the case that parallel writing is performed.

Description

  The present invention relates to a technique for recording data input at a constant speed in parallel on a plurality of storage media connected to the same bus.

For example, with an artificial satellite, observation data generated by observation equipment (cameras and sensors) must be held in the satellite while flying in a range that cannot communicate with the ground (for example, Japan) (for example, behind the earth). , Equipped with a data recording device.
On the other hand, the observation device is a low-function device, and observation data cannot be stored inside the device, so it is difficult to realize flow control for data transmission with the data recording device.
In addition, with the increase in definition of observation equipment (cameras and sensors), observation data input to a data recording device has become larger and faster.
However, even in a data recording device, the memory that can operate normally in the space environment is limited, so a huge buffer memory cannot be held, and since it is a vacuum, the discharge means is scarce and the electronic equipment cannot be operated at high speed. There are circumstances.

  In data recording devices, with the increase in observation data from observation devices, large capacity and low power consumption non-volatile memory such as NAND flash memory is being installed. However, this is a storage medium having characteristics that require time for data recording. For this reason, data recording time cannot be achieved in one device chip as the observation data from the observation equipment increases.

  As an improvement in the data recording performance of the NAND flash memory, there is a method in which a plurality of NAND flash memories are connected to the same memory bus and parallel writing is performed on the plurality of NAND flash memories.

In FIG. 7, the structure of the NAND flash memory device chip is briefly introduced.
Hereinafter, the device chip of the NAND flash memory is also referred to as a NAND flash memory chip.

The NAND flash memory chip 200 includes a memory interface unit 201, a command processing unit 202, a page buffer 203, and a NAND flash memory 204 in one device chip.
The memory interface unit 201 is an interface with a memory bus.
The command processing unit 202 processes commands such as Read / Write / Erase sent from the host computer via the memory interface unit 201.
The page buffer 203 temporarily holds data to be read / written.
In the NAND flash memory 204, memory elements that actually hold data are arranged.

The NAND flash memory 204 is divided into a plurality of blocks, and one block is further divided into a plurality of pages.
In order to record new data, the data must be erased once, but the erase unit is called a block.
On the other hand, data write / read can be performed in units of pages.
FIG. 7 shows that one NAND flash memory 204 is composed of (y) blocks, and one block is composed of (x) pages.
Currently, a page generally has a recording capacity of 1 to 4 Kbytes, and a block has a recording capacity of 64 to 256 Kbytes.

FIG. 8 shows a write sequence for such a NAND flash memory 204.
First, the first command is sent from the host computer.
The first command usually includes address information indicating a block number to be written and a page number in the block.
Next, one page of data is transferred from the host computer.
The transferred data is temporarily held in the page buffer 203 in FIG.
Next, a second command is sent from the host computer.
In the NAND flash memory chip 200, triggered by the second command, the data held in the page buffer 203 in FIG. 7 is changed to a predetermined block indicated by the address information in the first command of the NAND flash memory 204 in FIG. In-chip write processing for transferring to a page is started.
In the host computer, it is necessary to wait for the completion of the in-chip write process in the NAND flash memory chip 200 before starting another process sequence.

Writing to the NAND flash memory 204 from the host computer is processed in the above sequence, but the memory bus connecting the host computer and the NAND flash memory chip 200 becomes empty during the on-chip writing process. By performing a sequence (from the first command transmission to the second command transmission in FIG. 8) to another NAND flash memory chip connected to the same bus, it is possible to improve the writing performance of the entire device.
This is shown in FIG.

  In FIG. 9, the state of parallel writing to the NAND flash memory chip # 1 (hereinafter simply referred to as chip # 1) and the NAND flash memory chip # 2 (hereinafter simply referred to as chip # 2) is shown in time series.

First, the host computer sends a write sequence for chip # 1 onto the memory bus.
Next, when the chip # 1 enters the in-chip write processing state, a write sequence for the chip # 2 is sent onto the memory bus.
As can be seen from FIG. 9, two pages of data are written by performing the above parallel writing. However, on the time axis, the in-chip writing process of chip # 1 is concealed (or chip) As a result, the chip writing process of # 1 is shortened).
If it is assumed that the time from sending the first command to sending the second command (usually, the write data transfer time is dominant) and the time for the in-chip write processing are equal, the two device chips shown in FIG. When writing is performed, writing can be performed in 3/4 time compared to the time for writing two pages in normal writing (that is, the writing performance is improved by about 33%).

Conventionally, as a method for controlling the NAND flash memory shown in FIG.
In Patent Document 1, a method as shown in FIG. 6 is used.

In FIG. 6, a NAND flash memory chip 200 is a device chip having the internal structure of FIG. 7, and is connected to the host computer 400 via the memory bus 300.
In the host computer 400, a command interface unit 401 is an interface with a higher system, for example, a file system of an operating system.
The read function unit 402 processes a read command instructed from the host system via the command interface unit 401.
The write function unit 403 processes a write command instructed from the host system via the command interface unit 401.
The erasing function unit 404 processes an erasing command instructed from the higher system via the command interface unit 401.
The address conversion function unit 405 converts a logical address designated by the host system into a block number and page number in the NAND flash memory 204.
The empty block management unit 406 manages the state of each block in the NAND flash memory 204.
The per-memory bitmap information storage unit 407 stores per-memory bitmap information that represents the state of each block of each NAND flash memory 204 as a bitmap.
The memory interface unit 408 executes a sequence with the NAND flash memory chip 200 as shown in FIG. 8 based on an instruction from each functional unit.

  In FIG. 6, data writing to one page of the NAND flash memory 204 is processed as follows.

First, the host system instructs the command interface unit 401 to write data specifying a logical address.
The command interface unit 401 calls the write function unit 403 because the instructed command is write.
The write function unit 403 calls the free block management unit 406 to obtain one block in which data can be written, that is, one erased free block.
Next, the write function unit 403 designates the obtained empty block to the memory interface unit 408 and instructs the memory interface unit 408 to execute the write sequence.
The memory interface unit 408 executes the write sequence shown in FIG. 8 via the memory bus 305, and returns control to the write function unit 403 when the in-chip write processing is completed.
The write control unit 403 calls the address conversion function unit 405 to store the correspondence between the logical address designated by the host system and the block number where data is actually written.

  The written data is read from the read function unit 402 by designating the block number in the device chip converted by the address conversion function unit 405. This is notified to the management unit 406 and managed as erased, that is, as an empty block, and prepared for the next data writing.

Next, an empty block search method in the conventional empty block management unit 406 will be described with reference to FIGS.
FIG. 10 shows a configuration of bit map information for each memory in which each block is vacant / in use with 1 bit.
The bit map information for each memory represents a vacant state of a block for each NAND flash memory chip 200 as a bit map.
More specifically, the state of block # 1 of chip # 1 is represented by bit 1 of the bitmap for chip # 1, the state of block # 2 is represented by bit 2, and the state of block #X of chip #N is This is represented by bit X in the chip #N bitmap.
Normally, if the value of the bit is “0”, the corresponding block is in use, and if it is “1”, it indicates that it is empty.

  FIG. 11 is a flow of search processing for an empty block using a bitmap of bitmap information for each memory.

The empty block management unit 406 puts “1” into the variable chipno in step S111 in order to search for an empty block from the chip # 1.
Step S112 is for checking whether the bitmaps for all chips have been searched. The empty block management unit 406 compares the variable chipno with the number N of NAND flash memory chips connected to the same bus.
If all the bitmaps have not been searched, the process advances to step S113, and the free block management unit 406 searches the bitmap information corresponding to the chip indicated by the value of the variable chipno from bit 1 and sets the bit value “1”. Search for '.
In step S114, it is determined whether or not there is a bit value “1” as a result of the search of the bitmap. If “1” is present, an empty block is detected, and the process proceeds to step S116. After that, the search for an empty block is terminated.

If a bit having the value “1” cannot be detected in the bitmap in step S114, the process proceeds to step S115, and the free block management unit 406 adds one to the variable chipno, and then returns to step S112.
If it is determined in step S112 that all the bitmaps have been searched, no empty block exists in any chip, and the empty block search ends as a failure.

International Publication WO2009-001514

  Conventionally, since the NAND flash memory is controlled as described above, when performing parallel writing to M NAND flash memories, N NAND flash memory chips connected to the same memory bus are The processing shown in FIG. 11 must be performed to obtain M free blocks for the number of parallel writes, and the free block management unit specifies the number of NAND flash memory chips connected to the same memory bus and is free It is necessary to add a function to obtain a block.

  It works well in systems that can have a huge buffer in the host system, such as use in a personal computer, and can wait for the next write command to be issued until the write is complete. If the data to be recorded is continuous data and cannot have a huge buffer, as in the system, the processing time increases by repeatedly calling the empty block management unit (for the number of parallel writes), There is a problem that defects occur.

  Or, in order to avoid this problem, the flow control that waits for the next data input to the host system during writing to the block or a sufficiently large buffer memory in the data recording device is conventionally installed. There is a problem that must be done.

  The main object of the present invention is to solve such a problem, and it is a main object to efficiently search for unused blocks and reduce the block search time during parallel writing.

The memory management device according to the present invention includes:
Each memory size is the same, and each is an N (N ≧ 2) memory that is equally divided into X (X ≧ 2) blocks, each of which is i-th (1 ≦ i ≦ 1). X) the block number of the block is connected to N memories that are common among the memories,
A block number-specific bitmap information storage unit that stores block number-specific bitmap information that represents whether each of the N blocks having the same block number is used or not, in a bitmap, for each block number; ,
When data is written in parallel to M blocks of M (1 ≦ M ≦ N) memories, the block number-specific bitmap information of the block number-specific bitmap information is sequentially analyzed to obtain M pieces. And an empty block management unit for searching for unused blocks.

In the present invention, for each block number, the block number-specific bitmap information is used to indicate whether the N blocks having the same block number are used or not. Sequential analysis is performed to search for M unused blocks.
For this reason, an unused block can be searched efficiently, and the block search time at the time of parallel writing can be shortened.

The figure which shows the structural example of the NAND flash control apparatus in Embodiment 1 and Embodiment 2. FIG. FIG. 3 is a diagram illustrating block number-specific bitmap information according to the first embodiment. FIG. 3 is a flowchart of an empty block search process in an empty block management unit according to the first embodiment. FIG. 6 is a diagram illustrating block number-specific bitmap information according to the second embodiment. FIG. 10 is a flow chart of empty block search processing in an empty block management unit according to the second embodiment. The figure which shows the apparatus structure which connected the several NAND flash memory to the same memory bus. The figure which shows the general internal structure of the device chip | tip of NAND flash memory. The figure which shows the write-in sequence from the outside with respect to the device chip of NAND flash memory. The figure which shows the method of parallel writing. The figure explaining the conventional bitmap information classified by memory. The free block search processing flowchart of the conventional free block management part.

Embodiment 1 FIG.
In the present embodiment, conventionally, the free block management bitmap information held for each chip of the NAND flash memory is held as a single piece of bitmap information by holding the free state of the same block number of each chip. In securing free blocks in data write processing, processing that repeatedly searches for huge bitmap information for each chip is unnecessary, avoiding an increase in free block search time during parallel writing, and continuous data can be recorded without data loss. A data recording apparatus is provided.

  FIG. 1 shows a configuration example of a NAND flash control device which is a data recording device according to the present embodiment.

1, N (N ≧ 2) NAND flash memory chips 200 are the same as those shown in FIG. 6, and have the internal configuration shown in FIG.
The host computer 100 corresponds to the host computer 400 shown in FIG.
Also in this embodiment, the host computer 100 and the N NAND flash memory chips 200 are connected by the memory bus 300.
The host computer 100 corresponds to an example of a memory management device.

In the host computer 100, the command interface unit 101, the read function unit 102, the write function unit 103, the erase function unit 104, the address conversion function unit 105, and the memory interface unit 108 are the command interface unit 401 and the read function unit shown in FIG. 402, the write function unit 403, the erase function unit 404, the address conversion function unit 405, and the memory interface unit 408.
In this embodiment, a bitmap information storage unit 107 by block number is provided instead of the bitmap information storage unit 407 by memory shown in FIG.
The block number-specific bitmap information storage unit 107 stores bit number-specific bitmap information.
As shown in FIG. 10, the bitmap information for each memory indicates whether each of the X blocks in the same NAND flash memory chip 200 is used or unused in a unit of the NAND flash memory chip 200 as a bitmap. Information.
On the other hand, the bitmap information for each block number is information that represents whether each of the N blocks having the same block number is used or unused for each block number.
Details of the bitmap information by block number will be described later.
Further, in the present embodiment, since the bitmap information by block number is used instead of the bitmap information by memory, the empty block search algorithm by the empty block management unit 106 is different from the empty block management unit 406 in FIG.
The empty block management unit 106 searches for empty blocks by sequentially analyzing the bitmaps by block number of the bitmap information by block number.
Details of the empty block search algorithm by the empty block management unit 106 will be described later.

The host computer 100 is a memory controller including, for example, a CPU (Central Processing Unit), a RAM (Random Access Memory), and a ROM (Read Only Memory).
Further, the command interface unit 101 and the memory interface unit 108 are realized by an interface circuit, for example.
The read function unit 102, write function unit 103, erase function unit 104, address conversion function unit 105, and empty block management unit 106 are realized, for example, by the CPU executing a program.
Programs for realizing the functions of the read function unit 102, the write function unit 103, the erase function unit 104, the address conversion function unit 105, and the empty block management unit 106 are stored in, for example, a ROM, and the CPU sequentially reads these programs. Run with.
At least some of the functions of the read function unit 102, the write function unit 103, the erase function unit 104, the address conversion function unit 105, and the empty block management unit 106 may be realized by hardware such as firmware or a circuit.
Also, the block number-specific bitmap information storage unit 107 is realized by, for example, a register or RAM in the CPU.
In the following, differences from the prior art will be described, and description of processing common to the prior art will be omitted.

  FIG. 2 shows the configuration of the block number-specific bitmap information in the first embodiment.

As shown in FIG. 2, each NAND flash memory chip 200 is equally divided into X (X ≧ 2) blocks of block # 1 to block #X, and the i-th (1 ≦ 1) of each NAND flash memory chip 200 is obtained. The block number of the block i ≦ X) is common among the N NAND flash memory chips 200.
The block number-specific bitmap information is composed of one, that is, X bitmaps for each identical block number.
That is, the block # 1 bitmap indicates the empty state of the block # 1 of the chip # 1 by bit 1 and the empty state of the block # 1 of the chip #N by bit N.
Also, the block #X bitmap represents the empty state of the block #X from the block #X to the chip #N of the chip # 1 by the bit 1 to the bit N, respectively.
In the bitmap information by block number according to the present embodiment, an unused block, that is, an empty block is represented by “1”.

  FIG. 3 is a flowchart showing an operation example of the empty block management unit 106 using the block number-specific bitmap information shown in FIG. 2 in the first embodiment.

In FIG. 3, M (1 ≦ M ≦ N) is given as the number of chips to be written in parallel, and a search for an empty block is started. In order to search for an empty block from the block # 1 bitmap, a variable blkno is set in step S31. Put '1' in
Step S32 is for checking whether all the bitmaps have been searched. The free block management unit 106 compares the variable blkno with the total number of blocks X of each NAND flash memory.
If all the bitmaps have not been searched, the process proceeds to step S33, the bitmap corresponding to the block number indicated by the value of the variable blkno is searched, and the number of bits having the value “1” is searched.
In step S34, as a result of the search, the free block management unit 106 determines the number of bit values “1”. If there are M or more “1” s, the number of free blocks is detected, and the process proceeds to step S36. After updating the bitmap (by changing the bit of “1” from the top to “0” by M in the search), the search for the empty block is ended.
If M or more bits having the value “1” cannot be detected in the bitmap in step S34, the process proceeds to step S35, and after adding the variable blkno, the process returns to step S32.
If it is determined in step S32 that all the bitmaps have been searched, there are no M empty blocks in any block number, and the empty block search ends as a failure.

As described above, it is possible to retrieve a set of free blocks suitable for parallel writing by searching for a small number of small bitmaps equal to the number of loops required for bit search for a single conventional chip. Parallel write processing can be performed with the same amount of processing as extracting one empty block, and as a result, continuous input data can be recorded without loss.
In the prior art, in order to search for M empty blocks, it is necessary to repeat the loop of FIG. 11 at least M times.
On the other hand, in this embodiment, it may be possible to search for M free blocks by performing the process of FIG. 3 only once.

  In FIG. 3, M and N may be arbitrary values as long as the condition of (N ≧ M) is satisfied, and M = 1, that is, can be used for securing the same free block as in the conventional example.

As described above, in the present embodiment,
A data recording apparatus for recording continuous input data in parallel on a plurality of storage media connected on the same bus,
(1) An empty block management unit that holds a block state and a data recording state for each block obtained by dividing the recording medium into a fixed size;
(2) The empty block management unit includes bitmap information indicating empty states of the blocks of a plurality of storage media connected on the same bus for each same block number,
(3) A data recording apparatus has been described in which the bitmap information is searched in the order of block numbers to secure empty blocks equal to the number of blocks to be recorded in parallel.

Embodiment 2. FIG.
In the second embodiment, the block number-specific bitmap information obtained by adding the number of bit values “1” to each bitmap of the block number-specific bitmap information in the first embodiment is used in step (S33) of FIG. A method for performing a process corresponding to the bitmap search at a higher speed will be described.
A configuration example of the NAND flash control device according to the present embodiment is also the same as that shown in FIG.
The only difference from the first embodiment is that the number of bit values '1' is added to the block number-specific bitmap information and the operation example of the empty block management unit 106 is different.

  FIG. 4 shows the configuration of the block number-specific bitmap information in the second embodiment.

In FIG. 4, the block # 1 bitmap to the block #X bitmap are the same as those in FIG.
In each bitmap, an area for holding the number of bits of the bit value “1” in each bitmap, that is, the number of empty blocks is added.

  FIG. 5 is a flowchart showing an operation example of the empty block management unit 106 using the block number-specific bitmap information shown in FIG. 4 in the second embodiment.

In FIG. 5, M (1 ≦ M ≦ N) of the number of chips to be written in parallel is given, and a search for an empty block is started. In order to search for an empty block from the block # 1 bitmap, a variable blkno is set in step S51. Put '1' in
Step S52 is for checking whether all bitmaps have been searched. The free block management unit 106 compares the variable blkno with the total number X of blocks in each NAND flash memory.
If all the bitmaps have not been searched, the process proceeds to step S53, and the free block management unit 106 obtains the number of free blocks free added to the bitmap corresponding to the block number indicated by the value of the variable blkno.
In step S54, the free block management unit 106 checks the value of free, and if it is equal to or greater than M, the free block management unit 106 determines that the necessary number of free blocks can be secured, and proceeds to step S56, from which the bit value “1”, That is, after searching for an empty block, the bit map is updated in step S57 (the bit of “1” is changed to “0” by M from the head in the search, and M is subtracted from the number of empty blocks). End the block search.
If freeno is smaller than M in step S54, it is determined that the required number M of empty blocks cannot be secured from the corresponding bitmap, and the process proceeds to step S55. After adding the variable blkno, the process returns to step S52. .
If it is determined in step S52 that all the bitmaps have been searched, no chip having M empty blocks exists in any block number, so that the empty block search ends as a failure.

As described above, by replacing the bitmap search in step S33 of FIG. 3 in the first embodiment with the extraction of variables, the M empty block searches in the first embodiment can be processed at higher speed, and the result As a result, it is possible to record higher-speed continuous input data without any loss.
That is, according to the present embodiment, the analysis of the bitmap can be omitted for the block number for which the number of empty blocks is insufficient, so that the empty block search can be processed at a higher speed.

  In FIG. 5, M and N may be arbitrary values as long as the condition of (N ≧ M) is satisfied, and M = 1, that is, can be used for securing the same free block as the conventional example.

  In the present embodiment, the data recording apparatus has been described in which the number indicating the empty block in the bitmap information is held in the bitmap information for each identical block number.

  In the first and second embodiments, the description has been made on the NAND flash memory. However, if the memory is equally divided into a plurality of blocks, the memory targeted by the present invention is the NAND flash memory. Not limited to.

  DESCRIPTION OF SYMBOLS 100 Host computer, 101 Command interface part, 102 Read function part, 103 Write function part, 104 Erase function part, 105 Address conversion function part, 106 Empty block management part, 107 Bit number information storage part by block number, 108 Memory interface part , 200 NAND flash memory chip, 300 memory bus.

Claims (5)

Each memory size is the same, and each is an N (N ≧ 2) memory that is equally divided into X (X ≧ 2) blocks, each of which is i-th (1 ≦ i ≦ 1). X) the block number of the block is connected to N memories that are common among the memories,
A block number-specific bitmap information storage unit that stores block number-specific bitmap information that represents whether each of the N blocks having the same block number is used or not, in a bitmap, for each block number; ,
When data is written in parallel to M blocks of M (1 ≦ M ≦ N) memories, the block number-specific bitmap information of the block number-specific bitmap information is sequentially analyzed to obtain M pieces. And a free block management unit that searches for unused blocks. The block number-specific bitmap information storage unit
For each block number, the N blocks having the same block number are each used as a bitmap, indicating whether each of the N blocks is used or unused, and also indicating the number of unused blocks among the N blocks The memory management device according to claim 1, wherein bitmap information is stored. The empty block management unit
When there are M or more unused blocks in any block number, the block number bitmap is changed so that the block number indicates that M blocks are newly used. The memory management device according to claim 1, wherein: The empty block management unit
When there are M or more unused blocks in any block number, the block number bitmap is changed so that the block number indicates that M blocks are newly used. The memory management device according to claim 2, wherein the number of unused blocks of the block number is reduced by M. The memory management device includes:
The memory management device according to claim 1, wherein the memory management device is connected to N NAND flash memories.

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