JP2014158176A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that in a conventional flip-flop, the power consumption cannot be sufficiently reduced.SOLUTION: A semiconductor device includes: a disparity detection circuit 11 for detecting a disparity between input data and output data and outputting a disparity detection signal S11; a set-reset latch 12 for generating an internal clock signal CKx on the basis of the disparity detection signal S11 and an operational clock signal CKS; and a data holding section 15 for holding the input data by using the internal clock signal CKx as a trigger signal. The set-reset latch is constituted from a reverse OR circuit or a reverse AND circuit.

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device on which an edge trigger type flip-flop is mounted.

  In recent years, semiconductor devices have been strongly demanded to reduce power consumption. The semiconductor device includes, for example, a clock tree that transmits an operation clock signal and a flip-flop that performs a data holding operation based on the operation clock signal. In such a semiconductor device, current consumption in the clock tree and the flip-flop increases as the operating clock signal increases.

  Thus, Patent Documents 1 to 6 disclose examples of flip-flops that perform a conditional clock operation that suppresses the operation of an internal transistor according to an operation clock signal when there is no transition of input data. By performing this conditional clock operation, it is possible to suppress the toggle of the internal transistor according to the operation clock, so that the power consumption in the flip-flop can be reduced. Patent Documents 7 to 10 disclose techniques for improving hazard resistance in flip-flops that perform a conditional clock operation.

  The flip-flops described in Patent Documents 1 to 6 have a problem of causing a malfunction when a hazard occurs in input data. By using the technology disclosed in Patent Documents 7 to 10, the problem of the hazard is solved. can do. However, the flip-flops described in Patent Documents 7 to 10 have more transistors that receive an operation clock signal in the flip-flop than the flip-flops described in Patent Documents 1 to 6 in order to improve hazard resistance. For this reason, the flip-flops described in Patent Documents 7 to 10 have a problem that the input capacitance of the clock input terminal increases, and the power consumption increases due to the increase of the input capacitance.

  In view of this, the technique described in Non-Patent Document 1 discloses a technique for improving hazard resistance while maintaining the same input capacitance as the flip-flops described in Patent Documents 1 to 6.

JP 2006-229745 A Japanese Patent Laid-Open No. 10-41789 JP-A-4-298115 Japanese Patent Laid-Open No. 10-163820 JP-A-1-286609 JP 2000-13195 A JP-A-11-340795 JP 2004-56667 A JP-A-8-274594 JP 2000-232339 A

AGM Strollo, E. Napoli, D. De Caro, "New Clock-Gating Techniques for Low-Power Flip-Flops", Low Power Electronics and Design, 2000. ISLPED '00. Proceedings of the 2000 International Symposium on, pp. 114 -119, 2000

  However, the technique described in Non-Patent Document 1 has a problem that the gating circuit becomes unstable at the timing when the gating circuit transitions from the clock cutoff state to the clock passing state.

  According to one embodiment, a semiconductor device detects a mismatch between input data and output data and generates a mismatch detection signal, and generates an internal clock signal based on the mismatch detection signal and the operation clock signal. A set reset latch and a data holding unit for holding input data using an internal clock signal as a trigger signal are provided, and the set reset latch is configured using an inverting OR circuit or an inverting AND circuit.

  According to one embodiment, a semiconductor device with high stability and low power consumption can be provided.

1 is a block diagram of a flip-flop according to a first exemplary embodiment; 3 is a truth table showing a relationship between an input value to an internal clock generation unit of the flip-flop according to the first embodiment and an internal clock signal; 1 is a circuit diagram of a mismatch detection circuit of a flip-flop according to a first embodiment; 3 is a truth table of the mismatch detection circuit of the flip-flop according to the first embodiment; 3 is a circuit diagram of an SR latch of the flip-flop according to the first embodiment; FIG. 3 is a truth table of the SR latch of the flip-flop according to the first embodiment; 3 is a circuit diagram of a data holding unit of the flip-flop according to the first embodiment; FIG. 3 is a timing chart showing the operation of the flip-flop according to the first exemplary embodiment; 2 is a circuit diagram of a flip-flop described in Non-Patent Document 1. FIG. 10 is a circuit diagram illustrating a problem of a flip-flop gating circuit described in Non-Patent Document 1. FIG. 10 is a circuit diagram illustrating a problem of a flip-flop gating circuit described in Non-Patent Document 1. FIG. 10 is a circuit diagram illustrating a problem of a flip-flop gating circuit described in Non-Patent Document 1. FIG. FIG. 3 is a circuit diagram for explaining the operation of the SR latch of the flip-flop according to the first embodiment; FIG. 3 is a circuit diagram for explaining the operation of the SR latch of the flip-flop according to the first embodiment; FIG. 3 is a circuit diagram for explaining the operation of the SR latch of the flip-flop according to the first embodiment; 6 is a graph illustrating a difference in stability between the flip-flop according to the first embodiment and the flip-flop described in Non-Patent Document 1. FIG. 5 is a circuit diagram of a flip-flop that does not control a clock signal. 3 is a graph comparing power consumption of a semiconductor device including a flip-flop according to the first embodiment and a semiconductor device including another flip-flop. 4 is a graph showing a difference in power consumption depending on output data of the flip-flop according to the first embodiment and a general flip-flop. FIG. 3 is a block diagram of a flip-flop according to a second exemplary embodiment. 10 is a truth table showing a relationship between an input value to the SR latch of the flip-flop according to the second embodiment and an internal clock signal; FIG. 6 is a circuit diagram of a flip-flop mismatch detection circuit according to a second embodiment; 5 is a truth table of a mismatch detection circuit of a flip-flop according to a second embodiment; 6 is a circuit diagram of an SR latch of a flip-flop according to a second embodiment; FIG. 10 is a truth table of the SR latch of the flip-flop according to the second embodiment; 6 is a timing chart showing the operation of the flip-flop according to the second exemplary embodiment; FIG. 6 is a block diagram illustrating a modification of the flip-flop according to the first embodiment. FIG. 22 is a truth table showing a relationship between an input value to the SR latch of the flip-flop shown in FIG. 21 and an internal clock signal. FIG. 10 is a block diagram showing a modification of the flip-flop according to the second exemplary embodiment; 24 is a truth table showing a relationship between an input value to the SR latch of the flip-flop shown in FIG. 23 and an internal clock signal. FIG. 6 is a circuit diagram of a flip-flop according to a fourth embodiment; FIG. 6 is a circuit diagram of an exclusive OR circuit of a flip-flop according to a fourth embodiment; FIG. 6 is a circuit diagram of an SR latch of a flip-flop according to a fourth embodiment; FIG. 10 is a circuit diagram of a flip-flop as a comparative example of the flip-flop according to the fourth embodiment; FIG. 10 is a circuit diagram of an exclusive inversion OR circuit used in another form of the flip-flop according to the fourth embodiment. FIG. 10 is a circuit diagram of an SR latch used in another form of the flip-flop according to the fourth embodiment. FIG. 10 is a circuit diagram of a flip-flop according to a fifth embodiment; FIG. 10 is a circuit diagram of a flip-flop according to the first embodiment to which the mismatch detection circuit according to the fifth embodiment is applied. FIG. 10 is a schematic diagram of a layout of a flip-flop according to a fifth embodiment; FIG. 37 is a schematic diagram of a layout of the flip-flop shown in FIG. 36. 10 is a timing chart illustrating an operation of the flip-flop according to the fifth exemplary embodiment. 1 is a block diagram of a semiconductor device showing a circuit configuration as a first example of a semiconductor device including a flip-flop according to a first embodiment; FIG. 3 is a block diagram of a semiconductor device showing a circuit configuration of a second example of the semiconductor device including the flip-flop according to the first embodiment; FIG. 6 is a block diagram of a semiconductor device showing a circuit configuration of a third example of the semiconductor device including the flip-flop according to the first embodiment;

Embodiment 1
Hereinafter, embodiments will be described with reference to the drawings. Hereinafter, the circuit configuration of the flip-flop will be mainly described. However, the flip-flop is used as one of circuits constituting the semiconductor device. FIG. 1 is a block diagram of the flip-flop 1 according to the first embodiment.

  As shown in FIG. 1, the flip-flop 1 according to the first embodiment includes a data input terminal D, a clock input terminal CK, and a data output terminal Qo. The clock input terminal CK is a terminal to which a clock signal CKS is input. The data input terminal D is a terminal to which input data Din is input. The data output terminal Qo is a terminal for outputting the output data Do. The flip-flop 1 changes the logic level of the output data Do according to the rising edge of the clock signal CKS when a state transition (for example, a change in logic level) occurs in the input data Din. That is, in the flip-flop 1 according to the first embodiment, the clock signal CKS in which the first logic level in the period immediately before the trigger edge is low and the second logic level in the period immediately after the trigger edge is high is used. Based on this, the holding operation of the input data Din is performed.

  As illustrated in FIG. 1, the flip-flop 1 according to the first embodiment includes a clock control circuit 10 and a data holding unit 15. The clock control circuit 10 changes the logic level of the internal clock signal CKx according to the clock edge of the clock signal CKS only when the input data Din has a logic level different from that of the output data Do. That is, the clock control circuit 10 has a clock gating function corresponding to the input data Din and the output data Do. Then, the flip-flop 1 supplies the internal clock signal CKx to the data holding unit 15. The data holding unit 15 holds the input data Din using the internal clock signal CKx as a trigger signal. In the flip-flop 1 according to the first embodiment, the data holding unit 15 takes in the input data Din according to the rising edge, and sets the output data Do to a logic level according to the input data Din. That is, the flip-flop 1 uses a rising edge triggered flip-flop as the data holding unit 15. That is, in the flip-flop 1 according to the first embodiment, as the internal clock signal CKx, the third logic level in the period immediately before the trigger edge is low level, and the fourth logic level in the period immediately after the trigger edge is high level. Is used.

  In the following description, a signal that gives a trigger edge that instructs the data holding unit 15 to take in the input data Din is referred to as an internal clock signal CKx. The clock control circuit 10 generates an inverted internal clock signal CKxB having a logic level that is inverted from that of the internal clock signal CKx. The data holding unit 15 operates based on the internal clock signal CKx and the inverted internal clock signal CKxB. That is, when both the flip-flop 1 and the data holding unit 15 used in the flip-flop 1 are the rising edge trigger type, the clock control circuit 10 generates the internal clock signal CKx in accordance with the rising edge of the clock signal CKS. Launch. On the other hand, when the flip-flop is the falling edge trigger type and the data holding unit 15 used in the flip-flop is the rising edge trigger type, the clock control unit 10 sets the internal clock in accordance with the falling edge of the clock signal CKS. The signal CKx falls.

  The clock control circuit 10 includes a mismatch detection circuit 11 and an internal clock generation unit 12. The mismatch detection circuit 11 detects a mismatch between the input data Din and the output data Do and outputs a mismatch detection signal S11. In the flip-flop 1 according to the first embodiment, an exclusive OR circuit (indicated as XOR in the figure) is used as the mismatch detection circuit 11. The mismatch detection circuit 11 sets the mismatch detection signal S11 to a high level (for example, 1) in a state where the two input signals are detected to be mismatched (hereinafter referred to as a mismatch detection state). The mismatch detection signal S11 is set to a low level (for example, 0) in a state where it is detected that the match is detected (hereinafter referred to as a match detection state).

  The internal clock generator 12 has an internal clock signal CKx having a trigger edge corresponding to the trigger edge of the clock signal CKS when the trigger edge of the clock signal CKS is input when the mismatch detection signal S11 enters the mismatch detection state. Is generated. In order to explain more specifically, FIG. 2 shows a truth table showing the operation of the internal clock generator 12.

  First, in the flip-flop 1 according to the first embodiment, for the clock signal CKS, the logic level of the period immediately before the trigger edge is the first logic level (for example, low level or 0), and the logic level is immediately after the trigger edge. The logic level during this period becomes the second logic level (for example, high level or 1). The internal clock signal CKx has a logic level in the period immediately before the trigger edge as the third logic level (for example, low level or 0), and the logic level in the period immediately after the trigger edge is the fourth logic level. Level (for example, high level or 1).

  As shown in FIG. 2, when the mismatch detection signal S11 is in a match detection state (for example, low level), the internal clock generation unit 12 sets the internal clock signal CKx to a high level when the clock signal CKS becomes a high level. And When the mismatch detection signal S11 is at a low level, the internal clock generation unit 12 maintains the internal clock CKx at a high level even if the clock signal CKS toggles after the internal clock signal CKx once becomes a high level. Further, when the mismatch detection signal S11 is in a mismatch detection state (for example, high level), the internal clock generation unit 12 toggles the internal clock signal CKx so as to have the same logic level as the clock signal CKS.

  Here, the operation of the internal clock generation unit 12 will be described from another viewpoint. As shown in FIG. 2, the internal clock generator 12 sets the internal clock signal CKx to a low level when the mismatch detection signal S11 is in a mismatch detection state (for example, a high level) during a period in which the clock signal CKS is at a low level. . After that, when the clock signal CKS becomes high level by inputting the trigger edge of the clock signal CKS while the mismatch detection signal S11 maintains the mismatch detection state, the internal clock signal CKx has the logic level of the clock signal CKS. The internal clock signal CKx is switched from the low level to the high level in accordance with the switching. Further, even when the state of the mismatch detection signal S11 switches between the match detection state and the mismatch detection state during the period when the clock signal CKS is at the high level, the internal clock generation unit 12 maintains the internal clock signal CKx at the high level. To do. Further, when the state of the mismatch detection signal S11 is switched between the match detection state and the mismatch detection state during the period when the clock signal CKS is at the low level, the internal clock generation unit 12 once sets the internal clock signal CKx to the low level. The internal clock signal CKx is maintained at a low level.

  As shown in FIG. 2, the internal clock generation unit 12 outputs an inverted internal clock signal CKxB having a logic level inverted from the internal clock signal CKx in addition to the internal clock signal CKx.

  The internal clock generator 12 includes a set / reset latch (hereinafter referred to as SR latch) 13 and an inverter 14. The SR latch 13 has a set input terminal S, a reset input terminal R, a first output terminal (for example, a latch output terminal QL), and a second output terminal (for example, an inverted latch output terminal QLB). The SR latch 13 receives the mismatch detection signal S11 at one of the set input terminal S and the reset input terminal S, and receives an operation clock signal (for example, a clock signal CKS) at the other of the set input terminal S and the reset input terminal R. ) And the internal clock signal CKx is generated based on the mismatch detection circuit S11 and the clock signal CKS. In the first embodiment, the mismatch detection signal S11 is input to the set input terminal S as a set signal. A clock signal CKS is input to the reset input terminal R as a reset signal. As will be described in detail later, the SR latch 13 has a feature that the number of transistors to which the clock signal CKS is input is 2 or less.

  Then, the internal clock generator 12 outputs an inverted clock signal CKxB having a logic level that is inverted from the internal clock signal CKx from the latch output terminal QL of the SR latch 13. The internal clock generator 12 inverts the inverted clock signal CKxB by the inverter 14 and outputs the internal clock signal CKx.

  Subsequently, a detailed circuit configuration of each block of the flip-flop 1 according to the first embodiment will be described. First, a circuit diagram of the mismatch detection circuit 11 is shown in FIG. As shown in FIG. 3, the mismatch detection circuit 11 has a first input terminal In1, a second input terminal In2, and an output terminal OUT. The output data Do is supplied to the first input terminal In1, the input data Din is supplied to the second input terminal In2, and the mismatch detection signal S11 is output from the output terminal OUT. The mismatch detection circuit 11 includes an inverter, PMOS transistors P11 to P14, and NMOS transistors N11 to N14.

  The source of the PMOS transistor P11 is connected to a power supply terminal to which the power supply voltage VDD is supplied. The inverted output data DoB generated by inverting the output data Do with an inverter is applied to the gate of the PMOS transistor P11. The drain of the PMOS transistor P11 is connected to the source of the PMOS transistor P12. Inverted input data DinB generated by inverting input data Din with an inverter is applied to the gate of the PMOS transistor P12. The drain of the PMOS transistor P12 is connected to the output terminal OUT.

  The source of the PMOS transistor P13 is connected to the power supply terminal. Output data Do is supplied to the gate of the PMOS transistor P13. The drain of the PMOS transistor P13 is connected to the source of the PMOS transistor P14. Input data Din is applied to the gate of the PMOS transistor P14. The drain of the PMOS transistor P14 is connected to the output terminal OUT.

  The source of the NMOS transistor N12 is connected to the ground terminal to which the ground voltage VSS is supplied. Input data Din is applied to the gate of the NMOS transistor N12. The drain of the NMOS transistor N12 is connected to the source of the NMOS transistor P11. The inverted output data DoB generated by inverting the output data Do with an inverter is applied to the gate of the NMOS transistor N11. The drain of the NMOS transistor N11 is connected to the output terminal OUT.

  The source of the NMOS transistor N14 is connected to the ground terminal. Inverted input data DinB generated by inverting input data Din with an inverter is applied to the gate of NMOS transistor N14. The drain of the NMOS transistor N14 is connected to the source of the NMOS transistor N13. Output data Do is supplied to the gate of the NMOS transistor N13. The drain of the NMOS transistor N13 is connected to the output terminal OUT.

  With the above circuit configuration, the mismatch detection circuit 11 configures an exclusive OR circuit. Therefore, a truth table of the mismatch detection circuit 11 is shown in FIG. As shown in FIG. 4, in the mismatch detection circuit 11, the output data Do input to the first input terminal In1 and the input data Din input to the second input terminal In2 have different logic levels. Sometimes, the mismatch detection signal S11 output from the output terminal OUT is set to the high level. On the other hand, the mismatch detection circuit 11 outputs the output terminal when the output data Do input to the first input terminal In1 and the input data Din input to the second input terminal In2 have the same logic level. The mismatch detection signal S11 output from OUT is set to low level.

  Next, a detailed circuit of the SR latch 13 will be described. FIG. 5 shows a detailed circuit diagram of the SR latch 13. As shown in FIG. 5, the SR latch 13 includes a first inverted OR circuit (for example, inverted OR circuit NOR1) and a second inverted OR circuit (for example, inverted OR circuit NOR2). In the SR latch 13, the mismatch detection signal S11 is input to one of the first input terminal of the inverting OR circuit NOR1 and the first input terminal of the inverting OR circuit NOR2. The SR latch 13 receives a clock signal at the other of the first input terminal of the inverting OR circuit NOR1 and the first input terminal of the inverting OR circuit NOR2. Further, in the SR latch 13, the output terminal of the inverting OR circuit NOR1 and the second input terminal of the inverting OR circuit NOR2 are connected, and the output terminal of the inverting OR circuit NOR2 and the second terminal of the inverting OR circuit NOR1 are connected. Input terminal is connected.

  More specifically, the inverting OR circuit NOR1 has a first input terminal connected to the set terminal S and a second input terminal connected to the output terminal of the inverting OR circuit NOR2. The output terminal of the inverting OR circuit NOR1 is connected to the inverting latch output terminal QLB. The inverting OR circuit NOR2 has a first input terminal connected to the reset terminal R and a second input terminal connected to the output terminal of the inverting OR circuit NOR1. The output terminal of the inverting OR circuit NOR2 is connected to the latch output terminal QL. A signal output from the latch output terminal QL becomes an inverted internal clock signal CKxB. In the first embodiment, the mismatch detection signal S11 is input to the set terminal S, and the clock signal CKS is input to the reset terminal R.

  The inverting OR circuit NOR1 includes PMOS transistors P15 and P16 and NMOS transistors N15 and N16. The source of the PMOS transistor P15 is connected to the power supply terminal. The mismatch detection signal S11 is input to the gate of the PMOS transistor P15. The drain of the PMOS transistor P15 is connected to the source of the PMOS transistor P16. The gate of the PMOS transistor P16 is connected to the output terminal of the inverting OR circuit NOR2. The drain of the PMOS transistor P16 is connected to the inverting latch output terminal QLB. The sources of the NMOS transistors N15 and N16 are connected to the ground terminal. The drains of the NMOS transistors N15 and N16 are connected to the inverting latch output terminal QLB. The mismatch detection signal S11 is input to the gate of the NMOS transistor N15. The gate of the NMOS transistor N16 is connected to the output terminal of the inverting OR circuit NOR2.

  The inverting OR circuit NOR2 includes PMOS transistors P17 and P18 and NMOS transistors N17 and N18. The source of the PMOS transistor P17 is connected to the power supply terminal. The gate of the PMOS transistor P17 is connected to the output terminal of the inverting OR circuit NOR1. The drain of the PMOS transistor P17 is connected to the source of the PMOS transistor P18. The clock signal CKS is input to the gate of the PMOS transistor P18. The drain of the PMOS transistor P18 is connected to the latch output terminal QL. The sources of the NMOS transistors N17 and N18 are connected to the ground terminal. The drains of the NMOS transistors N17 and N18 are connected to the latch output terminal QL. The gate of the NMOS transistor N17 is connected to the output terminal of the inverting OR circuit NOR1. The clock signal CKS is input to the gate of the NMOS transistor N18. The PMOS transistors P17 and P18 correspond to the first transistor and the second transistor, and the NMOS transistors N17 and N18 correspond to the third transistor and the fourth transistor. In the description of the PMOS transistor and the NMOS transistor, the control terminal is a gate, the first terminal is a source, and the second terminal is a drain.

  Here, the truth table of the SR latch 13 is shown in FIG. 6, and the operation of the SR latch 13 will be described. As shown in FIG. 6, when the mismatch detection signal S11 is low level and the clock signal CKS is high level, the SR latch 13 sets the output value of the latch output terminal QL to low level and the output value of the inverting latch output terminal QLB. Is set to the high level. When the mismatch detection signal S11 is high level and the clock signal CKS is low level, the SR latch 13 sets the output value of the latch output terminal QL to high level and sets the output value of the inverting latch output terminal QLB to low level. When both the mismatch detection signal S11 and the clock signal CKS are at the low level, the SR latch 13 outputs the output value of the latch output terminal QL and the inverted latch output terminal QLB before the mismatch detection signal S11 and the clock signal CKS are both at the low level. Maintain the logic level of the output value. Furthermore, the SR latch 13 sets both the output value of the latch output terminal QL and the output value of the inverted latch output terminal QLB to the low level when both the mismatch detection signal S11 and the clock signal CKS are at the high level.

  In other words, in the flip-flop 1 according to the first embodiment, the latch output terminal QL and the inverted latch output terminal QLB, which are normally prohibited or can be used as conditions for use of the SR latch, have an input state in which both are at a low level. Use it actively. As a result, the SR latch 13 causes the rising edge of the clock signal CKS when the mismatch detection signal S11 is at a logic level where the input data Din and the output data Do are different (for example, when the mismatch detection signal S11 is at a high level). Only when is inputted, the internal clock signal CKx is toggled in accordance with the toggle of the clock signal CKS.

  Next, a detailed circuit of the data holding unit 15 will be described. FIG. 7 shows a detailed circuit diagram of the data holding unit 15. As shown in FIG. 7, the data holding unit 15 has a data input terminal DF, a clock input terminal TCA, an inverted clock input terminal TCB, and a data output terminal QF. Input data Din is input to the data input terminal DF, an internal clock signal CKx is input to the clock input terminal TCA, and an inverted internal clock signal CKxB is input to the inverted clock input terminal TCB. Further, the value output from the slave latch SL is output from the data output terminal QF. The logic level of the output data Do is determined by the value output from the data output terminal QF.

  As shown in FIG. 7, the data holding unit 15 includes a master latch MA and a slave latch SL. The master latch MA is in a through state in which the input data Din supplied from the data input terminal DF is transmitted to the slave latch SL while the internal clock signal CKx is at the low level. The master latch MA is in a hold state in which the value input to the master latch MA is held when the rising edge of the internal clock signal CKx is input while the internal clock signal CKx is at a high level. The slave latch SL is in a hold state in which the value input to the slave latch SL is held when the falling edge of the internal clock signal CKx is input while the internal clock signal CKx is at the low level. The slave latch SL is in a through state in which the value given from the master latch MA is output while the internal clock signal CKx is at a high level. That is, the master latch MA is a latch circuit that holds the value that is input when the rising edge of the internal clock signal CKx is input, and the slave latch SL is the input of the falling edge of the internal clock signal CKx. This is a latch circuit that holds a value input at the time. In other words, the master latch MA holds the held data in accordance with the first internal clock signal CKx included in the internal clock signal. The slave latch SL holds the output value of the master latch MA according to the second clock signal CKxB that is included in the internal clock signal and has a logic level that is inverted from that of the first internal clock signal.

  The master latch MA includes inverters INV1 to INV3, a transfer switch TSWa1, and a transfer switch TSWb1. The inverter INV1 inverts the input data Din and transmits it to the transfer switch TSWb1. The transfer switch TSWb1 is a switch circuit that becomes conductive when the internal clock signal CKx is at a low level and is cut off when the internal clock signal CKx is at a high level. The inverter INV2 further inverts the inverted signal of the input data Din input via the transfer switch TSWb1 and transmits the inverted signal to the slave latch SL. The inverter INV3 further inverts the output value of the inverter INV2 and returns it to the input of the inverter INV2. The transfer switch TSWa1 is provided between the output terminal of the inverter INV3 and the wiring connecting the input terminal of the inverter INV2 and the transfer switch TSWb1. The transfer switch TSWa1 is a switch circuit that is turned on when the internal clock signal CKx is at a high level and is cut off when the internal clock signal CKx is at a low level. That is, the transfer switch TSWa1 and the transfer switch TSWb1 are in a conductive state exclusively with each other.

  The transfer switch TSWb1 includes an NMOS transistor MN and a PMOS transistor MP. Then, one of the source / drain of the NMOS transistor MN and one of the source / drain of the PMOS transistor MP are connected to each other. The other of the source and drain of the NMOS transistor MN and the other of the source and drain of the PMOS transistor MP are connected to each other. The gate of the NMOS transistor MN is connected to the inverted clock input terminal TCB and is supplied with the inverted internal clock signal CKxB. The gate of the PMOS transistor MP is connected to the clock input terminal TCA and is supplied with the internal clock signal CKx.

  The transfer switch TSWa1 includes an NMOS transistor MN and a PMOS transistor MP. Then, one of the source / drain of the NMOS transistor MN and one of the source / drain of the PMOS transistor MP are connected to each other. The other of the source and drain of the NMOS transistor MN and the other of the source and drain of the PMOS transistor MP are connected to each other. The gate of the NMOS transistor MN is connected to the clock input terminal TCA and is supplied with the internal clock signal CKx. The gate of the PMOS transistor MP is connected to the inverted clock input terminal TCB and is supplied with the inverted internal clock signal CKxB.

  The slave latch SL includes inverters INV4 to INV6, a transfer switch TSWa2, and a transfer switch TSWb2. The transfer switch TSWa2 transmits the output value of the master latch MA to the inverter INV4. The transfer switch TSWa2 is a switch circuit that is turned on when the internal clock signal CKx is at a high level and is cut off when the internal clock signal CKx is at a low level. The inverter INV4 inverts the output value of the master latch MA input via the transfer switch TSWa2 and transmits it to the inverter INV6. The inverter INV5 further inverts the output value of the inverter INV4 and returns it to the input of the inverter INV4. The transfer switch TSWb2 is provided between the output terminal of the inverter INV5 and the wiring connecting the input terminal of the inverter INV4 and the transfer switch TSWa2. The transfer switch TSWb2 is a switch circuit that is turned on when the internal clock signal CKx is at a low level and is cut off when the internal clock signal CKx is at a high level. That is, the transfer switch TSWa2 and the transfer switch TSWb2 are in a conductive state exclusively with each other. The inverter INV6 inverts the output value of the inverter INV4 and transmits it to the data output terminal QF.

  The transfer switch TSWa2 has the same circuit configuration as that of the transfer switch TSWa1, and the transfer switch TSWb2 has the same circuit configuration as that of the transfer switch TSWb1.

  Next, the operation of the flip-flop 1 according to the first embodiment will be described. FIG. 8 is a timing chart showing the operation of the flip-flop 1. First, the period TM1 in FIG. 8 will be described. In the period TM1, the logic level of the input data Din changes from the low level to the high level before the timing T1 when the rising edge of the clock signal CKS is input. Therefore, in the period TM1, the mismatch detection circuit 11 sets the mismatch detection signal S11 to the high level as the logic level of the input data Din is switched. Further, in response to the mismatch detection signal S11 becoming high level, the SR latch 13 sets the internal clock signal CKx to low level. At this time, the master latch MA changes from the hold state to the through state, and the slave latch SL changes from the through state to the hold state. That is, the master latch MA transmits a signal whose logic level is high in accordance with the input data Din to the slave latch SL, and the slave latch SL is supplied from the master latch MA during a period before the input data Din is high. The logic level (that is, low level) of the received signal is held.

  When the rising edge of the clock signal CKS is input at timing T1, the SR latch 13 changes the internal clock signal CKx from the low level to the high level. In response to the rising edge of the internal clock signal CKx, the master latch MA of the data holding unit 15 changes from the through state to the hold state, and holds the value of the input data Din. In response to the rising edge of the internal clock signal CKx, the slave latch SL of the data holding unit 15 changes from the hold state to the through state, and the value of the input data Din output from the master latch MA is output from the data output terminal QF. To do. As a result, the value of the output data Do matches the value of the input data Din, so that the mismatch detection signal S11 is at a low level.

  Next, the operation of the flip-flop 1 according to the first embodiment in the period TM2 in which the rising edge of the clock signal CKS is input while the logic level of the input data Din is not changed will be described. In the period TM2, the logic level of the input data Din is maintained. Therefore, the mismatch detection circuit 11 maintains the mismatch detection signal S11 at the low level. As a result, the mismatch detection signal S11 input to the set terminal S of the SR latch 13 is maintained at a low level. Therefore, even if the rising edge of the clock signal CKS is input, the SR latch 13 can maintain the logic level of the internal clock signal CKx. To maintain. Therefore, the master latch MA maintains the hold state, and the slave latch SL maintains the through state. That is, the logic level of the output data Do does not change even when the rising edge of the clock signal CKS is input at the timing T2. As described above, the flip-flop 1 according to the first embodiment does not toggle the internal clock signal CKx even if the rising edge of the clock signal CKS is input unless the input data Din has a logic level change.

  Next, the operation of the flip-flop 1 according to the first embodiment in the period TM3 in which the hazard has occurred in the input data Din will be described. In the period TM3, the rising edge of the clock signal CKS is input at the timing T3, but a hazard occurs in the input data Din in the period before and after the timing T3.

  When this hazard occurs, the logic levels of the input data Din and the output data Do are different during the hazard occurrence period. Therefore, during the hazard occurrence period, the mismatch detection signal S11 output from the mismatch detection circuit 11 is at the high level. It becomes. If a hazard occurs while the clock signal CKS is at a low level, the clock signal CKS input to the reset terminal R of the SR latch 13 becomes a low level, and the mismatch detection signal S11 input to the set terminal S becomes a high level. Therefore, if a hazard occurs during the period when the clock signal CKS is at low level, the SR latch 13 sets the internal clock signal CKx to low level. On the other hand, if a hazard occurs while the clock signal CKS is at high level, the clock signal CKS input to the reset terminal R of the SR latch 13 becomes high level, and the mismatch detection signal S11 input to the set terminal S becomes high level. Therefore, the SR latch 13 maintains the logic level of the internal clock signal CKx at a high level.

  If a hazard occurs while the clock signal CKS is at the low level, the internal clock signal CKx is switched from the high level to the low level, so that the master latch MA is changed from the hold state to the through state, and the slave latch SL is changed from the through state to the hold state. It becomes. Therefore, when a hazard occurs while the clock signal CKS is at a low level, the master latch MA is in a state of transmitting the value of the input data Din to the slave latch SL, and the slave latch SL is held by the master latch MA before the hazard occurs. It will be in the state which holds the value which had been. Therefore, even if a hazard occurs, the flip-flop 1 maintains the logic level of the output data Do.

  In the example shown in FIG. 8, the rising edge of the clock signal CKS is input at timing T3 after the hazard has converged. At this timing T3, since the input data Din is at a high level, the mismatch detection signal S11 is at a low level. Therefore, at timing T3, the clock signal CKS input to the reset terminal R of the SR latch 13 becomes high level, and the mismatch detection signal S11 input to the set terminal S becomes low level, so that the SR latch 13 receives the internal clock signal CKx. From low level to high level. Further, in response to the internal clock signal CKx becoming high level, the master latch MA changes from the through state to the hold state, and the slave latch SL changes from the hold state to the through state. At this timing T3, since the input data Din is in a state before the occurrence of the hazard, the master latch MA outputs a signal having the same logic level as that before the occurrence of the hazard to the slave latch SL. Further, since the value transmitted to the slave latch SL at the timing T3 is the same as before the occurrence of the hazard, even if the slave latch SL enters the through state, the same value as before the occurrence of the hazard is output to the data output terminal QF. That is, in the flip-flop 1 according to the first embodiment, the value of the output data Do does not change due to the occurrence of a hazard unless the rising edge of the clock signal CKS is input during the hazard occurrence period.

  As described above, in the flip-flop 1 according to the first embodiment, when the logic level does not change in the input data Din, the internal clock signal CKx is prevented from being toggled based on the rising edge of the clock signal CKS. Thereby, the flip-flop 1 according to the first embodiment suppresses the operation of the internal circuit of the data holding unit 15 and reduces power consumption. Further, the flip-flop 1 according to the first embodiment can maintain a stable operation without causing the output data Din to react to the hazard even when a hazard occurs in the input data Din. Furthermore, in the flip-flop 1 according to the first embodiment, the operation stability can be improved. Therefore, the effect relating to the stability of the operation will be described in more detail below.

  Therefore, FIG. 9 shows a circuit diagram of the flip-flop 100 described in Non-Patent Document 1 (hereinafter referred to as a conventional flip-flop 100). As shown in FIG. 9, the conventional flip-flop 100 includes a gating circuit 101, a data holding unit FF01, and an exclusive inversion OR circuit 102. In the conventional flip-flop 100, the exclusive inverting OR circuit 102 outputs a comparison signal COMP indicating whether the input data DATA and the output data Q are in a coincidence state or a disagreement state. The gating circuit 101 outputs a gating clock signal CKg whose logic level changes according to the operation clock CLK when the comparison signal COMP indicates a mismatch state. The conventional flip-flop 100 holds the input data DATA according to the gating clock signal CKg.

  Further, the conventional flip-flop 100 includes a gating circuit 101 including PMOS transistors P101 and P012, an NMOS transistor N101, and inverters INV01 and INV02. The source of the PMOS transistor P101 is connected to the power supply terminal, and the operation clock CLK is supplied to the gate. The source of the PMOS transistor P102 is connected to the drain of the PMOS transistor P101, and the comparison signal COMP is input to the gate. The NMOS transistor N101 has a source connected to the ground terminal and a drain connected to the drain of the PMOS transistor P102. An inverted gating clock signal CKgB having an inversion relationship with the gating clock signal CKg is output from the wiring connecting the drain of the NMOS transistor N101 and the drain of the PMOS transistor P102.

  The inverter INV01 receives the inverted gating clock signal CKgB and outputs the gating clock signal CKg. The inverter INV02 has an input connected to the output of the inverter INV01 and an output connected to the input of the inverter INV01. 9 shows a transistor level circuit for the inverter INV02. As shown in FIG. 9, the inverter INV02 includes a PMOS transistor P103 and an NMOS transistor N102. The source of the PMOS transistor P103 is connected to the power supply terminal, and the gate is the input of the inverter INV02. The source of the NMOS transistor N102 is connected to the ground terminal, and the gate is an input of the inverter INV02. The drain of the PMOS transistor P103 and the drain of the NMOS transistor N102 are connected. The connection point between the drain of the PMOS transistor P103 and the drain of the NMOS transistor N102 is the output of the inverter INV02.

  This conventional flip-flop 100 has the same basic operation as that of the flip-flop 1 according to the first embodiment, but the comparison signal COMP is in a non-coincidence state from the coincidence state (for example, high level) during the period when the operation clock CLK is low level. The circuit state becomes unstable when transitioning to (for example, low level). On the other hand, the flip-flop 1 according to the first embodiment is a circuit even when the comparison signal COMP changes from a coincidence state (for example, high level) to a disagreement state (for example, low level) while the operation clock CLK is at a low level. Can be operated in a stable state. Therefore, in the following, the operation of the conventional flip-flop 100 and the operation of the flip-flop 1 according to the first embodiment are compared, and the stability of the circuit operation will be described.

  First, in the conventional flip-flop 100 shown in FIG. 10, when the operation clock CLK changes from the high level to the low level when the comparison signal is coincident, and the gating circuit 101 becomes stable, the circuit diagram of the gating circuit 101. Indicates. As shown in FIG. 10, in the gating circuit 101, when the comparison signal COMP is at a high level, the PMOS transistor P102 is turned off. Then, when the clock signal CLK becomes low level, the PMOS transistor P101 is turned on and the NMOS transistor N101 is turned off. In the gating circuit 101, the inverted gating clock signal CKgB is set to the low level during the period in which the clock signal CLK is at the high level, and the NMOS transistor N102 of the inverter INV02 is turned on. Therefore, in the state shown in FIG. 10, the gating circuit 101 maintains the gating clock signal CKg at the high level even when the clock signal CLK is switched from the high level to the low level.

  Subsequently, in the conventional flip-flop 100 shown in FIG. 11, the circuit of the gating circuit 101 at a timing at which the comparison signal COMP transitions from a high level (for example, a coincidence state) to a low level (a disagreement state) while the clock signal CLK is at a low level. The figure is shown. As shown in FIG. 11, at the timing when the comparison signal COMP transitions from the high level to the low level, first, the PMOS transistor P102 is turned on. At this time, the inverted gating clock signal CKgB transits from the low level to the high level, but the PMOS transistors P101 and P102 and the NMOS transistor N102 are in the conductive state until the inversion of the output of the inverter INV01 and the output of the inverter INV02 is completed. It becomes. Therefore, a through current Itran flows through the PMOS transistors P101 and P102 and the NMOS transistor N102 until the inversion of the outputs of the inverters INV01 and INV02 is completed.

  Subsequently, in the conventional flip-flop 100 shown in FIG. 12, when the comparison signal COMP transitions from the high level (for example, the coincidence state) to the low level (the disagreement state) during the period in which the clock signal CLK is at the low level, A circuit diagram of the gating circuit 101 is shown. In the state shown in FIG. 12, in the gating circuit 101, the PMOS transistors P101 and P102 are turned on and the NMOS transistors N101 and N102 are turned off according to the logic levels of the comparison signal COMP and the clock signal CLK. As a result, in the gating circuit 101, the inverted gating clock signal CKg becomes high level and the gating clock signal CKg becomes low level.

  As described above, in the gating circuit 101, when the comparison signal COMP changes from the high level to the low level during the period in which the clock signal CLK is at the low level, the through current Itran flows at the transition timing. Therefore, if the operating current Ionp of the PMOS transistors P101 and P102 becomes smaller than the operating current Ionn of the NMOS transistor N102 due to manufacturing variations or the like, the inverted gating clock signal CKgB cannot transition to the high level and cannot be gated. There arises a problem that the logic level of the clock signal CKg cannot be switched. On the other hand, in the clock control circuit 10 of the flip-flop 1 according to the first embodiment, since the SR latch 13 is configured using an inverting OR circuit, there is no problem with the through current Itran.

  Therefore, FIG. 13 shows the SR latch 13 according to the first embodiment in the same state as that shown in FIG. 10 (that is, the stable state after the clock signal CKS becomes low level when the mismatch detection signal S11 is low level). The circuit diagram of is shown. As shown in FIG. 13, in this state, the SR latch 13 sets the inverted internal clock signal CKxB to the low level by turning on the NMOS transistor N17 of the inverted OR circuit NOR2. In the SR latch 13, since the mismatch detection signal S11 is at low level and the inverted internal clock signal CKxB is at low level, the PMOS transistors P15 and P16 are turned on and the signal level of the inverted latch output terminal QLB is set to high level. . At this time, since the NMOS transistors N15 and N16 are turned off, no through current flows in the inverting OR circuit NOR1. Further, since the signal level of the inverting latch output terminal QLB is high and the clock signal CKS is low, the PMOS transistor P17 and the NMOS transistor N18 of the inverting OR circuit NOR2 are turned off. That is, no through current flows in the inverting OR circuit NOR2.

  Next, FIG. 14 shows the SR according to the first embodiment in the same state as that shown in FIG. 11 (that is, the timing at which the mismatch detection signal S11 transits from the low level to the high level during the period in which the clock signal CKS is at the low level). A circuit diagram of the latch 13 is shown. As shown in FIG. 14, in this state, in the SR latch 13, the PMOS transistor P15 of the inverting OR circuit NOR1 transitions from the on state to the off state, and the NMOS transistor N15 transitions from the off state to the on state. As a result, the signal level of the inverting latch output terminal changes from the high level to the low level. Further, the PMOS transistor P17 of the inverting OR circuit NOR2 changes from the off state to the on state in response to the signal level of the inverting latch output terminal changing from the high level to the low level, and the NMOS transistor N17 changes from the on state to the off state. It becomes. As a result, the inverted internal clock signal CKxB transitions from the low level to the high level. At this time, in the SR latch 13, since the PMOS transistor P15 and the NMOS transistor N15 simultaneously change states, and the PMOS transistor P17 and the NMOS transistor N17 simultaneously change states, the through current flowing from the power supply terminal toward the ground terminal Does not occur.

  Next, FIG. 15 shows the same state as that shown in FIG. 12 (that is, the stable state after the mismatch detection signal S11 transits from the low level to the high level during the period in which the clock signal CKS is at the low level). The circuit diagram of SR latch 13 concerning is shown. As shown in FIG. 15, in this state, since the inverted internal clock signal CKxB is at a high level, the states of the PMOS transistor P16 and the NMOS transistor N16 change from the state shown in FIG. Specifically, the PMOS transistor P16 of the inverting OR circuit NOR1 is turned off and the NMOS transistor N16 is turned on. As shown in FIG. 15, even in this state, in the SR latch 13, the power supply terminal and the ground terminal are not connected by the on-state transistor, so that no through current flows.

  From the above description, in the conventional flip-flop 100, when the input data and the output data change from the coincidence state to the disagreement state during the period when the clock signal is at the low level, the through current Itran flows and the circuit causes The condition may become unstable. However, in the flip-flop 100 according to the first embodiment, even when the input data and the output data change from the coincidence state to the disagreement state during the period when the clock signal is at the low level, the power supply terminal and the ground terminal are in the on state. The through current does not flow because they are not connected by the transistor. That is, the flip-flop 1 according to the first embodiment can maintain a stable operation even when the on-state current of the transistor varies. Further, in the flip-flop 1 according to the first embodiment, the power supply voltage can be set low because the flip-flop 1 has high resistance to variations in the on-state current of the transistors. FIG. 16 is a graph showing a change in the ratio of the operation flip-flop with respect to the power supply voltage of the conventional flip-flop 100 and the flip-flop 1 according to the first embodiment.

  As shown in FIG. 16, in the conventional flip-flop 100, the percentage of flip-flops that operate when the power supply voltage falls below 1V decreases. For example, the conventional flip-flop 100 requires a power supply voltage of about 0.7 V in order to operate 90% of the flip-flops. On the other hand, in the flip-flop 1 according to the first embodiment, 100% flip-flop operates up to about 0.4V. The power supply voltage for operating 90% flip-flops may be about 0.35V. In other words, by using the flip-flop 1 according to the first embodiment, the power supply voltage can be lowered and the power consumption can be reduced as compared with the conventional flip-flop 100.

  Another feature of the flip-flop 1 according to the first embodiment is that the input capacitance is small. In the flip-flop 1 according to the first embodiment, the clock signal CKS is input only to the two transistors (for example, the PMOS transistor P18 and the NMOS transistor N18) of the SR latch 13. Therefore, in the following, a normal flip-flop that does not control the clock signal and a flip-flop described in Patent Document 7 that controls the clock signal but has a large input capacity (for example, receives the clock signal by three transistors). The power consumption will be described.

  FIG. 17 shows a circuit diagram of a flip-flop that does not control the clock signal. In the following description, a flip-flop that does not control the clock signal is referred to as a general flip-flop 200. As shown in FIG. 17, in a general flip-flop 200, the clock distribution unit 201 supplies the internal clock signal CKx and the inverted internal clock signal CKxB to the data holding unit 15. The clock distribution unit 201 includes inverters 202 and 203. Then, the inverter 202 inverts the clock signal CKS to generate an inverted internal clock signal CKxB, and the inverter 203 further inverts the inverted internal clock signal CKxB to generate the internal clock signal CKx. In the inverter 202, for example, a PMOS transistor and an NMOS transistor are connected in series between a power supply terminal and a ground terminal. In other words, the clock signal CKS is received by a general flip-flop 2002 by two transistors.

  The flip-flop described in Patent Document 7 receives a clock signal by three transistors, and toggles an internal clock signal output to the data holding unit only during a period in which the input data and the output data do not match. Here, detailed description of the flip-flop circuit described in Patent Document 7 is omitted in order to compare the power consumption with respect to the input capacitance and the presence or absence of control of the clock signal.

  Subsequently, the power consumption of the semiconductor device having the general flip-flop 200, the semiconductor device having the flip-flop 100 described in Patent Document 7, and the semiconductor device having the flip-flop 1 according to the first embodiment is reduced. The compared graph is shown in FIG. In FIG. 18, the same circuit is formed using a general flip-flop 200, formed using the flip-flop 100, and formed using the flip-flop 1 according to the first embodiment. It is a comparison with the case. In FIG. 18, the power consumption of a circuit formed using a general flip-flop 200 is 1, and the power consumption of a circuit formed using another flip-flop is the power consumption of the general flip-flop 200. It is shown by the ratio.

  As shown in FIG. 18, when a circuit is formed using the flip-flop 100 disclosed in Patent Document 7, the power consumption of the flip-flop is reduced because the toggle of the internal clock signal is reduced, but the power consumption of the clock tree is reduced. Will increase. Therefore, when a circuit is formed using the flip-flop 100 described in Patent Document 7, the power consumption of the entire semiconductor device cannot be reduced. On the other hand, when a circuit is formed using the flip-flop 1 according to the first embodiment, the power consumption of the flip-flop 1 is reduced because the toggle of the internal clock signal CKx is reduced. Furthermore, since the input capacity of the clock input terminal CK to which the clock signal CKS is input is suppressed to the same level as the general flip-flop 200, the flip-flop 1 according to the first embodiment consumes less power in the clock tree. Does not increase. That is, by using the flip-flop 1, the power consumption of the entire semiconductor device can be suppressed.

  The relationship between the toggle rate of the output data of the general flip-flop 200 and the flip-flop 1 according to the first embodiment and the power consumption will be described. FIG. 19 is a graph showing the difference in power consumption due to the difference in the toggle rate between the output data of the flip-flop 1 according to the first embodiment and the general flip-flop 200. Note that the power consumption shown in FIG. 19 includes the power consumption of the clock buffer that transmits the clock signal to the flip-flop.

  As shown in FIG. 19, the general flip-flop 200 consumes constant power even if the toggle rate of the output data changes. This is because the general flip-flop 200 changes the contact voltage in the internal circuit based on the clock signal CKS regardless of whether the output data toggles. On the other hand, the flip-flop 1 according to the first embodiment consumes less power than the general flip-flop 200 when the toggle rate of the output data is lower than 50%. In particular, when the toggle rate of the output data is less than 1%, the flip-flop 1 according to the first embodiment consumes 80% or more less power than the general flip-flop 200. This is because the flip-flop 1 according to the first embodiment toggles the internal clock signal CKx only when the input data Din and the output data Do do not match.

  From the above description, by using the flip-flop 1 according to the first embodiment, the power consumption of the flip-flop 1 is reduced and the power consumption of the entire semiconductor device is suppressed while suppressing an increase in power consumption for the clock tree. be able to.

  Further, in the flip-flop 1 according to the first embodiment, when a hazard occurs in the input data Din while the clock signal CKS is at the low level, the master latch MA and the slave latch SL can capture the value of the input data Din. It becomes. However, the flip-flop 1 according to the first embodiment maintains the internal clock signal CKx at a low level until the rising edge of the input clock signal CKS is input after the hazard has converged. Therefore, when the logic level of the internal clock signal CKx returns to the high level according to the rising edge of the clock signal CKS, it is possible to prevent the logic level of the output data Do from transitioning due to the influence of a hazard. That is, by using the flip-flop 1 according to the first embodiment, it is possible to realize a flip-flop having a small input capacitance at the input terminal of the clock signal CKS while having resistance to the hazard of the input data Din. Moreover, the power consumption of the whole semiconductor device can be reduced by using the flip-flop 1 according to the first embodiment.

  Further, in the flip-flop 1 according to the first embodiment, since no through current is generated according to the state transition of the mismatch detection signal S11, a stable circuit operation can be realized. As described above, by stably operating the flip-flop 1, the power supply voltage can be set low and power consumption can be suppressed.

Embodiment 2
In the first embodiment, the flip-flop that changes the logic level of the output data Do according to the rising edge of the clock signal CKS has been described. In the second embodiment, a falling edge triggered flip flip will be described in which the logic level of the output data Do is changed in accordance with the falling edge of the clock signal CKS. That is, in the flip-flop 2 according to the second embodiment, the first logic level in the period immediately before the trigger edge becomes a high level, and the second logic level in the period immediately after the trigger edge becomes a low level. Based on this, the holding operation of the input data Din is performed.

  FIG. 20 is a block diagram of the flip-flop 2 according to the second embodiment. In the description of the second embodiment, the same components as those of the first embodiment are denoted by the same reference numerals as those of the first embodiment, and the description thereof is omitted.

  As illustrated in FIG. 20, the flip-flop 2 according to the second embodiment includes a clock control circuit 20 and a data holding unit 15. The clock control circuit 20 changes the logic level of the internal clock signal CKx according to the clock edge of the clock signal CKS only when the input data Din has a logic level different from that of the output data Do. Then, the flip-flop 2 gives the internal clock signal CKx to the data holding unit 15.

  The clock control circuit 20 includes a mismatch detection circuit 21 and an internal clock generation unit 22. The mismatch detection circuit 21 detects a mismatch between the input data Din and the output data Do and outputs a mismatch detection signal S21. In the flip-flop 2 according to the second embodiment, an exclusive inversion OR circuit (indicated as XNOR in the drawing) is used as the mismatch detection circuit 21. The mismatch detection circuit 21 sets the mismatch detection signal S21 to a low level (for example, 0) when two input signals are in a mismatch detection state, and sets the mismatch detection signal high when two input signals are in a match detection state. It is a level (for example, 1).

  The internal clock generator 22 has an internal clock signal CKx having a trigger edge corresponding to the trigger edge of the clock signal CKS when the trigger edge of the clock signal CKS is input when the mismatch detection signal S21 is in a mismatch detection state. Is generated. In the second embodiment, the trigger edge of the clock signal CKS is a falling edge, and the trigger edge of the internal clock signal CKx is a rising edge. In order to explain more specifically, FIG. 21 shows a truth table showing the operation of the internal clock generator 22.

  First, in the flip-flop 2 according to the second exemplary embodiment, the clock signal CKS has a logic level of the first logic level (for example, high level or 1) in the period immediately before the trigger edge, and the trigger edge The logic level in the immediately following period becomes the second logic level (for example, low level or 0). The internal clock signal CKx has a logic level in the period immediately before the trigger edge as the third logic level (for example, low level or 0), and the logic level in the period immediately after the trigger edge is the fourth logic level. Level (for example, high level or 1).

  As shown in FIG. 21, when the mismatch detection signal S21 is in a match detection state (for example, high level), the internal clock generation unit 22 sets the internal clock signal CKx to a high level when the clock signal CKS becomes a low level. And Then, when the mismatch detection signal S21 is at the high level, the internal clock generation unit 22 maintains the internal clock CKx at the high level even if the clock signal CKS is toggled after the internal clock signal CKx once becomes the high level. . Further, when the mismatch detection signal S21 is in a mismatch detection state (for example, low level), the internal clock generation unit 22 toggles the internal clock signal CKx at a logic level opposite to the logic level of the clock signal CKS.

  Here, the operation of the internal clock generation unit 22 will be described from another viewpoint. As shown in FIG. 21, the internal clock generator 22 sets the internal clock signal CKx to a low level when the mismatch detection signal S21 is in a mismatch detection state (for example, a low level) during a period in which the clock signal CKS is at a high level. . After that, when the clock signal CKS becomes low level by inputting the trigger edge of the clock signal CKS while the mismatch detection signal S21 maintains the mismatch detection state, the internal clock signal CKx is at the logic level of the clock signal CKS. In response to the switching, the internal clock signal CKx is switched from the low level to the high level. Further, even when the state of the mismatch detection signal S21 is switched between the match detection state and the mismatch detection state during the period in which the clock signal CKS is at the low level, the internal clock generation unit 22 maintains the internal clock signal CKx at the high level. . Further, when the state of the mismatch detection signal S21 is switched between the match detection state and the mismatch detection state during the period when the clock signal CKS is at the high level, the internal clock generation unit 22 once sets the internal clock signal CKx to the low level. Maintains the internal clock signal CKx at a low level.

  As shown in FIG. 21, the internal clock generation unit 22 outputs an inverted internal clock signal CKxB having a logic level inverted from the internal clock signal CKx in addition to the internal clock signal CKx.

  The internal clock generator 22 includes a set / reset latch (hereinafter referred to as SR latch) 23 and an inverter 24. The SR latch 23 has a set input terminal S, a reset input terminal R, a first output terminal (for example, a latch output terminal QL), and a second output terminal (for example, an inverted latch output terminal QLB). In the SR latch 23, the mismatch detection signal S21 is input to one of the set input terminal S and the reset input terminal S, and a clock signal (for example, a clock signal CKS) is input to the other of the set input terminal S and the reset input terminal R. And the internal clock signal CKx is generated based on the mismatch detection circuit S21 and the clock signal CKS. In the second embodiment, the mismatch detection signal S21 is input to the set input terminal S as a set signal. A clock signal CKS is input to the reset input terminal R as a reset signal. As will be described in detail later, the SR latch 23 has a feature that the number of transistors to which the clock signal CKS is input is 2 or less.

  Then, the internal clock generator 22 outputs an inverted clock signal CKxB having a logic level inverted from the internal clock signal CKx from the latch output terminal QL of the SR latch 23. The internal clock generator 22 inverts the inverted clock signal CKxB by the inverter 24 and outputs the internal clock signal CKx.

  Subsequently, a detailed circuit configuration of each block of the flip-flop 2 according to the second embodiment will be described. First, a circuit diagram of the mismatch detection circuit 21 is shown in FIG. As shown in FIG. 22, the mismatch detection circuit 21 is obtained by adding an inverter formed of a PMOS transistor P <b> 21 and an NMOS transistor N <b> 21 to the output stage of the mismatch detection circuit 11. By this inverter, the mismatch detection circuit 21 outputs a mismatch detection signal S21 whose logic is inverted from that of the mismatch detection signal S11.

  With such a circuit configuration, the mismatch detection circuit 21 constitutes an exclusive inversion OR circuit. Therefore, a truth table of the mismatch detection circuit 21 is shown in FIG. As shown in FIG. 23, in the mismatch detection circuit 21, the output data Do input to the first input terminal In1 and the input data Din input to the second input terminal In2 have different logic levels. Sometimes, the mismatch detection signal S21 output from the output terminal OUT is set to the low level. On the other hand, the mismatch detection circuit 21 outputs the output terminal when the output data Do input to the first input terminal In1 and the input data Din input to the second input terminal In2 have the same logic level. The mismatch detection signal S21 output from OUT is set to the high level.

  Next, a detailed circuit of the SR latch 23 will be described. FIG. 24 shows a detailed circuit diagram of the SR latch 23. As shown in FIG. 24, the SR latch 23 includes a first inverting AND circuit (for example, inverting AND circuit NAND1) and a second inverting AND circuit (for example, inverting AND circuit NAND2). In the SR latch 23, the mismatch detection signal S21 is input to one of the first input terminal of the inverting AND circuit NAND1 and the first input terminal of the inverting AND circuit NAND2. The SR latch 23 receives a clock signal at the other of the first input terminal of the inverting AND circuit NAND1 and the first input terminal of the inverting AND circuit NAND2. Further, in the SR latch 23, the output terminal of the inverting AND circuit NAND1 and the second input terminal of the inverting AND circuit NAND2 are connected, and the output terminal of the inverting AND circuit NAND2 and the second terminal of the inverting AND circuit NAND1 are connected. Input terminal is connected.

  More specifically, the inverting AND circuit NAND1 has a first input terminal connected to the set terminal S and a second input terminal connected to the output terminal of the inverting AND circuit NAND2. The output terminal of the inverting AND circuit NAND1 is connected to the inverting latch output terminal QLB. The inverting AND circuit NAND2 has a first input terminal connected to the reset terminal R and a second input terminal connected to the output terminal of the inverting AND circuit NAND1. The output terminal of the inverting AND circuit NAND2 is connected to the latch output terminal QL. A signal output from the latch output terminal QL becomes the internal clock signal CKx. In the first embodiment, the mismatch detection signal S21 is input to the set terminal S, and the clock signal CKS is input to the reset terminal R.

  The inverting AND circuit NAND1 includes PMOS transistors P25 and P26 and NMOS transistors N25 and N26. The sources of the PMOS transistors P25 and P26 are connected to the power supply terminal. The mismatch detection signal S21 is input to the gate of the PMOS transistor P25. The gate of the PMOS transistor P26 is connected to the output terminal of the inverting AND circuit NAND2. The drains of the PMOS transistors P25 and P26 are connected to the inverting latch output terminal QLB. The drain of the NMOS transistor N25 is connected to the inverting latch output terminal QLB. The gate of the NMOS transistor N25 is connected to the inverting AND circuit NAND2. The source of the NMOS transistor N25 is connected to the drain of the NMOS transistor N26. The mismatch detection signal S21 is input to the gate of the NMOS transistor N26. The source of the NMOS transistor N26 is connected to the ground terminal.

  The inverting AND circuit NAND2 includes PMOS transistors P27 and P28 and NMOS transistors N27 and N28. The sources of the PMOS transistors P27 and P28 are connected to the power supply terminal. The gate of the PMOS transistor P27 is connected to the output terminal of the inverting AND circuit NAND1. The clock signal CKS is input to the gate of the PMOS transistor P28. The drains of the PMOS transistors P27 and P28 are connected to the latch output terminal QL. The drain of the NMOS transistor N27 is connected to the latch output terminal QL. The clock signal CKS is input to the gate of the NMOS transistor N27. The source of the NMOS transistor N27 is connected to the drain of the NMOS transistor N28. The gate of the NMOS transistor N28 is connected to the output terminal of the inverting AND circuit NAND1. The source of the NMOS transistor N28 is connected to the ground terminal. The PMOS transistors P27 and P28 correspond to the first transistor and the second transistor, and the NMOS transistors N27 and N28 correspond to the third transistor and the fourth transistor.

  Here, the truth table of the SR latch 23 is shown in FIG. 25, and the operation of the SR latch 23 will be described. As shown in FIG. 25, when the mismatch detection signal S21 is low level and the clock signal CKS is high level, the SR latch 23 sets the output value of the latch output terminal QL to low level and the output value of the inverting latch output terminal QLB. Is set to the high level. When the mismatch detection signal S21 is high level and the clock signal CKS is low level, the SR latch 23 sets the output value of the latch output terminal QL to high level and sets the output value of the inverting latch output terminal QLB to low level. When both the mismatch detection signal S21 and the clock signal CKS are at the high level, the SR latch 23 outputs the output value of the latch output terminal QL and the inverted latch output before the mismatch detection signal S21 and the clock signal CKS are both at the high level. The logic level of the output value of the terminal QLB is maintained. Furthermore, the SR latch 23 sets both the output value of the latch output terminal QL and the output value of the inverted latch output terminal QLB to the high level when both the mismatch detection signal S21 and the clock signal CKS are at the low level.

  That is, in the flip-flop 2 according to the second embodiment, an input state in which both the latch output terminal QL and the inverted latch output terminal QLB, which are normally prohibited or conditionally usable as the SR latch usage mode, are at a high level. Is actively used. As a result, the SR latch 23 causes the falling edge of the clock signal CKS in a state where the mismatch detection signal S21 is at a different logic level between the input data Din and the output data Do (for example, a state where the mismatch detection signal S21 is at a low level). Only when is inputted, the internal clock signal CKx is toggled in accordance with the toggle of the clock signal CKS.

  Also in the SR latch 23 according to the second embodiment, the transistors of different conductivity types simultaneously change the conduction state to the opposite state according to the transition of the logic level of the mismatch detection signal S21, and the power supply terminal and the ground terminal are connected. Prevents conduction. Therefore, even in the second embodiment, the through current does not flow according to the switching of the logic level of the mismatch detection signal S21. That is, even in the SR latch 23 according to the second embodiment, the through current does not flow in accordance with the transition of the logic level of the input signal, so that the stability of the flip-flop 2 can be improved. In addition, the flip-flop 2 according to the second embodiment can reduce the power consumption by reducing the power supply voltage based on high stability, similarly to the flip-flop 1 according to the first embodiment.

  Next, the operation of the flip-flop 2 according to the second embodiment will be described. FIG. 26 shows a timing chart showing the operation of the flip-flop 2. First, the period TM1 in FIG. 26 will be described. In the period TM1, the logic level of the input data Din changes from the low level to the high level before the timing T1 when the falling edge of the clock signal CKS is input. Therefore, in the period TM1, the mismatch detection circuit 21 sets the mismatch detection signal S21 to the low level as the logic level of the input data Din is switched. The SR latch 23 sets the internal clock signal CKx to the low level in response to the mismatch detection signal S21 becoming the low level. At this time, the master latch MA changes from the hold state to the through state, and the slave latch SL changes from the through state to the hold state. That is, the master latch MA transmits a signal whose logic level is high in accordance with the input data Din to the slave latch SL, and the slave latch SL is supplied from the master latch MA during a period before the input data Din is high. The logic level (that is, low level) of the received signal is held.

  When the falling edge of the clock signal CKS is input at timing T1, the SR latch 23 changes the internal clock signal CKx from the low level to the high level. In response to the falling edge of the internal clock signal CKx, the master latch MA of the data holding unit 15 changes from the through state to the hold state, and holds the value of the input data Din. In response to the falling edge of the internal clock signal CKx, the slave latch SL of the data holding unit 15 changes from the hold state to the through state, and the value of the input data Din output from the master latch MA is changed from the data output terminal QF. Output. As a result, the value of the output data Do matches the value of the input data Din, so that the mismatch detection signal S21 is at a low level.

  Next, the operation of the flip-flop 2 according to the second embodiment in the period TM2 in which the falling edge of the clock signal CKS is input while the logic level of the input data Din does not change will be described. In the period TM2, the logic level of the input data Din is maintained. Therefore, the mismatch detection circuit 11 maintains the mismatch detection signal S21 at a low level. As a result, the mismatch detection signal S21 input to the set terminal S of the SR latch 23 is maintained at a high level. Therefore, even if the falling edge of the clock signal CKS is input, the SR latch 23 is connected to the internal clock signal CKx. Maintain a logic level. Therefore, the master latch MA maintains the hold state, and the slave latch SL maintains the through state. That is, the logic level of the output data Do does not change even when the falling edge of the clock signal CKS is input at the timing T2. As described above, the flip-flop 2 according to the second embodiment does not toggle the internal clock signal CKx even if the falling edge of the clock signal CKS is input unless the logic level of the input data Din is changed.

  Next, the operation of the flip-flop 2 according to the second embodiment in the period TM3 in which the hazard has occurred in the input data Din will be described. In the period TM3, the falling edge of the clock signal CKS is input at the timing T3, but a hazard occurs in the input data Din in the period before and after the timing T3.

  When this hazard occurs, the logic levels of the input data Din and the output data Do are different during the hazard occurrence period. Therefore, during the hazard occurrence period, the mismatch detection signal S21 output by the mismatch detection circuit 21 is at the low level. Become. When a hazard occurs while the clock signal CKS is at low level, the clock signal CKS input to the reset terminal R of the SR latch 23 becomes low level, and the mismatch detection signal S21 input to the set terminal S becomes high level. Therefore, if a hazard occurs during the period when the clock signal CKS is at the low level, the SR latch 23 sets the internal clock signal CKx to the low level. On the other hand, when a hazard occurs while the clock signal CKS is at a high level, the clock signal CKS input to the reset terminal R of the SR latch 23 is at a high level, and the mismatch detection signal S21 input to the set terminal S is at a high level. Therefore, the SR latch 23 maintains the logic level of the internal clock signal CKx at a high level.

  If a hazard occurs while the clock signal CKS is at the low level, the internal clock signal CKx is switched from the high level to the low level, so that the master latch MA is changed from the hold state to the through state, and the slave latch SL is changed from the through state to the hold state. It becomes. Therefore, when a hazard occurs while the clock signal CKS is at a low level, the master latch MA is in a state of transmitting the value of the input data Din to the slave latch SL, and the slave latch SL is held by the master latch MA before the hazard occurs. It will be in the state which holds the value which had been. Therefore, even if a hazard occurs, the flip-flop 2 maintains the logic level of the output data Do.

  In the example shown in FIG. 26, the falling edge of the clock signal CKS is input at timing T3 after the hazard has converged. At this timing T3, since the input data Din is at a high level, the mismatch detection signal S21 is at a high level. Therefore, at timing T3, the clock signal CKS input to the reset terminal R of the SR latch 23 becomes high level, and the mismatch detection signal S21 input to the set terminal S becomes low level, so that the SR latch 23 receives the internal clock signal CKx. From low level to high level. Further, in response to the internal clock signal CKx becoming high level, the master latch MA changes from the through state to the hold state, and the slave latch SL changes from the hold state to the through state. At this timing T3, since the input data Din is in a state before the occurrence of the hazard, the master latch MA outputs a signal having the same logic level as that before the occurrence of the hazard to the slave latch SL. Further, since the value transmitted to the slave latch SL at the timing T3 is the same as before the occurrence of the hazard, even if the slave latch SL enters the through state, the same value as before the occurrence of the hazard is output to the data output terminal QF. That is, in the flip-flop 1 according to the first embodiment, the value of the output data Do does not change due to the occurrence of a hazard unless the falling edge of the clock signal CKS is input during the hazard occurrence period.

  As described above, in the flip-flop 2 according to the second embodiment, when the logic level does not change in the input data Din, data is retained by preventing the internal clock signal CKx from being toggled based on the falling edge of the clock signal CKS. The internal circuit operation of the unit 15 is suppressed to reduce power consumption. Further, in the flip-flop 2 according to the second embodiment, it is possible to prevent malfunction of the data holding unit 15 due to occurrence of a hazard. Furthermore, also in the flip-flop 2 according to the second embodiment, the number of transistors to which the clock signal CKS is input is two. Therefore, also in the flip-flop 2 according to the second embodiment, the first function for reducing power consumption by preventing the internal clock signal CKx from being toggled and the second function for preventing malfunction caused by occurrence of a hazard. Can be realized while reducing the input capacitance of the clock input terminal CK.

  Further, since the flip-flop 2 according to the second embodiment can ensure the same high stability as the flip-flop 1 according to the first embodiment, the power consumption can be reduced by the low power supply voltage.

Embodiment 3
In the third embodiment, a flip-flop 1a that is a modification of the flip-flop 1 according to the first embodiment and a flip-flop 2a that is a modification of the flip-flop 2 according to the second embodiment will be described. In the description of the third embodiment, the same components as those in the first and second embodiments are denoted by the same reference numerals as those in the first and second embodiments, and the description thereof is omitted.

  First, a block diagram of the flip-flop 1a according to the third embodiment is shown in FIG. 27, and the flip-flop 1a will be described. As shown in FIG. 27, the flip-flop 1a according to the third embodiment uses a clock control circuit 30 instead of the clock control circuit 10 according to the first embodiment. The clock control circuit 30 generates the internal clock signal CKx that rises when the rising edge of the clock signal CKS is input in a state where the input data Din and the output data Do are different values.

  Here, the clock control circuit 30 will be described in more detail. As illustrated in FIG. 27, the clock control circuit 30 includes an internal clock generation unit 12 a instead of the internal clock generation unit 12 of the clock control circuit 10. The internal clock generation unit 12 a is a modification of the connection form of the SR latch 13. More specifically, in the internal clock generation unit 12a, the clock signal CKS is input to the set terminal S of the SR latch 13, and the mismatch detection signal S11 is input to the reset terminal R. In the clock control circuit 30, the inverted internal clock signal CKxB is output from the inverted latch output terminal QLB of the SR latch 13, and a signal obtained by inverting the inverted internal clock signal CKxB by the inverter 14 is used as the internal clock signal CKx.

  Here, a truth table showing the relationship between the input value to the internal clock generation unit 12a and the internal clock signal is shown in FIG. As shown in FIG. 28, the internal clock generation unit 12a of the flip-flop 1a has an inverted internal clock when the mismatch detection signal S11 is at a low level (eg, 0) and the clock signal CKS is at a high level (eg, 1). The signal CKxB is set to low level, and the internal clock signal CKx is set to high level. The internal clock generator 12a of the flip-flop 1a sets the inverted internal clock signal CKxB to the high level and the internal clock signal CKx to the low level when the mismatch detection signal S11 is at the high level and the clock signal CKS is at the low level. When both the mismatch detection signal S11 and the clock signal CKS are at the low level, the internal clock generation unit 12a of the flip-flop 1a generates the inverted internal clock signal CKxB and the internal clock signal before the mismatch detection signal S11 and the clock signal CKS are both at the low level. The logic level of the clock signal CKx is maintained. Further, the internal clock generator 12a of the flip-flop 1a sets the inverted internal clock signal CKxB to a low level and the internal clock signal CKx to a high level when both the mismatch detection signal S11 and the clock signal CKS are at a high level.

  That is, the internal clock generation unit 12a of the flip-flop 1a is configured when the mismatch detection signal S11 does not match the input data Din and the output data Do (for example, when the mismatch detection signal S11 is at a high level). As with the flip-flop 1 according to 1, the internal clock signal CKx is toggled at the same logic level as the clock signal CKS. On the other hand, the internal clock generation unit 12a of the flip-flop 1a has the first embodiment when the mismatch detection signal S11 matches the input data Din and the output data Do (for example, when the mismatch detection signal S11 is at the low level). As with the flip-flop 1, the internal clock signal CKx is maintained at a high level even when the clock signal CKS is toggled.

  As described with reference to FIGS. 27 and 28, the flip-flop 1 a according to the third embodiment uses the clock control circuit 30 in which the connection relation of each block in the clock control circuit 10 is modified. This realizes the same functions and effects as those of the flip-flop 1.

  Next, a block diagram of the flip-flop 2a according to the third embodiment is shown in FIG. 29, and the flip-flop 2a will be described. As shown in FIG. 29, the flip-flop 2a according to the third embodiment uses a clock control circuit 40 instead of the clock control circuit 20 according to the second embodiment. The clock control circuit 40 generates the internal clock signal CKx that rises when the falling edge of the clock signal CKS is input in a state where the input data Din and the output data Do are different values.

  Here, the clock control circuit 40 will be described in more detail. As shown in FIG. 29, the clock control circuit 40 is a modification of the connection form of the internal clock generation unit 22 of the clock control circuit 20. More specifically, in the internal clock generator 22a, the clock signal CKS is input to the set terminal S of the SR latch 23, and the mismatch detection signal S21 is input to the reset terminal R. In the clock control circuit 40, the internal clock signal CKx is output from the inverted latch output terminal QLB of the SR latch 23, and a signal obtained by inverting the internal clock signal CKx by the inverter 24 is used as the inverted internal clock signal CKxB.

  Here, FIG. 30 shows a truth table showing the relationship between the input value to the internal clock generation unit 22a and the internal clock signal. As shown in FIG. 30, the internal clock generation unit 22a of the flip-flop 2a has an internal clock signal when the mismatch detection signal S21 is at a low level (eg, 0) and the clock signal CKS is at a high level (eg, 1). CKx is set to low level and the inverted internal clock signal CKx is set to high level. When the mismatch detection signal S21 is high level and the clock signal CKS is low level, the internal clock generation unit 22a of the flip-flop 2a sets the internal clock signal CKx to high level and the inverted internal clock signal CKxB to low level. When both the mismatch detection signal S11 and the clock signal CKS are at a high level, the internal clock generation unit 22a of the flip-flop 2a has the internal clock signal CKx before the mismatch detection signal S21 and the clock signal CKS are both at a high level. The logic level of the inverted internal clock signal CKxB is maintained. Further, when both the mismatch detection signal S11 and the clock signal CKS are at the low level, the internal clock generation unit 22a of the flip-flop 2a sets the internal clock signal CKx to the high level and the inverted internal clock signal CKxB to the high level.

  That is, the internal clock generation unit 22a of the flip-flop 2a is configured so that the mismatch detection signal S21 is in a state where the input data Din and the output data Do do not match (for example, when the mismatch detection signal S11 is at a low level). As with the flip-flop 2, the internal clock signal CKx is toggled at a logic level inverted from that of the clock signal CKS. On the other hand, the internal clock generation unit 22a of the flip-flop 2a is configured when the mismatch detection signal S21 matches the input data Din and the output data Do (for example, when the mismatch detection signal S11 is at a high level). The internal clock signal CKx is maintained at a high level even when the clock signal CKS is toggled as in the flip-flop 2 according to 2.

  As described with reference to FIGS. 29 and 30, the flip-flop 2 a according to the third embodiment uses the clock control circuit 40 in which the connection relation of each block in the clock control circuit 20 is modified. The same functions and effects as those of the flip-flop 2 according to the above are realized.

Embodiment 4
In the fourth embodiment, an embodiment in which a data holding unit 15S (for example, a scan flip-flop) corresponding to a scan test is used as the data holding unit 15 will be described. In the fourth embodiment, an exclusive OR circuit 11a which is another form of the exclusive OR circuit 11 will also be described. In the description of the fourth embodiment, the same components as those described in the above embodiment are denoted by the same reference numerals as those in the above embodiment, and the description thereof is omitted.

  FIG. 31 is a block diagram of the flip-flop 3 according to the fourth embodiment. As shown in FIG. 31, in the flip-flop 3 according to the fourth embodiment, the clock control circuit 10 and the data holding unit 15 of the flip-flop 1 according to the first embodiment are replaced with the clock control circuit 50 and the data holding unit 15S. Is.

  First, the data holding unit 15S will be described. In the scan test, input data Din and scan data Sin are used as input signals. Therefore, in the flip-flop 3, the input data includes first input data (for example, input data Din) and second input data (for example, scan data Sin). Therefore, as shown in FIG. 31, the data holding unit 15S is obtained by replacing the master latch MA of the data holding unit 15 with a master latch MAS. The master latch MAS is obtained by adding inverters INVs and INVse and transfer switches TSWbs and TSWS to the master latch MA. Further, the data holding unit 15S has a first wiring through which either the input data Din or the scan data Sin is transmitted according to a selection signal SFT given from the outside. The data holding unit 15S holds the held data transmitted to the first wiring according to the internal clock signal CKx.

  The transfer switch TSWbs is provided between the output of the inverter INV1 and the transfer switch TSWb1. The inverter INVs has an input connected to the shift data input terminal SI to which the shift data SI is input, and an output connected to the transfer switch TSWb1 via the transfer switch TSWas. The wiring connecting the transfer switches TSWas, TSWbs and the transfer switch TSWb1 corresponds to the first wiring. The inverter INVse inverts the selection signal SFT given from the outside via the shift enable terminal SE to generate an inverted selection signal SFTB. The selection signal SFT is given to the transfer switches TSWas, TSWas and the SR latch 13a. Further, the inversion selection signal SFTB is given to the transfer switches TSWas and TSWas.

  Here, the transfer switches TSWas and TSWbs are exclusively turned on according to the selection signal SFT. More specifically, when the selection signal SFT is in a high level state instructing selection of the shift data Sin, the transfer switch TSWas is turned on and the transfer switch TSWbs is turned off. Further, when the selection signal SFT is in a low level state instructing selection of the input data Din, the transfer switch TSWas is cut off and the transfer switch TSWbs is turned on.

  Thereby, the data holding unit 15S holds the shift data Sin according to the internal clock signal CKx when the selection signal SFT is at a high level, and the input data Din according to the internal clock signal CKx when the selection signal SFT is at a low level. Hold.

  Subsequently, the clock control circuit 50 is obtained by replacing the mismatch detection circuit 11 and the SR latch 13 of the clock control circuit 10 of the first embodiment with the mismatch detection circuit 11a and the SR latch 13a. In the flip-flop 3 according to the fourth embodiment, the mismatch detection circuit 11a refers to the input data Din as input data, detects a mismatch between the input data Din and the output data Do, and outputs a mismatch detection signal S11. The mismatch detection circuit 11a operates as an exclusive OR circuit like the mismatch detection circuit 11, but the circuit configuration is different from the mismatch detection circuit 11. A circuit diagram of the mismatch detection circuit 11a is shown in FIG.

  As shown in FIG. 32, the mismatch detection circuit 11a includes transfer switches 111a and 111b. The transfer switch 111a includes an NMOS transistor MN and a PMOS transistor MP. Then, one of the source / drain of the NMOS transistor MN and one of the source / drain of the PMOS transistor MP are connected to each other. The other of the source and drain of the NMOS transistor MN and the other of the source and drain of the PMOS transistor MP are connected to each other. The inverted input data DinB obtained by inverting the input data Din is supplied to the gate of the NMOS transistor MN. Input data Din is supplied to the gate of the PMOS transistor MP. The transfer switch 111a is a switch circuit that becomes conductive during a period in which the input data Din is at a low level. In the fourth embodiment, as shown in FIG. 30, the inverted input data DinB is generated by inverting the input data Din by the inverter INV1 of the data holding unit 15S.

  The transfer switch 111b includes an NMOS transistor MN and a PMOS transistor MP. Then, one of the source / drain of the NMOS transistor MN and one of the source / drain of the PMOS transistor MP are connected to each other. The other of the source and drain of the NMOS transistor MN and the other of the source and drain of the PMOS transistor MP are connected to each other. The input data Din is given to the gate of the NMOS transistor MN. The inverted input data DinB is given to the gate of the PMOS transistor MP. The transfer switch 111b is a switch circuit that becomes conductive during a period in which the input data Din is at a high level. That is, the transfer switch 111a and the transfer switch 111b are exclusively connected.

  In the mismatch detection circuit 11a, the output data Do is given to the transfer switch 111a, and the inverted output data DoB given as the input signal of the inverter INV6 is given to the transfer switch 111b. The inverted output data DoB is the output data Do before being inverted by the inverter INV6, and has a logic level inverted from that of the output data Do.

  When the input data Din is at a low level, the mismatch detection circuit 11a turns on the transfer switch 111a and turns off the transfer switch 111b, and outputs a mismatch detection signal S11 according to the logic level of the output data Do. . Further, the mismatch detection circuit 11a is configured such that when the input data Din is at a high level, the transfer switch 111a is cut off and the transfer switch 111b is turned on, and the mismatch detection signal S11 according to the logic level of the inverted output data DoB. Is output. That is, if the input data Din and the output data Do are both low level, the mismatch detection circuit 11a outputs a low level mismatch detection signal S11 via the transfer switch 111a. The mismatch detection circuit 11a outputs a low level mismatch detection signal S11 via the transfer switch 111b when both the input data Din and the output data Do are at a high level. The mismatch detection circuit 11a outputs a high level mismatch detection signal S11 via the transfer switch 111a when the input data Din is at a low level and the output data Do is at a high level. If the input data Din is at a high level and the output data Do is at a low level, the mismatch detection circuit 11a outputs a high level mismatch detection signal S11 through the transfer switch 111b.

  As described above, the mismatch detection circuit 11a operates as an exclusive OR circuit like the mismatch detection circuit 11 shown in FIG. 3, but can reduce circuit elements.

  Next, the SR latch 13a will be described. The SR latch 13a is obtained by adding a function of stopping the gating function of the clock signal CKS to the SR latch 13 according to the first embodiment in accordance with the selection signal SFT. That is, when the selection signal SFT indicates that the scan data Sin is selected, the SR latch 13a changes the logic level in response to the change in the logic level of the clock signal CKS regardless of the logic level of the mismatch detection signal S11. An internal clock signal CKx is generated. FIG. 33 shows a detailed circuit diagram of the SR latch 13a.

  As shown in FIG. 33, the SR latch 13a is obtained by replacing the inverting OR circuit NOR2 with the inverting OR circuit NOR2S. The inverting OR circuit NOR2S is obtained by adding a fifth transistor (for example, PMOS transistor P37) and a sixth transistor (for example, NMOS transistor N36) to the inverting OR circuit NOR2.

  The PMOS transistor P37 is connected to the PMOS transistor P17 in parallel by receiving the inverted selection signal SFTB obtained by inverting the selection signal SFT at the control terminal. In the NMOS transistor N37, the inverted selection signal SFTB is supplied to a control terminal (eg, gate terminal), and is connected between the first terminal (eg, source terminal) of the NMOS transistor N17 and the ground terminal.

  In the SR latch 13a, since the selection signal SFT is at a high level for selecting the shift data Sin and the inverted selection signal SFTB is at a low level, the PMOS transistor P37 is turned on and the NMOS transistor N37 is turned off. As a result, the SR latch 13a operates as an inverter constituted by the PMOS transistor P18 and the NMOS transistor N18 during the period in which the selection signal SFT instructs the selection of the shift data Sin, and the PMOS transistor P17 and the NMOS transistor N17 are disabled. Function. That is, the SR latch 13a can switch whether to disable or enable the gating function of the clock signal CK according to the logic level of the selection signal SFT.

  In the scan test, since a signal with a high toggle rate is input as the shift data Sin, the effect of gating the clock signal CK by transition between input data and output data is small. Therefore, even if the gating function of the clock signal CK by the clock control circuit 50 is disabled during the scan test, the difference in power consumption is small.

  Further, the flip-flop 3 according to the fourth embodiment reduces the circuit area while realizing the function of switching the gating function of the clock signal CK to be invalid or valid according to the logic level of the selection signal SFT. Can do. Therefore, in order to explain the circuit area, FIG. 34 shows a block diagram when a flip-flop is configured using the clock control circuit 10 according to the first embodiment and the data holding unit 15S.

  In the example shown in FIG. 34, the clock control circuit 10a using the mismatch detection circuit 11a instead of the mismatch detection circuit 11 of the clock control circuit 10 is shown. The flip-flop shown in FIG. 34 is hereinafter referred to as a flip-flop 300.

  As shown in FIG. 34, in the flip-flop 300, in order to use both input data Din and shift data Sin as input data to be referred to, inverters INVa, TSWas between the transfer switches TSWas and TSWas and the transfer switch TSWb1 are used. INVb is provided. In FIG. 34, the master latch having the inverters INVa and INVb is shown as a master latch MASc, and the data holding unit is shown as a data holding unit 15Sc. Then, the monitor signal X having the same logic level as that of the input data Din and the shift data Sin is obtained from the input of the inverter INVb. Further, an inverted monitor signal XB having the same logic level as that of the inverted input data DinB and the inverted shift data SinB is obtained from the output of the inverter INVb. With this configuration, the flip-flop 300 can hold data in the data holding unit 15Sc with the same logic as the flip-flop 3.

  In the example shown in FIG. 34, when the inverter is configured by two transistors, four transistors are added to the data holding unit 15S according to the fourth embodiment. On the other hand, the clock control circuit 10a shown in FIG. 34 can reduce the number of transistors in the SR latch by two as compared with the clock control circuit 50 shown in FIG. In other words, the flip-flop 3 according to the fourth embodiment can have fewer transistors than the flip-flop 300 shown in FIG. Thus, the flip-flop 3 according to the fourth embodiment can realize a flip-flop corresponding to a scan test with a small number of transistors.

  Here, the same deformation as the deformation from the inconsistency detection circuit 11 to the inconsistency detection circuit 11a is applied to the inconsistency detection circuit 21, and the same deformation as the deformation from the SR latch 13 to the SR latch 13a is performed. The SR latch 23a applied to the latch 23 will be described.

  A detailed circuit diagram of the mismatch detection circuit 21a is shown in FIG. As shown in FIG. 35, the mismatch detection circuit 21a includes transfer switches 211a and 211b. The transfer switch 211a includes an NMOS transistor MN and a PMOS transistor MP. Then, one of the source / drain of the NMOS transistor MN and one of the source / drain of the PMOS transistor MP are connected to each other. The other of the source and drain of the NMOS transistor MN and the other of the source and drain of the PMOS transistor MP are connected to each other. The input data Din is given to the gate of the NMOS transistor MN. The inverted input data DinB obtained by inverting the input data Din is given to the gate of the PMOS transistor MP. The transfer switch 111a is a switch circuit that becomes conductive during a period in which the input data Din is at a high level. In the fourth embodiment, as shown in FIG. 30, the inverted input data DinB is generated by inverting the input data Din by the inverter INV1 of the data holding unit 15S.

  The transfer switch 211b includes an NMOS transistor MN and a PMOS transistor MP. Then, one of the source / drain of the NMOS transistor MN and one of the source / drain of the PMOS transistor MP are connected to each other. The other of the source and drain of the NMOS transistor MN and the other of the source and drain of the PMOS transistor MP are connected to each other. The inverted input data DinB is given to the gate of the NMOS transistor MN. Input data Din is supplied to the gate of the PMOS transistor MP. The transfer switch 211b is a switch circuit that becomes conductive during a period in which the input data Din is at a low level. That is, the transfer switch 211a and the transfer switch 211b are exclusively in a conductive state.

  In the mismatch detection circuit 21a, the output data Do is given to the transfer switch 211a, and the inverted output data DoB given as an input signal of the inverter INV6 is given to the transfer switch 211b. The inverted output data DoB is the output data Do before being inverted by the inverter INV6, and has a logic level inverted from that of the output data Do.

  When the input data Din is at a high level, the mismatch detection circuit 21a generates a mismatch detection signal S21 corresponding to the logic level of the inverted output data DoB, with the transfer switch 211a being in a conductive state and the transfer switch 211b being in a cutoff state. Output. Further, when the input data Din is at the low level, the mismatch detection circuit 21a outputs the mismatch detection signal S21 according to the logic level of the output data Do when the transfer switch 211a is cut off and the transfer switch 211b is turned on. To do. That is, if the input data Din and the output data Do are both low level, the mismatch detection circuit 21a outputs a high level mismatch detection signal S21 via the transfer switch 211b. If both the input data Din and the output data Do are at a high level, the mismatch detection circuit 21a outputs a high level mismatch detection signal S21 via the transfer switch 211a. The mismatch detection circuit 21a outputs a low level mismatch detection signal S21 via the transfer switch 211a when the input data Din is at a high level and the output data Do is at a low level. If the input data Din is low level and the output data Do is high level, the mismatch detection circuit 21a outputs a low level mismatch detection signal S21 via the transfer switch 211b.

  As described above, the mismatch detection circuit 21a operates as an exclusive inversion OR circuit like the mismatch detection circuit 21 shown in FIG. 23, but can reduce circuit elements.

  Next, the SR latch 23a will be described. The SR latch 23a is obtained by adding a function of stopping the gating function of the clock signal CKS in accordance with the selection signal SFT to the SR latch 23 according to the second embodiment. A detailed circuit diagram of the SR latch 23a is shown in FIG.

  As shown in FIG. 36, the SR latch 23a is obtained by replacing the inverting AND circuit NAND2 with an inverting AND circuit NAND2S. The NAND circuit NAND2S is obtained by adding a fifth transistor (for example, a PMOS transistor P47) and a sixth transistor (for example, an NMOS transistor N46) to the NAND circuit NAND2.

  In the PMOS transistor P47, the selection signal SFT is supplied to a control terminal (for example, a gate terminal), and is connected between a first terminal (for example, a source terminal) of the PMOS transistor P27 and a power supply terminal. The NMOS transistor N47 is connected to the NMOS transistor N28 in parallel by the selection signal SFT being given to the control terminal (for example, gate terminal).

  In the SR latch 23a, the PMOS transistor P47 is turned off and the NMOS transistor N47 is turned on while the selection signal SFT is at a high level for selecting the shift data Sin. As a result, the SR latch 23a operates as an inverter composed of the PMOS transistor P28 and the NMOS transistor N28 during the period in which the selection signal SFT instructs the selection of the shift data Sin, so that the PMOS transistor P27 and the NMOS transistor N27 are disabled. Function. That is, the SR latch 23a can switch whether to disable or enable the gating function of the clock signal CK according to the logic level of the selection signal SFT.

Embodiment 5
FIG. 37 shows a block diagram of the flip-flop 4 according to the fifth embodiment. As shown in FIG. 37, the flip-flop 4 according to the fifth embodiment is a modification of the flip-flop 1 according to the first embodiment. In the description of the fourth embodiment, the same components as those described in the above embodiment are denoted by the same reference numerals as those in the above embodiment, and the description thereof is omitted.

  As shown in FIG. 37, the flip-flop 4 according to the fifth embodiment includes a clock control circuit 10a having a mismatch detection circuit 11a instead of the mismatch detection circuit 11. Then, the mismatch detection circuit 11a refers to the input data Din and the inverted input data DinB as the data on the input side, and refers to the holding values (for example, the holding value X and the inverted holding value XB) of the master latch MA as the output side data. To do. The mismatch detection circuit 11a detects a mismatch between the input data Din and the held value X of the master latch, and outputs a mismatch detection signal S11.

  A block diagram of a flip-flop 400 using 10a as the clock control circuit 10 of the flip-flop 1 according to the first embodiment is shown in FIG. As shown in FIG. 38, in the flip-flop 400, the mismatch detection circuit 11a refers to the input data Din and the inverted input data DinB as the input side data, and refers to the output data Do and the inverted output data DoB as the output side data. .

  That is, the flip-flop 4 according to the fifth embodiment differs from the flip-flop 400 in the signal referred to by the mismatch detection circuit 11a. Thereby, in the flip-flop 4 according to the fifth embodiment, the ease of layout can be improved. Therefore, a schematic diagram of the layout of the flip-flop 4 is shown in FIG. 39, and a schematic diagram of the layout of the flip-flop 400 is shown in FIG.

  As shown in FIGS. 39 and 40, in the flip-flop, a clock control circuit and a slave latch are arranged with a master latch interposed therebetween. With such an arrangement, it is possible to shorten the length of the wiring that transmits the input data Din and the inverted input data DinB and the wiring that transmits the signal Mo from the master latch to the slave latch.

  Here, in the flip-flop 4 according to the fifth embodiment, the output-side data referred to by the mismatch detection circuit 11a of the clock control circuit is the hold value X and the inverted hold value XB of the master latch. Therefore, as shown in FIG. 39, in the flip-flop 4, the wiring for transmitting the hold value X and the inverted hold value XB only connects adjacent regions.

  On the other hand, in the flip-flop 400, it is necessary to wire the wiring for transmitting the output data Do and the inverted output data DoB across the master latch. That is, in the flip-flop 400, the number of wirings that must be wired across the layout cells is larger than that in the flip-flop 4.

  Here, the operation of the flip-flop 4 according to the fifth embodiment will be described. FIG. 41 shows a timing chart showing the operation of the flip-flop 4 according to the fifth embodiment. As shown in FIG. 41, the operation of the flip-flop 4 is the same as that of the first embodiment except that the pulse width of the mismatch detection signal S11 is narrower than that of the flip-flop 1 according to the first embodiment shown in FIG. This is the same as the flip-flop 1. In the flip-flop 4 according to the fifth embodiment, the mismatch detection circuit 11a refers to the holding value X and the inverted holding value X of the master latch MA as output side data. Therefore, in the flip-flop 4, only a period until the master latch MA updates the hold value after the internal clock signal CKx transits from the high level to the low level in response to the change in the signal level of the input data Din. The detection signal S11 becomes high level. However, the SR latch 13 maintains the internal clock signal CKx at the high level until the clock signal CKS becomes the high level after the mismatch detection signal S11 once becomes the high level and the internal clock signal CKx transits to the high level. . Therefore, even if the pulse width of the mismatch detection signal S11 becomes narrow, no problem occurs in the substantial operation, and the flip-flop 4 according to the fifth embodiment operates substantially the same as the flip-flop 1 according to the first embodiment. It can be performed.

  From the above description, in the flip-flop 4 according to the fifth exemplary embodiment, the number of wirings arranged across the layout cells can be reduced. As a result, the flip-flop 4 according to the fifth embodiment can achieve high wiring properties and improve the ease of layout.

Embodiment 6
In the sixth embodiment, a specific usage mode of the flip-flops 1 to 4 described in the above embodiment will be described. In the following description, three usage modes from the first example to the third example will be described. Further, in the following description, an example of a semiconductor device using the flip-flop 1 will be described as a usage form of the flip-flops 1 to 4.

  First, FIG. 42 shows a first example of a block diagram of a semiconductor device 8a showing a circuit configuration as a first example of a semiconductor device including the flip-flop 1 according to the first embodiment. As shown in FIG. 42, the semiconductor device 8a supplies the clock signal CKS to the plurality of flip-flops 1 through the clock tree and the gating buffer. Then, various operations are executed by supplying output signals of the plurality of flip-flops 1 to the logic circuit. In addition, the semiconductor device 8a includes a control signal generation unit that gives an instruction to the gating buffer whether to transmit the clock signal CKS to the subsequent circuit or to block it. In the example of FIG. 42, the control signal generation unit generates a control signal to be given to the gating buffer based on a signal output from the logic circuit according to the processing result.

  As described above, by providing the gating buffer, the toggle of the clock signal CKS supplied to the flip-flop 1 can be suppressed. However, even in such a case, it is possible to suppress the toggle frequency of the internal clock signal CKx based on the input data Din by using the flip-flop 1. In other words, by using the flip-flop 1, it is possible to further reduce the power consumption of the semiconductor device as compared with the case where the clock control is performed by the gating buffer.

  Next, FIG. 43 shows a block diagram of a semiconductor device 8b showing a circuit configuration as a second example of the semiconductor device including the flip-flop 1 according to the first embodiment. As shown in FIG. 43, the semiconductor device 8b is obtained by replacing the gating buffer of the semiconductor device 8a shown in FIG. 42 with a clock buffer included in the clock tree. That is, in the semiconductor device 8b, each of the plurality of flip-flops 1 is directly supplied with the clock signal CKS from the clock tree.

  Since the gating buffer generally has a large variation in driving capability, a circuit is configured with elements larger than the clock buffer in consideration of the variation. Therefore, the semiconductor device 8b can reduce the circuit scale as compared with the semiconductor device 8a. In such a case, the input data Din is not changed by using the flip-flop 1 according to the first embodiment (that is, the supply of the clock signal CKS to the flip-flop can be stopped by the gating buffer). The power consumption of the semiconductor device 8b can be reduced. Further, the power consumption can be reduced to the following level when the clock signal CKS is supplied to the general flip-flop 200 via the gating buffer.

  Subsequently, FIG. 44 shows a block diagram of a semiconductor device 8c showing a circuit configuration of a third example of the semiconductor device including the flip-flop according to the first embodiment. As shown in FIG. 44, the semiconductor device 8c includes a calculation unit (for example, a CPU core 81), an interrupt control unit 82, a ROM (Read Only Memory) 83, a RAM (Random Access Memory) 84, a timer 85, an analog-digital conversion. A circuit 86 and an input / output interface 87 are provided.

  The CPU core 81 performs a calculation operation based on a program storage unit (not shown) or a program stored in the ROM 83 or the like. The ROM 83, RAM 84, timer 85, analog / digital conversion circuit 86, and input / output interface 87 are peripheral circuits used for the CPU core 81. In the semiconductor device 8c, the CPU core 81 and the peripheral circuit are connected to each other via the local bus BUS. The interrupt control unit 82 issues an interrupt request INT based on the error signal ERR that the peripheral circuit notifies of the occurrence of an error. In the semiconductor device 8c, when an interrupt request INT is issued, the CPU core 81 executes an interrupt process for dealing with the error, and performs a return process for the generated error.

  Here, the interrupt control unit 82 includes the flip-flop 1 according to the first embodiment. Then, the interrupt control unit 82 receives the error signal ERR by the flip-flop 1. The error signal ERR is a signal having a low occurrence frequency. When the internal clock signal CKx is always toggled based on the clock signal for waiting for such a signal, power consumption is wasted. Therefore, by using the flip-flop 1 according to the first embodiment for a standby portion of a signal with a low toggle frequency such as the error signal ERR1, the semiconductor device 8c can reduce the power consumption of the signal standby.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, although the rising edge trigger type flip-flop is used as the data holding unit 15 in the above embodiment, a falling edge trigger type flip-flop can be used as the data holding unit 15. In this case, the inverted internal clock signal CKxB may be input to the clock input terminal TCA of the falling edge trigger type flip-flop, and the internal clock signal CKx may be input to the inverted clock input terminal TCB.

1-4, 1a, 2a Flip-flop 5a-5c Semiconductor device 10, 10a, 20, 30, 40, 50 Clock control circuit 11, 11a, 21, 21a Mismatch detection circuit 12, 12a, 22, 22a Internal clock generator 13 , 13a, 23, 23a SR latch 14, 24 Inverter 15, 15S Data holding unit 111a, 111b Transfer switch 81 CPU core 82 Interrupt control unit 83 ROM
84 RAM
85 Timer 86 Analog-to-digital conversion circuit 87 Input / output interface BUS Local bus ERR Error signal INT Interrupt request NOR1, NOR2, NOR2S Inverted OR circuit NAND1, NAND2, NAND2S Inverted AND circuit MA Master latch MAS Master latch SL Slave latch TSWa1, TSWa2, TSWas Transfer switch TSWb1, TSWb2, TSWbs Transfer switch MP PMOS transistor MN NMOS transistor D Data input terminal CK Clock input terminal Qo Data output terminal S Set terminal R Reset terminal QL Latch output terminal QLB Inverted latch output terminal DF Data input terminal TCA Clock input terminal TCB Inverted clock input terminal QF Data output terminal NQ L latch output wiring RST reset signal SI shift data input terminal SE shift control terminal Din input data DinB inverted input data CKS clock signal Do output data DoB inverted output data S11, S21 mismatch detection signal CKx internal clock signal CKxB inverted internal clock signal Sin shift Data SFT Shift control signal SFTB Inverted shift control signal

Claims (13)

A mismatch detection circuit that detects a mismatch between input data and output data and outputs a mismatch detection signal;
The mismatch detection signal is input to one of a set input terminal and a reset input terminal, an operation clock signal is input to the other of the set input terminal and the reset input terminal, and the mismatch detection circuit and the operation clock signal are A set-reset latch that generates an internal clock signal based on
A data holding unit that holds the input data using the internal clock signal as a trigger signal,
The set-reset latch is
A semiconductor device constituted by one of an inverted logical sum circuit and an inverted logical product circuit. The set-reset latch includes a first inverting OR circuit and a second inverting OR circuit each having a first input terminal, a second input terminal, and an output terminal,
The mismatch detection signal is input to one of a first input terminal of the first inverting OR circuit and a first input terminal of the second inverting OR circuit,
The operation clock signal is input to the other of the first input terminal of the first inverting OR circuit and the first input terminal of the second inverting OR circuit,
An output terminal of the first inverting OR circuit and a second input terminal of the second inverting OR circuit are connected;
The semiconductor device according to claim 1, wherein an output terminal of the second inverting OR circuit is connected to a second input terminal of the first inverting OR circuit. The mismatch detection circuit is an exclusive OR circuit,
The mismatch detection signal is supplied to a first input terminal of the first inverting OR circuit,
The operation clock signal is supplied to a first input terminal of the second inverting OR circuit,
The set / reset latch receives a notification that the input data and the output data are in a mismatch state by the mismatch detection signal, and outputs the operation clock signal from the output terminal of the second inverting OR circuit. The semiconductor device according to claim 2, wherein the internal clock signal having a reverse phase is generated. The set / reset latch includes a first inverting AND circuit and a second inverting AND circuit each having a first input terminal, a second input terminal, and an output terminal;
The mismatch detection signal is input to one of a first input terminal of the first inverting AND circuit and a first input terminal of the second inverting AND circuit,
The operation clock signal is input to the other of the first input terminal of the first inverting AND circuit and the first input terminal of the second inverting AND circuit,
An output terminal of the first inverting AND circuit and a second input terminal of the second inverting AND circuit are connected;
2. The semiconductor device according to claim 1, wherein an output terminal of the second inverting AND circuit is connected to a second input terminal of the first inverting AND circuit. The mismatch detection circuit is an exclusive inversion OR circuit,
The mismatch detection signal is supplied to a first input terminal of the first inverting AND circuit,
The operation clock signal is supplied to a first input terminal of the second inversion AND circuit.
The set / reset latch receives a notification that the input data and the output data are in a mismatch state by the mismatch detection signal, and outputs the operation clock signal from the output terminal of the second inverting AND circuit. The semiconductor device according to claim 5, wherein the internal clock signal having the same phase is generated.   2. The semiconductor device according to claim 1, wherein the number of transistors to which the operation clock signal is input is two or less. The input data includes first input data and second input data,
The data holding unit includes a first wiring through which either the first input data or the second input data is transmitted according to a selection signal given from the outside, and the first wiring is connected to the first wiring. The transferred held data is held according to the internal clock signal,
When the selection signal indicates that the second input data is selected, the set / reset latch has a logic level corresponding to a change in the logic level of the operation clock signal regardless of the logic level of the mismatch detection signal. The semiconductor device according to claim 1, wherein the internal clock signal that changes is generated.   The semiconductor according to claim 7, wherein the mismatch detection circuit refers to the first input data as the input data, detects a mismatch between the first input data and the output data, and outputs a mismatch detection signal. apparatus. The set / reset latch includes a first inverted OR circuit and a second inverted OR circuit,
The second inverting OR circuit includes:
A first transistor of a first conductivity type, wherein an output terminal of the first inverting OR circuit is connected to a control terminal, and a first terminal is connected to a power supply terminal;
The operation clock signal is supplied to a control terminal, a first terminal is connected to a second terminal of the first transistor, and a second terminal is an output terminal of the second inverting OR circuit. A second transistor of the conductivity type;
A second transistor of a second conductivity type, wherein an output terminal of the first inverting OR circuit is connected to a control terminal, and a second terminal is connected to an output terminal of the second inverting OR circuit;
The operation clock signal is supplied to the control terminal, the second terminal is connected to the output terminal of the second inverting OR circuit, and the first terminal is connected to the ground terminal. A transistor,
An inverted selection signal obtained by inverting the selection signal is supplied to a control terminal, and a fifth transistor of a first conductivity type connected in parallel with the first transistor;
A sixth transistor of a second conductivity type, which is provided between the first terminal of the fourth transistor and the ground terminal, the inverted selection signal being applied to a control terminal;
The semiconductor device according to claim 7. The set / reset latch includes a first inverting AND circuit and a second inverting AND circuit,
The second inverting AND circuit includes:
A first transistor of a first conductivity type in which an output terminal of the first inverting AND circuit is connected to a control terminal and a second terminal is connected to an output terminal of the second inverting AND circuit;
The operation clock signal is applied to the control terminal, the first terminal is connected to the power supply terminal, and the second terminal is connected to the output terminal of the second inverting AND circuit. Transistors
A second transistor of a second conductivity type, wherein an output terminal of the first inverting OR circuit is connected to a control terminal, and a second terminal is connected to an output terminal of the second inverting OR circuit;
The operation clock signal is supplied to the control terminal, the second terminal is connected to the output terminal of the second inverting OR circuit, and the first terminal is connected to the ground terminal. A transistor,
A fifth transistor of a first conductivity type, wherein the selection signal is applied to a control terminal, and is connected between the first terminal of the first transistor and the power supply terminal;
A second transistor of a second conductivity type, which is supplied to the control terminal and connected in parallel with the fourth transistor;
The semiconductor device according to claim 7. The data holding unit
A master latch that holds the held data in accordance with a first internal clock signal included in the internal clock signal;
A slave latch that is included in the internal clock signal and holds an output value of the master latch in accordance with a second clock signal having a logic level that is inverted from the first internal clock signal;
The mismatch detection circuit refers to the held value of the master latch as the output data,
The semiconductor device according to claim 1, wherein a mismatch between the input data and a held value of the master latch is detected and the mismatch detection signal is output. A plurality of flip-flop circuits each having the mismatch detection circuit, the set-reset latch, and the data holding unit;
The semiconductor device according to claim 1, further comprising: a clock tree that distributes the operation clock signal to each of the plurality of flip-flops. A calculation unit that performs a calculation operation based on a program;
Peripheral circuits used in the arithmetic unit;
An interrupt control unit that issues an interrupt request to the arithmetic unit based on an error signal notified from the peripheral circuit;
A flip-flop circuit that receives the error signal in the interrupt control unit, and includes the mismatch detection circuit, the set-reset latch, and the data holding unit;
The semiconductor device according to claim 1, comprising:

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