JP2014157862A - Semiconductor integrated circuit, display device, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, a display device, and an electronic device which can be reduced in size when a plurality of units are connected in parallel to be used.SOLUTION: An LED driver 4B has: current sink terminals Tcs 1-Tcs 4 connected to an LED 5 (5A1...5An, 5B1...5Bn, 5C1... 5Cn, 5D1...5Dn); input terminal T3 connected to an external LED driver 4B; a first buffer 41B which outputs the minimum voltage out of the terminal voltage of the current sink terminals Tcs 1-Tcs 4 and the terminal voltage of the input terminal T3; an output terminal T4 which outputs the minimum voltage to be outputted from the first buffer 41B; an error amplifier 42 in which the minimum voltage to be outputted from the first buffer 41B is inputted; and a PWM circuit (a PWM comparator 43, an oscillation circuit 45) which controls drive voltage of the LED 5 on the basis of the output of the error amplifier 42.

Description

  The present invention relates to a semiconductor integrated circuit, a display device, and an electronic device.

  Conventionally, an LED (Light Emitting Diode) is used as a backlight of a liquid crystal panel. For example, Patent Document 1 discloses a technique for driving at a constant current while suppressing an increase in mounting area even when a large current is passed through an LED array. In this LED drive circuit, the minimum voltage among the terminal voltages on the LED string side in each constant current drive element is monitored.

JP 2010-161264 A

  By the way, depending on the size of the liquid crystal panel, a plurality of ICs on which LED driving circuits are mounted may be used in parallel. In this case, it is important to reduce the chip size as well as disperse the heat generated by each chip.

  An object of the present invention is to provide a semiconductor integrated circuit, a display device, and an electronic apparatus that can be reduced in size when used in parallel.

  According to one aspect of the present invention, a current sink terminal connected to the LED, an input terminal connected to an external semiconductor integrated circuit, a terminal voltage of the current sink terminal, and a minimum of the terminal voltage of the input terminal A first buffer that outputs a voltage; an output terminal that outputs a minimum voltage output from the first buffer; an error amplifier that receives a minimum voltage output from the first buffer; and an output of the error amplifier. A semiconductor integrated circuit comprising a PWM circuit for controlling the driving voltage of the LED is provided.

  According to another aspect of the present invention, there is provided a display device comprising: a display unit; an LED that irradiates the display unit; and a semiconductor integrated circuit that drives the LED, wherein the semiconductor integrated circuit includes the LED A current sink terminal connected to the input terminal; an input terminal connected to an external semiconductor integrated circuit; a first buffer that outputs a terminal voltage of the current sink terminal and a terminal voltage of the input terminal; An output terminal for outputting a minimum voltage output from the first buffer, an error amplifier to which the minimum voltage output from the first buffer is input, and a drive voltage of the LED are controlled based on the output of the error amplifier. A PWM circuit, and the output terminal included in the specific semiconductor integrated circuit is connected to the input terminal included in another specific semiconductor integrated circuit via a wiring. It allows the display device a plurality of said semiconductor integrated circuit is cascaded provided.

  According to another aspect of the present invention, there is provided an electronic apparatus including a display device, wherein the display device includes a display unit, an LED that irradiates the display unit, and a plurality of semiconductor integrated devices that drive the LED. The semiconductor integrated circuit includes a current sink terminal connected to the LED, an input terminal connected to an external semiconductor integrated circuit, a terminal voltage of the current sink terminal, and a terminal voltage of the input terminal. A first buffer that outputs the minimum voltage, an output terminal that outputs the minimum voltage output from the first buffer, an error amplifier that receives the minimum voltage output from the first buffer, and the error amplifier A PWM circuit for controlling the drive voltage of the LED based on the output of the LED, and the output terminal of the specific semiconductor integrated circuit is connected to another specific semiconductor through a wiring. By being connected to the input terminal of the integrated circuit comprises, an electronic apparatus in which a plurality of said semiconductor integrated circuit is cascaded is provided.

  According to the present invention, it is possible to provide a semiconductor integrated circuit, a display device, and an electronic device that can be reduced in size when used in parallel.

The typical block block diagram of the display apparatus which concerns on 1st Embodiment. The typical circuit block diagram of the LED driver which concerns on a basic technique. It is explanatory drawing of the current sink block with which the LED driver which concerns on basic technology is provided, Comprising: (a) Typical circuit block diagram of current sink block, (b) Current and voltage between source and drain of nMOS provided in current sink block The graph which shows the relationship. The graph which shows the relationship between the electric current which flows through the error amplifier with which the LED driver which concerns on basic technology is provided, and the input voltage of an error amplifier. The typical circuit block diagram in the case of using the some LED driver which concerns on basic technology in parallel connection. The typical circuit block diagram which paid its attention to the specific LED driver among the several LED drivers which concern on basic technology. The typical circuit block diagram of the LED driver which concerns on 1st Embodiment. The typical circuit block diagram in the case of using the some LED driver which concerns on 1st Embodiment connected in parallel. The typical circuit block diagram which paid its attention to the specific LED driver among the some LED drivers which concern on 1st Embodiment. The typical circuit block diagram of the LED driver which concerns on 2nd Embodiment. The typical circuit block diagram in the case of using the some LED driver which concerns on 2nd Embodiment in parallel connection. The typical circuit block diagram which paid its attention to the specific LED driver among the several LED drivers which concern on 2nd Embodiment. The typical circuit block diagram of the LED driver which concerns on 3rd Embodiment. The typical circuit block diagram in the case of using the several LED driver which concerns on 3rd Embodiment connected in parallel. The typical circuit block diagram which paid its attention to the specific LED driver among the some LED drivers which concern on 3rd Embodiment. The typical circuit block diagram of the source driver with which the display apparatus which concerns on the 1st-3rd embodiment is provided. FIG. 17 is a time chart showing the operation of the source driver shown in FIG. The typical block block diagram which shows the specific example of the display apparatus which concerns on the 1st-3rd embodiment. It is explanatory drawing of the specific example of the display apparatus which concerns on the 1st-3rd embodiment, Comprising: (a) The example of the surface photograph which mounted the slave chip on the COF board, (b) The typical plane block of the slave chip Diagram. It is explanatory drawing of the specific example of the display apparatus which concerns on 1st-3rd embodiment, Comprising: (a) The example of the surface photograph which mounted the master chip on the COF board, (b) The typical plane block of the master chip Diagram.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness of each component and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, and structure of each component. The arrangement is not specified below. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First Embodiment]
Hereinafter, the first embodiment will be described with reference to FIGS.

  As shown in FIG. 7, the LED driver (semiconductor integrated circuit) 4B according to the first embodiment is connected to LEDs 5 (5A1... 5An, 5B1... 5Bn, 5C1... 5Cn, 5D1... 5Dn). Tcs1 to Tcs4, an input terminal T3 connected to the external LED driver 4B, a first buffer 41B that outputs a minimum voltage among the terminal voltages of the current sink terminals Tcs1 to Tcs4 and the input terminal T3, The output terminal T4 that outputs the minimum voltage output from the first buffer 41B, the error amplifier 42 that receives the minimum voltage output from the first buffer 41B, and the drive voltage of the LED 5 based on the output of the error amplifier 42 PWM circuit (PWM comparator 43, oscillation circuit 45). For example, as shown in FIG. 8, the output terminal T4 included in the LED driver 4B2 is connected to the input terminal T3 included in the LED driver 4B1 via the wiring 83. Thereby, a plurality of LED drivers 4B1 to 4B4 can be cascade-connected.

  Further, the voltage is boosted so that the minimum voltage among the terminal voltages of all the current sink terminals Tcs1 to Tcs4 included in the plurality of LED drivers 4B1 to 4B4 is equal to or higher than a predetermined voltage. In this case, an external booster circuit may be operated by the leading LED driver 4B1 among the plurality of LED drivers 4B1 to 4B4.

(Display device)
A schematic block configuration of the display device according to the first embodiment is expressed as shown in FIG. This display device is a display device used in an electronic device such as a television receiver or a portable game device. As shown in FIG. 1, a microcomputer 1, an LCD driver 2, a liquid crystal panel 3, and an LED driver 4 are used. And the LED 5.

  The microcomputer 1 performs overall control of the entire apparatus. When a video signal is input from a media playback device (not shown), a data signal for driving the RGB pixels of the liquid crystal panel 3 and a frame synchronization signal for synchronizing screen display processing in the liquid crystal panel 3 are generated. To do. The frame synchronization signal includes a horizontal synchronization signal for synchronizing the frame in the horizontal direction and a vertical synchronization signal for synchronizing the frame in the vertical direction.

  The LCD driver 2 includes a source driver and a gate driver. Based on the data signal and the frame synchronization signal from the microcomputer 1, the source signal and the gate signal of the liquid crystal panel 3 are generated and supplied to the liquid crystal panel 3. The liquid crystal panel 3 extends a plurality of source signal lines and gate signal lines in a vertical direction and a horizontal direction, and a liquid crystal pixel provided at each intersection of both signal lines according to on / off of an active element (field effect transistor). Drive. The LCD driver 2 and the liquid crystal panel 3 are not limited to the active matrix type, and may be a simple matrix type.

  The LED 5 is a backlight that irradiates the liquid crystal panel 3 from the back. Between the liquid crystal panel 3 and the LED 5, light guide means for uniformly irradiating the entire surface of the liquid crystal panel 3 with the light from the LED 5 is provided. The LED driver 4 performs light emission control of the LED 5. In the present embodiment, a plurality of LED drivers 4 are connected in parallel according to the size of the liquid crystal panel 3.

(LED driver related to basic technology)
A schematic circuit configuration of the LED driver 4A according to the basic technique is expressed as shown in FIG. 2, a plurality of LEDs 5A1... 5An, 5B1... 5Bn, 5C1... 5Cn, 5D1... 5Dn are connected in series, and these LEDs 5A1. Are connected in parallel. The LED driver 4A includes a buffer (return select circuit) 41A, an error amplifier (error amplifier) 42, a PWM comparator 43, a boost controller 44, an oscillation circuit 45, a current sensor 46, output terminals T1 and T2, Current sink terminals Tcs1 to Tcs4 are provided. The LEDs 5A1... 5An, 5B1... 5Bn, 5C1... 5Cn, 5D1... 5Dn are connected to the current sink terminals Tcs1 to Tcs4, respectively. Each of the current sync terminals Tcs1 to Tcs4 is connected to the buffer 41A via a current sync block described later. The buffer 41A selects and outputs the minimum voltage among the terminal voltages of the current sink terminals Tcs1 to Tcs4 (hereinafter sometimes simply referred to as “the minimum voltage of the current sink terminals Tcs1 to Tcs4”). The error amplifier 42 compares the minimum voltage output from the buffer 41A with a reference voltage, and outputs a voltage corresponding to the difference. The PWM comparator 43 compares the output of the error amplifier 42 with the triangular wave output from the oscillation circuit 45 and determines the pulse width of the PWM signal. An external capacitor C1 and a resistor R are connected via the output terminal T1, and phase compensation is performed. An external coil L, a diode D, and a capacitor C2 are connected via an output terminal T2 to constitute a booster circuit. A switching transistor 51 and a detection resistor 52 are disposed in series between the output terminal T2 and the ground.

  The current sync block included in the LED driver 4A according to the basic technology is expressed as shown in FIG. Specifically, FIG. 3A is a schematic circuit configuration diagram of the current sink block, and FIG. 3B is a diagram between the source and drain of an nMOS (negative channel metal oxide semiconductor) 63 provided in the current sink block. It is a graph which shows the relationship between current Ids and voltage Vds. The current sink block realizes a function of flowing a constant current without channel variations. As shown in FIG. 3A, when it is desired to pass a current Ids of, for example, 20 mA between the source and drain of the nMOS 63, it is assumed that the resistance value of the resistor 64 is 10Ω. The comparator 62 compares the drain voltage of 200 mV with the reference voltage from the reference voltage source 61. In this case, if a current of 20 mA is to flow with high accuracy between the channels, it is necessary to supply a voltage Vds of 0.6 V or higher between the source and drain of the nMOS 63 as shown in FIG. Therefore, the voltage is boosted by an external booster circuit with feedback so that the terminal voltages of the current sink terminals Tcs1 to Tcs4 are 0.6V or more.

  A graph showing the relationship between the current Ierror flowing through the error amplifier 42 included in the LED driver 4A according to the basic technology and the input voltage Vtcsx of the error amplifier 42 is expressed as shown in FIG. That is, the voltage input to the error amplifier 42 becomes the minimum voltage Vtcsx (x = 1 to 4) of the current sink terminals Tcs1 to Tcs4. As shown in FIG. 4, when the input voltage Vtcsx (= Vout) of the error amplifier 42 is low so that the minimum voltage of the current sink terminals Tcs1 to Tcs4 is 0.6 V or more, the error amplifier output is controlled to increase. To do.

  A schematic circuit configuration when a plurality of LED drivers 4A1 to 4A4 according to the basic technology are connected in parallel is shown as shown in FIG. Further, a schematic circuit configuration focusing on the LED driver 4A1 among the plurality of LED drivers 4A1 to 4A4 is expressed as shown in FIG. When used in parallel as described above, as shown in FIG. 5, the top LED driver 4A1 operates the booster circuit, and the other LED drivers 4A2 to 4A4 operate only the current sync block. Then, the error amplifier outputs of the LED drivers 4A2 to 4A4 at the head are set as indicated by bold lines in FIG. 6 so that the minimum voltage of the current sink terminals Tcs1 to Tcs4 of the LED drivers 4A2 to 4A4 is 0.6 V or more. Connect to the error amplifier output of the LED driver 4A1.

  Therefore, according to this basic technique, one wiring 71 to 73 is required for each IC of the LED drivers 4A2 to 4A4. Further, when the minimum voltage of the current sink terminals Tcs1 to Tcs4 of the specific LED driver 4A is higher than that of the other LED driver 4A, the specific LED driver 4A operates to lower the error amplifier output of the other LED driver 4A. To do. Therefore, as shown in FIG. 5, it is necessary to dispose a diode 74 in each of the wirings 71 to 73.

(LED driver according to the first embodiment)
A schematic circuit configuration of the LED driver 4B according to the first embodiment is expressed as shown in FIG. As shown in FIG. 7, the LED driver 4B includes a first buffer 41B that outputs a minimum voltage among the terminal voltages of the current sink terminals Tcs1 to Tcs4 and the terminal voltage of the input terminal T3. In other words, the first buffer 41B is obtained by adding a buffer that outputs the minimum voltage and the minimum voltage of the external input to the buffer 41A that outputs the minimum voltage of the current sink terminals Tcs1 to Tcs4. The output terminal T4 outputs the minimum voltage output from the first buffer 41B. Other configurations are the same as those of the basic technology.

  A schematic circuit configuration in the case where a plurality of LED drivers 4B1 to 4B4 according to the first embodiment are connected in parallel is used as shown in FIG. Also, a schematic circuit configuration focusing on the LED driver 4B1 among the plurality of LED drivers 4B1 to 4B4 is expressed as shown in FIG. In the present embodiment, as shown in FIG. 8, a plurality of LED drivers 4B1 to 4B4 are cascade-connected via wirings 81 to 83. That is, the output terminal T4 of the LED driver 4B4 is connected to the input terminal T3 of the LED driver 4B3 via the wiring 81 (see the thick line in FIG. 9). Similarly, the output terminal T4 of the LED driver 4B3 is connected to the input terminal T3 of the LED driver 4B2 via the wiring 82. Furthermore, the output terminal T4 of the LED driver 4B2 is connected to the input terminal T3 of the LED driver 4B1 via the wiring 83. In this case, an external diode 74 is not necessary for the wirings 81 to 83. In this way, wiring is performed one by one between the chips, and the minimum voltages of all current sink terminals Tcs1 to Tcs4 are monitored. Here, all the current sink terminals Tcs1 to Tcs4 are 4 × 4 = 16 terminals. The voltage is boosted by the booster circuit so that the minimum voltage among the 16 terminal voltages is 0.6V or higher. Other configurations are the same as those of the basic technology.

  As described above, the LED driver 4B according to the first embodiment includes the first buffer 41B that outputs the minimum voltage among the terminal voltages of the current sink terminals Tcs1 to Tcs4 and the terminal voltage of the input terminal T3. Therefore, a plurality of LED drivers 4B1 to 4B4 can be cascade-connected. In this case, the wiring between the chips can be made one, and the external diode 74 is not necessary, so that the size can be reduced. Particularly in notebook personal computers and tablet terminals, it is highly necessary to reduce the size and thickness of a PCB (Printed Circuit Board), and therefore it is effective to apply the LED driver 4B according to the present embodiment.

[Second Embodiment]
Hereinafter, only differences between the second embodiment and the first embodiment will be described.

  As shown in FIG. 10, the first buffer 41B includes a second buffer 41c that outputs a minimum voltage among the terminal voltages of the current sink terminals Tcs1 to Tcs4, a minimum voltage output from the second buffer 41c, and an input terminal T5. And a third buffer 47 that outputs a minimum voltage of the terminal voltages of the first and second terminals. In this case, the output terminal T6 outputs the minimum voltage output from the third buffer 47.

  A schematic circuit configuration of the LED driver 4C according to the second embodiment is expressed as shown in FIG. As shown in FIG. 10, the LED driver 4C includes a third buffer 47 subsequent to the second buffer 41c, and outputs the minimum voltage output from the third buffer 47 from the output terminal T6. Here, the second buffer 41c outputs the minimum voltage among the terminal voltages of the current sink terminals Tcs1 to Tcs4. The third buffer 47 outputs the minimum voltage of the minimum voltage output from the second buffer 41c and the terminal voltage of the input terminal T5. In this case, the second buffer 41c and the third buffer 47 perform the same function as the first buffer 41B.

  A schematic circuit configuration in the case of using a plurality of LED drivers 4C1 to 4C4 according to the second embodiment connected in parallel is expressed as shown in FIG. A schematic circuit configuration focusing on the LED driver 4C1 among the plurality of LED drivers 4C1 to 4C4 is expressed as shown in FIG. Also in the present embodiment, as shown in FIG. 11, a plurality of LED drivers 4C1 to 4C4 are cascade-connected via wirings 84 to 86. That is, the output terminal T6 of the LED driver 4C4 is connected to the input terminal T5 of the LED driver 4C3 via the wiring 84 (see the thick line in FIG. 12). Similarly, the output terminal T6 of the LED driver 4C3 is connected to the input terminal T5 of the LED driver 4C2 via the wiring 85. Further, the output terminal T6 of the LED driver 4C2 is connected to the input terminal T5 of the LED driver 4C1 via the wiring 86. Other configurations are the same as those of the first embodiment.

  As described above, the LED driver 4C according to the second embodiment includes the second buffer 41c that outputs the minimum voltage among the terminal voltages of the current sink terminals Tcs1 to Tcs4, and the minimum output from the second buffer 41c. A third buffer 47 for outputting the minimum voltage of the voltage and the terminal voltage of the input terminal T5. Even in this case, since the second buffer 41c and the third buffer 47 perform the same function as the first buffer 41B, the same effect as that of the first embodiment can be obtained.

[Third Embodiment]
Hereinafter, only differences between the third embodiment and the first or second embodiment will be described.

  As shown in FIG. 13, the first buffer 41B includes a fourth buffer 48 that outputs the terminal voltage of the input terminal T7, a terminal voltage output from the fourth buffer 48, and a terminal voltage of the current sink terminals Tcs1 to Tcs4. And a fifth buffer 41D that outputs the minimum voltage. In this case, the output terminal T8 outputs the minimum voltage output from the fifth buffer 41D.

  A schematic circuit configuration of the LED driver 4D according to the third embodiment is expressed as shown in FIG. As illustrated in FIG. 13, the LED driver 4D includes a fifth buffer 41D subsequent to the fourth buffer 48, and outputs the minimum voltage output from the fifth buffer 41D from the output terminal T8. Here, the fourth buffer 48 outputs the terminal voltage of the input terminal T7. The fifth buffer 41D outputs the minimum voltage among the terminal voltage output from the fourth buffer 48 and the terminal voltages of the current sink terminals Tcs1 to Tcs4. In this case, the fourth buffer 48 and the fifth buffer 41D perform the same function as the first buffer 41B.

  A schematic circuit configuration in the case where a plurality of LED drivers 4D1 to 4D4 according to the third embodiment are used in parallel is expressed as shown in FIG. Also, a schematic circuit configuration focusing on the LED driver 4D1 among the plurality of LED drivers 4D1 to 4D4 is expressed as shown in FIG. Also in this embodiment, as shown in FIG. 14, a plurality of LED drivers 4D1 to 4D4 are cascade-connected via wirings 87 to 89. That is, the output terminal T8 of the LED driver 4D4 is connected to the input terminal T7 of the LED driver 4D3 via the wiring 87 (see the thick line in FIG. 15). Similarly, the output terminal T8 of the LED driver 4D3 is connected to the input terminal T7 of the LED driver 4D2 via the wiring 88. Further, the output terminal T8 of the LED driver 4D2 is connected to the input terminal T7 of the LED driver 4D1 via the wiring 89. Other configurations are the same as those of the first embodiment.

  As described above, the LED driver 4D according to the third embodiment includes the fourth buffer 48 that outputs the terminal voltage of the input terminal T7, the terminal voltage output from the fourth buffer 48, and the current sink terminals Tcs1 to Tcs4. And a fifth buffer 41D that outputs the minimum voltage of the terminal voltages of the first and second terminals. Even in this case, since the fourth buffer 48 and the fifth buffer 41D perform the same function as the first buffer 41B, the same effects as those of the first embodiment can be obtained.

[Specific examples of LCD driver]
Next, specific examples of the LED driver 4 included in the display devices according to the first to third embodiments will be described in detail. Of course, the configuration of the LED driver 4 is not limited to the following configuration, and can be changed as appropriate.

A schematic circuit configuration of the source driver 21 included in the display devices according to the first to third embodiments is expressed as shown in FIG. As shown in FIG. 16, the liquid crystal panel 3 includes m data lines LD and n scanning lines LS. Pixel circuits are arranged in a matrix at intersections of the data lines LD and the scanning lines LS. In FIG. 16, only the TFT for each pixel is shown. The gate of the TFT _{ij in} the i-th row and j-th column is connected to the scanning line LS _j in the j-th column, and its source is connected to the data line LD _i in the _i- th row. The data lines LD _{1 to} LD _m have a structure in which a data line assigned to red, a data line assigned to green, and a data line assigned to blue are repeatedly arranged in this order. That is, the data lines LD ₁ , LD ₄ , LD ₇ ,... Are assigned to red, the data lines LD ₂ , LD ₅ , LD ₈ , ... are assigned to green, and the data lines LD ₃ , LD ₆ , LD ₉ ,. Is assigned to blue. When generalized, the data line LD _3k-2 is assigned to red, the data line LD _3k-1 is assigned to green, and the data line LD _3k is assigned to blue, where k is a natural number. In FIG. 16, the LD _{10 and} later are omitted for the sake of simplicity.

The gate driver 22 receives the data from the timing controller 23 and sequentially selects and drives the plurality of scanning lines LS _{1 to} LS _n . The source driver 21 receives the luminance data from the timing controller 23 and supplies a driving voltage corresponding to the luminance data to the plurality of data lines LD _{1 to} LD _m . The source driver 21 includes digital / analog converters DAC _{1 to} DAC _m , driver amplifiers DRV _{1 to} DRV _m , output switches SWA _{1 to} SWA _m , a red charge averaging switch group SWR, and a green charge averaging switch group SWG. A blue charge averaging switch group SWB, output terminals P _{1 to} P _m, and a data input terminal 26. The source driver 21 may be a functional IC integrated on a single semiconductor substrate. The output terminals P _{1 to} P _m are connected to the corresponding data lines LD _{1 to} LD _m . Luminance data for each pixel is input from the timing controller 23 to the data input terminal 26.

The driver amplifier DRV ₁ outputs a drive voltage for inverting and driving the data line LD ₁ to the output terminal P ₁ through the output switch SWA ₁ . The driver amplifier DRV ₂ outputs a drive voltage for inverting the data line LD ₂ to the output terminal P ₂ through the output switch SWA ₂ . The same applies to the driver amplifiers DRV _{3 to} DRV _m . Two driver amplifiers DRV _i and DRV _{i + 1} that invertly drive two adjacent data lines LD _i and LD _{i + 1} respectively drive the two data lines LD _i and LD _{i + 1} with opposite polarities.

The red charge averaging switch group SWR includes a plurality of red charge averaging switches that pair and connect the two most recent data lines assigned to red. In this embodiment, the red charge averaging switch group SWR includes red charge averaging switches SWR ₁ , SWR ₂ ,... Provided between the data lines LD ₁ , LD ₄ , LD ₇ ,. including. The red charge averaging switch SWR ₁ connects the data lines LD ₁ and LD ₄ . The red charge averaging switch SWR ₂ connects the data lines LD ₇ and LD ₁₀ . When generalized, the red charge averaging switch SWR _l connects the data lines LD _61-5 and LD _61-2 , where l is a natural number. Similarly, the green charge averaging switch group SWG includes green charge averaging switches SWG ₁ , SWG ₂ ,. When generalized, the green charge averaging switch SWG _l connects the data lines LD _6l-4 and LD _{6l-1 where} l is a natural number. Similarly the blue charge averaging switch group SWB, blue charge averaging switches _SWB 1, _{SWB 2,} including .... When generalized, the blue charge averaging switch SWB _l connects the data lines LD _61-3 and LD ₆₁ with l being a natural number.

The control unit 25 controls the connection state of the output switches SWA _{1 to} SWA _m , the red charge averaging switch group SWR, the green charge averaging switch group SWG, and the blue charge averaging switch group SWB. The drive signal generator 24 receives luminance data for each pixel via the data input terminal 26 and generates a signal to be supplied to each data line LD as a digital value. The digital value for each data line LD is output to the digital / analog converters DAC _{1 to} DAC _m . The digital / analog converters DAC _{1 to} DAC _m convert the digital values into analog voltages and output the analog values to corresponding driver amplifiers DRV ₁ to DRV _m .

Drive voltage _Vd 1 to Vd ₆ to be applied to the data line _LD 1 to Ld _6, the driving voltage Vd ₁ and the driving voltage Vd ₄ is a drive voltage to be applied to the data lines assigned to red, opposite to each other Polarity. The drive voltage Vd ₂ and the drive voltage Vd ₅ are drive voltages to be applied to the data lines assigned to green and have opposite polarities. The drive voltage Vd ₃ and the drive voltage Vd ₆ are drive voltages to be applied to the data lines assigned to blue and have opposite polarities.

Next, the operation of the source driver 21 will be described. In general, many images displayed on a liquid crystal panel include a large area composed of a single color. For example, while a computer word processor or spreadsheet software is running, most of the image is white. Also, the login screen when starting up the computer is almost one color. Therefore, in general, there is a high probability that pixels of the same color, in particular, the closest pixel of the same color have the same gradation. Therefore, for data lines, it can be said that the most recent data lines assigned to the same color have a high probability of being driven based on the same luminance data. Based on this discussion, we focus on the data line _LD 1 to Ld ₆ in the following, the data line LD ₁ and LD _4, the data line LD ₂ and LD _5, the data line LD ₃ and LD ₆ is based on the same luminance data, respectively The driven situation will be described.

A time chart showing the operation of the source driver 21 shown in FIG. 16 is expressed as shown in FIG. Reference sign SWA shown in FIG. 17 is a generic name of the output switches SWA _{1 to} SWA _m . The source driver 21 repeats the following operation every time a scanning line is selected. Here, a case where the _j-th scanning line LS _j is selected will be described.

First, at time _{t 1,} the control unit 25 to the output switch _SWA 1 _{~SWA m} turned on, the gate driver 22 selects the scanning lines LS _j, driven. Thereby, charges corresponding to the drive voltage are stored in each data line. Driving voltages having opposite polarities based on the same luminance data are applied to the data lines LD ₁ and LD ₄ . That is, a drive voltage that is substantially symmetrical with respect to the reference potential is applied to the data lines LD ₁ and LD ₄ . The same applies to the data lines LD ₂ and LD ₅ and the data lines LD ₃ and LD ₆ .

At time t ₂ after the scanning line LS _j is driven for a predetermined time, the gate driver 22 stops driving the scanning line LS _j and the control unit 25 turns off the output switches SWA _{1 to} SWA _m . Thereby, each data line is electrically isolated.

Then, at time t _3, the control unit 25 is a red charge averaging switch group SWR, green charge averaging switch group SWG, and turned on a blue charge averaging switch group SWB. As a result, the data line LD ₁ and the data line LD ₄ are connected, and charges move from the data line LD ₁ to the data line LD ₄ through the red charge averaging switch SWR ₁ . As a result, the drive voltage Vd ₁ and the drive voltage Vd ₄ relax toward the reference potential. The same applies to the data line LD ₂ and the data line LD ₅ , and the data line LD ₃ and the data line LD ₆ .

Then at time t ₄ after a predetermined charge averaging time τ has elapsed, the control unit 25 is a red charge averaging switch group SWR, green charge averaging switch group SWG, and blue charge averaging switch group SWB and an off state To do. Thereby, each data line is separated from the other data lines. The charge averaging time τ is set longer than the time necessary for the drive voltage of each data line to reach the vicinity of the reference potential. Thus, at time _{t 4,} the driving voltage _Vd 1 to Vd ₆ becomes near the reference potential. Then, the next scanning line LS _{j + 1} is selected, and a driving voltage is supplied to each data line. At this time, a driving voltage having a polarity opposite to the driving voltage applied when the scanning line LS _j is selected is applied to each data line.

  Thus, in the source driver 21 provided in the display device according to the first to third embodiments, the data lines assigned to the same color are connected by the charge averaging switch. In general, there is a high probability that data lines assigned to the same color are driven based on substantially the same luminance data. Therefore, in this embodiment, the data lines connected by the charge averaging switch are often driven based on substantially the same luminance data. In this case, it is possible to improve the image quality by making the drive voltage uniform by the polarity of the data lines, or to reduce the electric charge discarded by averaging.

[Specific examples of display devices]
Next, specific examples of the display devices according to the first to third embodiments will be described in detail. Of course, the configuration of the display device is not limited to the following configuration, and can be changed as appropriate.

As shown in FIG. 18, the display device 150 according to the first to third embodiments is connected to the display unit 110 and the COF substrate 114 ₁ mounted with the semiconductor integrated circuits 126 ₁ and 126 _2. 114 ₂ and a PCB substrate 116 which is connected to the COF substrates 114 ₁ and 114 ₂ and mounts various discrete components. The display unit 110 corresponds to the liquid crystal panel 3, and the semiconductor integrated circuits 126 ₁ and 126 ₂ correspond to the LED driver 4.

In the display device 150 according to the first to third embodiments, a surface photograph example in which the semiconductor integrated circuit (slave chip) 126 ₂ is mounted on the COF substrate 114 (114 ₁ , 114 ₂ ) is shown in FIG. is expressed as shown in a semiconductor integrated circuit (slave chip) 126 ₁ of schematic plane block diagram of FIG. 19 (a) is expressed as shown in FIG. 19 (b). As shown in FIGS. 19A and 19B, the semiconductor integrated circuits 126 ₂ and 126 ₁ are mounted on a film-shaped COF structure. The mounting dimensions of the semiconductor integrated circuits 126 ₂ and 126 ₁ are about 1.3 mm × 23.0 mm. Since the film-shaped COF substrate 114 is flexible, it can be bent and arranged on the back side of the display unit 110. The semiconductor integrated circuit (slave chip) 126 _2, as shown in FIG. 19 (b), for example, a level shifter (L / S) 106, a timing controller (TCON) 101a, a low voltage differential signaling (LVDS) 108a, DC / DC converters 104 ₁ , 104 ₂ , 104 ₃ , a voltage control IC (VCON) 103, an LDO regulator 102, and a source driver (S / D) 107 a are mounted. The DC / DC converters 104 ₁ and 104 ₂ are for + 5V and −5V, respectively, and are used for the upper power supply and lower power supply of the source driver (S / D) 107a. DC / DC converter ₁₀₄₃ is for + 25V, used for the upper power supply of the gate driver.

In the display device 150 according to the first to third embodiments, a surface photograph example in which the semiconductor integrated circuit (master chip) 126 ₁ is mounted on the COF substrate 114 is represented as shown in FIG. A schematic planar block configuration of the semiconductor integrated circuit (master chip) 126 ₁ in FIG. 20A is expressed as shown in FIG. The semiconductor integrated circuit (master chip) 126 _1, as shown in FIG. 20 (b), for example, LED driver 105, a timing controller (TCON) 101b, the low voltage differential signaling (LVDS) 108b, DC / DC converter 104 _{4. A} source driver (S / D) 107b and a 4ch current sink 109 are mounted.

  As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit, a display device, and an electronic device that can be reduced in size when used in parallel.

[Other embodiments]
As described above, the present invention has been described according to the first to third embodiments. However, it should be understood that the descriptions and drawings constituting a part of this disclosure are exemplary and limit the present invention. should not do. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  As described above, the present invention includes various embodiments not described herein. For example, in the first to third embodiments, the configuration in which one chip of the LED driver 4 is provided with four channels is exemplified, but the number of channels can be changed as appropriate. Moreover, although the configuration in which the four LED drivers 4 are cascade-connected is illustrated, the number of LED drivers 4 to be cascade-connected can be changed as appropriate.

  The semiconductor integrated circuit of the present invention can be applied to LED backlights for liquid crystal monitors, LED displays, and LED lighting. Moreover, it is also possible to apply to various electronic devices using these.

3. Display (liquid crystal panel)
4, 4B, 4C, 4D ... Semiconductor integrated circuit (LED driver)
41B ... 1st buffer 41c ... 2nd buffer 47 ... 3rd buffer 48 ... 4th buffer 41D ... 5th buffer 42 ... Error amplifier 43 ... PWM comparator 45 ... Oscillator circuit 5, 5A1 ... 5An, 5B1 ... 5Bn, 5C1 ... 5Cn 5D1 ... 5Dn ... LED
Tcs1 to Tcs4 ... current sink terminals T3, T5, T7 ... input terminals T4, T6, T8 ... output terminals 81-89 ... wiring L ... coil D ... diode C2 ... capacitance

Claims (16)

A current sink terminal connected to the LED;
An input terminal connected to an external semiconductor integrated circuit;
A first buffer that outputs a minimum voltage of a terminal voltage of the current sink terminal and a terminal voltage of the input terminal;
An output terminal for outputting a minimum voltage output from the first buffer;
An error amplifier to which a minimum voltage output from the first buffer is input;
A semiconductor integrated circuit comprising: a PWM circuit that controls a drive voltage of the LED based on an output of the error amplifier. The first buffer outputs a second buffer that outputs the minimum voltage of the terminal voltages of the current sink terminal, and outputs a minimum voltage of the minimum voltage output from the second buffer and the terminal voltage of the input terminal. And a third buffer that
The semiconductor integrated circuit according to claim 1, wherein the output terminal outputs a minimum voltage output from the third buffer. The first buffer includes: a fourth buffer that outputs a terminal voltage of the input terminal; a fifth buffer that outputs a minimum voltage of a terminal voltage output from the fourth buffer and a terminal voltage of the current sink terminal; With
The semiconductor integrated circuit according to claim 1, wherein the output terminal outputs a minimum voltage output from the fifth buffer.   4. The plurality of semiconductor integrated circuits are cascade-connected by connecting the output terminal of the external semiconductor integrated circuit to the input terminal via a wiring. 2. A semiconductor integrated circuit according to claim 1.   5. The semiconductor integrated circuit according to claim 4, wherein the voltage is boosted so that a minimum voltage among terminal voltages of all of the current sink terminals included in the plurality of semiconductor integrated circuits is equal to or higher than a predetermined voltage.   6. The semiconductor integrated circuit according to claim 5, wherein an external booster circuit is operated by the first semiconductor integrated circuit among the plurality of semiconductor integrated circuits. A display unit;
An LED for illuminating the display unit;
A display device comprising a semiconductor integrated circuit for driving the LED,
The semiconductor integrated circuit is:
A current sink terminal connected to the LED;
An input terminal connected to an external semiconductor integrated circuit;
A first buffer that outputs a minimum voltage of a terminal voltage of the current sink terminal and a terminal voltage of the input terminal;
An output terminal for outputting a minimum voltage output from the first buffer;
An error amplifier to which a minimum voltage output from the first buffer is input;
A PWM circuit for controlling the drive voltage of the LED based on the output of the error amplifier;
A plurality of the semiconductor integrated circuits are cascade-connected by connecting the output terminal included in the specific semiconductor integrated circuit to the input terminal included in another specific semiconductor integrated circuit via a wiring. Characteristic display device. The first buffer outputs a second buffer that outputs the minimum voltage of the terminal voltages of the current sink terminal, and outputs a minimum voltage of the minimum voltage output from the second buffer and the terminal voltage of the input terminal. And a third buffer that
The display device according to claim 7, wherein the output terminal outputs a minimum voltage output from the third buffer. The first buffer includes: a fourth buffer that outputs a terminal voltage of the input terminal; a fifth buffer that outputs a minimum voltage of a terminal voltage output from the fourth buffer and a terminal voltage of the current sink terminal; With
The display device according to claim 7, wherein the output terminal outputs a minimum voltage output from the fifth buffer.   10. The method according to any one of claims 7 to 9, wherein the voltage is boosted so that a minimum voltage among terminal voltages of all of the current sink terminals included in the plurality of semiconductor integrated circuits is equal to or higher than a predetermined voltage. The display device described.   The display device according to claim 10, wherein an external booster circuit is operated by the first semiconductor integrated circuit among the plurality of semiconductor integrated circuits. An electronic device including a display device,
The display device
A display unit;
An LED for illuminating the display unit;
A plurality of semiconductor integrated circuits for driving the LEDs,
The semiconductor integrated circuit is:
A current sink terminal connected to the LED;
An input terminal connected to an external semiconductor integrated circuit;
A first buffer that outputs a minimum voltage of a terminal voltage of the current sink terminal and a terminal voltage of the input terminal;
An output terminal for outputting a minimum voltage output from the first buffer;
An error amplifier to which a minimum voltage output from the first buffer is input;
A PWM circuit for controlling the drive voltage of the LED based on the output of the error amplifier;
A plurality of the semiconductor integrated circuits are cascade-connected by connecting the output terminal included in the specific semiconductor integrated circuit to the input terminal included in another specific semiconductor integrated circuit via a wiring. Features electronic equipment. The first buffer outputs a second buffer that outputs the minimum voltage of the terminal voltages of the current sink terminal, and outputs a minimum voltage of the minimum voltage output from the second buffer and the terminal voltage of the input terminal. And a third buffer that
The electronic device according to claim 12, wherein the output terminal outputs a minimum voltage output from the third buffer. The first buffer includes: a fourth buffer that outputs a terminal voltage of the input terminal; a fifth buffer that outputs a minimum voltage of a terminal voltage output from the fourth buffer and a terminal voltage of the current sink terminal; With
The electronic device according to claim 12, wherein the output terminal outputs a minimum voltage output from the fifth buffer.   15. The method according to claim 12, wherein the voltage is boosted so that a minimum voltage among terminal voltages of all of the current sink terminals included in the plurality of semiconductor integrated circuits is equal to or higher than a predetermined voltage. The electronic device described.   16. The electronic apparatus according to claim 15, wherein an external booster circuit is operated by the first semiconductor integrated circuit among the plurality of semiconductor integrated circuits.