JP2014157647A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of suppressing a standby current by adjusting the potential of a source line while considering the data holding characteristics of memory cells.SOLUTION: A semiconductor memory device comprises: a memory cell array in which static type memory cells are arranged; a source line potential adjustment circuit that is connected between a source line connected to a source of a drive transistor and a ground potential and that adjusts a potential to be applied to the source line; and a source line potential control circuit that controls the source line potential adjustment circuit to determine a potential which is between the ground potential and a power supply potential and which is of the source line at which data can be held in the memory cell during a standby period. The source line potential control circuit reads predetermined data written in a memory cell of the memory cell array after the standby period; and on the basis of the result of the reading, instructs the source line potential adjustment circuit to adjust the potential applied to the source line.

Description

  The present invention relates to a semiconductor memory device, and can be suitably used for a semiconductor memory device having static memory cells, for example.

  In a semiconductor integrated circuit such as an LSI (Large Scale Integrated circuit), the threshold voltage of the transistor used in the semiconductor integrated circuit is changed for each technology as the operating power supply voltage is reduced and the transistor used is miniaturized. It has declined. In a transistor having a low threshold voltage, a standby current flowing between the source and the drain increases when the transistor is in an off state and a standby state.

  In a circuit such as a logic circuit, standby current can be reduced by cutting off power supply to a circuit portion that does not operate. However, in a memory circuit such as a static RAM (Random Access Memory) that needs to hold data, the power supply cannot be cut off even in a non-operating state.

  Furthermore, in a circuit such as a static RAM, a portion occupied by a highly integrated circuit such as a memory cell is large, and the capacity occupied in the chip tends to increase year by year. For this reason, reduction of standby current in memory cells is becoming more and more important in reducing power consumption of semiconductor integrated circuits, and various methods have been proposed (Patent Documents 1-4).

JP 2004-206745 A JP 2006-85786 A JP 2007-317346 A JP 2011-60401 A

  In the above-mentioned documents and the like, a method of adjusting the potential of the source line in a fixed manner in order to suppress the standby current due to manufacturing variation or the like is shown. However, the potential of the source line is data associated with aging of the memory cell. It is desirable to change it in consideration of changes in retention characteristics.

  In order to solve the above problems, a semiconductor memory device capable of suppressing a standby current by adjusting a potential of a source line in consideration of data retention characteristics of a memory cell is provided.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor memory device includes a memory cell array in which static memory cells having a transfer transistor, a drive transistor, and a load transistor are arranged, a source line connected to the source of the drive transistor, A source line potential adjustment circuit for adjusting the potential applied to the source line and connected between the ground potentials, and a potential between the ground potential and the power supply potential by controlling the source line potential adjustment circuit, A source line potential control circuit for determining a potential of a source line capable of holding data in a memory cell during a period. The source line potential control circuit reads predetermined data written in the memory cells of the memory cell array after the standby period, and adjusts the potential applied to the source line with respect to the source line potential adjustment circuit based on the read result. To instruct.

  According to one embodiment, it is possible to suppress the standby current by adjusting the potential of the source line in consideration of the data retention characteristics of the memory cell.

1 is a schematic diagram illustrating an overall configuration of a semiconductor integrated circuit 1 according to a first embodiment. 2 is a schematic block diagram of a configuration of a peripheral circuit 20 that controls an ARVSS potential adjustment circuit 18 according to the first embodiment. FIG. It is a figure explaining the structure of the ARVSS electric potential adjustment circuit 18 according to this Embodiment 1. FIG. It is a figure explaining the adjustment flow of the source potential ARVSS according to the first embodiment. It is a figure explaining the timing chart of the adjustment flow of the source potential ARVSS according to the first embodiment. It is a figure explaining the layout arrangement | positioning of the ARVSS electric potential adjustment circuit 18 according to this Embodiment 1. FIG. FIG. 11 is a schematic block diagram of a configuration of a peripheral circuit 20 that controls an ARVSS potential adjustment circuit 18 according to a modification of the first embodiment. FIG. 7 is a schematic block diagram of a configuration of a peripheral circuit 20 that controls an ARVSS potential adjustment circuit 19 according to the second embodiment. It is a figure explaining the structure of the ARVSS electric potential adjustment circuit 19 according to this Embodiment 2. FIG. It is a figure explaining the adjustment flow of the ARVSS electric potential according to this Embodiment 2. FIG. It is a figure explaining the timing chart of adjustment of the ARVSS electric potential according to this Embodiment 2. FIG. It is a figure explaining the temperature characteristic of data retention of the memory cell MC. It is a figure explaining the structure of ARVSS electric potential adjustment circuit 18 # according to this Embodiment 3. FIG. It is a figure explaining the timing chart of the adjustment of the source potential ARVSS according to the third embodiment. FIG. 10 is a schematic block diagram of a configuration of a peripheral circuit 20 that controls an ARVSS potential adjustment circuit 18 according to a fourth embodiment. It is a figure explaining the adjustment flow of the source potential ARVSS according to the fourth embodiment. It is a figure explaining the specific example of the counter value of the binary search (binary search tree) according to this Embodiment 4. FIG. FIG. 10 is a schematic block diagram of a configuration of a peripheral circuit 20 that controls an ARVSS potential adjustment circuit 18 according to a modification of the fourth embodiment. It is a figure explaining the adjustment flow of the source electric potential ARVSS according to the modification of this Embodiment 4. FIG. It is a figure explaining the structure of the read assist circuit 200 according to this Embodiment. It is a figure explaining the structure of the write assist circuit 220 according to this Embodiment. It is a figure explaining the circuit which adjusts the timing which drives the word line according to this Embodiment 6. FIG. It is a figure explaining the circuit which adjusts the timing which drives the sense amplifier according to the modification of this Embodiment 6. FIG. It is a figure explaining the layout arrangement | positioning of various adjustment circuits.

  This embodiment will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
<Configuration of semiconductor integrated circuit>
FIG. 1 is a schematic diagram illustrating the overall configuration of a semiconductor integrated circuit 1 according to the first embodiment.

  Referring to FIG. 1, semiconductor integrated circuit 1 includes an SRAM module 10 and a peripheral circuit 20. The peripheral circuit 20 outputs various control signals to the SRAM module 10 and receives data output from the SRAM module 10 to execute various processes.

  The SRAM module 10 processes a memory array MA having memory cells MC, a word line decoder 12 for driving a word line WL, a control unit 14 for controlling the entire SRAM module 10, and input / output data for the memory array MA. And an ARVSS potential adjusting circuit 18 for adjusting the potential of the source line SL (also referred to as source potential ARVSS).

  In this example, the memory cells MC are arranged in a matrix in the memory array MA as an example. It is assumed that a plurality of word lines WL and bit lines BL and BLL are provided corresponding to the memory cell rows and the memory cell columns.

  Memory cell MC includes transistors Tr1 and Tr3 that are load transistors, transistors Tr2 and Tr4 that are drive transistors, and transistors AT1 and AT2 that are transfer transistors. In this example, as an example, the transistors Tr1 and Tr3 are P-channel MOS transistors, and the transistors Tr2, Tr4, AT1, and AT2 are N-channel MOS transistors.

  Transistor Tr1 is provided between power supply potential VDDM and storage node N0, and has its gate electrically coupled to storage node N1. Transistor Tr2 is provided between source potential ARVSS (source side) (<power supply potential VDDM) and node N0, and its gate is electrically coupled to storage node N1. Transistor Tr3 is provided between power supply potential VDDM and storage node N1, and has its gate electrically coupled to storage node N0. Transistor Tr4 is provided between source potential ARVSS and storage node N1, and has its gate electrically coupled to storage node N0. Transistor AT1 is provided between storage node N0 and bit line BL, and has its gate electrically coupled to word line WL. Transistor AT2 is provided between storage node N1 and bit line BLL, and has its gate electrically coupled to word line WL. As the word line WL rises, the transfer transistors AT1 and AT2 are turned on, and the storage nodes N0 and N1 are electrically coupled to the bit lines BL and BLL, respectively.

  Data writing and reading to and from the memory cell MC are well-known techniques and will not be described in detail. However, when writing data, the bit lines BL and BLL are set to potential levels corresponding to the write data. As the word line WL rises, the transistors AT1 and AT2 are turned on and the storage nodes N0 and N1 are set to potentials corresponding to the potential levels of the bit lines BL and BLL. As a result, data is written into the memory cell MC.

  On the other hand, when reading data, the transistors AT1 and AT2 are turned on as the word line WL rises, and the potentials of the bit lines BL and BLL are set to potential levels corresponding to the storage nodes N0 and N1. Then, data written in the memory cell MC is read based on the set potential difference between the bit lines BL and BLL. As an example, data “1” is set when the potential of the bit line BL is higher than that of the bit line BLL, and data “0” is set when the potential of the bit line BLL is higher than that of the bit line BL. The setting of the data is an example, and the data values may be inverted.

  FIG. 2 is a schematic block diagram of a configuration of peripheral circuit 20 that controls ARVSS potential adjustment circuit 18 according to the first embodiment.

  Referring to FIG. 2, in this example, peripheral circuit 20 includes, as an example, POR (Power On Reset) circuit 22, BIST (Built In Self Test) circuit 24, comparison circuit 26, and compression circuit 28. , AND circuit 30 and counter circuit 32.

  The POR circuit 22 outputs a control signal (POR signal) after the elapse of a predetermined period (after the power supply becomes stable) as the power is turned on.

  The BIST circuit 24 executes a BIST (Built In Self Test) process according to the input of the POR signal from the POR circuit 22. In this example, a process for adjusting the source potential ARVSS of the source line SL is executed as an example of the BIST process.

  First, the BIST circuit 24 outputs a counter reset signal CRS to the counter circuit 32. As a result, the counter circuit 32 is reset and sets the counter value to an initial value (eg, “0”).

  The BIST circuit 24 executes processing for writing predetermined test data to the SRAM module 10 as necessary. Specifically, an instruction (command) for executing a data write process (WRITE) is input. For example, the clock signal CLK defining the operation, the chip activation signal CEN for instructing the start of the operation, the address AD for designating the memory cell to be written in the memory array MA, the write control signal WEN for instructing the operation during the write, Write data DI or the like, which is data, is input to the SRAM module 10 as necessary. The control unit 14 controls the word line decoder 12 and the I / O circuit 16 in accordance with instructions from the BIST circuit 24. The I / O circuit 16 sets the potentials of the bit lines BL and BLL to potentials corresponding to the write data DI in order to perform write processing on the instructed memory cell MC. Further, the word line decoder 12 raises the word line WL corresponding to the designated memory cell MC. Thereby, predetermined test data can be written to the memory cell MC.

  The BIST circuit 24 outputs a standby signal RS to the SRAM module 10 in order to determine the data retention characteristics of the memory cell MC. Thereby, the SRAM module 10 is set to the standby mode. In the standby mode, the source potential ARVSS of the source line SL is set to a potential adjusted by the ARVSS potential adjustment circuit 18. Then, the test data written in the memory cell MC according to the set source potential ARVSS is held or destroyed.

  Then, the BIST circuit 24 executes a process of reading the test data written to the SRAM module 10 in order to determine the data retention characteristic of the memory cell MC. Specifically, an instruction (command) for executing a data read process (READ) is input. Various signals similar to those described above are input to the SRAM module 10. The control unit 14 controls the word line decoder 12 and the I / O circuit 16 in accordance with instructions from the BIST circuit 24. The word line decoder 12 raises the word line WL in order to execute a read process on the designated memory cell MC. The I / O circuit 16 amplifies the potential difference between the bit lines BL and BLL set to a potential corresponding to the level of data stored in the memory cell MC with the rise of the word line WL by a sense amplifier, and reads the read data DQ Output as.

  The read data DQ is output to the comparison circuit 26. In addition, in this example, it is assumed that the writing and reading processing is executed for each of a plurality of bits (each row of the memory array MA). It should be noted that in writing for each of a plurality of bits, all data values need not be the same and can be set to arbitrary values.

Then, the BIST circuit 24 outputs an expected value to the comparison circuit 26.
The comparison circuit 26 compares the read data DQ read from the SRAM module 10 with the expected value output from the BIST circuit 24. The expected value is the write data DI input from the BIST circuit 24 to the memory cells MC of the memory array MA as predetermined test data. Although it is possible to compare with the expected value bit by bit, in this example, the case of comparing with the expected value for each of a plurality of bits (for example, for each row) is shown. Then, the comparison result (whether or not it matches the expected value) is output to the compression circuit 28. In this example, the comparison circuit 26 can use an EXOR (exclusive OR) circuit as an example. Specifically, “0” is output if the read data DQ and the expected value match, and “1” is output if they do not match.

  The compression circuit 28 compresses the comparison result output from the comparison circuit 26 for each of a plurality of bits, and outputs “0” if all the data match, and “1” if even one does not match. Output. For example, an OR (logical sum) circuit can be used as the compression circuit.

  The BIST circuit 24 receives the compressed data “0” or “1” from the compression circuit 28 and executes a process of writing predetermined test data to the SRAM module 10 again as necessary. Then, after setting to the standby mode, the written predetermined test data is read, and the above determination processing is repeated.

  The AND circuit 30 receives the input of the clock signal CLK and the compressed data from the compression circuit 28, and outputs a counter UP control signal (one-shot pulse signal) based on the AND logic operation result. Specifically, when the compression circuit 28 outputs the compressed data “1”, the counter UP control signal “1” is output to the counter circuit 32. When the compression circuit 28 outputs the compressed data “0”, the counter UP control signal maintains the state “0”.

  The counter circuit 32 increments the counter value according to the counter UP control signal “1” (one-shot pulse signal), and outputs a counter signal C <N−1: 0>. Here, the counter signal C <N−1: 0> means N counter signals C <0> to C <N−1>. In this example, it is assumed that counter signals C <0> to C <N−1> are sequentially set to “1” one by one in accordance with counter UP control signal “1” as an example. In the initial state, the counter signals C <0> to C <N−1> are all “0”.

  Although described later in accordance with counter signals C <0> to C <N−1> from the counter circuit 32, the circuit of the ARVSS potential adjustment circuit 18 operates to adjust the source potential ARVSS.

  FIG. 3 is a diagram for explaining the configuration of the ARVSS potential adjustment circuit 18 according to the first embodiment.

  Referring to FIG. 3, the ARVSS potential adjustment circuit 18 includes adjustment transistors Tr (a) to Tr (f) for adjusting the source potential ARVSS, which is the potential of the source line, to a plurality of potentials, and inverters. IV and AND circuits AND <0> to AND <N-1>. Specifically, the transistors Tr (a) to Tr (f) (also collectively referred to as the transistor Tr) are provided in parallel between the source line SL and the ground potential VSSM (0 V), respectively. The transistors Tr (a) to Tr (f) are N-channel MOS transistors as an example in this example. The AND circuits AND <0> to AND <N-1> are collectively referred to as an AND circuit AND.

  The gate of transistor Tr (a) receives an input of an inverted signal of standby signal RS via inverter IV.

  The gates of the transistors Tr (b) to Tr (d) receive the output signals of the AND circuits AND <0> to AND <2>. Further, the gate of the transistor Tr (e) receives the input of the output signal of the AND circuit AND <N−1>.

The gate of the transistor Tr (f) receives the standby signal RS.
In this example, the transistors Tr corresponding to the AND circuits AND <3> to AND <N-2> are omitted for simplification of description.

  The AND circuit AND <0> receives the counter signal C <0> and the standby signal RS and outputs an AND logic operation result to the transistor Tr (b). The AND circuit AND <1> receives the counter signal C <1> and the standby signal RS and outputs an AND logic operation result to the transistor Tr (c). The AND circuit AND <2> receives the counter signal C <2> and the standby signal RS and outputs an AND logic operation result to the transistor Tr (d). The AND circuit AND <N−1> receives the counter signal C <N−1> and the standby signal RS and outputs an AND logic operation result to the transistor Tr (e).

  The transistor Tr (a) is turned on when the standby signal RS is “0” and turned off when it is “1”. That is, it is turned on in the normal operation (normal operation mode) in which the standby signal RS is “0”. It is assumed that the transistor Tr (a) is set to a transistor having a large passing current Ids at the time of ON. When the transistor Tr (a) is turned on, the source potential ARVSS of the source line is set to a value approximate to the ground potential VSSM (0 V). In the normal operation, the transistor Tr (a) is turned on and the source potential ARVSS is set to 0V, so that the memory cell MC has an operation margin because the potential changes between the power supply potential VDDM and the ground potential VSSM. This is a sufficiently secured state (a state in which stable data writing and data reading are possible). When the standby signal RS is “1” (standby mode), it is turned off.

  On the other hand, the transistor Tr (f) is turned on when the standby signal RS is “1” and turned off when it is “0”. That is, it is turned on in the standby mode. It is assumed that the transistor Tr (f) is set to a transistor having a small passing current Ids at the time of ON. When the transistor Tr (f) is turned on, the source potential ARVSS of the source line is set to rise to a potential (for example, VDDM / 2) (initial potential) at which data destruction of the memory cell MC occurs. And When only the transistor Tr (f) is turned on, the data stored in the memory cell MC is initialized, for example, data “0”.

  The transistors Tr (b) to Tr (e) are turned on in accordance with the output signal of the corresponding AND circuit. The AND circuit AND is turned on when the standby signal RS is “1” and the counter signal C is “1”. It is assumed that the transistors Tr (b) to Tr (e) are set to transistors having a small passing current Ids enough to lower the source potential ARVSS stepwise (about several tens of mV). As an example, it is assumed that the transistor size is set to −10 mV each time one transistor Tr is turned on. When the standby signal RS is “1”, that is, in the standby mode, the source potential ARVSS decreases every time the adjustment transistor Tr is turned on from the initial potential (every time the counter signal C becomes “1”).

  In this example, the source potential ARVSS is adjusted stepwise from the initial potential according to the counter signal C so that the data stored in the memory cell MC is adjusted to a potential that is not destroyed.

  In this example, the case where four transistors are provided as the adjustment transistors provided to lower the potential from the initial potential (transistors Tr (b) to Tr (e)) is illustrated. When a counter signal is input, N adjustment transistors can be provided. Note that the standby current can be effectively reduced by reducing (finely setting) the adjustment width (step width) of the source potential ARVSS.

  In this example, the transistor Tr (f) is provided and turned on when the standby signal RS is “1”, and the initial potential is set and adjusted to prevent the source potential ARVSS from floating and the source potential. It is possible to shorten the test time required for automatic adjustment.

<Source potential ARVSS adjustment flow>
FIG. 4 is a diagram illustrating an adjustment flow of source potential ARVSS according to the first embodiment.

  The adjustment flow is a flow for adjusting the source potential ARVSS to an optimum potential set in the standby mode.

  In general, it is tested whether data written in the memory cell MC can be held in the standby mode (standby period). Specifically, as a test, the source potential is adjusted stepwise from the initial potential (potential at which data destruction occurs) (lowering the potential) to lower the source potential ARVSS to a potential level at which data destruction does not occur.

  Referring to FIG. 4, first, power is turned on (step S2). For example, a switch (not shown) is turned on so that the power supply voltage and the semiconductor integrated circuit 1 are connected.

  Next, it is determined whether or not the POR signal is turned on (step S4). Specifically, the POR circuit 22 sets the POR signal to “1” (ON) when it is determined that the power supply voltage is in a stable state.

  If it is determined in step S4 that the POR signal is ON (YES in step S4), the process proceeds to step S6. The state of step S4 is maintained until the POR signal is turned ON.

  Next, in step S6, the counter is reset (step S6). Specifically, the BIST circuit 24 outputs a counter reset signal CRS (“1”) to the counter circuit 32 in response to the input of the POR signal. The counter circuit 32 receives the counter reset signal CRS and resets (initializes) the counter value. Accordingly, the counter signal C <N−1: 0> based on the counter value is set to “0”.

  Next, a data writing process is executed on the SRAM module 10 (step S8). Specifically, as described above, the BIST circuit 24 inputs write data DI, which is predetermined test data, to the SRAM module 10.

  Then, a standby mode test is executed (step S10). The standby mode test is to test whether or not the data written in the SRAM module 10 can be held in the standby mode (standby period). Specifically, the standby signal RS is set to “1”, and the source potential ARVSS is set to a potential set in the standby mode by the ARVSS potential adjusting circuit 18 according to the counter signal C. In this example, in the initial state, the source potential ARVSS is set to a potential (for example, VDDM / 2) at which data destruction occurs.

  Next, a data read process is executed on the SRAM module 10 (step S12). Specifically, as described above, the BIST circuit 24 instructs the SRAM module 10 to read out the written test data. The SRAM module 10 outputs the read data DQ to the comparison circuit 26.

  Next, expected value determination processing is executed (step S14). Specifically, the comparison circuit 26 compares the read data DQ read from the SRAM module 10 with the expected value given from the BIST circuit 24, and whether the read data DQ and the expected value match. Determine whether. Then, the result is output to the compression circuit 28.

  The compression circuit 28 compresses the comparison result output from the comparison circuit 26 and outputs “0” (PASS in step S14) if all the data match. Then, the process proceeds to step S16. The case where all the data match is the case where the write data DI and the read data DQ all match. That is, when the source potential ARVSS set in the standby period is set by the standby mode test, the data stored in the memory cell MC is not destroyed (data can be held).

  In step S16, the processing of the BIST circuit 24 is ended (stopped). Specifically, since it is determined that the source potential ARVSS does not cause data destruction, the processing for adjusting the source potential ARVSS is terminated. Further, the counter circuit 32 is stopped.

  On the other hand, if at least one of the compression circuits 28 does not match in step S14, the compression circuit 28 outputs “1” (FAIL in step S14), and proceeds to step S18. In step S18, the BIST circuit 24 determines whether or not the counter value is the upper limit (max) according to the output signal of the compression circuit 28. For example, the BIST circuit 24 can determine whether or not the counter value is the upper limit (max) based on the number of times the output signal “1” is input from the compression circuit 28. If the BIST circuit 24 determines that the counter value is the upper limit (max) (YES in step S18), it outputs an error (step S20). Specifically, the BIST circuit 24 outputs error information indicating that adjustment cannot be performed because the counter value is the upper limit (max) to the outside. The peripheral circuit can execute predetermined error processing according to the error information. For example, it is possible to provide notification of maintenance or notification of parts replacement to the outside.

  In step S18, if the BIST circuit 24 determines that the counter value is not the upper limit (max) (NO in step S18), the BIST circuit 24 increases the counter value (step S22). Specifically, the counter circuit 32 increments (UP) the counter value based on the counter UP control signal “1” (one-shot pulse) output from the AND circuit 30 in accordance with the output signal “1” from the compression circuit 28. To do. Thereby, in this example, the counter signals C <0> to C <N−1> are sequentially set to “1” according to the counter value. The counter signal C is used for setting the source potential ARVSS in the standby mode (standby period).

  Specifically, during the standby mode test in step S10 (when the standby signal RS is “1”), the corresponding transistor of the ARVSS potential adjustment circuit 18 is turned on according to the counter signal C (“1”). Then, the source potential ARVSS is set to be gradually lowered from the initial potential by the number of ON of the transistor.

  And after step S22, it returns to said step S8 again and repeats the said process. For example, if the data does not match (FAIL) in the expected value determination process (step S14), there is a high possibility that the data has been destroyed by the standby mode test. Therefore, it is necessary to test again after adjusting the source potential ARVSS. Therefore, the data writing process is executed again, and the next standby mode test is executed (step S10). In step S12, a data read process is executed on the SRAM module 10 and an expected value determination process is executed (step S14). This process is repeated until the data match (PASS) in the expected value determination process (step S14). The counter value is incremented by the number of repetitions, and the source potential ARVSS set in the standby mode (standby period) is adjusted.

<Timing chart of adjustment flow of source potential ARVSS>
FIG. 5 is a diagram illustrating a timing chart of the adjustment flow of source potential ARVSS according to the first embodiment.

  Referring to FIG. 5, first, counter circuit 32 is initialized ((1) counter reset) in accordance with counter reset signal CRS. As a result, the counter signals C are all set to “0”.

  Next, the BIST circuit 24 executes a process of writing predetermined test data to the memory array MA in synchronization with the clock signal CLK ((2) WRITE). In this example, the write control signal WEN is set to “0” (WRITE is turned on).

  Next, a standby mode test ((3) standby) is executed. The write control signal WEN is set to “1” (WRITE is turned off). In this case, the transistor Tr (f) is turned on by setting the standby signal RS to “1”. Accordingly, the source potential ARVSS is set to the initial potential (VDDM / 2) (a potential at which data in the memory cell MC is destroyed).

  Next, the BIST circuit 24 executes a process of reading predetermined test data written from the memory array MA in synchronization with the clock signal CLK ((4) READ).

  Then, the count UP control signal is set to “1” in accordance with the result (expected value mismatch) of the expected value determination process ((5) expected value determination (compression)). Thereby, the counter circuit 32 sets the counter signal C <0> to “1” when the count-up control signal is set to “1”.

  Then, the BIST circuit 24 again executes a process of writing predetermined test data to the memory array MA in synchronization with the clock signal CLK ((2) WRITE).

  Next, a standby mode test ((3) standby) is executed. At this time, the transistor Tr (f) is turned on by setting the standby signal RS to “1”, and the counter signal C <0> is set to “1”, so that the source potential ARVSS is VDDM / 2. -ΔV1 is set. Note that ΔV1 is a potential at which the transistor Tr (b) is turned on and lowered. Thereby, it is tested whether or not the data of the memory cell MC can be held in accordance with the source potential ARVSS in the standby period.

  Next, the BIST circuit 24 executes a process of reading predetermined test data written from the memory array MA in synchronization with the clock signal CLK ((4) READ).

  Then, the count UP control signal is set to “1” in accordance with the result (expected value mismatch) of the expected value determination process ((5) expected value determination (compression)). Accordingly, the counter circuit 32 sets the counter signal C <1> to “1” when the count-up control signal is set to “1”.

  Then, (2) WRITE → (3) standby → (4) READ → (5) expected value determination (compression) is repeated until the expected values match as a result of the expected value determination (compression). That is, the source potential ARVSS is lowered to a potential level at which data destruction does not occur.

  In this example, the case where the expected values match as a result of repeating the process k times is shown. Therefore, the ARVSS potential is adjusted to VDDM / 2−ΔVk. As a result, in the standby mode, the source potential ARVSS at the time of matching is adjusted according to the set counter signal.

Then, the processing of the BIST circuit 24 and the counter circuit 32 is finished.
The adjustment flow can be executed every time the power is turned on or every time a certain time has elapsed. Thereby, it is not necessary to consider the adjustment of the source potential ARVSS based on the aging and manufacturing variation of the memory cell MC at the design stage, and the source potential ARVSS is adjusted to the actual value of the data holding voltage according to the state of the finished memory cell MC. Can be raised. In other words, since the potential of the source line (source potential ARVSS) can be adjusted in consideration of the data retention characteristics of the memory cell, there is a remarkable effect in suppressing the standby current in the standby mode (standby period).

<Layout layout>
FIG. 6 is a diagram illustrating a layout arrangement of the ARVSS potential adjustment circuit 18 according to the first embodiment.

  As shown in FIG. 6, the ARVSS potential adjusting circuit 18 can be arranged between the memory array MA and the I / O circuit 16 and can be arranged in the vicinity of the memory cell. Note that the source line SL has the ground potential VSSM in the normal operation, and needs to be set to a potential (for example, VDDM / 2−ΔVk) necessary for data retention in the standby mode. It is desirable to arrange with noise taken into account. In this example, the case where it is arranged inside the SRAM module 10 will be described. However, the arrangement is not limited to the inside of the module, and it can be arranged outside. In such a case as well, a floor plan and a wiring layout that take into account the influence of noise on the wiring of the source line SL on the chip (semiconductor integrated circuit) are desirable.

(Modification of Embodiment 1)
FIG. 7 is a schematic block diagram of a configuration of peripheral circuit 20 that controls ARVSS potential adjusting circuit 18 according to the modification of the first embodiment.

  In the above description, the configuration in which the BIST circuit 24, the counter circuit 32, the ARVSS potential adjustment circuit 18 and the like are provided for one memory array MA has been described. In this modification, a configuration in which the BIST circuit 24, the counter circuit 32, and the ARVSS potential adjustment circuit 18 are provided in common for a plurality of memory arrays MA will be described.

  Referring to FIG. 7, in this example, a configuration in which a plurality of memory arrays MA are provided in memory array group 11 is shown. The source potential ARVSS is adjusted in common for the plurality of memory arrays MA. A comparison circuit 26 is provided corresponding to each memory array MA. One compression circuit 29 is provided corresponding to the plurality of comparison circuits 26.

  The process of writing predetermined test data to each memory array MA, the process of reading out, and the like are the same as described above, and therefore detailed description thereof will not be repeated.

  Then, the read data read from each memory array MA is compared in the corresponding comparison circuit 26. The comparison circuit 26 is the same as described above, and outputs “0” if the read data read from the memory array MA matches the expected value, and outputs “1” if they do not match.

  The compression circuit 29 compresses the comparison result output from the comparison circuit 26 provided corresponding to each memory array MA, and outputs “0” if all the data match, and even one does not match. If there is, “1” is output. That is, “1” is output if there is a mismatch in one memory array MA.

  Then, as described above, the counter UP control signal is output based on the compressed data from the compression circuit 29, and the source potential ARVSS is adjusted. Subsequent processing is the same as described above.

  With this configuration, it is possible to reduce the number of components and the layout area by providing the common ARVSS potential adjustment circuit 18 and the counter circuit 32 for a plurality of memory arrays MA. It should be noted that the source potentials are not made common to the plurality of memory arrays MA, but the memory arrays MA having similar data retention characteristics are grouped, and the common source potential is used for the grouped memory array group. ARVSS may be adjusted. With this method, the standby current in the standby mode (standby period) can be efficiently suppressed.

(Embodiment 2)
In the first embodiment, in the standby mode test, the potential of the memory cell data is destroyed (for example, VDDM / 2) as the initial potential as the initial potential of the source potential ARVSS, and the potential is lowered step by step. The method of adjusting to the source potential ARVSS that does not cause data destruction that matches the expected value has been described. That is, in the above method, the case has been described in which the test data needs to be repeatedly written (WRITE) to the memory array MA until the read data matches the expected value. Therefore, it may take time to adjust the source potential ARVSS due to the rewriting process of the test data.

  In the second embodiment, a method for shortening the adjustment time of the source potential ARVSS will be described.

  FIG. 8 is a schematic block diagram of a configuration of peripheral circuit 20 that controls ARVSS potential adjustment circuit 19 according to the second embodiment.

  Referring to FIG. 8, compared with the configuration of FIG. 2, the configuration is that the ARVSS potential adjustment circuit 18 is replaced with the ARVSS potential adjustment circuit 19, and the counter circuit 32 is changed to the counter circuit 36. The difference is that an inverting circuit 34 is provided.

  Since the other basic configuration is the same as that described in FIG. 2, detailed description thereof will not be repeated.

  The counter circuit 36 is an UP / DOWN counter, and increments the counter value in response to the counter UP control signal from the AND circuit 30 and decrements the counter value in response to the counter DOWN control signal from the BIST circuit 24.

  The inverting circuit 34 outputs a signal obtained by inverting the compressed data of the compression circuit 28 to the AND circuit 30 and the BIST circuit 24. Therefore, if all the data match, “1” is output from the inverting circuit 34. If even one does not match, “0” is output.

  FIG. 9 is a diagram illustrating a configuration of ARVSS potential adjustment circuit 19 according to the second embodiment.

  Referring to FIG. 9, ARVSS potential adjustment circuit 19 receives counter signals C of AND circuits AND <0> to AND <N−1> as compared with ARVSS potential adjustment circuit 18 described in FIG. 3. The difference is that inverting circuits IV <0> to IV <N-1> are provided corresponding to the nodes.

  The ARVSS potential adjustment circuit 19 includes a plurality of adjustment transistors Tr (a) to Tr (f) for adjusting the potential as described with reference to FIG.

  The AND circuit AND <0> receives the inverted signal of the counter signal C <0> and the standby signal RS, and outputs an AND logic operation result to the transistor Tr (b). The AND circuit AND <1> receives the inverted signal of the counter signal C <1> and the standby signal RS, and outputs an AND logic operation result to the transistor Tr (c). The AND circuit AND <2> receives the inverted signal of the counter signal C <2> and the standby signal RS and outputs an AND logic operation result to the transistor Tr (d). The AND circuit AND <N-1> receives the inverted signal of the counter signal C <N-1> and the standby signal RS and outputs an AND logic operation result to the transistor Tr (e).

  The transistor Tr (a) is turned on when the standby signal RS is “0” and turned off when it is “1”. That is, it is turned on in the normal operation (normal operation mode) in which the standby signal RS is “0”. It is assumed that the transistor Tr (a) is set to a transistor having a large passing current Ids at the time of ON. When the transistor Tr (a) is turned on, the source potential ARVSS of the source line is set to a value approximate to the ground potential VSSM (0 V). In the normal operation, the transistor Tr (a) is turned on and the source potential ARVSS is set to 0V, so that the memory cell MC has an operation margin because the potential changes between the power supply potential VDDM and the ground potential VSSM. This is a sufficiently secured state (a state in which stable data writing and data reading are possible). When the standby signal RS is “1” (standby mode), it is turned off.

  On the other hand, when the standby signal RS is “1” as described above, the transistor Tr (a) is turned off and the transistor Tr (f) is turned on.

  Further, in the initial state, all the counter signals C <0> to C <N−1> are “0”, so that all the inverted signals through the inverting circuit IV are “1”.

  Therefore, in the initial state, when the standby signal RS is “1”, the AND circuits AND all output “1”, and the corresponding transistors Tr are all turned on.

  Accordingly, since all the adjustment transistors other than the transistor Tr (a) are turned on, the source potential ARVSS is set to a potential close to the ground potential VSSM (0 V).

  In other words, in the initial state of the standby mode test, the source potential ARVSS is set to a value close to 0 V, so that the memory cell MC has a sufficient operation margin because the potential changes between the power supply potential VDDM and the ground potential VSSM. This is a secured state (a state where stable data writing and data reading are possible).

  The transistors Tr (b) to Tr (e) are all turned on in the initial state, and the corresponding transistors are turned off in response to the counter signal C being set from “0” to “1”. In this example, as an example, it is assumed that the transistor size is set to +10 mV each time one transistor Tr is turned off. When the standby signal RS is “1”, that is, in the standby mode, the source potential ARVSS increases every time the adjustment transistor Tr is turned off from the initial potential (every time the counter signal C becomes “1”).

  In this example, the source potential ARVSS is adjusted from the initial potential stepwise in accordance with the counter signal C incremented by the counter value, so that the data stored in the memory cell MC becomes a potential that is destroyed from a state that is not destroyed. Adjust until.

  Then, after adjusting the source potential ARVSS to a potential at which data stored in the memory cell MC is destroyed, the counter value is decremented by one. That is, the source potential ARVSS is readjusted to a potential at which the data stored in the memory cell MC is not destroyed in the standby mode according to the counter signal C decremented by the counter value.

  In this example, the case where four transistors (transistors Tr (b) to Tr (e)) are provided as adjustment transistors provided to raise the potential stepwise from the initial potential is illustrated. When N counter signals are input, N adjustment transistors can be provided. Note that the standby current can be further reduced by reducing (finely) setting the adjustment width (step width) of the source potential ARVSS.

  In this example, the potential is raised stepwise until the data stored in the memory cell MC is in a state of being destroyed. Since the data is not destroyed in the stepwise raising process, the above-described first embodiment. Unlike the method described, it is not necessary to write test data to the memory array MA each time. Therefore, the time for repeatedly writing test data to the memory array MA is eliminated, and the adjustment time of the source potential ARVSS can be shortened. In addition, power consumption required for data writing can be reduced.

<Source potential ARVSS adjustment flow>
FIG. 10 is a diagram illustrating an adjustment flow of the ARVSS potential according to the second embodiment.

  The adjustment flow is a flow for adjusting the source potential ARVSS to an optimum potential set in the standby mode.

  In general, it is tested whether data written in the memory cell MC can be held in the standby mode (standby period). Specifically, as a test, the source potential is adjusted stepwise from the initial potential (potential at which data destruction does not occur) (by increasing the potential) to raise the source potential ARVSS to a potential level at which data destruction occurs, This is a method of returning to the potential level where the previous data destruction does not occur.

  Referring to FIG. 10, first, power is turned on (step S2). For example, a switch (not shown) is turned on so that the power supply voltage and the semiconductor integrated circuit 1 are connected.

  Next, it is determined whether or not the POR signal is turned on (step S4). Specifically, the POR circuit 22 sets the POR signal to “1” (ON) when it is determined that the power supply voltage is in a stable state.

  If it is determined in step S4 that the POR signal is ON (YES in step S4), the process proceeds to step S6. The state of step S4 is maintained until the POR signal is turned ON.

  Next, in step S6, the counter is reset (step S6). Specifically, the BIST circuit 24 outputs a counter reset signal CRS (“1”) to the counter circuit 36 in response to the input of the POR signal. The counter circuit 36 receives the counter reset signal CRS and resets (initializes) the counter value. Accordingly, the counter signal C <N−1: 0> based on the counter value is set to “0”.

  Next, a data writing process is executed on the SRAM module 10 (step S8). Specifically, as described above, the BIST circuit 24 inputs write data DI, which is predetermined test data, to the SRAM module 10.

  Then, a standby mode test is executed (step S10). The standby mode test is a test of whether or not the data written in the SRAM module 10 can be held in the standby period. Specifically, the standby signal RS is set to “1”, and the source potential ARVSS is set to a potential set in the standby mode by the ARVSS potential adjusting circuit 18 according to the counter signal C. In this example, in the initial state, the source potential ARVSS is set to a potential (for example, 0 V) that does not cause data destruction.

  Next, a data read process is executed on the SRAM module 10 (step S12). Specifically, as described above, the BIST circuit 24 instructs the SRAM module 10 to read out the written test data. The SRAM module 10 outputs the read data DQ to the comparison circuit 26.

  Next, expected value determination processing is executed (step S14). Specifically, the comparison circuit 26 compares the read data DQ read from the SRAM module 10 with the expected value given from the BIST circuit 24, and whether the read data DQ and the expected value match. Determine whether. Then, the result is output to the compression circuit 28.

  The compression circuit 28 compresses the comparison result output from the comparison circuit 26 and outputs “0” (PASS in step S14) if all the data match. In this example, since the inverting circuit 34 is provided on the output side of the compression circuit 28, the result is “1” if they match, and “0” if they do not match. Then, the process proceeds to step S18.

  In step S18, the BIST circuit 24 determines whether or not the counter value is the upper limit (max) according to the inverted signal of the output signal of the compression circuit 28. For example, the BIST circuit 24 can determine whether or not the counter value is the upper limit (max) based on the number of times the inverted signal “1” of the output signal from the compression circuit 28 is input.

  In step S18, when the BIST circuit 24 determines that the counter value is the upper limit (max) (YES in step S18), the processing of the BIST circuit 24 and the counter circuit 36 is ended (stopped). Since the counter value is the upper limit, the source potential ARVSS cannot be adjusted any more and the processing for adjusting the source potential ARVSS is terminated.

  On the other hand, if the BIST circuit 24 determines in step S18 that the counter value is not the upper limit (max) (NO in step S18), the BIST circuit 24 increases the counter value (step S22). Specifically, the counter circuit 36 increments (UP) the counter value based on the counter UP control signal “1” (one-shot pulse) output from the AND circuit 30 in accordance with the output signal “1” from the inverting circuit 34. To do. Thereby, in this example, the counter signals C <0> to C <N−1> are sequentially set to “1” according to the counter value. The counter signal C is used for setting the source potential ARVSS during the standby period.

  Specifically, during the standby mode test in step S10 (when the standby signal RS is “1”), the corresponding transistor of the ARVSS potential adjustment circuit 18 is turned off according to the counter signal C (“1”). Then, the source potential ARVSS is set stepwise up from the initial potential by the number of transistors that are turned off.

  And after step S22, it returns to said step S10 again and repeats the said process. Specifically, a standby mode test is executed (step S10). In step S12, a data read process is executed on the SRAM module 10 and an expected value determination process is executed (step S14). This process is repeated until the data does not match (FAIL) in the expected value determination process (step S14). The counter value is incremented by the number of repetitions, and the source potential ARVSS set in the standby mode (standby period) is adjusted.

  On the other hand, if at least one of the compression circuits 28 does not match in step S14, the compression circuit 28 outputs “1” (FAIL in step S14), and proceeds to step S24.

  In step S24, the BIST circuit 24 determines whether the counter value is the lower limit (min) according to the inverted signal of the output signal of the compression circuit 28. Specifically, the case where the counter value is the lower limit corresponds to, for example, a case where data does not match (FAIL) in the expected value determination process in the initial state. In this case, there is a possibility that there is an abnormality in the memory cell MC itself because data destruction has occurred despite the fact that the operation margin is most secured.

  Therefore, when the counter value is the lower limit (min) (YES in step S24), error information is output to the outside (step S20). The peripheral circuit can execute predetermined error processing according to the error information. For example, it is possible to provide notification of maintenance or notification of parts replacement to the outside.

  On the other hand, if the BIST circuit 24 determines in step S24 that the counter value is not the lower limit (min) according to the inverted signal of the output signal of the compression circuit 28 (NO in step S24), the BIST circuit 24 DOWNs the counter value (step S26). ). Specifically, the BIST circuit 24 outputs a counter DOWN control signal to the counter circuit 36. As a result, the counter value of the counter circuit 36 is decremented and returned by one. Then, a count signal based on the counter value returned by one is set, and the source potential ARVSS is readjusted. In the case of this method, it is necessary to increase the source potential to a level at which the data does not match in the expected value determination processing. Therefore, after raising the source potential to the level at which the data does not match, the level is returned to the optimum level. This is because it is necessary to adjust the source potential.

  Then, the process proceeds to step S16, and the processes of the BIST circuit 24 and the counter circuit 36 are finished (stopped). Specifically, the process for adjusting the source potential ARVSS is terminated. Further, the counter circuit 36 is stopped.

<Timing chart of adjustment flow of source potential ARVSS>
FIG. 11 is a diagram illustrating a timing chart for adjusting the ARVSS potential according to the second embodiment.

  Referring to FIG. 11, first, counter circuit 36 is initialized ((1) counter reset) in accordance with counter reset signal CRS. As a result, the counter signals C are all set to “0”. Since an inverting circuit is provided, “1” is input to the input nodes of all AND circuits AND as described above.

  Next, the BIST circuit 24 executes a process of writing predetermined test data to the memory array MA in synchronization with the clock signal CLK ((2) WRITE). The write control signal WEN is set to “0” (WRITE is turned on).

  Next, a standby mode test ((3) standby) is executed. The write control signal WEN is set to “1” (WRITE is turned off). In this case, the transistors Tr (b) -Tr (f) are turned on by setting the standby signal RS to “1”. As a result, the source potential ARVSS is set in the vicinity of the initial potential (VDDS (= 0V)) (set to a potential capable of holding data in the memory cell).

  Next, the BIST circuit 24 executes a process of reading predetermined test data written from the memory array MA in synchronization with the clock signal CLK ((4) READ).

  Then, the count UP control signal is set to “1” in accordance with the result (expected value match) of the expected value determination process ((5) expected value determination (compression)). Accordingly, the counter circuit 36 sets the counter signal C <0> to “1” when the count-up control signal is set to “1”.

  Then, the standby mode test ((3) standby) is executed again. At this time, the standby signal RS is set to “1” and the inverted signal of the counter signal C <0> is set to “0”, so that the transistor Tr (a) is turned off. As a result, the source potential ARVSS is set to a potential increased by ΔV1. Thereby, it is tested whether or not the data of the memory cell MC can be held in accordance with the source potential ARVSS in the standby period.

  Next, the BIST circuit 24 executes a process of reading predetermined test data written from the memory array MA in synchronization with the clock signal CLK ((4) READ).

  Then, the count UP control signal is set to “1” in accordance with the result (expected value match) of the expected value determination process ((5) expected value determination (compression)). Accordingly, the counter circuit 36 sets the counter signal C <1> to “1” when the count-up control signal is set to “1”.

  Then, (3) standby → (4) READ → (5) expected value determination (compression) is repeated until the expected values are not matched as a result of the expected value determination (compression). That is, the source potential ARVSS is raised to a potential level at which data destruction occurs.

  In this example, the case where the expected values do not match as a result of repeating the process (k + 1) times is shown. Therefore, the source potential ARVSS is adjusted to ΔVk + 1. Thereafter, the counter value is decremented and returned to one. That is, the source potential ARVSS that has been repeated k times is readjusted to ΔVk. As a result, in the standby mode, the source potential ARVSS at the time of matching is adjusted according to the set counter signal.

Then, the processing of the BIST circuit 24 and the counter circuit 36 is finished.
The adjustment flow can be executed every time the power is turned on or every time a certain time has elapsed. Thereby, it is not necessary to consider the adjustment of the source potential ARVSS based on the aging and manufacturing variation of the memory cell MC at the design stage, and the source potential ARVSS is adjusted to the actual value of the data holding voltage according to the state of the finished memory cell MC. Can be raised. That is, since the potential of the source line (source potential ARVSS) can be adjusted in consideration of the data retention characteristics of the memory cell, there is a remarkable effect in that the standby current in the standby mode (standby period) is suppressed.

  Further, as described above, the source potential ARVSS is adjusted from a low position, and at that time, the data is maintained in a held state. Therefore, data writing (WRITE) is required only once. Therefore, the second and subsequent data writing (WRITE) is unnecessary compared to the first embodiment, and the adjustment time (test time) can be shortened.

  In this example, the ARVSS potential adjustment circuit 19 is set so that the source potential ARVSS is the lowest in the initial state in which the counter signal C that is the output of the counter value of the counter circuit 36 is all “0”. However, when the counter signal C, which is the output of the counter value, is all “1”, the source potential ARVSS is set to be the lowest, and the counter value is decremented to start. Also good. In that case, the inverting circuit may not be provided.

  In the above description, the standby mode test describes the method of adjusting the source line potential by searching for the source potential that can hold data and the impossible source potential in the standby period. However, a margin is provided to some extent. Sometimes it is desirable.

  For example, the temperature at the time of adjusting the source potential ARVSS is room temperature, and when the temperature changes in the actual standby mode, or when the normal operation and the standby mode are simultaneously performed on the chip, the so-called IR drop amount is There may be a case where the source potential ARVSS is larger than that at the time of adjustment.

  In that case, it may be difficult to hold data in the standby mode (standby period) with the adjusted source potential ARVSS.

  Therefore, after adjusting the source potential ARVSS, a signal for readjusting the counter value in a direction that can further secure a margin is generated from the BIST circuit 24, and the margin of the source potential ARVSS in consideration of the temperature worst amount and IR drop amount is incorporated. May be. Specifically, the counter value of the counter circuit may be increased / downed by several steps in a direction in which there is a margin for the data retention characteristic. Further, the margin amount may be adjusted by holding in advance that data retention characteristics change due to aging of the memory cell as data (amount of deterioration of data retention voltage). With this method, it is possible to easily cope with changes in the operating environment of the chip.

  In the above description, the case where the adjustment of the source potential ARVSS is started upon receiving a trigger signal such as the POR signal of the POR circuit after the power is turned on has been described. Or the case where the said adjustment was performed for every predetermined period progress was demonstrated.

  At this time, as described above, the counter value of the counter circuit is reset according to the counter reset signal CRS, so that the source potential of the ARVSS potential adjustment circuit is also reset.

  When the setting of the source potential is adjusted step by step from the high potential side or the low potential side every time, it may take some time.

  Therefore, the counter value at the previous adjustment of the source potential ARVSS is stored in a separately provided storage element (non-volatile), and the stored counter value at the next adjustment of the source potential ARVSS is used as an initial value. It may be used. By this method, the adjustment of the source potential ARVSS is started based on the stored counter value at the next adjustment of the source potential ARVSS, so that the convergence of the test can be accelerated and the adjustment time can be shortened. It is.

(Embodiment 3)
FIG. 12 is a diagram for explaining temperature characteristics of data retention in the memory cell MC.

  Referring to FIG. 12, a case where the number of fail bits (Fail bit count) varies depending on temperature is shown. In this example, the number of fail bits when the power supply potential VDDM is changed when the temperatures are different is shown as an example. As shown in the figure, there is shown a case where there is a difference of ΔV (as an example, about 0.1 V) even when the number of fail bits is the same at high temperature and low temperature. That is, in order to ensure the same operation reliability at high temperatures and low temperatures, it is necessary to increase the power supply potential VDDM at higher temperatures than at lower temperatures. In this example, the data holding temperature characteristic of the power supply potential VDDM is described, but the same applies to the source potential. That is, it is necessary to ensure a sufficient operation margin when the temperature is high than when the temperature is low. That is, it is necessary to lower the potential level of the source potential ARVSS at a higher temperature.

  Therefore, in consideration of the temperature characteristics of data retention in the memory cell MC, it is desirable to add a margin to the source potential ARVSS in accordance with the high temperature operating environment.

  In the third embodiment, a method of adjusting the optimum source potential by reflecting the temperature characteristic of data retention of the memory cell MC in the ARVSS potential adjustment circuit will be described.

  FIG. 13 is a diagram illustrating the configuration of the ARVSS potential adjustment circuit 18 # according to the third embodiment.

  Referring to FIG. 13, ARVSS potential adjustment circuit 18 # includes a temperature adjustment circuit 50 and an ARVSS potential adjustment unit 52.

  Since the ARVSS potential adjustment unit 52 has a circuit configuration similar to that of the ARVSS potential adjustment circuit 18 described with reference to FIG. 3, detailed description thereof will not be repeated. The ARVSS potential adjustment circuit 18 # has a configuration obtained by adding a temperature adjustment circuit 50 to the circuit configuration of the ARVSS potential adjustment circuit 18. In this regard, the ARVSS potential adjustment circuit 18 is configured to adjust the source potential ARVSS by the ARVSS potential adjustment unit 52 and further adjust the source potential ARVSS using the temperature adjustment circuit 50.

  Since the configuration of the ARVSS potential adjustment unit 52 is the same as that of the ARVSS potential adjustment circuit 18, the same operation as described above is executed.

  The temperature adjustment circuit 50 includes a temperature detection circuit SV, buffers BF0 and BF1, and OR circuits OR_000, OR_040, and OR_080. Temperature adjustment circuit 50 further includes AND circuits AND_M40, AND_000, AND_040, AND_080, AND_120, and transistors TR_M40, TR_000, TR_040, TR_080, TR_120. In this example, as an example, the transistors TR_M40, TR_000, TR_040, TR_080, TR_120 are N-channel MOS transistors.

  The temperature detection circuit SV detects the temperature of the chip and outputs a detection signal based on the detected temperature. Specifically, as an example, if the temperature is 0 ° C. or higher, the detection signal TMP_000 is set to “1”. On the other hand, when the temperature is lower than 0 ° C., the detection signal TMP_000 is set to “0”.

  If the temperature is 40 ° C. or higher, the detection signal TMP_040 is set to “1”. On the other hand, if it is lower than 40 ° C., the detection signal TMP_040 is set to “0”.

  If the temperature is 80 ° C. or higher, the detection signal TMP_080 is set to “1”. On the other hand, if it is less than 80 ° C., the detection signal TMP_080 is set to “0”.

  If the temperature is 120 ° C. or higher, the detection signal TMP_120 is set to “1”. On the other hand, if it is lower than 120 ° C., the detection signal TMP_120 is set to “0”.

  The buffer BF0 is connected to the power supply potential VDDM, and outputs “1” to one of the input nodes of the AND circuit AND_M40.

  The OR circuit OR_000 receives the detection signals TMP_000, TMP_040, TMP_080, and TMP_120 and outputs the OR logic operation result as the control signal TMPEN_000. Therefore, when the temperature is 0 ° C. or higher, the control signal TMPEN — 000 is set to “1”. When the temperature is lower than 0 ° C., the control signal TMPEN — 000 is set to “0”.

  The OR circuit OR_040 receives the detection signals TMP_040, TMP_080, and TMP_120 and outputs the OR logic operation result as the control signal TMPEN_040. Therefore, when the temperature is 40 ° C. or higher, the control signal TMPEN — 040 is set to “1”. When the temperature is lower than 40 ° C., the control signal TMPEN — 040 is set to “0”.

  The OR circuit OR_080 receives the detection signals TMP_080 and TMP_120 and outputs the OR logic operation result as the control signal TMPEN_080. Therefore, when the temperature is 80 ° C. or higher, the control signal TMPEN — 080 is set to “1”. When the temperature is lower than 80 ° C., the control signal TMPEN — 080 is set to “0”.

  The buffer BF1 receives the detection signal TMP_120 and outputs it as the control signal TMPEN_120. Therefore, when the temperature is 120 ° C. or higher, the control signal TMPEN — 120 is set to “1”. When the temperature is less than 120 ° C., the control signal TMPEN — 120 is set to “0”.

  The AND circuit AND_M40 receives the input of the buffer BF0 and the standby signal RS and outputs the AND logic operation result to the gate of the transistor TR_M40 as the control signal TM40. Since the output signal of the buffer BF0 is set to “1”, the control signal TM40 is set to “1” or “0” according to the standby signal RS.

  The AND circuit AND_000 receives the control signal TMPEN_000 and the standby signal RS and outputs the AND logic operation result to the gate of the transistor TR_000 as the control signal T000. The control signal T000 is set to “1” or “0” according to the control signal TMPEN — 000 when the standby signal RS is set to “1”.

  The AND circuit AND_040 receives the control signal TMPEN_040 and the standby signal RS and outputs the AND logic operation result to the gate of the transistor TR_040 as the control signal T040. The control signal T040 is set to “1” or “0” according to the control signal TMPEN_040 when the standby signal RS is set to “1”.

  The AND circuit AND_080 receives the control signal TMPEN_080 and the standby signal RS and outputs the AND logic operation result to the gate of the transistor TR_080 as the control signal T080. Control signal T080 is set to “1” or “0” in accordance with control signal TMPEN — 080 when standby signal RS is set to “1”.

  The AND circuit AND_120 receives the control signal TMPEN_120 and the standby signal RS and outputs the AND logic operation result to the gate of the transistor TR_120 as the control signal T120. The control signal T120 is set to “1” or “0” according to the control signal TMPEN — 120 when the standby signal RS is set to “1”.

  Transistor TR_M40 is arranged between source line SL and ground potential VSSM, and has a gate receiving control signal TM40 that is an output signal of AND circuit AND_M40. As described above, the AND circuit AND_M40 receives the input of the buffer BF0 and the standby signal RS and outputs an AND logic operation result as the control signal TM40. Therefore, the transistor TR_M40 receiving the control signal TM40 at the gate is turned on when the standby signal RS is “1” and turned off when the standby signal RS is “0”. That is, it is turned on in the standby mode. It is assumed that the transistor TR_M40 is set to a transistor having a small passing current Ids when turned on.

  Transistor TR_000 is arranged between source line SL and ground potential VSSM, and has a gate receiving control signal T000, which is an output signal of AND circuit AND_000. When the standby signal RS is set to “1” and the temperature is 0 ° C. or higher, the control signal T000 is set to “1”, so that the transistor TR_000 is turned on.

  Transistor TR_040 is arranged between source line SL and ground potential VSSM, and has a gate receiving control signal T040 that is an output signal of AND circuit AND_040. When the standby signal RS is set to “1” and the temperature is 40 ° C. or higher, the control signal T040 is set to “1”, so that the transistor TR_040 is turned on.

  Transistor TR_080 is arranged between source line SL and ground potential VSSM, and has a gate receiving control signal T080 as an output signal of AND circuit AND_080. When the standby signal RS is set to “1” and the temperature is 80 ° C. or higher, the control signal T080 is set to “1”, so that the transistor TR_080 is turned on.

  Transistor TR_120 is arranged between source line SL and ground potential VSSM, and has a gate receiving control signal T102, which is an output signal of AND circuit AND_120. When the standby signal RS is set to “1” and the temperature is 120 ° C. or higher, the control signal T120 is set to “1”, so that the transistor TR_120 is turned on.

  That is, in the temperature adjustment circuit 50, when the standby signal RS is set to “1”, the transistor TR_M40 is turned on in the initial state. When the temperature is 0 ° C. or higher, the transistors TR_M40 and TR_000 are turned on. Further, when the temperature is 40 ° C. or higher, the transistors TR_M40, TR_000, TR_040 are turned on. When the temperature is 80 ° C. or higher, the transistors TR_M40, TR_000, TR_040, TR_080 are turned on. When the temperature is 120 ° C. or higher, the transistors TR_M40, TR_000, TR_040, TR_080, TR_120 are turned on.

  Note that the transistors for adjustment TR_000, TR_040, TR_080, and TR_120 in the temperature adjustment circuit 50 are set to transistors having a small passing current Ids to adjust the source potential ARVSS stepwise (about several mV) according to the temperature change. Shall.

  In this example, the source potential ARVSS is adjusted by the ARVSS potential adjustment unit 52 when the standby signal RS is “1”, that is, in the standby mode. Further, the temperature of the chip is further detected, and the adjustment transistors TR_000, TR_040, TR_080, and TR_120 are turned on according to the detection result, thereby adjusting the source potential ARVSS adjusted by the ARVSS potential adjustment unit 52 by further lowering the predetermined potential. .

  In this configuration, that is, the potential of the source potential ARVSS is further adjusted according to the temperature of the chip by the temperature adjustment circuit 50, so that the potential adjusted by the ARVSS potential adjustment unit 52 is fixed in consideration of the temperature characteristics of data retention of the memory cell MC Therefore, it is not necessary to secure a margin, and it is possible to adjust the source potential to reflect the temperature characteristics.

<Timing chart for adjusting source potential ARVSS>
FIG. 14 is a diagram illustrating a timing chart for adjusting the source potential ARVSS according to the third embodiment.

  Referring to FIG. 14, from the first time t0 to time t1 (period A), the adjustment process of the source potential ARVSS is executed. In this example, a case where the source potential ARVSS is adjusted stepwise by the method described in Embodiment 1 will be described.

  Specifically, the counter circuit 32 is initialized according to the counter reset signal CRS. As a result, the counter signals C are all set to “0”. Then, a standby mode test is executed. As described above, the source potential is set to the initial potential (VDDM / 2) (the potential at which data in the memory cell is destroyed). Then, as described above, the count UP control signal is set to “1” in accordance with the result (expected value mismatch) of the expected value determination process ((5) expected value determination (compression)). Accordingly, the counter circuit 32 sets the counter signal C <1> to “1” when the count-up control signal is set to “1”.

  Then, (2) WRITE → (3) standby → (4) READ → (5) expected value determination (compression) is repeated until the expected values match as a result of the expected value determination (compression). That is, the source potential ARVSS is lowered to a potential level at which data destruction does not occur.

  In this example, the case where the expected value matches when the counter signal C <k> is set to “1” is shown. In this example, the source potential ARVSS is adjusted to VDDM / 2−ΔVk.

  Then, normal operation is performed from time t1 to time t2 (period B). Specifically, the standby signal RS is set to “0”, and normal data write processing, read processing, and the like are performed on the memory array MA.

  The case where the temperature of the chip rises according to the operation process for the memory array MA and the detection signals TMP_000, TMP_040, TMP_080, and TMP_120 are sequentially set to “1” is shown.

  Next, at time t2, the standby mode (standby period) is set. In this example, the standby mode (standby period) is set from time t2 to time t4 (period C). Specifically, the standby signal RS is set to “1”, and the memory array MA enters the standby mode. Accordingly, since the detection signals TMP_000, TMP_040, TMP_080, and TMP_120 are “1” and the standby signal RS is set to “1”, the transistors TR_000, TR_040, TR_080, and TR_120 are all turned on. As a result, the source potential ARVSS further decreases from the set potential by the predetermined potential ΔV1. That is, in this example, the source potential ARVSS is set to VDDM / 2−ΔVk−ΔV1 as an example. As a result, even when the temperature of the chip rises and the data retention characteristic is affected, the standby current is suppressed in consideration of the data retention characteristic of the memory cell MC in the standby mode (standby period) by adjusting the source potential ARVSS. It becomes possible.

  In the standby period, since the processing for the memory array MA is stopped, the temperature of the chip is lowered, and the detection signals TMP_120, TMP_080, TMP_040, and TMP_000 are sequentially set to “0”. In response to this, the transistors TR_120, TR_080, TR_040, TR_000 are sequentially turned off. Therefore, as the transistor TR is turned off, that is, with the temperature change of the chip, the source potential ARVSS is adjusted stepwise and rises. At time t3, when the detection signal TMP_000 is set to “0”, the transistors TR_120, TR_080, TR_040, and TR_000 are all turned off, so that the source potential ARVSS is adjusted to VDDM / 2−ΔVk. When the temperature of the chip is thereby lowered and the data retention characteristic is improved, the source potential ARVSS is adjusted (increased) so that the data retention characteristic of the memory cell MC is taken into consideration in the standby mode (standby period). It is possible to efficiently suppress the standby current.

  Next, normal operation is performed from time t4 to time t5 (period D). Specifically, the standby signal RS is set to “0”, and normal data write processing, read processing, and the like are performed on the memory array MA.

  In this case, the temperature of the chip rises according to the operation process for the memory array MA, and the detection signals TMP_000 and TMP_040 are sequentially set to “1”.

  Next, after time t5, the standby mode (standby period) (period E) is set. Specifically, the standby signal RS is set to “1”, and the memory array MA enters the standby mode. Accordingly, since the detection signals TMP_000 and TMP_040 are “1” and the standby signal RS is set to “1”, the transistors TR_000 and TR_040 are turned on. As a result, the source potential ARVSS further decreases from the set potential by the predetermined potential ΔV2. That is, in this example, the source potential ARVSS is set to VDDM / 2−ΔVk−ΔV2 as an example. As a result, even when the temperature of the chip rises and the data retention characteristic is affected, by adjusting the source potential ARVSS, it is possible to suppress the standby current in consideration of the data retention characteristic of the memory cell MC in the standby period. Become.

  In the standby period, since the processing for the memory array MA is stopped, the temperature of the chip is lowered, and the detection signals TMP_040 and TMP_000 are sequentially set to “0”. In response to this, the transistors TR_040 and TR_000 are sequentially turned off. Therefore, as the transistor TR is turned off, that is, with the temperature change of the chip, the source potential ARVSS is adjusted stepwise and rises. At time t6, when the detection signal TMP_000 is set to “0”, the transistors TR_040 and TR_000 are all turned off, so that the source potential ARVSS is adjusted to VDDM / 2−ΔVk. When the temperature of the chip is thereby lowered and the data retention characteristic is improved, the source potential ARVSS is adjusted (increased) so that the data retention characteristic of the memory cell MC is taken into consideration in the standby mode (standby period). It is possible to efficiently suppress the standby current.

  Therefore, with this configuration, the ARVSS potential adjustment circuit can adjust the optimal source potential by reflecting the data retention temperature characteristic of the memory cell MC, and can effectively suppress the standby current in the standby mode (standby period). It is.

(Embodiment 4)
Next, a method for shortening the time for setting the source potential ARVSS will be described.

  In the fourth embodiment, a case where the setting of the optimum source potential ARVSS is shortened according to a so-called binary search (binary search tree) will be described.

  FIG. 15 is a schematic block diagram of a configuration of peripheral circuit 20 that controls ARVSS potential adjustment circuit 18 according to the fourth embodiment.

  Referring to FIG. 15, compared with the configuration of FIG. 2, in this configuration, a binary search execution circuit 60 is provided instead of AND circuit 30, and counter circuit 32 is replaced with UP / DOWN counter circuit 36. The point is different.

  The binary search execution circuit 60 is a circuit that executes a binary search, and includes a count value output circuit 62, a binary search control circuit 64, and a counter control signal output circuit 66.

  In this example, the compression circuit 28 outputs the compressed data “0” or “1” to the binary search execution circuit 60.

  The counter reset signal CRS is output to the UP / DOWN counter circuit 36 and the binary search control circuit 64. In the UP / DOWN counter circuit 36, the counter value is reset according to the counter reset signal CRS and set to the initial value “0”.

  The binary search control circuit 64 generally manages processing related to the adjustment of the source potential ARVSS according to the input of the counter reset signal CRS. Specifically, a test start signal is output to the BIST circuit 24, and the BIST circuit 24 outputs a predetermined signal to the memory cell MC of the SRAM module 10 according to the instruction of the test start signal as described in the first embodiment. Execute processing to write test data. Then, the SRAM module 10 is set to the standby mode. Then, in order to determine the data retention characteristic of the memory cell MC, a process of reading the test data written to the SRAM module 10 is executed.

  Then, the BIST circuit 24 outputs an expected value to the comparison circuit 26. Then, the comparison circuit 26 compares the read data DQ read from the SRAM module 10 with the expected value output from the BIST circuit 24, and compresses the comparison result (whether or not it matches the expected value). It outputs to the circuit 28. The compression circuit 28 compresses the comparison result output from the comparison circuit 26 and outputs “0” to the binary search control circuit 64 if all the data match, and “1” if even one does not match. Is output to the binary search control circuit 64.

  The BIST circuit 24 outputs a test end signal to the binary search control circuit 64 after executing this series of processing in accordance with the instruction of the test start signal. Specifically, as a series of processes, the BIST circuit 24 writes predetermined test data to the SRAM module 10, sets the standby mode, reads the written test data, and outputs an expected value. After that, a test end signal is output to the binary search control circuit 64.

  The binary search control circuit 64 outputs an UP / DOWN control signal and an output start signal to the counter control signal output circuit 66 in accordance with the compressed data “0” or “1” from the compression circuit 28 and the test end signal from the BIST circuit 24. .

  The UP / DOWN control signal is a control signal that defines the UP direction and the DOWN direction of the count UP control signal output from the counter control signal output circuit 66 or the counter DOWN control signal.

  The output start signal is a signal that serves as a trigger for the counter control signal output circuit 66 to output a counter UP control signal or a counter DOWN control signal. The counter control signal output circuit 66 outputs a count value pulse signal according to the count value from the count value output circuit 62 based on the clock signal CLK as a counter UP control signal or a counter DOWN control signal. When the output of the count value pulse signal ends, the counter control signal output circuit 66 outputs an output end signal to the binary search control circuit 64.

  Further, the binary search control circuit 64 outputs the initial count value setting signal and the initial count value M to the count value output circuit 62. Thus, the count value output circuit 62 sets the initial count value M according to the initial count value setting signal and outputs the count value to the counter control signal output circuit 66.

  Further, the binary search control circuit 64 outputs a count value right shift signal to the count value output circuit 62. The count value output circuit 62 shifts the bit string of the set count value to the right according to the count value right shift signal. That is, the count value is set to ½.

  The binary search control circuit 64 outputs a binary search end signal to the BIST circuit 24 when it is determined that the binary search is completed according to the compressed data. If it is determined that the binary search cannot be completed, the potential adjustment error signal is output to the BIST circuit 24.

  FIG. 16 is a diagram illustrating an adjustment flow of source potential ARVSS according to the fourth embodiment.

  The adjustment flow is a flow for adjusting the source potential ARVSS to an optimum potential set in the standby mode.

  In general, it is tested whether data written in the memory cell MC can be held in the standby mode (standby period). Specifically, a source potential that can be adjusted to a plurality of levels is adjusted (increase or decrease potential) in accordance with a binary search method to search for a potential level that does not cause data destruction.

  Referring to FIG. 16, first, power is turned on (step S2). For example, a switch (not shown) is turned on so that the power supply voltage and the semiconductor integrated circuit 1 are connected.

  Next, it is determined whether or not the POR signal is turned on (step S4). Specifically, the POR circuit 22 sets the POR signal to “1” (ON) when it is determined that the power supply voltage is in a stable state.

  If it is determined in step S4 that the POR signal is ON (YES in step S4), the process proceeds to step S6. The state of step S4 is maintained until the POR signal is turned ON.

  Next, in step S6, the counter is reset (step S6). Specifically, the BIST circuit 24 outputs a counter reset signal CRS (“1”) to the counter circuit 36 in response to the input of the POR signal. The counter circuit 36 receives the counter reset signal CRS and resets (initializes) the counter value. Accordingly, the counter signal C <N−1: 0> based on the counter value is set to “0”. Further, the BIST circuit 24 outputs a counter reset signal CRS “1” to the binary search execution circuit 60. Accordingly, the binary search execution circuit 60 starts a binary search.

  Next, an initial counter value is set (step S7). The binary search control circuit 64 outputs an initial count value M and an initial count value setting signal and outputs them to the count value output circuit 62. The initial count value M is set to “2 ^ N−1” or “1”. As a result, the count value output circuit 62 sets “2 ^ N−1” or “1” as the initial count value. Then, the set count value is output to the counter control signal output circuit 66. In this example, the symbol “^” indicates that it is a power.

  Next, a counter UP control signal or a counter DOWN control signal is output (step S7 #). Specifically, the binary search control circuit 64 instructs the counter control signal output circuit to output a counter UP control signal or a counter DOWN control signal. The binary search control circuit 64 outputs an UP control signal to the counter control signal output circuit 66 when the initial count value M is set to “2 ^ N−1”. On the other hand, when the initial count value M is set to “1”, the DOWN control signal is output to the counter control signal output circuit 66. Counter control signal output circuit 66 outputs a counter UP control signal or a counter DOWN control signal in accordance with the count value set in count value output circuit 62 and the UP control signal or DOWN control signal output from binary search control circuit 64. As an example, when the initial count value M is set to “2 ^ N−1”, the counter control signal output circuit 66 generates a clock pulse corresponding to the value of the initial count value “2 ^ N−1” according to the UP control signal. Is output to the UP / DOWN counter circuit 36 as a counter UP control signal. As a result, the counter value of the UP / DOWN counter circuit 36 is incremented from the initial value “0” according to the clock pulse and set to a value of “2 ^ N−1”. Accordingly, the N counter signals C <0> to C <N−1> of the counter signal C <N−1: 0> are all set to “1”. As an example, when the initial count value M is set to “1”, the counter control signal output circuit 66 uses the clock pulse corresponding to the value of the initial count value “1” as the counter DOWN control signal according to the DOWN control signal. The data is output to the UP / DOWN counter circuit 36. As a result, the counter value of the UP / DOWN counter circuit 36 is decremented from the initial value 0 according to the clock pulse and set to a value of “2 ^ N−1”. Accordingly, the N counter signals C <0> to C <N−1> of the counter signal C <N−1: 0> are all set to “1”.

  The binary search control circuit 64 outputs a test start signal to the BIST circuit 24.

  Next, a data writing process is executed on the SRAM module 10 (step S8). Specifically, as described above, the BIST circuit 24 that has received the input of the test start signal from the binary search control circuit 64 inputs write data DI, which is predetermined test data, to the SRAM module 10.

  Then, a standby mode test is executed (step S10). The standby mode test is to test whether or not the data written in the SRAM module 10 can be held in the standby mode (standby period). Specifically, the standby signal RS is set to “1”, and the source potential ARVSS is set to a potential set in the standby mode by the ARVSS potential adjusting circuit 18 according to the counter signal C. In this example, since the counter signals C <0> to C <N−1> are all set to “1”, as described above, the source potential ARVSS is set to a potential (for example, 0 V) that does not cause data destruction. Is done.

  Next, a data read process is executed on the SRAM module 10 (step S12). Specifically, as described above, the BIST circuit 24 instructs the SRAM module 10 to read out the written test data. The SRAM module 10 outputs the read data DQ to the comparison circuit 26.

  Next, expected value determination processing is executed (step S14). Specifically, the comparison circuit 26 compares the read data DQ read from the SRAM module 10 with the expected value given from the BIST circuit 24, and whether the read data DQ and the expected value match. Determine whether. Then, the result is output to the compression circuit 28.

  The compression circuit 28 compresses the comparison result output from the comparison circuit 26 and outputs “0” (PASS in step S14) if all the data match. On the other hand, if even one piece of data does not match, “1” is output (FAIL in step S14).

  If even one piece of data does not match in step S14 (FAIL in step S14), the binary search control circuit 64 outputs error information to the BIST circuit 24 (step S20). In this case, that is, the source potential ARVSS is set to a potential (0 V) at which data destruction does not occur, and data destruction has occurred despite the fact that the operation margin is most secured. There may be an abnormality. Therefore, the peripheral circuit can execute predetermined error processing according to the error information. For example, it is possible to provide notification of maintenance or notification of parts replacement to the outside.

  Then, the processes of the BIST circuit 24 and the counter circuit 36 are finished (stopped) (step S68). Specifically, the process for adjusting the source potential ARVSS is terminated. Further, the counter circuit 36 is stopped. Then, the process ends (END).

  On the other hand, if all the data match in step S14 (PASS in step S14), the binary search control circuit 64 sets the count value of the count value output circuit 62 to 2 ^ (N-1) (step S14). S30). Specifically, the binary search control circuit 64 outputs a count value right shift signal to the count value output circuit 62. Further, the count value is incremented by one. Thereby, the count value of the count value output circuit 62 is set to 2 ^ (N-1). This process is a process of setting the count value to a value that is 1/2 (half) of 2 ^ N. This is a process for setting the counter value of the UP / DOWN counter circuit 36 to an intermediate value between the upper limit (max) and the lower limit (min) of the counter value based on the count value.

  Then, a counter DOWN control signal is output (step S32). Specifically, the binary search control circuit 64 instructs the counter control signal output circuit 66 to output a counter DOWN control signal. Here, the binary search control circuit 64 outputs a DOWN control signal to the counter control signal output circuit 66. The counter control signal output circuit 66 outputs a counter DOWN control signal according to the count value set in the count value output circuit 62 and the DOWN control signal output from the binary search control circuit 64. The counter control signal output circuit 66 outputs a clock pulse corresponding to the count value 2 ^ (N-1) according to the DOWN control signal to the UP / DOWN counter circuit 36 as a counter DOWN control signal. Thereby, the counter value of the UP / DOWN counter circuit 36 is set to 2 ^ (N-1) -1. Then, a counter signal C <N−1: 0> based on the counter value is set.

  Then, the following loop processing is executed. In this example, the loop process is executed (N-1) times.

Specifically, first, an immediately preceding expected value determination process is executed (step S36).
Then, with respect to the immediately preceding expected value determination process, it is determined whether or not the read data DQ matches the expected value. If the expected values match (PASS in step S36), step S38 is skipped. Then, a standby mode test is executed (step S40). Specifically, the standby signal RS is set to “1”, and the source potential ARVSS is set to a potential set in the standby mode by the ARVSS potential adjusting circuit 18 according to the counter signal C.

  On the other hand, if the read data DQ and the expected value do not match with respect to the immediately preceding expected value determination process (NO in step S36), a data write process is executed on the SRAM module 10 (step S38). Specifically, as described above, the BIST circuit 24 that has received the input of the test start signal from the binary search control circuit 64 inputs write data DI, which is predetermined test data, to the SRAM module 10. Since the immediately preceding expected value determination process is inconsistent, there is a possibility that the data has been destroyed. Therefore, it is necessary to execute the data writing process again. Then, the standby mode test of step S40 is executed (step S40).

  Next, a data read process is executed on the SRAM module 10 (step S42). Specifically, as described above, the BIST circuit 24 instructs the SRAM module 10 to read out the written test data. The SRAM module 10 outputs the read data DQ to the comparison circuit 26.

  Next, the binary search control circuit 64 sets the count value of the count value output circuit 62 to the previous count value / 2 (step S44).

  Specifically, the binary search control circuit 64 outputs a count value right shift signal to the count value output circuit 62. As a result, the count value of the count value output circuit 62 is set to a half value.

  Next, expected value determination processing is executed (step S46). Specifically, the comparison circuit 26 compares the read data DQ read from the SRAM module 10 with the expected value given from the BIST circuit 24, and whether the read data DQ and the expected value match. Determine whether. Then, the result is output to the compression circuit 28. The compression circuit 28 compresses the comparison result output from the comparison circuit 26, and outputs “0” if all the data match (PASS in step S46). To do. On the other hand, if even one piece of data does not match (FAIL in step S46), “1” is output.

  If even one piece of data does not match in step S46 (FAIL in step S46), the binary search control circuit 64 outputs a counter UP control signal (step S50). Specifically, the binary search control circuit 64 instructs the counter control signal output circuit 66 to output a counter UP control signal. Here, the binary search control circuit 64 outputs an UP control signal to the counter control signal output circuit 66. The counter control signal output circuit 66 outputs a counter UP control signal according to the count value set in the count value output circuit 62 and the UP control signal output from the binary search control circuit 64. The counter control signal output circuit 66 outputs a clock pulse corresponding to the count value according to the UP control signal to the UP / DOWN counter circuit 36 as a counter UP control signal. As a result, the counter value corresponding to the clock pulse of the UP / DOWN counter circuit 36 is incremented and set. Then, a counter signal C <N−1: 0> based on the counter value is set. And it returns to step S34 by a loop process (step S52), and repeats said process. In this example, the loop process is repeated (N-1) times as described above.

  On the other hand, if all the data match in step S46 (PASS in step S46), the binary search control circuit 64 outputs a counter DOWN control signal (step S48). Specifically, the binary search control circuit 64 instructs the counter control signal output circuit 66 to output a counter DOWN control signal. Here, the binary search control circuit 64 outputs a DOWN control signal to the counter control signal output circuit 66. The counter control signal output circuit 66 outputs a counter DOWN control signal according to the count value set in the count value output circuit 62 and the DOWN control signal output from the binary search control circuit 64. The counter control signal output circuit 66 outputs a clock pulse corresponding to the count value in accordance with the DOWN control signal to the UP / DOWN counter circuit 36 as a counter DOWN control signal. As a result, the counter value corresponding to the clock pulse of the UP / DOWN counter circuit 36 is decremented and set. Then, a counter signal C <N−1: 0> based on the counter value is set. And it returns to step S34 by a loop process (step S52), and repeats said process. In this example, the loop process is repeated (N−1) times as described above.

  The count value of the count value output circuit 62 is set to “1” by repeating the loop processing (N−1) times.

  And after repeating the said process, a loop process is complete | finished and the last expected value determination process is performed (step S54). Then, with respect to the immediately preceding expected value determination process, it is determined whether or not the read data DQ matches the expected value. If the expected values match (PASS in step S54), step S56 is skipped. Then, a standby mode test is executed (step S58). Specifically, the standby signal RS is set to “1”, and the source potential ARVSS is set to a potential set in the standby mode by the ARVSS potential adjusting circuit 18 according to the counter signal C.

  If the read data DQ and the expected value do not match with respect to the immediately preceding expected value determination process (NO in step S54), a data write process is executed on the SRAM module 10 (step S56). Specifically, as described above, the BIST circuit 24 that has received the input of the test start signal from the binary search control circuit 64 inputs write data DI, which is predetermined test data, to the SRAM module 10. Since the previous expected value determination process is inconsistent, the data may be destroyed, so the data write process is executed again. Then, the next standby mode test is executed (step S58).

  Next, a data read process is executed on the SRAM module 10 (step S60). Specifically, as described above, the BIST circuit 24 instructs the SRAM module 10 to read out the written test data. The SRAM module 10 outputs the read data DQ to the comparison circuit 26.

  Then, an expected value determination process is executed (step S62). Then, regarding the expected value determination process, it is determined whether or not the read data DQ and the expected value match. If the expected values match (PASS in step S62), the process proceeds to step S68, and the processing of the BIST circuit 24 and the counter circuit 36 is ended (stopped). Specifically, the process for adjusting the source potential ARVSS is terminated. Further, the counter circuit 36 is stopped.

  On the other hand, if the expected values do not match (FAIL in step S62), the process proceeds to step S64, and the counter is incremented by one. Specifically, the binary search control circuit 64 instructs the counter control signal output circuit 66 to output a counter UP control signal. Here, the binary search control circuit 64 outputs an UP control signal to the counter control signal output circuit 66. The counter control signal output circuit 66 outputs a counter UP control signal (one clock pulse) in accordance with the count value (“1”) set in the count value output circuit 62 and the UP control signal output from the binary search control circuit 64. To do. As a result, the counter value corresponding to the clock pulse of the UP / DOWN counter circuit 36 is incremented and set. Then, a counter signal C <N−1: 0> based on the counter value is set.

  In step S68, the processing of the BIST circuit 24 and the counter circuit 36 is ended (stopped). Specifically, the process for adjusting the source potential ARVSS is terminated. Further, the counter circuit 36 is stopped.

  FIG. 17 is a diagram illustrating a specific example of the counter value of the binary search (binary search tree) according to the fourth embodiment.

  With reference to FIG. 17, a 3-bit (N = 3) UP / DOWN counter circuit 36 will be described in this example.

That is, this corresponds to the case of N = 3.
The count value output circuit 62 sets “7” which is “2 ^ 3-1” as the initial count value M. The bit signal of the count value of the count value output circuit 62 is “111”.

  The UP / DOWN counter circuit 36 is set to “0” according to the counter reset signal CRS. Therefore, the bit signal of the counter value of the UP / DWON counter circuit 36 is “000”.

  First, a counter UP control signal is output to the UP / DOWN counter circuit 36 according to the count value of the count value output circuit 62. In this example, the clock pulse is output seven times. As a result, the UP / DOWN counter circuit 36 is incremented and set to “7”. Therefore, the bit signal of the counter value of the UP / DOWN counter circuit 36 is “111”. Counter signals C <0> to C <7> are all set to “1”. Therefore, the source potential ARVSS is set to an initial potential (near VSSM (= 0 V)) (set to a potential capable of holding data in the memory cell). In this example, the source potential ARVSS can be adjusted in eight stages. When the levels L0 to L7 (> L0), the source potential ARVSS is set to the level L0.

  In the standby mode test based on the source potential, the compressed data “1” is output (1).

  Next, the count value of the count value output circuit 62 is set to “4”, which is 2 ^ (3-1). Specifically, the binary search control circuit 64 outputs a count value right shift signal to the count value output circuit 62. Further, the count value is incremented by one. Thereby, the count value of the count value output circuit 62 is set to “4”. The count value bit signal of the count value output circuit 62 is set to “100”.

  A counter DOWN control signal is output to the UP / DOWN counter circuit 36 in accordance with the count value of the count value output circuit 62. In this example, the clock pulse is output four times. As a result, the UP / DOWN counter circuit 36 is decremented and set to “3”. The bit signal of the counter value of the UP / DOWN counter circuit 36 is “011”. Counter signals C <0> to C <3> are set to “1”. Counter signals C <4> to C <7> are set to “0”.

  Next, in the loop processing, since the compressed data is “1” in the previous expected value determination, that is, the data match (PASS), the data writing is skipped and the standby mode test is executed.

  In this case, according to the counter signal, the source potential ARVSS is set to a potential at which four transistors from the initial potential are turned off (raised). In this example, the source potential ARVSS can be adjusted in eight stages. When the levels L0 to L7 (> L0), the source potential ARVSS is set to the level L4.

  In this example, the case where “1” is output as the compressed data according to the standby mode test based on the source potential is shown (2).

  Next, the count value of the count value output circuit 62 is set to a half value “2”. Specifically, the binary search control circuit 64 outputs a count value right shift signal to the count value output circuit 62. As a result, the count value of the count value output circuit 62 is set from “4” to “2”. The count value bit signal of the count value output circuit 62 is set to “010”.

  In the expected value determination, since the compressed data is “1”, that is, the data match (PASS), a counter DOWN control signal is output.

  A counter DOWN control signal is output to the UP / DOWN counter circuit 36 in accordance with the count value of the count value output circuit 62. In this example, the clock pulse is output twice. As a result, the UP / DOWN counter circuit 36 is decremented and set to “1”. The bit signal of the counter value of the UP / DOWN counter circuit 36 is “001”. Counter signals C <0> to C <1> are set to “1”. Counter signals C <2> to C <7> are set to “0”. Thereby, the first loop processing is completed.

  Then, by the second loop processing, the compressed data is “1” in the previous expected value determination, that is, the data match (PASS), so the data writing is skipped and the standby mode test is executed.

  In this case, according to the counter signal, the source potential ARVSS is set to a potential in which six transistors are turned off from the initial potential (raised). In this example, the source potential ARVSS can be adjusted in eight stages. When the levels L0 to L7 (> L0), the source potential ARVSS is set to the level L6.

  In this example, the case where “0” is output as the compressed data according to the standby mode test based on the source potential is shown (3).

  Next, the count value of the count value output circuit 62 is set to a half value “1”. Specifically, the binary search control circuit 64 outputs a count value right shift signal to the count value output circuit 62. As a result, the count value of the count value output circuit 62 is set from “2” to “1”. The count value bit signal is set to “001”.

  In the expected value determination, since the compressed data is “0”, that is, data mismatch (FAIL), a counter UP control signal is output.

  A counter UP control signal is output to the UP / DOWN counter circuit 36 in accordance with the count value of the count value output circuit 62. In this example, a clock pulse is output once. As a result, the UP / DOWN counter circuit 36 is incremented and set to “2”. The bit signal of the counter value of the UP / DOWN counter circuit 36 is “010”. Counter signals C <0> to C <2> are set to “1”. Counter signals C <3> to C <7> are set to “0”. This completes the second loop process.

Since the loop process has been performed (N−1) times, that is, twice, the loop process ends.
Then, since the compressed data is “0”, that is, the data does not match (FAIL) in the previous expected value determination, the data writing is executed and the standby mode test is executed.

  In this case, according to the counter signal, the source potential ARVSS is set to a potential at which five transistors are turned off from the initial potential (raised). In this example, the source potential ARVSS can be adjusted in eight stages. When the levels L0 to L7 (> L0), the source potential ARVSS is set to the level L5.

  In this example, the case where “1” is output as the compressed data according to the standby mode test based on the source potential is shown (4). This stops the counter.

  That is, in brief, when the source potential ARVSS can be adjusted in eight stages (levels L0 to L7) so as to follow the binary search method (binary search tree), first, the source potential ARVSS is set to the level L0. The compressed data (determination signal as to whether or not the data is held) is determined, and when the compressed data is “1”, the level is set to the intermediate level L4. Then, the compressed data is determined to determine which group the appropriate source potential ARVSS belongs to. If the compressed data is “1”, the appropriate source potential ARVSS is any of the levels L4 to L7, and if the compressed data is “0”, the appropriate source potential ARVSS is any of the levels L0 to L3. is there. That is, the range is narrowed by setting the source potential ARVSS to an intermediate level. It is possible to reduce the set number of times by repeating the method.

  In this example, it is repeated (N-1) times, and in this example, it is repeated twice. Specifically, since the compressed data is “1”, it is set to level L6, which is an intermediate level between levels L4 to L7. Then, the compressed data is determined to determine which group the appropriate source potential ARVSS belongs to. If the compressed data is “1”, the appropriate source potential ARVSS is either level L6 or L7, and if the compressed data is “0”, the appropriate source potential ARVSS is either level L4 or L5. is there. In this example, since the compressed data is “0”, the level is set to L5. Then, the compressed data is determined to determine whether the appropriate source potential ARVSS is L4 or L5. If the compressed data is “1”, the appropriate source potential ARVSS is level L5, and if the compressed data is “0”, the appropriate source potential ARVSS is level L4. In this example, since the compressed data is “1”, the source potential ARVSS is set to the level L5.

Therefore, the expected value determination process is performed (N + 1) times, that is, four times.
In the first embodiment or the second embodiment, since the source potential ARVSS is adjusted step by step, it may take a long time to perform the expected value determination processing by adjusting the source potential step by step. By using this method, an appropriate source potential ARVSS can be set by (N + 1) times of expected value determination processing, and the processing can be completed efficiently and quickly.

(Modification of Embodiment 4)
Next, a modification of the fourth embodiment will be described.

  The modification of the fourth embodiment is a case where the setting of the optimum source potential ARVSS is shortened according to a so-called binary search (binary search tree), as in the fourth embodiment.

  FIG. 18 is a schematic block diagram of a configuration of peripheral circuit 20 that controls ARVSS potential adjustment circuit 18 according to the modification of the fourth embodiment.

  Referring to FIG. 18, the difference from the configuration of FIG. 15 is that binary search execution circuit 60 is replaced with binary search execution circuit 60 #. Another difference is that the UP / DOWN counter circuit 36 is deleted.

  Binary search execution circuit 60 # includes a binary search control circuit 64, a count value output circuit 62, an N-bit addition / subtraction circuit 65, and an N-bit register 67. The N-bit addition / subtraction circuit 65 is provided in place of the counter control signal output circuit 66. The N-bit register 67 is provided in place of the UP / DOWN counter circuit 36.

  A register reset signal RRS is output from the BIST circuit 24 to the N-bit register 67 and the binary search control circuit 64 instead of the counter reset signal CRS. The N-bit register is reset in response to a register reset signal RRS and set to an initial value “0”. All register values <N-1: 0> are set to “0”. In this example, the register value <N-1: 0> is used in the same manner as the counter signal C <N-1: 0>.

  The binary search control circuit 64 generally manages processing related to the adjustment of the source potential ARVSS according to the input of the register reset signal RRS. Specifically, a test start signal is output to the BIST circuit 24, and the BIST circuit 24 outputs predetermined test data to the memory cells MC of the SRAM module 10 as described above according to the instruction of the test start signal. Execute the writing process. Then, the SRAM module 10 is set to the standby mode. Then, in order to determine the data retention characteristic of the memory cell MC, a process of reading the test data written to the SRAM module 10 is executed.

  Then, the BIST circuit 24 outputs an expected value to the comparison circuit 26. Then, the comparison circuit 26 compares the read data DQ read from the SRAM module 10 with the expected value output from the BIST circuit 24, and compresses the comparison result (whether or not it matches the expected value). It outputs to the circuit 28. The compression circuit 28 compresses the comparison result output from the comparison circuit 26 and outputs “0” to the binary search control circuit 64 if all the data match, and “1” if even one does not match. Is output to the binary search control circuit 64.

  The BIST circuit 24 outputs a test end signal to the binary search control circuit 64 after executing this series of processing in accordance with the instruction of the test start signal. Specifically, as a series of processes, the BIST circuit 24 writes predetermined test data to the SRAM module 10, sets the standby mode, reads the written test data, and outputs an expected value. After that, a test end signal is output to the binary search control circuit 64.

  The binary search control circuit 64 outputs an addition / subtraction control signal to the N-bit addition / subtraction circuit 65 in accordance with the compressed data “0” or “1” from the compression circuit 28 and the test end signal from the BIST circuit 24.

  The addition / subtraction control signal is a signal for controlling addition / subtraction in the N-bit addition / subtraction circuit 65. Specifically, the N-bit addition / subtraction circuit 65 receives the count value set in the count value output circuit 62 and the register value set in the N-bit register 67, and adds or subtracts according to the addition / subtraction control signal. Perform subtraction processing.

  The data capture signal is a signal that instructs the binary search control circuit 64 to capture the processing result of the N-bit addition / subtraction circuit 65 to the N-bit register 67. The N-bit register 67 captures the processing result of the N-bit addition / subtraction circuit 65 in accordance with the data capture signal and sets the register value. The register value set by the N-bit register 67 is input so that it can be processed by the N-bit addition / subtraction circuit 65.

  Further, the binary search control circuit 64 outputs the initial count value setting signal and the initial count value M to the count value output circuit 62. Accordingly, the count value output circuit 62 sets the initial count value M in accordance with the initial count value setting signal and outputs the count value to the N-bit addition / subtraction circuit 65.

  Further, the binary search control circuit 64 outputs a count value right shift signal to the count value output circuit 62. The count value output circuit 62 shifts the bit string of the set count value to the right according to the count value right shift signal. That is, the count value is set to ½.

  The binary search control circuit 64 outputs a binary search end signal to the BIST circuit 24 when it is determined that the binary search is completed according to the compressed data. If it is determined that the binary search cannot be completed, the potential adjustment error signal is output to the BIST circuit 24.

  FIG. 19 is a diagram illustrating a flow of adjusting the source potential ARVSS according to the modification of the fourth embodiment.

  The adjustment flow is a flow for adjusting the source potential ARVSS to an optimum potential set in the standby mode.

  In general, it is tested whether data written in the memory cell MC can be held in the standby mode (standby period). Specifically, a source potential that can be adjusted to a plurality of levels is adjusted (increase or decrease potential) according to a binary search method to search for a potential level that does not cause data destruction.

  Referring to FIG. 19, first, power is turned on (step S2). For example, a switch (not shown) is turned on so that the power supply voltage and the semiconductor integrated circuit 1 are connected.

  Next, it is determined whether or not the POR signal is turned on (step S4). Specifically, the POR circuit 22 sets the POR signal to “1” (ON) when it is determined that the power supply voltage is in a stable state.

  If it is determined in step S4 that the POR signal is ON (YES in step S4), the process proceeds to step S6. The state of step S4 is maintained until the POR signal is turned ON.

  Next, in step S6, the register is reset (step S5). Specifically, the BIST circuit 24 outputs a register reset signal RRS (“1”) to the N-bit register 67 in response to the input of the POR signal. The N-bit register 67 receives the register reset signal RRS and resets (initializes) the register value. Accordingly, register value <N−1: 0> is set to “0”. Further, the BIST circuit 24 outputs a register reset signal RRS “1” to the binary search execution circuit 60. Accordingly, the binary search execution circuit 60 starts a binary search.

  Next, the register value is set to “2 ^ N−1” (step S7A). The binary search control circuit 64 outputs an initial count value M and an initial count value setting signal and outputs them to the count value output circuit 62. The initial count value M is set to “2 ^ N−1” or “1”. As a result, the count value output circuit 62 sets “2 ^ N−1” or “1” as the initial count value. Then, the set count value is output to the N-bit addition / subtraction circuit 65. In this example, the symbol “^” indicates that it is a power.

  Then, when “2 ^ N−1” is set as the initial count value in the count value output circuit 62, the binary search control circuit 64 adds an N-bit addition / subtraction signal as an addition / subtraction control signal. Output to circuit 65. Accordingly, the N-bit addition / subtraction circuit 65 adds the initial value “0” and the initial count value “2 ^ N−1” of the N-bit register 67. Then, the binary search control circuit 64 outputs a data capture signal to the N-bit register 67 so as to capture the result. As a result, the register value of the N-bit register 67 is set to “2 ^ N−1”.

  Further, when the count value output circuit 62 is set to 1 as the initial count value, the binary search control circuit 64 outputs a signal instructing subtraction to the N-bit addition / subtraction circuit 65 as the addition / subtraction control signal. As a result, the N-bit addition / subtraction circuit 65 subtracts the initial count value 1 from the initial value “0” of the N-bit register 67. Then, the binary search control circuit 64 outputs a data capture signal to the N-bit register 67 so as to capture the result. As a result, the register value of the N-bit register 67 is set to “2 ^ N−1”.

  The binary search control circuit 64 outputs a test start signal to the BIST circuit 24.

  Next, a data writing process is executed on the SRAM module 10 (step S8). Specifically, as described above, the BIST circuit 24 that has received the input of the test start signal from the binary search control circuit 64 inputs write data DI, which is predetermined test data, to the SRAM module 10.

  Then, a standby mode test is executed (step S10). The standby mode test is to test whether or not the data written in the SRAM module 10 can be held in the standby mode (standby period). Specifically, the standby signal RS is set to “1”, and the source potential ARVSS is set to a potential set in the standby mode by the ARVSS potential adjusting circuit 18 according to the counter signal C. In this example, since the register values <0> to <N-1> are all set to “1”, as described above, the source potential ARVSS is set to a potential (for example, 0 V) that does not cause data destruction. .

  Next, a data read process is executed on the SRAM module 10 (step S12). Specifically, as described above, the BIST circuit 24 instructs the SRAM module 10 to read out the written test data. The SRAM module 10 outputs the read data DQ to the comparison circuit 26.

  Next, expected value determination processing is executed (step S14). Specifically, the comparison circuit 26 compares the read data DQ read from the SRAM module 10 with the expected value given from the BIST circuit 24, and whether the read data DQ and the expected value match. Determine whether. Then, the result is output to the compression circuit 28.

  The compression circuit 28 compresses the comparison result output from the comparison circuit 26 and outputs “0” (PASS in step S14) if all the data match. On the other hand, if even one piece of data does not match, “1” is output (FAIL in step S14).

  If even one piece of data does not match in step S14 (FAIL in step S14), the binary search control circuit 64 outputs error information to the BIST circuit 24 (step S20). In this case, that is, the source potential ARVSS is set to a potential (0 V) at which data destruction does not occur, and data destruction has occurred despite the fact that the operation margin is most secured. There may be an abnormality. Therefore, the peripheral circuit can execute predetermined error processing according to the error information. For example, it is possible to provide notification of maintenance or notification of parts replacement to the outside.

  Then, the processes of the BIST circuit 24 and the counter circuit 36 are finished (stopped) (step S68). Specifically, the process for adjusting the source potential ARVSS is terminated. Further, the counter circuit 36 is stopped. Then, the process ends (END).

  On the other hand, if all the data match in step S14 (PASS in step S14), the binary search control circuit 64 sets the count value of the count value output circuit 62 to 2 ^ (N-1) (step S14). S30). Specifically, the binary search control circuit 64 outputs a count value right shift signal to the count value output circuit 62. Further, the count value is incremented by one. Thereby, the count value of the count value output circuit 62 is set to 2 ^ (N-1). This process is a process of setting the count value to a value that is 1/2 (half) of 2 ^ N. This is a process for setting the counter value of the UP / DOWN counter circuit 36 to an intermediate value between the upper limit (max) and the lower limit (min) of the counter value based on the count value.

  Then, a process of subtracting the register value by the count value is executed (step S33). Specifically, the binary search control circuit 64 instructs the N-bit addition / subtraction circuit 65 to subtract the count value “2 ^ (N−1)” from the register value “2 ^ N−1”. The addition / subtraction control signal to be output is output. As a result, a subtraction process is executed in the N-bit addition / subtraction circuit 65, and a value of “2 ^ (N−1) −1” is set. Then, the binary search control circuit 64 outputs a data capture signal so as to capture data into the N-bit register 67. As a result, the register value of the N-bit register 67 is set to a value of “2 ^ (N−1) −1”. Then, the source potential ARVSS of the ARVSS potential adjusting circuit 18 is adjusted based on the register value.

  Then, the following loop processing is executed. In this example, the loop process is executed (N-1) times.

Specifically, first, an immediately preceding expected value determination process is executed (step S36).
Then, with respect to the immediately preceding expected value determination process, it is determined whether or not the read data DQ matches the expected value. If the expected values match (PASS in step S36), step S38 is skipped. Then, a standby mode test is executed (step S40). Specifically, the standby signal RS is set to “1”, and the source potential ARVSS is set to a potential set in the standby mode by the ARVSS potential adjusting circuit 18 according to the register value <N−1: 0>. .

  On the other hand, if the read data DQ and the expected value do not match with respect to the immediately preceding expected value determination process (NO in step S36), a data write process is executed on the SRAM module 10 (step S38). Specifically, as described above, the BIST circuit 24 that has received the input of the test start signal from the binary search control circuit 64 inputs write data DI, which is predetermined test data, to the SRAM module 10. Since the immediately preceding expected value determination process is inconsistent, there is a possibility that the data has been destroyed. Therefore, it is necessary to execute the data writing process again. Then, the standby mode test of step S40 is executed (step S40).

  Next, a data read process is executed on the SRAM module 10 (step S42). Specifically, as described above, the BIST circuit 24 instructs the SRAM module 10 to read out the written test data. The SRAM module 10 outputs the read data DQ to the comparison circuit 26.

  Next, the binary search control circuit 64 sets the count value of the count value output circuit 62 to the previous count value / 2 (step S44).

  Specifically, the binary search control circuit 64 outputs a count value right shift signal to the count value output circuit 62. As a result, the count value of the count value output circuit 62 is set to a half value.

  Next, expected value determination processing is executed (step S46). Specifically, the comparison circuit 26 compares the read data DQ read from the SRAM module 10 with the expected value given from the BIST circuit 24, and whether the read data DQ and the expected value match. Determine whether. Then, the result is output to the compression circuit 28. The compression circuit 28 compresses the comparison result output from the comparison circuit 26, and outputs “0” if all the data match (PASS in step S46). To do. On the other hand, if even one piece of data does not match (FAIL in step S46), “1” is output.

  If even one piece of data does not match in step S46 (FAIL in step S46), a process of adding the register value with the count value is executed (step S51). Specifically, the binary search control circuit 64 outputs an addition / subtraction control signal that instructs the N-bit addition / subtraction circuit 65 to add the count value to the register value. As a result, addition processing is executed in the N-bit addition / subtraction circuit 65. Then, the binary search control circuit 64 outputs a data capture signal to the N-bit register 67. As a result, the register value of the N-bit register 67 is set to the processing result of the N-bit addition / subtraction circuit 65. Then, the source potential ARVSS of the ARVSS potential adjusting circuit 18 is adjusted based on the register value. And it returns to step S34 by a loop process (step S52), and repeats said process. In this example, the loop process is repeated (N-1) times as described above.

  On the other hand, if all the data match in step S46 (PASS in step S46), a process of subtracting the register value by the count value is executed (step S47). Specifically, the binary search control circuit 64 outputs an addition / subtraction control signal that instructs the N-bit addition / subtraction circuit 65 to subtract the count value from the register value. As a result, the N-bit addition / subtraction circuit 65 executes a subtraction process. Then, the binary search control circuit 64 outputs a data capture signal to the N-bit register 67. As a result, the register value of the N-bit register 67 is set to the processing result of the N-bit addition / subtraction circuit 65. Then, the source potential ARVSS of the ARVSS potential adjusting circuit 18 is adjusted based on the register value. And it returns to step S34 by a loop process (step S52), and repeats said process. In this example, the loop process is repeated (N−1) times as described above.

  The count value of the count value output circuit 62 is set to “1” by repeating the loop processing (N−1) times.

  And after repeating the said process, a loop process is complete | finished and the last expected value determination process is performed (step S54). Then, with respect to the immediately preceding expected value determination process, it is determined whether or not the read data DQ matches the expected value. If the expected values match (PASS in step S54), step S56 is skipped. Then, a standby mode test is executed (step S58). Specifically, the standby signal RS is set to “1”, and the source potential ARVSS is set to a potential set in the standby mode by the ARVSS potential adjusting circuit 18 according to the register value <N−1: 0>. .

  If the read data DQ and the expected value do not match with respect to the immediately preceding expected value determination process (NO in step S54), a data write process is executed on the SRAM module 10 (step S56). Specifically, as described above, the BIST circuit 24 that has received the input of the test start signal from the binary search control circuit 64 inputs write data DI, which is predetermined test data, to the SRAM module 10. Since the immediately preceding expected value determination process is inconsistent, there is a possibility that the data is destroyed, so the data write process is executed again, and the next standby mode test is executed (step S58).

  Next, a data read process is executed on the SRAM module 10 (step S60). Specifically, as described above, the BIST circuit 24 instructs the SRAM module 10 to read out the written test data. The SRAM module 10 outputs the read data DQ to the comparison circuit 26.

  Then, an expected value determination process is executed (step S62). Then, regarding the expected value determination process, it is determined whether or not the read data DQ and the expected value match. If the expected values match (PASS in step S62), the process proceeds to step S69, where the processing of the BIST circuit 24 and the N-bit register 67 is terminated (stopped). Specifically, the process for adjusting the source potential ARVSS is terminated.

  On the other hand, if the expected values do not match (FAIL in step S62), the process proceeds to step S64, and 1 is added to the register value of the N-bit register 67. Specifically, the binary search control circuit 64 outputs an addition / subtraction control signal that instructs the N-bit addition / subtraction circuit 65 to add the count value (“1”) set in the count value output circuit 62. To do. As a result, addition processing is executed in the N-bit addition / subtraction circuit 65. Then, the binary search control circuit 64 outputs a data capture signal to the N-bit register 67. As a result, the register value of the N-bit register 67 is set to the processing result of the N-bit addition / subtraction circuit 65. Then, the source potential ARVSS of the ARVSS potential adjusting circuit 18 is adjusted based on the register value.

  In step S69, the processing of the BIST circuit 24 and the N-bit register 67 is terminated (stopped). Specifically, the process for adjusting the source potential ARVSS is terminated.

  The processing flow is basically the same as that of the fourth embodiment, and the specific example of FIG. 17 is the same as that in which the counter value of the UP / DOWN counter circuit 36 is replaced with the register value of the N-bit register 67. is there.

  Therefore, as described above, it is possible to set an appropriate source potential ARVSS by (N + 1) times of expected value determination processing according to the binary search method (binary search tree), which is efficient and early. The process can be completed.

  In the fourth embodiment, a case has been described in which clock pulses are used as the counter UP control signal and the counter DOWN control signal in order to increment or decrement the counter value of the UP / DOWN counter circuit. In this example, a register is used. Thus, since the same function as the UP / DOWN counter circuit is realized, it is not necessary to increment or decrement using the clock pulse, and the setting of the source potential ARVSS can be completed earlier and efficiently.

  In the fourth embodiment, the method of adjusting the counter signal or the register value by bit operation or the like in the binary search execution circuit has been described. However, the present invention is not limited to this method, and binary search (binary search tree) is performed in software. It may be executed by a program to set a counter signal or a register value.

(Embodiment 5)
In the above embodiment, the method of adjusting the source potential ARVSS to an appropriate value has been described. On the other hand, the present invention is not limited to the source potential and can be similarly applied to the case of adjusting other potentials.

FIG. 20 is a diagram illustrating a configuration of read assist circuit 200 according to the present embodiment.
Referring to FIG. 20A, the read assist circuit 200 is a circuit that adjusts the word line driving potential LCVDD for data reading (READ).

  Specifically, the read assist circuit 200 includes transistors 202, 204, 206, 208 and 210.

  Transistor 202 is provided between power supply potential VDDM and node Np, and has its gate receiving LCVDD control signal La. Transistor 210 is provided between nodes Np and Nq, and has a gate receiving power supply potential VDDM.

  Node Nq is provided between ground potential VSSM and its gate receives LCVDD control signal Lb.

  Transistors 206 and 208 are provided between node Np and ground potential VSSM, and their gates receive a decode signal. The connection node of transistors 206 and 208 is connected to word line WL.

  In this example, the transistors 202 and 206 are P-channel MOS transistors, and the transistors 204, 208, and 210 are N-channel MOS transistors.

  The LCVDD control signals La and Lb are complementary to each other. When the LCVDD control signal La is “1”, the LCVDD control signal Lb is “0”. When the LCVDD control signal La is “0”, the LCVDD control signal Lb is “1”. In the initial state, the LCVDD control signal La is set to “1” and the LCVDD control signal Lb is set to “0”. Therefore, the transistors 202 and 204 are in an off state.

  On the other hand, when driving the word line, the LCVDD control signal La is set to “0” and the LCVDD control signal Lb is set to “1”. Accordingly, the transistors 202 and 204 are turned on. In addition, the gate of the transistor 210 is turned on because it is connected to the power supply potential VDDM. Accordingly, a passing current passing through the transistor 210 flows. The transistor 210 is a transistor that adjusts the word line driving potential LCVDD to the initial potential. In the case of this example, it is assumed that the transistor size is set so that the word line drive potential LCVDD is a potential lower than the power supply potential VDDM by a predetermined potential. In response to the decode signal “0”, the word line WL is pulled up to the word line drive potential LCVDD. In the initial state, the decode signal is set to “1”. In response to the decode signal “1”, the transistor 208 is turned on. In the initial state, the word line WL is set to the ground potential VSSM (0 V). The decode signal is generated in the word line decoder 12 in accordance with an address signal for selecting a row of memory cells.

  Referring to FIG. 20B, here, a timing chart of activation of LCVDD control signals La and Lb and word line WL is shown.

It is assumed that the decode signal is “0”.
At time t10, the LCVDD control signal La is set to “1” and the LCVDD control signal Lb is set to “0”. Therefore, the transistors 202 and 204 are in an off state.

  Next, at time t11, the LCVDD control signal La is set to “0”, and the LCVDD control signal Lb is set to “1”. Therefore, the transistors 202 and 204 are on. As a result, the word line WL is activated and set to the word line drive potential LCVDD.

  At time t12, the LCVDD control signal La is set to “1” and the LCVDD control signal Lb is set to “0”. As a result, the transistors 202 and 204 are turned off. Then, the word line WL is deactivated and set to the ground potential VSSM (0 V).

  Referring again to FIG. 20A, in this example, in the read assist circuit 200, an adjustment transistor for adjusting the word line drive potential LCVDD to a plurality of potentials is provided. Specifically, transistors Trn1 to Trn3 are provided in parallel between node Np and node Nq, respectively. Each gate receives an LCVDD potential adjustment signal. Each time at least one of the transistors Trn1 to Trn3 is turned on in accordance with the LCVDD potential adjustment signal, the word line driving potential LCVDD is decreased by the potential corresponding to the passing current at the time of turning on. become.

  As described in the first embodiment, the counter signal C of the counter circuit 32 can be used as the LCVDD potential adjustment signal. As a result, as described in the first embodiment, it is possible to adjust the word line driving potential LCVDD for optimum data reading. The configuration of other embodiments can be similarly applied.

(Modification 1 of Embodiment 5)
FIG. 21 is a diagram illustrating a configuration of write assist circuit 220 according to the present embodiment.

  Referring to FIG. 21A, the write assist circuit 220 is a circuit that adjusts the power supply potential ARVDD for data writing (WRITE). In the above configuration, the configuration in which the power supply potential VDDM is supplied to the memory cell MC has been described. However, the power supply potential ARVDD may be supplied instead of the power supply potential VDDM in order to assist data writing. It is.

  Specifically, the write assist circuit 220 includes transistors 222, 224, 226, 228, and 230.

  Transistors 222 and 224 are provided between power supply potential VDD and node Nr, and their gates receive inputs of ARVDD control signals Wa and Wb, respectively. In addition, the power supply potential ARVDD is supplied from the connection node to the memory cell MC instead of the power supply potential VDDM. Note that the power supply potential VDD is higher than the power supply potential VDDM.

  Transistor 226 is provided between nodes Nr and Ns, and its gate receives input of ARVDD control signal Wb.

  Transistors 228 and 230 are connected in series between node Ns and ground potential VSSM, and the gate of transistor 228 is connected to node Nr. Further, the gate of the transistor 230 receives the input of the ARVDD control signal Wc.

  In this example, the transistors 222, 224, and 226 are P-channel MOS transistors, and the transistors 228 and 230 are N-channel MOS transistors.

  The ARVDD control signal Wa is a power switch for the memory cell MC, and is set to “0” during the SRAM operation period. In the initial state, the ARVDD control signal Wb is set to “1”, and the ARVDD control signal Wc is set to “0”. Therefore, the transistor 222 is in an on state, and the transistors 224, 226, and 230 are in an off state.

  On the other hand, when data is written to the memory cell MC, the ARVDD control signal Wb is set to “0” when the word line is driven. The ARVDD control signal Wc is set to “1”. Accordingly, the transistors 224, 226, and 230 are turned on.

  Further, the gate of the transistor 228 is turned on because it is connected to the node Nr. Accordingly, a passing current passing through the transistor 228 flows. The transistor 228 is a transistor that adjusts the potential ARVDD, which is the power supply potential of the memory cell, to an initial potential when data writing is executed. In the case of this example, it is assumed that the transistor size is set so that the power supply potential ARVDD is a potential lower than the power supply potential VDD by a predetermined potential.

  Referring to FIG. 21B, here, a timing chart of activation of ARVDD control signals Wa and Wb and word line WL is shown. In this example, it is assumed that the word line WL is activated at the time of data writing.

  At time t20, the ARVDD control signal Wb is set to “1”. The ARVDD control signal Wc is set to “0”.

Therefore, the transistors 224, 226, and 230 are in an off state.
Next, at time t21, the ARVDD control signal Wb is set to “0” and the ARVDD control signal Wc is set to “1”. Therefore, the transistors 224, 226, and 230 are in an on state. Further, the transistor 228 is turned on. As a result, a current path is formed between the supply line of the power supply potential ARVDD and the ground potential VSSM (0 V). Then, the word line WL is activated, and data writing to the memory cell MC is executed according to the set potential ARVDD.

  At time t22, the ARVDD control signal Wb is set to “1” and the ARVDD control signal Wc is set to “0”. As a result, the transistors 224, 226, and 230 are turned off. Further, the transistor 228 is turned off. Then, the word line WL is deactivated.

  Referring again to FIG. 21A, in this example, in the write assist circuit 220, an adjustment transistor for adjusting the power supply potential ARVDD to a plurality of potentials is provided. Specifically, the transistors Trp1 to Trp3 are provided in parallel between the node Nr and the node Ns, respectively. Each gate receives an input of the ARVDD potential adjustment signal. Each time at least one of the transistors Trp1 to Trp3 is turned on in accordance with the ARVDD potential adjustment signal, the power supply potential ARVDD is lowered by the potential corresponding to the passing current at the time of turning on. .

  As described in the first embodiment, the counter signal C of the counter circuit 32 can be used as the ARVDD potential adjustment signal. As a result, as described in Embodiment Mode 1, it is possible to adjust the power supply potential ARVDD for optimum data writing. The configuration of other embodiments can be similarly applied.

Note that the potential adjustment can be similarly applied to potentials of other peripheral circuits.
(Embodiment 6)
In the above embodiment, the case where the potential level is adjusted according to the control signal has been described. However, the present invention is not limited to the adjustment of the potential level, and the timing signal and the like can also be adjusted.

  FIG. 22 is a diagram illustrating a circuit for adjusting the timing for driving the word line according to the sixth embodiment.

  Referring to FIG. 22A, here, a word line active period adjusting circuit 240 for generating a word line active signal is shown.

  Word line active period adjustment circuit 240 includes AND circuits 244, 250, 254, delay circuits 242, 248, 252, and a selector 258.

  The AND circuit 244 receives the input of the word line activation control signal WCEN and the input of the word line activation period adjustment signal via the delay circuit 242, and outputs the AND logic operation result.

  The AND circuit 250 receives the output signal from the AND circuit 244 via the delay circuit 248 and the word line active period adjustment signal and outputs the AND logic operation result.

  The AND circuit 254 receives the output signal from the AND circuit 250 via the delay circuit 252 and the word line active period adjustment signal and outputs the AND logic operation result.

  Selector 258 receives word line activation control signal WCEN and the output signals of AND circuits 244, 250, and 254, and outputs one of the output signals in accordance with the word line activation period adjustment signal. Specifically, when the word line activation period adjustment signal is not input, the selector 258 outputs the word line activation control signal WCEN as it is without delay as the word line activation signal WLEN.

  The word line activation period adjustment signal is input to the corresponding AND circuit and delays the word line activation control signal WCEN. Specifically, when “1” is input to the AND circuit 244 as the word line activation adjustment signal, the word line activation control signal WCEN is replaced with the selector 258 by the word line activation control signal WCEN delayed by the delay through the delay circuit 242. Is output.

  When the word line activation control signal “1” is input to the AND circuits 244 and 250, the word line activation control signal WCEN is selected from the word line activation control signal WCEN delayed by the delay circuits 242 and 248. Is output to H.258.

  When the word line activation adjustment signal “1” is input to the AND circuits 244, 250, and 254, the word line activation control signal WCEN is delayed by the delay through the delay circuits 242, 248, and 252. Signal WCEN is output to selector 258.

  The selector 258 switches the output word line activation control signal WCEN and outputs it as the word line activation signal WLEN. Specifically, when the word line activation adjustment signal “1” is input only to the AND circuit 244, the output signal of the AND circuit 244 is output as the word line activation signal WLEN. When the word line activation adjustment signal “1” is input to the AND circuits 244 and 250, the output signal of the AND circuit 250 is output as the word line activation signal WLEN. When the word line activation adjustment signal “1” is input to the AND circuits 244, 250, and 254, the output signal of the AND circuit 254 is output as the word line activation signal WLEN.

  Referring to FIG. 22B, here, a configuration of a driver for driving the word line WL is shown.

  Specifically, the driver includes transistors 262 and 264 and a NAND circuit 260. Transistors 262 and 264 are provided between word line drive potential LCVDD and ground potential VSSM, and each gate receives an input of NAND circuit 260. Transistor 262 is a P-channel MOS transistor, and transistor 264 is an N-channel MOS transistor.

  NAND circuit 260 receives the decode signal and word line activation signal WLEN and outputs the NAND logic operation result. Specifically, when both the decode signal and the word line activation signal WLEN are “1”, the output signal of the NAND circuit 260 is set to “0” and the transistor 262 is turned on. As a result, the word line drive potential LCVDD is supplied to the word line WL. On the other hand, in other cases, the output signal of the NAND circuit 260 is set to “1” and the transistor 264 is turned on. Thereby, the word line WL is set to the ground potential VSSM.

  Referring to FIG. 22C, here, a timing chart of the word line activation control signal WCEN, the word line activation signal WLEN and the like related to the rise of the word line WL is shown.

  The case where the word line activation control signal WCEN is set to “1” at time t30 is shown.

Then, at time t31, the decode signal is set to “1”.
At time t32, the word line activation control signal WCEN is delayed and the word line activation signal WLEN is set to “1”. At the same time, the word line WL rises.

  As described in the first embodiment, the counter signal C of the counter circuit 32 can be used as the word line active period adjustment signal. As a result, the word line activation signal WLEN, which is a timing signal for starting up the word line, can be adjusted to an appropriate timing, and the word line WL can be pulled up at an appropriate timing. As a result, it is possible to suppress abnormalities in data writing or reading due to the timing being too early or too late. The configuration of other embodiments can be similarly applied.

(Modification of Embodiment 6)
FIG. 23 is a diagram illustrating a circuit for adjusting the timing for driving the sense amplifier according to the modification of the sixth embodiment.

  Referring to FIG. 23A, here, there is shown a sense amplifier activation timing adjustment circuit 270 that generates a sense amplifier activation signal that activates the sense amplifier.

  Sense amplifier activation timing adjustment circuit 270 includes delay circuits 272, 274, 276 and a selector 278. The delay circuits 272, 274, and 276 are assumed to have different delay times. The selector 278 switches the signal output from the delay circuit according to the sense amplifier activation timing adjustment signal and outputs it as the sense amplifier activation signal SEN.

  Referring to FIG. 23B, here, a timing chart for explaining the delay of the sense amplifier activation signal is shown.

The case where the sense amplifier activation control signal SCEN is set to “1” at time t40 is shown.
Then, at time t41, the sense amplifier activation signal SEN delayed by a predetermined period by the delay circuit is output.

  As described in the first embodiment, the counter signal C of the counter circuit 32 can be used as the sense amplifier activation timing adjustment signal. Thus, the sense amplifier activation signal SEN, which is a timing signal for starting up the sense amplifier, can be adjusted to an appropriate timing, and the sense amplifier can be activated at an appropriate timing. As a result, it is possible to suppress abnormalities or errors in data reading due to the timing being too early or too late. The configuration of other embodiments can be similarly applied.

<Layout layout>
FIG. 24 is a diagram for explaining the layout arrangement of various adjustment circuits.

  Referring to FIG. 24, it is possible to arrange the ARVSS potential adjusting circuit 18 between the memory array MA and the I / O circuit 16 as described above and arrange it in the vicinity of the memory cell.

  The write assist circuit 220 that adjusts the power supply potential ARVDD can also be arranged in the vicinity of the memory cell by arranging the ARVSS potential adjustment circuit 18 between the memory array MA and the I / O circuit 16.

  In this example, the control unit 14 provides the read assist circuit 200 to adjust the word line drive potential LCVDD.

  Further, the case where the control unit 14 also includes a word line active period adjusting circuit 240 and a sense amplifier active timing adjusting circuit 270 is shown. The I / O circuit 16 includes a sense amplifier.

  The configuration is not limited to potential adjustment, and timing adjustment can be performed by providing an adjustment circuit. In other words, it is possible to improve product defects caused by deterioration of in-chip element characteristics after the completion of the wafer process by adjusting and setting timing and potential in the SRAM.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

  DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit, 10 SRAM module, 11 Memory array group, 12 Word line decoder, 14 Control part, 18, 19 ARVSS electric potential adjustment circuit, 20 Peripheral circuit, 24 BIST circuit, 26 Comparison circuit, 28, 29 Compression circuit, 32 , 36 counter circuit, 50 temperature adjustment circuit, 52 potential adjustment unit, 60 binary search execution circuit, 62 count value output circuit, 64 binary search control circuit, 65-bit addition / subtraction circuit, 66 counter control signal output circuit, 67 N-bit register , 200 read assist circuit, 220 write assist circuit, 240 word line active period adjustment circuit, 270 sense amplifier activation timing adjustment circuit.

Claims (11)

A memory cell array in which static memory cells having a transfer transistor, a drive transistor, and a load transistor are disposed;
A source line potential adjusting circuit connected between a source line connected to a source of the driving transistor and a ground potential, and for adjusting a potential applied to the source line;
A source line for controlling the source line potential adjustment circuit to determine a potential between the ground potential and a power supply potential, which can hold data in the memory cell during a standby period. A potential control circuit,
The source line potential control circuit reads predetermined data written in a memory cell of the memory cell array after the standby period, and applies the data to the source line with respect to the source line potential adjustment circuit based on a read result A semiconductor memory device instructing to adjust a potential. A plurality of memory cell arrays are provided,
The semiconductor memory device according to claim 1, wherein the source line potential adjustment circuit and the source line potential control circuit are provided in common to source lines of the plurality of memory cell arrays. The source line potential adjustment circuit includes a plurality of adjustment transistors provided between the source line and the ground potential,
3. The semiconductor memory device according to claim 1, wherein the source line potential control circuit includes a counter circuit for turning on / off the plurality of adjustment transistors in stages based on the read result.   4. The semiconductor memory device according to claim 3, wherein the counter circuit turns on / off the plurality of adjustment transistors in stages according to a binary search method based on the read result.   The source line potential control circuit instructs the source line potential adjustment circuit to adjust a potential applied to the source line based on a change in data retention characteristics of the memory cell according to the read result and the aging deterioration. The semiconductor memory device according to claim 1. The source line potential control circuit includes:
Determining whether or not the source line potential adjustment circuit can adjust the potential applied to the source line based on the read result;
The semiconductor memory device according to claim 1, wherein an error is output to the outside when it is determined that adjustment is not possible. The source line potential control circuit includes:
Storing information instructing the source line potential adjustment circuit to adjust the potential applied to the source line based on the read result;
The next adjustment of the potential of the source line instructs the source line potential adjustment circuit to adjust the potential applied to the source line based on the stored information. A semiconductor memory device according to claim 1. A temperature detection circuit for detecting the temperature of the chip on which the memory cell array is mounted;
The source line potential control circuit instructs the source line potential adjustment circuit to adjust a potential applied to the source line based on the read result and the detection result of the temperature detection circuit. 7. The semiconductor memory device according to any one of 6.   9. The semiconductor device according to claim 8, wherein the source line potential control circuit instructs the source line potential adjustment circuit to readjust the potential applied to the source line based on a detection result of the temperature detection circuit. Storage device. A memory cell array in which static memory cells having a transfer transistor, a drive transistor, and a load transistor are disposed;
A word line potential adjustment circuit for adjusting a potential applied to a word line connected to the gate of the transfer transistor;
A word line for controlling the word line potential adjustment circuit to determine a potential between the power supply potential and the ground potential, which is a potential of the word line when data is written to or read from the memory cell. A potential control circuit,
The word line potential control circuit reads predetermined data written in a memory cell of the memory cell array, and adjusts a potential applied to the word line with respect to the word line potential adjustment circuit based on a read result. A semiconductor memory device. A memory cell array in which static memory cells having a transfer transistor, a drive transistor, and a load transistor are disposed;
An activation timing adjustment circuit for adjusting an activation timing of an internal circuit for driving the memory cell array;
An activation timing control circuit for controlling the activation timing adjustment circuit to determine the activation timing of the internal circuit when writing or reading data in the memory cell;
The activation timing control circuit reads predetermined data written in a memory cell of the memory cell array, and adjusts the activation timing of the internal circuit with respect to the activation timing adjustment circuit based on a read result. A semiconductor memory device.

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