JP2014154196A - Associative memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an associative memory such that similarity retrieval can be accurately performed even when Euclidean distances are used.SOLUTION: An associative memory 100 includes: distance arithmetic circuits DPto DPwhich calculate Manhattan distances between R (R: an integer equal to or larger than 2) reference data having a bit length of M×W (W: an integer equal to or larger than 1, W: an integer equal to or larger than 2) bits and retrieval data having a bit length of M×W bits; and distance/clock number conversion circuits DCto DC. The distance/clock number conversion circuits DCto DCuse the Manhattan distances calculated by the corresponding distance arithmetic circuits to detect the numbers of clocks matching Euclidean distances between the reference data and retrieval data. The distance/clock number conversion circuits output timing signals indicative of timings when the numbers of clocks matching the Euclidean distances of the reference data to the retrieval data.

Description

  The present invention relates to an associative memory.

  In recent years, applications that require pattern matching typified by character recognition and image recognition have attracted much attention. In particular, by realizing pattern matching on LSI (Large Scale Integrated Circuit), it will be applicable to high-functional applications such as artificial intelligence and mobile devices in the future, and the realization of this technology has received much attention. .

  In pattern matching, "complete match search process" that searches for a pattern that completely matches the search data from multiple reference data stored in the database, and "most similar search" that searches for the most similar pattern to the search data. Treatment ".

  The former is called CAM (Content Addressable Memory), and is used to realize the routing of the IP address table of the network router and the cache of the processor. In order for a computer to perform flexible search / comparison such as the human brain, it is indispensable to realize the latter most similar search process. A memory having a function for realizing such a flexible comparison is particularly referred to as an associative memory.

  As means for realizing an associative memory, (1) an implementation method using a digital method (Non-patent Document 1), (2) an implementation method using an analog method, and (3) a digital / analog fusion method (Non-Patent Document 2) have been proposed. Yes.

Y. Oike, et al., “A High-Speed and Low-Voltage Associative Co-Processor with Hamming Distance Ordering Using Word-Parallel and Hierarchical Search Architecture,” CICC, 2004. M. A. Abedin, et al., “Nearest-euclidean-distance search associative memory with fully parallel mixed digital-analog match circuitry,” Proc. Of SSDM2006, pp. 282-283, 2006. Y. Oike et al., “A Word-Parallel Digital Associative Engine with Wide SearchRange Based on Manhattan Distance,” CICC, 2004.

  The associative memory described in Non-Patent Document 1 performs a similarity search using a Hamming distance between search data and reference data. For this reason, in the associative memory described in Non-Patent Document 1, it is difficult to perform a similarity search using the Euclidean distance. Since the associative memory described in Non-Patent Document 2 converts the distance representing the similarity between the search data and the reference data into a voltage, an erroneous search is likely to occur.

  Therefore, the present invention has been made to solve such a problem, and an object of the present invention is to provide an associative memory capable of accurately performing a similarity search even when the Euclidean distance is used.

  The associative memory according to the embodiment of the present invention has R (R is an integer of 2 or more) reference data each having a bit length of M × W (M is an integer of 1 or more, W is an integer of 2 or more) bits. Reference data storage means for storing R × Rx, which is provided corresponding to the R pieces of reference data, and represents an absolute value of a difference between the search data having a bit length of M × W bits and the reference data The first distance calculation means for calculating W absolute value differences as the distance between the search data and the reference data, and the reference calculated using the distance calculated by the first distance calculation means for each reference data. Timing signal output process for performing timing signal output processing for outputting the timing signal indicating the timing at which the number of clocks matching the Euclidean distance between the data and the search data is detected for the R reference data And k timing signals (k is an integer satisfying 1 ≦ k <R) are detected in order from the earliest output of the timing signal based on the R timing signals output from the timing signal output means. And a match signal output means for outputting the detected k timing signals as a match signal indicating the similarity between the search data and the reference data.

  In the associative memory according to the embodiment of the present invention, the timing signal output means uses the absolute value difference between each reference data and the search data calculated by the first distance calculation means to search data for each reference data. A timing signal is output at the timing when the number of clocks matching the Euclidean distance is detected. That is, the timing signal output means converts the absolute value difference calculated for each reference data into a clock number corresponding to the Euclidean distance between the reference data and the search data, and outputs the timing signal at a timing at which the converted clock number is obtained. Output. As a result, the output timing of the timing signal of the reference data is determined according to the magnitude of the Euclidean distance between the reference data and the search data, and the search using the Euclidean distance can be appropriately performed for each reference data.

  Therefore, according to the embodiment of the present invention, a similarity search can be accurately performed even when the Euclidean distance is used.

It is a schematic block diagram which shows the structure of the content addressable memory which concerns on 1st Embodiment. FIG. 2A is a schematic diagram showing the configuration of the distance / clock number conversion circuit shown in FIG. FIG. 2B is a schematic diagram illustrating a configuration example of the counter coincidence detection circuit illustrated in FIG. 2A. FIG. 3 is a diagram for explaining the operation of the Winner detector shown in FIG. FIG. 4 is a schematic diagram showing a configuration of a distance / clock number conversion circuit in the second embodiment. FIG. 5A is a diagram illustrating search times in the first and second embodiments. FIG. 5B is a diagram illustrating a search time in the case of the third embodiment. FIG. 6 is a schematic block diagram showing the configuration of the associative memory according to the third embodiment. FIG. 7 is a schematic diagram showing a configuration example of the distance / clock number conversion circuit shown in FIG. FIG. 8 is a schematic diagram showing a configuration example of the counter coincidence detection circuit shown in FIG. FIG. 9A is a schematic diagram illustrating a configuration example of the counter and the coincidence detection circuit illustrated in FIG. FIG. 9B is a diagram illustrating an operation example of the counter illustrated in FIG. 9A. FIG. 10A is a diagram illustrating an operation example of the distance / clock number conversion circuit according to the third embodiment. FIG. 10B is a diagram illustrating an operation example of the counter in the example illustrated in FIG. 10A. FIG. 10C is a diagram illustrating an operation example of the counter in the example illustrated in FIG. 10A. FIG. 10D is a diagram illustrating an operation example of the counter in the example illustrated in FIG. 10A. FIG. 11 is a schematic diagram illustrating a circuit configuration example of a distance calculation circuit according to the fourth embodiment. FIG. 12 is a schematic diagram illustrating a circuit configuration example of the arithmetic circuit illustrated in FIG. FIG. 13 is a diagram for explaining the square calculation process in the fourth embodiment. FIG. 14 is a schematic diagram illustrating a configuration example of a counter coincidence detection circuit according to the fourth embodiment. FIG. 15 is a schematic diagram showing a configuration example of the distance / clock number conversion circuit in the modification example (1).

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
FIG. 1 is a schematic block diagram showing a configuration of an associative memory according to an embodiment of the present invention. Referring to FIG. 1, an associative memory 100 according to the first embodiment of the present invention includes a memory array unit 10 and a Winner detector 20.

  Memory array unit 10 includes a memory unit 1, a row decoder 2, a column decoder 3, a read / write circuit 4, and a search data storage circuit 5.

Memory unit 1, the reference data storage circuit _{(Storage Cell: SC) SC 11} ~SC 1W, SC 21 ~SC 2W, ···, and _SC R1 _{to SC RW,} the distance calculation circuit (absolute value difference calculation circuit) (Distance _Processor: including _{DP) DP 11 ~DP 1W, DP} 21 ~DP 2W, ···, and _DP R1 _{to DP RW,} and a distance / clock number conversion circuit _DC 1 to DC _R. Each of W and R is an integer of 2 or more.

Distance calculating circuit _DP 11 _{to DP 1W,} respectively provided corresponding to the reference data storage circuit _SC 11 _{to SC 1W.} The distance calculating circuit _DP 21 _{to DP 2W} are respectively provided corresponding to the reference data storage circuit _SC 21 _{to SC 2W.} In the same manner, the distance calculation circuit _DP R1 _{to DP RW} are respectively provided corresponding to the reference data storage circuit _SC R1 _{to SC RW.}

Distance / clock number converting circuit DC ₁ is provided corresponding to the distance calculation circuit _DP 11 _{to DP 1W.} Distance / clock number converting circuit DC ₂ is provided corresponding to the distance computing circuit _DP 21 _{to DP 2W.} In the same manner, the distance / clock number converting circuit DC _R are provided corresponding to the distance calculation circuit _DP R1 _{to DP RW.}

Reference data storage circuits SC _{11 to} SC _1W , SC _{21 to} SC _2W ,..., SC _{R1 to} SC _RW store reference data written by the row decoder 2, the column decoder 3, and the read / write circuit 4. . In this case, the reference data storage circuits SC _{11 to} SC _1W store M × W (M is an integer of 1 or more) bits of reference data 1, and the reference data storage circuits SC _{21 to} SC _2W have M × W bits. The reference data 2 is stored, and the reference data storage circuits SC _{R1 to} SC _RW store the M × W bit reference data R in the same manner. That is, the reference data storage circuit _{SC 11 ~SC 1W, SC 21 ~SC} 2W, ···, each _SC R1 _{to SC RW} stores M-bit reference data.

The distance calculation circuits DP _{11 to} DP _1W include M × W bit reference data 1 stored in the reference data storage circuits SC _{11 to} SC _1W , M × W bit search data stored in the search data storage circuit 5, and Is calculated by a method described later. The distance calculation circuits DP _{21 to} DP _2W search for the M × W bit reference data 2 stored in the reference data storage circuits SC _{21 to} SC _2W and the M × W bit search stored in the search data storage circuit 5. The distance from the data is calculated by the method described later. In the same manner, the distance calculation circuits DP _{R1 to} DP _RW perform the M × W bit reference data R stored in the reference data storage circuits SC _{R1 to} SC _RW and the M × W stored in the search data storage circuit 5. The distance from the W-bit search data is calculated by a method described later. The distance calculation circuits DP _{11 to} DP _1W , the distance calculation circuits DP _{21 to} DP _2W ,..., And the distance calculation circuits DP _{R1 to} DP _RW calculate the distance between the reference data and the search data in parallel. .

The distance calculation circuits DP _{11 to} DP _1W output the distance between the reference data 1 and the search data to the distance / clock number conversion circuit DC ₁ as an M × W bit distance signal. The distance calculation circuits DP _{21 to} DP _2W output the distance between the reference data 2 and the search data to the distance / clock number conversion circuit DC ₂ as an M × W bit distance signal. Similarly, the distance calculation circuits DP _{R1 to} DP _RW output the distance between the reference data R and the search data to the distance / clock number conversion circuit DC _R as an M × W bit distance signal.

Each of the distance calculation circuits DP _{11 to} DP _1W calculates the distance between the reference data 1 and the search data using the following equation.

In Expression (1), D _rj (r = 1 to R, j = 1 to W) represents a distance (absolute value difference) between the reference data and the search data. n _Mr indicates the Manhattan distance between the reference data and the search data. In Expression (1), In _j is search data, and Re _rj is reference data. Each of the data In _j and Re _rj consists of M bits.

In this way, the distance calculation circuits DP _{11 to} DP _1W calculate the distance between the M × W bit reference data 1 and the M × W bit search data by M bits, and each has a bit length of M bits. The W distance signals D _1j are output to the distance / clock number conversion circuit DC ₁ .

Similarly, the distance calculation circuits DP _{21 to} DP _2W ,... And the distance calculation circuits DP _{R1 to} DP _RW respectively calculate the distance between the reference data 2 to R and the search data using the equation (1). . The distance calculation circuits DP _{21 to} DP _2W ,... And the distance calculation circuits DP _{R1 to} DP _RW also receive W distance signals D _{2j to} DR _Rj each having a bit length of M bits. and outputs it to the converter _DC 2 _{~DC R.}

Distance / clock number converting circuit DC ₁ receives a W number of distance signal _{D 1j} from the distance calculation circuit _DP 11 _{to DP 1W,} the clock number CN_total1 of the clock signal CLK corresponding to the sum of the square of the distance signal _{D 1j} It counts by the method mentioned later. Then, a timing signal C ₁ indicating the timing at which the clock number CN_total 1 is counted is output to the Winner detector 20.

Distance / clock number converting circuit DC _2, the distance calculation circuit _DP 21 receives the W-number of distance signal _{D 2j} from _{to DP 2W,} the clock number CN_total2 of the clock signal CLK corresponding to the sum of the square of the distance signal _{D 2j} It counts by the method mentioned later. Then, the timing signal C ₂ indicating the timing when the clock number CN_total 2 is counted is output to the Winner detector 20.

In the same manner, the distance / clock number converting circuit DC _R, the distance calculation circuit _DP R1 _{to DP RW} received a W number of distance signal _{D Rj} from the matching clock signals to the sum of the square of the distance signal _{D Rj} The clock number CN_totalR of CLK is counted by a method described later. Then, a timing signal _{C R} indicating the timing of counting the number of clocks CN_totalR to Winner detector 20.

The row decoder 2 designates an address in the row direction of the memory unit 1. The column decoder 3 designates an address in the column direction of the memory unit 1. Read / write circuit 4 writes reference data to reference data storage circuits SC _{11 to} SC _1W , SC _{21 to} SC _2W ,..., SC _{R1 to} SC _RW designated by row decoder 2 and column decoder 3. The search data is written into the search data storage circuit 5.

  The search data storage circuit 5 stores the search data (M × W bit data) written by the read / write circuit 4.

Winner detector 20 receives a timing signal _C 1 -C _R from the distance / clock number converting each circuit _DC 1 to DC _R. Then, among the received timing signal C ₁ -C _R, k matches timing in chronological order (k is an integer satisfying a 1 ≦ k <R) detects the number of timing signals, a k-number of timing signal detection Output as match signals M _{1 to} M _k indicating the similarity between the search data and the reference data.

Figure 2A is a schematic block diagram showing the configuration of a distance / clock number converting circuit DC ₁ shown in FIG. Also each of the distance / clock number conversion circuits DC 2 _~ Distance / clock number conversion circuit DC _R shown in FIG. 1, has the same configuration as the distance / clock number conversion circuit DC ₁ shown in Figure 2A. As shown in FIG. 2A, the distance / clock number converting circuit DC ₁ includes a buffer 21～2W, a counter coincidence detection circuit 31～3W.

  The buffer 21 receives a search start signal SB from a control circuit (not shown) of the associative memory 100 and receives a clock signal CLK from a clock generation circuit (not shown) built in the associative memory 100. Then, when the search start signal SB is switched from the L (Low) level to the H (High) level, the buffer 21 outputs the received clock signal CLK to the buffer 22 and the counter match detection circuit 31. When the buffer 22 receives the clock signal CLK from the buffer 21 and receives an H level coincidence signal (DETECT1) to be described later from the counter coincidence detection circuit 31, the buffer 22 receives the clock signal CLK from the buffer 23 (not shown) and the counter coincidence detection circuit. To 32. Similarly, the buffer 2W receives the clock signal CLK from the buffer 2W-1 (not shown), and receives an H level coincidence signal (DETECTW-) described later from the counter coincidence detection circuit 3W-1 (not shown). 1), the clock signal CLK is output to the counter coincidence detection circuit 3W.

Counter coincidence detection circuits 31 to 3W are provided corresponding to distance calculation circuits DP _{11 to} DP _1W , respectively. The counter match detection circuits 31 to 3W are connected in series. Here, a schematic configuration of the counter coincidence detection circuits 31 to 3W will be described.

Figure 2B is a diagram showing a configuration example of the counter match detection circuit 31~3W at a distance / clock number conversion circuit DC _1. In the example of FIG. 2B, the case of W = 2 is shown. The counter coincidence detection circuit 31 includes a clock number conversion circuit 31a, a counter 31b, and a coincidence detection circuit 31c. The counter coincidence detection circuit 32 includes a clock number conversion circuit 32a, a counter 32b, and a coincidence detection circuit 32c. Hereinafter, the function of each component will be described.

The clock number conversion circuit 31 a receives the distance signal D ₁₁ having a bit length of M bits from the distance calculation circuit DP ₁₁ and the clock signal CLK from the buffer 21. Clock number conversion circuit 31a counts the number of clocks of the clock signal CLK, the distance signal timing of detecting the number of clocks to match the D ₁₁ is the distance indicated, outputs an H-level coincidence detection signal to the counter 31b in the counter 31b Process. The clock number conversion circuit 31a repeats this process until an H level coincidence signal (DETECT1) is output from the coincidence detection circuit 31c described later, and stops operating when the H level coincidence signal (DETECT1) is output. To do.

  The counter 31b counts up the counter value every time the coincidence detection signal from the clock number conversion circuit 31a rises, and outputs the counter value to the coincidence detection circuit 31c.

Coincidence detection circuit 31c receives the counter value from the counter 31b, receives the distance signal _{D 11} having a bit length of M bits from the distance computing circuit _{DP 11.} Coincidence detection circuit 31c compares the distance and counter value distance signal D ₁₁ indicates, when the distance signal D ₁₁ is the distance the counter value indicating the match, the number of clocks converts H level coincidence signal (DETECT1) Output to the circuit 31 a and the buffer 22. Coincidence detection circuit 31c includes distance and counter value distance signal _{D 11} indicates and is when they do not match, outputs L-level coincidence signal (DETECT1) to the clock number conversion circuit 31a and the buffer 22.

The clock number conversion circuit 32 a is driven when it receives the clock signal CLK from the buffer 22. Clock number conversion circuit 32a receives the distance signal _{D 12} having a bit length of M bits from the distance calculation circuit _{DP 12.} As with the clock number conversion circuit 31a, the clock number conversion circuit 32a counts the number of clocks of the clock signal CLK, the clock number that matches the distance the distance signal D ₁₂ indicates the timing of detecting the coincidence of the H-level counter 32b Processing to output a detection signal is performed. The clock number conversion circuit 32a repeats this process until an H level coincidence signal (DETECT2) is output from the coincidence detection circuit 32c described later. The clock number conversion circuit 32a stops its operation when the H level coincidence signal (DETECT2) is output.

  The counter 32b counts up the counter value every time the coincidence detection signal from the clock number conversion circuit 32a rises, and outputs the counter value to the coincidence detection circuit 32c.

Coincidence detection circuit 32c receives the counter value from the counter 32b, receives the distance signal _{D 12} having a bit length of M bits from the distance calculation circuit _{DP 12.} Coincidence detection circuit 32c compares the distance and counter value distance signal D ₁₂ indicates, when the distance signal the distance and counter value D ₁₂ indicates a match, the number of clocks converts H level coincidence signal (DETECT2) and outputs to the circuit 32a, and outputs it to the Winner detector 20 H level coincidence signal (DETECT2) as a timing signal _{C 1.} Moreover, the coincidence detection circuit 32c, when the distance and counter value distance signal _{D 12} indicates a match, and outputs L-level coincidence signal (DETECT2) to the clock number conversion circuit 32a.

Here, for example, the distance calculation circuit DP ₁₁ distance signal D ₁₁ of M bits indicating the distance "2" from is output, the distance calculation circuit DP ₁₂ distance signal D ₁₂ of M bits indicating the distance "3" from is output An example of the operation in the case of failure will be described.

The clock number conversion circuit 31 a receives the M-bit distance signal D ₁₁ indicating the distance “2”, and counts the number of clocks matching the distance “2” in synchronization with the clock of the clock signal CLK from the buffer 21. When the counted number of clocks matches the distance, the clock number conversion circuit 31a outputs an H level coincidence detection signal. When the coincidence detection signal rises, the counter 31b counts up the counter value and outputs a counter value indicating “1” to the coincidence detection circuit 31c. At this time, since the distance signal _{D 11} indicates the distance "2" and the counter value "1" does not coincide, the coincidence detection circuit 31c from the L-level coincidence signal (DETECT1) is output.

When the output coincidence detection signal becomes L level, the clock number conversion circuit 31a resets the counted clock number. Then, the clock number conversion circuit 31a again counts the clock number of the clock signal CLK, and when the counted clock number coincides with the distance “2”, it outputs an H level coincidence detection signal to the counter 31b. When the coincidence detection signal rises, the counter 31b counts up the counter value and outputs a counter value indicating “2” to the coincidence detection circuit 31c. Coincidence detecting circuit 31c, since the distance signal _{D 11} indicates the distance "2" and the counter value and "2" coincide, outputs a coincidence signal (DETECT1) to the buffer 22 and the clock number conversion circuit 31a. That is, an H level coincidence signal (DETECT1) is output at the timing when the number of clocks from the start of search becomes “4”. Then, the clock number conversion circuit 31a stops its operation in response to the H level coincidence signal (DETECT1).

The buffer 22 receives the H level coincidence signal (DETECT1) from the coincidence detection circuit 31c, and outputs the clock signal CLK to the clock number conversion circuit 32a. The clock number conversion circuit 32 a counts the clock number of the clock signal CLK in synchronization with the clock signal CLK from the buffer 22. Clock number conversion circuit 32a, the distance receives the distance signal D ₁₂ of M bits indicating "3", at the timing when the number of clock count matches the distance "3", and outputs the H-level coincidence detection signal to a counter 32b . When the coincidence detection signal from the clock number conversion circuit 32a rises, the counter 32b counts up the counter value and outputs a counter value indicating “1” to the coincidence detection circuit 32c. At this time, since the distance “3” and the counter value “1” do not match, the match detection circuit 32c outputs an L level match signal (DETECT2).

  When the output coincidence detection signal becomes L level, the clock number conversion circuit 32a resets the counted clock number. Then, the clock number conversion circuit 32a again counts the clock number of the clock signal CLK. When the counted clock number coincides with the distance “3”, it outputs an H level coincidence detection signal to the counter 32b. When the coincidence detection signal from the clock number conversion circuit 32a rises, the counter 32b counts up the counter value and outputs a counter value indicating “2” to the coincidence detection circuit 32c. At this time, since the distance “3” and the counter value “2” do not match, the match detection circuit 32c outputs an L level match signal (DETECT2).

When the coincidence detection signal becomes L level, the clock number conversion circuit 32a resets the counted clock number again and counts the clock signal CLK. When the counted clock number coincides with the distance “3”, the clock number conversion circuit 32a sets the counter 32b to H level. The coincidence detection signal is output. Then, the clock number conversion circuit 32a stops its operation in response to the H level coincidence signal (DETECT2). When the coincidence detection signal from the clock number conversion circuit 32a rises, the counter 32b counts up the counter value and outputs a counter value indicating “3” to the coincidence detection circuit 32c. Since the distance “3” and the counter value “3” match, the coincidence detection circuit 32 c outputs an H-level coincidence signal (DETECT2) to the clock number conversion circuit 32 a and also uses the Winner detector 20 as the timing signal C _1. Output to. In other words, the number of clocks counted in the clock number conversion circuit 32a is "9 (= 3 + 3 + 3)", the timing signal C ₁ at the timing of the clock number from the search start "13 (= 4 + 9)" is output.

  The number of clocks CN_total1 “13” counted by the counter match detection circuits 31 and 32 as a whole is the number of clocks “4 (= 2 + 2)” counted by the counter match detection circuit 31 and the number of clocks counted by the counter match detection circuit 32 “ 9 (= 3 + 3 + 3) ”. That is, it corresponds to counting the number of clocks that match the sum of the square value of the distance “2” and the square value of the distance “3” by the counter coincidence detection circuits 31 and 32.

Distance / clock number converting circuit DC ₁ is generally subjected to W-number of distance signals _D 11 _{to D 1W.} Each of the _W distance signals D _{11 to} D _1W has a bit length of M bits. Therefore, the distance / clock number converting circuit DC ₁ receives the distance signal _D 11 _D 12 ··· _{D 1W} having a bit length of M × W bits. In the counter coincidence detection circuit 31, only the number of times the distance signal D ₁₁ is equal to the distance indicated, repeatedly counting the number of clocks that matches the distance. The counter coincidence detection circuit 32~3W respectively, after receiving the coincidence signal from the counter coincidence detecting circuit 31~3W-1, the number of clocks respectively coincide with the distance signal _D 12 _{to D 1W,} matches the distance Count repeatedly. As a result, the distance / clock number conversion circuit overall number of clocks CN_total1 counted in DC ₁ is equal to the number of clocks sum of which is counted in each of the counter match detection circuit 31～3W. Clock number counted in each of the counter match detection circuit 31~3W respectively, to correspond to the square of the distance indicated by the distance signal D ₁₁ to D _1W, counted in the distance / clock number conversion circuit DC ₁ The total clock number CN_totalR represents the sum of the square values of the distance signals D _{11 to} D _1W .

Here, the Euclidean distance n _E is expressed by the following equation.

| In _j −R _erj | ^{2 on} the right side of Expression (2) matches the square value of the distance between the search data and the reference data in | In _j −R _erj | on the right side of Expression (1). Accordingly, as described above, the calculation of the Euclidean distance n _Er is performed by repeatedly performing the process of counting the number of clocks matching the distance for each of the W distances calculated by the equation (1) as many times as the distance matches. Realized. Then, in the example of FIG. 2B, the counter coincidence detection circuit 32 outputs the timing signal C ₁ indicating the timing of the number of clocks counted by the counter coincidence detection circuits 31 and 32 as a whole to the search data by the Euclidean distance n _Er . This corresponds to searching for similar reference data and outputting a Winner signal indicating that reference data similar to the search data has been detected. Incidentally, each of the distance / clock number conversion circuit _DC 2 to DC _R also, by operating the same operation of the distance / clock number converting circuit DC _1, respectively, and outputs a timing signal _C 2 -C _R.

Next, the operation of the Winner detector 20 will be described. FIG. 3 is a diagram for explaining the operation of the Winner detector 20 shown in FIG. Distance / clock number converting circuit _DC 1 to DC _R, as shown in FIG. 3, and outputs for example a timing signal _C 1 -C _R respectively in synchronization with the clock signal CLK to the Winner detector 20.

Winner detector 20 receives a timing signal _C 1 -C _R, detects the rising timing _t 1 ~t _R of the received timing signal _C 1 -C _R. Then, the Winner detector 20 detects the k timing signals C ′ _{1 to} C ′ _k in order from the earliest rise timing t _{1 to} t _R. The Winner detector 20 outputs timing signals C ′ _{1 to} C ′ _k as match signals M _{1 to} M _k .

For example, when detecting a match signal _M 1, _{M 2} of two (k = 2), Winner detector 20, of the timing signal _C 1 -C _R, two timing signals _{C 1} to rising timing ascending order , C ₃ are detected, and the detected timing signals C ₁ , C ₃ are output as match signals M ₁ , M ₂ . Similarly, when detecting _k timing signals C ′ _{1 to} C ′ _k other than k = 2, the Winner detector 20 similarly detects k timing signals C ′ _{1 to} C ′ _k, and The detected k timing signals C ′ _{1 to} C ′ _k are output as match signals M _{1 to} M _k .

If a k = 1, Winner detector 20 outputs a timing signal corresponding to the reference data most similar to the search data (either of the timing signal _C 1 -C _R) as a match signal _{M 1.} When k ≠ 1, the Winner detector 20 outputs k timing signals C ′ _{1 to} C ′ _k corresponding to k reference data similar to the search data as match signals M _{1 to} M _k. To do. In this case, in the k timing signals C ′ _{1 to} C ′ _k , the k rising timings differ from each other by at least one cycle of the clock signal CLK. _'1 -C' _k is detected accurately. That is, the associative memory 100 can accurately detect k reference data similar to the search data.

Operation of the distance / clock number converting circuit _DC 1 to DC _R is executed in synchronization with the clock signal CLK. Therefore, the operation of the associative memory 100 may be speeded up by increasing the frequency of the clock signal CLK. In the present embodiment, the clock number conversion circuits 31a and 32a stop operating when the coincidence signals (DETECT1 and DETECT2) are output. Therefore, in the distance / clock number conversion circuit DC _i , power consumption can be reduced as compared with the case where the clock number conversion circuits DC _{i1 to} DC _iR are operated until all the distances match.

Second Embodiment
In the present embodiment, an example in which a search using the Euclidean distance is performed using a configuration different from the distance / clock number conversion circuit described in the first embodiment will be described.

Figure 4 is a schematic configuration diagram showing a configuration example of a distance / clock number converting circuit DC ₁ in this embodiment. In FIG. 4, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment. In the example of FIG. 4 shows a configuration example of a distance / clock number converting circuit DC ₁ in the case of W = 2. The distance / clock number conversion circuits DC _{2 to} DC _R have the same configuration.

As shown in FIG. 4, the distance / clock number conversion circuit DC ₁ includes a buffer 23, distance / clock number conversion units 310 and 320, and a counter match detection unit 300.

  The buffer 23 receives a search start signal SB from a control circuit (not shown) of the associative memory 100 and receives a clock signal CLK from a clock generation circuit (not shown) built in the associative memory 100. Then, when the search start signal SB is switched from the L level to the H level, the buffer 23 outputs the received clock signal CLK to the distance / clock number conversion units 310 and 320.

The distance / clock number conversion units 310 and 320 are provided corresponding to the distance calculation circuits DP ₁₁ and DP ₁₂ , respectively. The distance / clock number conversion unit 310 includes a clock number conversion circuit 31a, a demultiplexer 31d, an OR circuit 31e, and a coincidence detection circuit 31c ′. The distance / clock number conversion unit 320 includes a clock number conversion circuit 32a, a demultiplexer 32d, an OR circuit 32e, and a coincidence detection circuit 32c ′. The counter coincidence detection unit 300 includes a demultiplexer 300a, a counter 300b, and an AND circuit 300c.

  The demultiplexer 31d receives an enable signal (EN) from a control circuit (not shown) of the associative memory 100, and receives a coincidence signal (DETECT1) from a coincidence detection circuit 31c 'described later. Upon receiving the L level coincidence signal (DETECT1), the demultiplexer 31d outputs an H level (= 1) EN signal to the clock number conversion circuit 31a, and an L level (= 0) EN signal to the OR circuit 31e. Output. When the demultiplexer 31d receives the H level coincidence signal (DETECT1), it outputs an L level EN signal to the clock number conversion circuit 31a, and outputs an H level EN signal to the OR circuit 31e.

The clock number conversion circuit 31 a receives the M-bit distance signal D ₁₁ from the distance calculation circuit DP ₁₁ and receives the clock signal CLK from the buffer 23. Clock number conversion circuit 31a receives the H-level EN signal from the demultiplexer 31d, it counts the number of clocks of the clock signal CLK, and detects a match between the counted number of clocks and the distance signal D ₁₁ is the distance indicated. Clock number conversion circuit 31a at a timing and distance indicated number of clocks and the distance signal D ₁₁ obtained by counting matches, outputs the H level coincidence detection signal indicating "1" to the OR circuit 31e. The clock number conversion circuit 31a receives a signal output from a demultiplexer 300a described later, and resets the clock number counted at the timing of receiving the signal. When receiving the L level EN signal from the demultiplexer 31d, the clock number conversion circuit 31a outputs an L level coincidence detection signal indicating "0" to the OR circuit 31e.

  The OR circuit 31e receives the coincidence detection signal (1 or 0) from the clock number conversion circuit 31a and the EN signal (1 or 0) from the demultiplexer 31d, and calculates the logical sum of the coincidence detection signal and the EN signal. Then, the drive signal composed of the calculation result is output to the demultiplexer 32d in the distance / clock number conversion circuit 320.

  The demultiplexer 32d receives a drive signal from the OR circuit 31e and a coincidence signal (DETECT2) from a coincidence detection circuit 32c 'described later. When the coincidence detection signal (DETECT2) is at the L level, the demultiplexer 32d outputs the drive signal from the OR circuit 31e to the clock number conversion circuit 32a, and an inverted signal obtained by inverting the drive signal from the OR circuit 31e. To 32e. When the coincidence signal (DETECT2) is at the H level, an inverted signal obtained by inverting the drive signal from the OR circuit 31e is output to the clock number conversion circuit 32a, and the drive signal from the OR circuit 31e is output to the OR circuit 32e. Output.

The clock number conversion circuit 32 a receives the M-bit distance signal D ₁₂ from the distance calculation circuit DP ₁₂ and receives the clock signal CLK from the buffer 23. Clock number conversion circuit 32a receives a drive signal indicating "1" from the demultiplexer 32d, it counts the number of clocks of the clock signal CLK, and detects a match between the counted number of clocks and the distance signal D ₁₂ is the distance indicated . Clock number conversion circuit 32a at a timing and distance clock speed and distance signals D ₁₂ counted indicates matches, it outputs the coincidence detection signal indicating "1" to the OR circuit 32e. The clock number conversion circuit 32a receives a signal output from a demultiplexer 300d described later, and resets the clock number counted at the timing of receiving the signal. When receiving the drive signal indicating “0” from the demultiplexer 32d, the clock number conversion circuit 32a outputs the drive signal indicating “0” to the OR circuit 32e.

  The OR circuit 32e receives the coincidence detection signal (1 or 0) from the clock number conversion circuit 32a and the drive signal (1 or 0) from the demultiplexer 32d, calculates the logical sum of the two received signals, A signal indicating the calculation result is output to the demultiplexer 300a in the counter coincidence detection unit 300.

The demultiplexer 300a receives a signal from the OR circuit 32e, and receives a Search-End signal indicating whether or not the search is completed from an AND circuit 300c described later. When the Search-End signal is at the L level, the demultiplexer 300a outputs the signal from the OR circuit 32e to the counter 300b and the clock number conversion circuits 31a and 32a, and the Search-End signal is switched from the L level to the H level. When, and outputs it to the Winner detector 20 a signal from the OR circuit 32e as a timing signal _{C 1.}

  Each time the counter 300b receives a signal from the demultiplexer 300a, the counter 300b increments the counter value by one, and outputs the counted up M-bit counter value to the coincidence detection circuits 31c 'and 32c'. The counter value “0” is set as the initial value of the counter 300b.

Coincidence detection circuit 31c 'receives a counter value of M bits from the counter 300b, receives the distance signals _{D 11} from the distance computing circuit _{DP 11.} Coincidence detection circuit 31c 'detects a match between the distance indicated counter value and the distance signal D ₁₁ is. When the counter value ≧ distance is satisfied, the coincidence detection circuit 31c ′ outputs an H level coincidence signal (DETECT1) to the demultiplexer 31d and the AND circuit 300c. If the counter value does not match the distance, that is, if the counter value <distance is satisfied, an L level match signal (DETECT1) is output to the demultiplexer 31d and the AND circuit 300c.

Coincidence detection circuit 32c 'receives a counter value of M bits from the counter 300b, receives the distance signals _{D 12} from the distance computing circuit _{DP 12.} Coincidence detection circuit 32c 'detects a match between the distance indicated by the counter value and the distance signal D _12. When the counter value and the distance satisfy the counter value ≧ distance, the coincidence detection circuit 32c ′ outputs an H level coincidence signal (DETECT2) to the demultiplexer 32d and the AND circuit 300c. If the counter value does not match the distance, that is, if the counter value <distance is satisfied, an L level match signal (DETECT2) is output to the demultiplexer 32d and the AND circuit 300c.

  The AND circuit 300c calculates a logical product of the match signal (DETECT1) from the match detection circuit 31c ′ and the match signal (DETECT2) from the match detection circuit 32c ′, and outputs a Search-End signal indicating the calculation result. Output to the multiplexer 300a. That is, in the case of the H level coincidence signal (DETECT1, DETECT2), the Search-End signal indicating “1” is output to the demultiplexer 300a, and the search is terminated. If at least one of the coincidence signals is at the L level, a Search-End signal indicating “0” is output to the demultiplexer 300a, and the search is continued.

Here, for example, the distance calculation circuit DP ₁₁ distance signal D ₁₁ of M bits indicating the distance "2" from is output, the distance calculation circuit DP ₁₂ distance signal D ₁₂ of M bits indicating the distance "3" from is output An example of the operation in the case of failure will be described.

When the EN signal is input, since the coincidence signal (DETECT1) has not risen, the demultiplexer 31d outputs an H level EN signal to the clock number conversion circuit 31a, and outputs an L level EN signal to the OR circuit 31e. To do. Clock number conversion circuit 31a is de receives the H-level EN signal from the multiplexer 31d, counts the number of clocks of the clock signal CLK from the buffer 23, the distance signal from the clock speed and distance calculating circuit _{DP 11} counted _{D 11} A coincidence detection signal (= 1) is output at a timing coincident with the distance “2” indicated by.

The OR circuit 31e demultiplexes the drive signal (= 1) that is the logical OR operation result of the coincidence detection signal (= 1) from the clock number conversion circuit 31a and the EN signal (= 0) from the demultiplexer 31d. Output to. When receiving the drive signal (= 1) from the OR circuit 31e, the demultiplexer 32d outputs the drive signal (= 1) to the clock number conversion circuit 32a because the coincidence signal (DETECT2) has not risen, and the drive signal The inverted signal (= 0) is output to the OR circuit 32e. Clock number conversion circuit 32a, when the demultiplexer 32d receives a drive signal (= 1), counts the number of clocks of the clock signal CLK from the buffer 23, and the number of clocks counted, distance signal from the distance computing circuit DP ₁₂ A coincidence detection signal (= 1) is output at the timing when the distance “3” indicated by D ₁₂ coincides.

  The OR circuit 32e receives a signal (= 1) representing a logical OR operation result of the coincidence detection signal (= 1) from the clock number conversion circuit 32a and the inverted signal (= 0) from the demultiplexer 32d. Output to. The demultiplexer 300a outputs the signal (= 1) from the OR circuit 32e to the counter 300b and the clock number conversion circuits 31a and 32a. When receiving the signal (= 1) from the demultiplexer 300a, the clock number conversion circuit 31a and the clock number conversion circuit 32a respectively reset the counted clock numbers. Upon receiving the signal (= 1) from the demultiplexer 300a, the counter 300b counts up the counter value and outputs the counter value “1” to the coincidence detection circuits 31c ′ and 32c ′. Note that the total number of clocks of the clock signal CLK when the counter value “1” is obtained from the start of the search is 5 (= 2 + 3).

Coincidence detection circuit 31c 'has a distance "2" distance signal _{D 11} indicates from the distance calculation circuit _{DP 11,} since the counter value from the counter 300b and "1" does not match (distance> counter value), the L level A coincidence signal (DETECT1) is output. Moreover, the coincidence detection circuit 32c ', the distance between the distance "3" indicated by the distance signal _{D 12} from the arithmetic circuit _{DP 12,} the counter value "1" and because do not match (distance> counter value) from the counter 300b, L A level coincidence signal (DETECT2) is output.

  Since the coincidence signal (DETECT1) has not risen, the demultiplexer 31d inputs the H level EN signal to the clock number conversion circuit 31a and outputs the L level EN signal to the OR circuit 31e. The clock number conversion circuit 31a again counts the number of clocks of the clock signal CLK, and the coincidence detection signal indicating “1” to the OR circuit 31e at the timing when the counted number of clocks of the clock signal CLK coincides with the distance “2”. Is output.

  The OR circuit 31e outputs a drive signal (= 1) indicating the logical OR operation result of the coincidence detection signal (= 1) from the clock number conversion circuit 31a and the EN signal (= 0) from the OR circuit 31e. . When receiving the drive signal (= 1) from the OR circuit 31e, the demultiplexer 32d outputs the drive signal (= 1) to the clock number conversion circuit 32a because the coincidence signal (DETECT2) has not risen. An inverted signal (= 0) is output to the OR circuit 32e. The clock number conversion circuit 32a again counts the clock number of the clock signal CLK, and the coincidence detection signal indicating “1” to the OR circuit 31e at the timing when the counted clock number of the clock signal CLK coincides with the distance “3”. Is output.

  When the OR circuit 32e outputs a signal (= 1) indicating a logical OR operation result between the coincidence detection signal (= 1) from the clock number conversion circuit 32a and the inverted signal (= 0) from the demultiplexer 32d. The demultiplexer 300a outputs the signal (= 1) from the OR circuit 32e to the counter 300b and the clock number conversion circuits 31a and 32a. As a result, the clock number conversion circuit 31a and the clock number conversion circuit 32a reset the counted clock numbers, respectively. The counter 300b receives the signal (= 1) from the demultiplexer 300a, counts up the counter value, and outputs the counter value “2” to the coincidence detection circuits 31c ′ and 32c ′. Note that the total number of clocks when the counter value “2” is obtained from the start of the search is 10 (= 2 + 3 + 2 + 3).

In coincidence detection circuit 31c ', and the distance "2" distance signal _{D 11} indicates the counter value from the counter 300b "2" and for matches (Distance ≦ counter value), H-level coincidence signal (DETECT1) output Is done. On the other hand, the coincidence detection circuit 32c ', and the distance "3" distance signal _{D 12} indicates, since the counter value from the counter 300b and "2" does not match (distance> counter value), L-level coincidence signal (DETECT2) Is output.

  When the coincidence signal (DETECT1) is switched from the L level to the H level, the demultiplexer 31d outputs an H level EN signal to the OR circuit 31e, and outputs an L level EN signal to the clock number conversion circuit 31a. Upon receiving the L level EN signal, the clock number conversion circuit 31a outputs a coincidence detection signal indicating “0” to the OR circuit 31e.

  The OR circuit 31e outputs a drive signal (= 1) indicating the logical OR operation result of the coincidence detection signal (= 0) from the clock number conversion circuit 31a and the EN signal (= 1) from the demultiplexer 31d. The demultiplexer 32d outputs the drive signal (= 1) from the OR circuit 31e to the clock number conversion circuit 32a, and outputs the inverted signal (= 0) of the drive signal to the OR circuit 32e.

  When receiving the drive signal (= 1) from the OR circuit 32e, the clock number conversion circuit 32a counts the clock signal CLK, and coincides with “1” at the timing when the counted clock number and the distance “3” coincide. The detection signal is output to the OR circuit 32e. The OR circuit 32e provides the demultiplexer 300a with a signal (= 1) indicating the result of the logical sum of the coincidence detection signal (= 1) from the clock number conversion circuit 32a and the drive signal (= 0) from the demultiplexer 32d. Output.

  The demultiplexer 300a outputs the signal (= 1) output from the OR circuit 32e to the counter 300b and the clock number conversion circuits 31a and 32a. As a result, the clock number conversion circuit 31a and the clock number conversion circuit 32a reset the counted clock numbers, respectively. Further, the counter 300b receives the signal (= 1) from the demultiplexer 300a, counts up the counter value, and outputs the counter value “3” to the coincidence detection circuits 31c ′ and 32c ′. Note that the total number of clocks when the counter value “3” is obtained from the start of the search is 13 (= 2 + 3 + 2 + 3 + 3).

In coincidence detection circuit 31c ', and the distance "2" indicated by the distance signal D ₁₁ from the distance computing circuit DP _11, the counter value from the counter 300b "3", to meet the distance ≦ counter value, H-level coincidence signal (DETECT1) is output. Further, the coincidence detection circuit 32c ', the distance between the distance "3" distance signal _{D 11} indicates from the arithmetic circuit _{DP 11,} the counter value from the counter 300b "3" and for matches (Distance ≦ counter value), H A level coincidence signal (DETECT2) is output.

  Since the coincidence signal (DETECT1) is at the H level, the demultiplexer 31d outputs an EN signal at the H level to the OR circuit 31e and outputs an EN signal at the L level to the clock number conversion circuit 31a. Upon receiving the L level EN signal, the clock number conversion circuit 31a outputs a coincidence detection signal indicating “0” to the OR circuit 31e. The OR circuit 31e outputs a drive signal (= 1) signal indicating a logical OR operation result between the coincidence detection signal (= 0) from the clock number conversion circuit 31a and the EN signal (= 1) from the OR circuit 31e. The

  When the coincidence signal (DETECT2) is switched from the L level to the H level, the demultiplexer 32d outputs an inverted signal (= 0) of the drive signal (= 1) from the OR circuit 31e to the clock number conversion circuit 32a, and drives it. The signal (= 1) is output to the OR circuit 32e. When receiving the drive signal (= 0) from the demultiplexer 32d, the clock number conversion circuit 32a outputs a coincidence detection signal indicating “0” to the OR circuit 32e. The OR circuit 32e receives a signal (= 1) indicating a logical OR operation result of the coincidence detection signal (= 0) from the clock number conversion circuit 32a and the drive signal (= 1) from the demultiplexer 32d. Output to.

The AND circuit 300c calculates a logical product of the H level coincidence signal (DETECT1) and the coincidence signal (DETECT2) from the coincidence detection circuits 31c ′ and 32c ′, and sends the Search-End signal (= 1) to the demultiplexer 300a. Output. Demultiplexer 300a ends the receive and searching Search-End signal (= 1), the signal from the OR circuit 32e, and outputs the to Winner detector 20 as a timing signal _{C 1.} In other words, the number of clocks from the search start timing signal C ₁ at the timing when the "13" is output.

The number of clocks “13” is equal to the sum (= 4 + 9) of the square values of the distances (D ₁₁ = 2 and D ₁₂ = 3) of the distance signal D ₁₁ and the distance signal D ₁₂ . As described above, the calculation of the Euclidean distance n _Er between the reference data and the search data is the same as the processing for counting the number of clocks matching the distance for each of the W distances calculated by the expression (1). This is realized by repeatedly performing the number of times. Then, in the example of FIG. 4, the counter coincidence detection unit 300 outputs the timing signal C ₁ indicating the timing at which the clock number “13” is counted by the distance / clock number conversion units 310 and 320 as a whole. _{This corresponds} to searching reference data similar to the search data by _Er and outputting a Winner signal indicating that reference data similar to the search data has been detected. Incidentally, each of the distance / clock number conversion circuit _DC 2 to DC _R also, by operating the same operation of the distance / clock number converting circuit DC _1, respectively, and outputs a timing signal _C 2 -C _R.

In the first embodiment, a counter is provided for each of the distance calculation circuits DP _{11 to} DP _RW . However, in the present embodiment, one counter is provided for each distance / clock number conversion circuit DC _i. Therefore, the circuit area can be reduced as compared with the first embodiment.

In the second embodiment described above, from the control circuit for the associative memory 100 (not shown), to the demultiplexer 300a of the distance / clock number conversion circuit DC _i, receives a control signal indicating the Manhattan distance or the Euclidean distance , when the control signal indicating the Manhattan distance is inputted, the first process may be adapted to output a timing signal C ₁ at the timing when ends at each distance / clock number conversion circuit DC _i. That is, in the example of FIG. 4, after the clock number conversion circuit 31a counts the clock number “2”, the timing signal C ₁ is output from the demultiplexer 300a at the timing when the clock number conversion circuit 32a counts the clock number “3”. Output. As a result, the timing signal C ₁ is output at the timing of the clock number from the search start "5" (= 2 + 3). This coincides with the sum of the Manhattan distances of the reference data and search data in one row. Therefore, with such a configuration, it is possible to perform a search by selectively using the Manhattan distance and the Euclidean distance.

<Third Embodiment>
In the first embodiment and the second embodiment described above, each distance / clock number conversion circuit uses the Euclidean distance by repeatedly performing the process of converting the distance into the clock number for each distance as many times as the distance matches. An example of performing a search was described.

For example, in the distance / clock number conversion circuit according to the first embodiment, when the timing signal is output at the timing when the process of converting the distance into the clock number is performed only once in each counter coincidence detection circuit, the Manhattan distance (formula (1 The timing signal is output at the timing of the number of clocks matching the sum of)). As described above, in the distance / clock number conversion circuit DC ₁ to DC _R distance / clock number conversion unit 310 and 320 in the second embodiment, the process of converting the distance into the number of clocks by performing only once the timing In the case of outputting a signal, the timing signal can be output at the timing of the number of clocks that matches the sum of Manhattan distances.

In the first embodiment and the second embodiment, even if the search is performed using either the Euclidean distance or the Manhattan distance, the timing is required if the number of clocks does not match for all distances in each distance / clock number conversion circuit. No signal is output. That is, in the case of the first embodiment or the second embodiment, the timing t1 at which the timing signal is output earliest (hereinafter, similar pattern p1) and the timing t2 at which the timing signal is output second (hereinafter, similar pattern p2) ) Is the relationship shown in FIG. 5A. The similar pattern p1 is a case where the distance is n _M1 , and the similar pattern p2 is a case where the distance is n _M2 (> n _M1 ). Also, τ _CLK represents a clock cycle. Therefore, the timing signal of the similar pattern p1 is output at the timing of t1 = n _M1 · τ _CLK , and the timing signal of the similar pattern p2 is output at the timing of t2 = n _M2 · τ _CLK .

If a match with the counted number of clocks is strictly detected for each distance as in the first embodiment and the second embodiment, a longer search time is required as search data and bit length increase. In this embodiment, as shown in FIG. 5B, the search time is reduced from the similar patterns p1 and p2 by the same value ( _nx · τ _CLK ), so that the search time is compared with the first embodiment and the second embodiment. A search algorithm for shortening will be described. In the following description, a case where the Manhattan distance is used will be described as an example.

FIG. 6 is a schematic block diagram illustrating a configuration example of the associative memory according to the present embodiment. In FIG. 6, the same reference numerals as those in the first embodiment are assigned to the same configurations as those in the first embodiment. Hereinafter, a configuration different from the first embodiment will be described. As shown in FIG. 6, the associative memory 110 includes distance / clock number conversion circuits DE _{1 to} DE _R instead of the distance / clock number conversion circuits DC _{1 to} DC _R, and includes an AND circuit 6, an effective bit setting unit 40, and the like. Is further provided.

Each of the distance calculation circuits DP _{11 to} DP _1W calculates the distance between the reference data 1 and the search data using the above-described equation (1). In addition, each of the distance calculation circuits DP _{21 to} DP _2W calculates the distance between the reference data 2 and the search data using the above-described equation (1). Similarly, each of the distance calculation circuits DP _{R1 to} DP _RW calculates the distance between the reference data R and the search data using the above-described equation (1).

The distance / clock number conversion circuit DE ₁ receives a distance signal D _1j having a length of N bits from the distance calculation circuits DP _{11 to} DP _1W, and matches the distance indicated by the distance signal D _1j by a method described later. The coincidence detection signal m _{1W —} n is output to the valid bit setting unit 40 at the timing of detecting Distance / clock number conversion circuit DE ₂ receives the distance signal _{D 2j} which from the distance calculating circuit _DP 21 _{to DP 2W} having a W number of N-bit length, the number of clocks to match the distance indicated by the distance signal _{D 2j} in the manner described below The coincidence detection signal m _{2W —} n is output to the valid bit setting unit 40 at the timing at which is detected. Thereafter, in the same manner, the distance / clock number conversion circuit DE _R, the distance calculation circuit _DP R1 _{to DP RW} receives the distance signal _{D Rj} having a W number of N-bit length from, indicated by the distance signal _{D Rj} by a method described later The coincidence detection signal m _{RW —} n is output to the valid bit setting unit 40 at the timing when the number of clocks that coincides with the distance is detected.

Figure 7 is a schematic configuration diagram showing a configuration example of a distance / clock number conversion circuit DE _1. As shown in FIG. 7, the distance / clock number conversion circuit DE ₁ includes counter coincidence detection circuits DE _{11 to} DE _1W and buffers 21 to 2W provided to correspond to the distance calculation circuits DP _{11 to} DP _1W , respectively. Have Has the same configuration is also the distance / clock number conversion circuit DE ₁ for the distance / clock number conversion circuit _DE 2 ... _{DE R.}

Counter match detection circuit _DE 11 _{~DE 1W} receives the distance signal _D 11 _{to D 1W} with N-bit length from each distance calculating circuit _DP 11 _{to DP 1W.} The counter coincidence detection circuit DE ₁₁ receives the clock signal CLK from the buffer 21. Counter match detection circuit _DE 12 _{~DE 1W,} when later from each counter match detection circuit _DE 11 _{~DE 1W-1} counter match signal _{m 11 _n~m 1W-1} _n is input to the buffer 22～2W, buffer The clock signal CLK is input from 22 to 2W.

The counter coincidence detection circuits DE _{11 to} DE _1W receive a signal indicating a search target bit (hereinafter referred to as a BAS signal) from a valid bit setting unit 40 described later. The counter coincidence detection circuit DE ₁₁ detects the coincidence between the counter value corresponding to the bit (n) indicated by the BAS signal and the distance indicated by the distance signal D ₁₁ , and the buffer 22 and the counter coincidence detection circuit DE ₁₁ are detected at the timing when the coincidence is detected. ₁₂ outputs an H level coincidence detection signal m ₁₁ _n. Upon receiving the H level match detection signal m ₁₁ _n, the counter match detection circuit DE ₁₂ detects the match between the counter value corresponding to the bit indicated by the BAS signal and the distance indicated by the distance signal D ₂ and detects the match. At timing, an H level coincidence detection signal m _{12 —} n is output to the buffer 23 and the counter coincidence detection circuit DE ₁₃ (not shown). Similarly, when the counter coincidence detection circuit DE _1W receives the H level coincidence detection signal m _1w-1 _n, it matches the counter value corresponding to the bit indicated by the BAS signal with the distance indicated by the distance signal D _1W. At the timing of detection and detection of coincidence, an H level coincidence detection signal m _{1w —} n is output.

Here, a schematic configuration diagram showing a configuration example of the counter coincidence detection circuit DE ₁₁ is shown in FIG. As shown in FIG. 8, the counter coincidence detection circuit DE ₁₁ includes an N-bit counter 312, a coincidence detection circuit 313, and a multiplexer 314. The counter coincidence detection circuits DE ₁₂ ... DE _1w also have the same configuration as the counter coincidence detection circuit DE ₁₁ .

  The counter 312 receives the clock signal CLK from the buffer 21, receives the BAS signal from the valid bit setting unit 40, and receives a reset signal (RST) from a control circuit (not shown) of the associative memory 110. The counter 312 counts up the bit indicated by the BAS signal in synchronization with the clock of the clock signal CLK, and outputs the counter value to the coincidence detection circuit 313.

Coincidence detection circuit 313 detects a match between the value of the counter value and the distance signal D ₁₁ corresponding to the bit indicated by the BAS signal. When the coincidence detection circuit 313 detects coincidence between the counter value corresponding to the bit indicated by the BAS signal and the value of the distance signal D ₁₁ , the coincidence detection circuit 313 outputs one detection signal m _{11 —} n indicating “1” to the multiplexer 314.

  FIG. 9A shows a circuit configuration example of the counter 312 and the coincidence detection circuit 313 in the present embodiment. In the example of FIG. 9A, the counter 312 is a 3-bit counter. The counter 312 includes three selectors 312a, 312b, and 312c, and frequency dividers 312d, 312e, and 312f connected to the selectors. The selectors 312 a, 312 b, and 312 c receive the BAS signal from the valid bit setting unit 40 and the clock signal CLK from the buffer 21. The selector 312a receives the BAS signal (BAS <1>) corresponding to the most significant bit and indicating the most significant bit. The selector 312b corresponds to the second most significant bit and receives a BAS signal (BAS <2>) indicating the second bit. The selector 312c corresponds to the least significant bit and receives a BAS signal (BAS <3>) indicating the least significant bit. The BAS signal is a signal indicating 1 or 0.

  The coincidence detection circuit 313 includes EXNOR circuits 313a, 313b, and 313c, and AND circuits 313d and 313e. The EXNOR circuits 313a, 313b, and 313c are connected to the frequency dividers 312d, 312e, and 312f, respectively.

  When the BAS signal (= 1) is input to any of the selectors 312a, 312b, 312c, the selector to which the BAS signal (= 1) is input inputs the clock signal CLK to the corresponding frequency divider. The frequency divider to which the clock signal CLK is input divides the clock signal CLK and outputs it to the coincidence detection circuit 313. It should be noted that the frequency dividers 312d and 312e are counted when a carry value by counting up the frequency divider corresponding to the lower bits is input even when the BAS signal indicating the lower bits is input. Do up.

FIG. 9B shows the operation of the counter 312 when the least significant bit is designated from the most significant by the BAS signal. When the most significant bit is designated by the BAS signal (BAS <1> = 1, BAS <2> = 0, BAS <3> = 0), the selector 312c is grounded, so the frequency divider 312f 312e outputs a signal value “0” to the EXNOR circuits 313b and 313c. The divider 312a, the clock signal CLK is input, as shown in i) of FIG. 9B, it outputs the counter value indicated a clock signal CLK ^{2 0} times peripheral signal to the EXNOR circuit 313a. That is, in this case, the counter 312 functions as a 1-bit counter.

If the second bit from the most significant bit is designated by the BAS signal (BAS <1> = 0, BAS <2> = 1, BAS <3> = 0), a signal is sent from the frequency divider 312f to the EXNOR circuit 313c. The value “0” is output. The divider 312e, the clock signal CLK is input, as shown in ii) of FIG. 9B, it outputs the counter value indicated a clock signal CLK ^{2 0} times peripheral signal to the EXNOR circuit 313b. The frequency divider 312d, the carry signal from the frequency divider 312e is input, as shown in ii) of FIG. 9B, a clock signal CLK to the counter value indicated by ² divided by ¹ signal to the EXNOR circuit 313a Output. That is, in this case, the counter 312 functions as a 2-bit counter.

When the least significant bit is specified by the BAS signal (BAS <1> = 0, BAS <2> = 0, BAS <3> = 1), the clock signal CLK is input to the frequency divider 312f. , as shown in iii) of FIG. 9B, outputs the counter value indicated a clock signal CLK ^{2 0} times peripheral signal to the EXNOR circuit 313c. The divider 312e, the carry signal from the frequency divider 312f is input, as shown in iii) of FIG. 9B, a clock signal CLK to the counter value indicated by ^{2 1} times the circumferential signal to EXNOR circuit 313b Output. Further, minute the divider 312d, divider carry signal from 312e is input, as shown in iii) of FIG. 9B, EXNOR circuit a counter value indicated a clock signal CLK at ^{2 twice} peripheral signals To 313a. That is, in this case, the counter 312 functions as a 3-bit counter.

Returning to FIG. 9A, the description will be continued. EXNOR circuit 313a, 313b, 313c is the distance signal _D value D of each bit of the _{ij <1>, D <2} >, subjected to D <3>, a frequency divider 312d, 312e, receives a respective counter value from 312f.

EXNOR circuit 313a includes a distance signal _D of the most significant bit of the _ij values D <1>, when the counter value output from the frequency divider 312d are identical, the detection signal indicating "1" to the AND circuit 313d The detection signal (= 1) is output to the multiplexer 314 as the coincidence detection signal m _ij _1 corresponding to the most significant bit. If the value D <1> of the most significant bit of the distance signal D _ij does not match the counter value, a detection signal indicating “0” is output to the AND circuit 313d, and the detection signal (= 0) is detected as coincidence. The signal m _ij _ 1 is output to the multiplexer 314.

The EXNOR circuit 313b sets “1” to the AND circuit 313d when the value D <2> of the second most significant bit of the distance signal D _ij matches the counter value output from the frequency divider 312e. A detection signal indicating “0” is output when the detection signals do not coincide with each other.

EXNOR circuit 313c includes a distance signal _D least significant bits of the value D <3> of _ij, when the counter value output from the frequency divider 312f match, a detection signal indicating "1" to the AND circuit 313e If it does not match, a detection signal indicating “0” is output.

The AND circuit 313d outputs a detection signal indicating the logical product of the detection signals input from the EXNOR circuit 313a and the EXNOR circuit 313b to the AND circuit 313e, and the detection signal corresponds to the second most significant bit. and outputs as the match detection signal _m ij _2 to the multiplexer 314. For example, when the detection signal (= 1) is output from the EXNOR circuit 313a and the EXNOR circuit 313b, that is, when the distance of the upper 2 bits matches the counter value, the detection signal indicating “1” There is output to the aND circuit 313e, the coincidence detection signal _m ij _2 indicating "1" is output to the multiplexer 314. In addition, when a detection signal (= 0) is output from at least one of the EXNOR circuit 313a and the EXNOR circuit 313b, that is, when the distance of the upper 2 bits does not match the counter value, “0” is indicated. detection signal is output to the aND circuit 313e, the coincidence detection signal _m ij _2 indicating "0" is output to the multiplexer 314.

The AND circuit 313e outputs a detection signal indicating a logical product value of the detection signals input from the EXNOR circuit 313c and the AND circuit 313d to the multiplexer 314 as a coincidence detection signal m _ij —3 corresponding to the least significant bit. For example, when the detection signal (= 1) is output from the EXNOR circuit 313c and the AND circuit 313d, that is, when the distance represented by all the bits matches the counter value, the coincidence detection signal m _ij _3 (= 1) is output. Further, when a detection signal (= 0) is output from at least one of the EXNOR circuit 313c and the AND circuit 313d, that is, when the distance represented by all bits does not match the counter value, the coincidence detection signal m _ij — 3 (= 0) is output to the multiplexer 314. In the coincidence detection circuit 313, unless the EXNOR circuit 313a outputs a detection signal indicating “1”, the AND circuits 313d and 313e output coincidence detection signals m _ij _2 and m _ij _3 indicating “1”, respectively. Never do.

Returning to FIG. 8, the multiplexer 314 in the counter coincidence detection circuit DE ₁₁ uses the buffer 22 and the counter coincidence detection circuit DE to output the coincidence detection signal m _{11 —} n output from the coincidence detection circuit 313 corresponding to the bit indicated by the BAS signal. ₁₂ is output. The coincidence detection signal m _{1W —} n output from the multiplexer 314 in the counter coincidence detection circuit DE _1W is output to the valid bit setting unit 40.

Next, the valid bit setting unit 40 will be described with reference to FIGS. Valid bit setting unit 40 receives the clock signal CLK, the distance / clock number conversion circuit _DE 1 ～DE coincidence detection signal outputted from the _{R m} iW _n (1 or 0). Valid bit setting unit 40 receives either the distance clock number conversion circuit _DE 1 _{~DE R} from the coincidence detection signal _m iW _n (= 1), in synchronization with the clock signal CLK, the counter match detecting circuits _{DE i1} ~ A BAS signal is output to each counter 312 and multiplexer 314 in DE _iW .

In order to input the BAS signal from the valid bit setting unit 40 to the counter coincidence detection circuits DE _{i1 to} DE _iW , one clock cycle is required. Valid bit setting unit 40, while inputting the BAS signal, and inputs the CLK_ACT signal to the AND circuit 6, so that the clock signal CLK is not input to the distance / clock number conversion circuit _DE 1 _{~DE R.} CLK_ACT signal is a signal obtained by inverting the coincidence detection signal _m iW _n.

That is, when the match detection signal _m iW _n rises (coincidence detection signal _m iW _n = 1), CLK_ACT signal indicating "0" is input to the AND circuit 6, if not rise the match detection signal _m iW _n (match Detection signal m _{1W —} n = 0), and CLK_ACT signal indicating “1” is input to the AND circuit 6. Valid bit setting unit 40 outputs from the distance / clock number conversion circuit _DE 1 _{~DE R} at the timing when the coincidence detection signal rises corresponding to the least significant bit timing signal _C 1 -C _R to Winner detector 20.

The AND circuit 6 receives the clock signal CLK and the CLK_ACT signal (1 or 0) from the valid bit setting unit 40. AND circuit 6 inputs the calculation result of the logical product of the CLK_ACT signal and the clock signal CLK from the effective bit setting unit 40 on the distance / clock number conversion circuit _DE 1 _{~DE R.} That is, when the CLK_ACT signal (= 0) is input from the valid bit setting unit 40, the clock signal CLK is not input to the distance / clock number conversion circuits DE _{1 to} DE _R and the CLK_ACT signal (= 1) is input. If it is, the clock signal CLK is inputted to the distance / clock number conversion circuit _DE 1 _{~DE R.}

Here, in the configuration shown in FIG. 6, an example of operation when the reference data is the reference data 1 and 2 and R = 2 and W = 3 will be described. FIG. 10A shows the distance between the reference data 1 and the search data, the reference data 2 and the search data in the distance / clock number conversion circuit DE ₁ for the reference data ₁ and the distance / clock number conversion circuit DE ₂ for the reference data 2. It is a figure which shows the process in which each distance is converted into the number of clocks.

In the example of FIG. 10A, the distance / clock number conversion circuit DE ₁ includes counter coincidence detection circuits DE _{11 to} DE ₁₃ , and the distance / clock number conversion circuit DE ₂ includes counter coincidence detection circuits DE _{21 to} DE ₂₃ . . In FIG. 10A, the underline of each counter value and distance value indicates a bit set by the effective bit setting unit 40, that is, a bit for which a match between the distance and the counter value is to be detected.

The counter coincidence detection circuits DE ₁₁ , DE ₁₂ , DE ₁₃ receive distance signals D _11, D ₁₂ , D ₁₃ from the distance calculation circuits DP ₁₁ , DP ₁₂ , DP _{13 ,} respectively. In this example, the distance indicated by the distance signal _{D 11} is _"5 10 (= 101 _2)", the distance indicated by the distance signal _{D 12} is _"4 10 (= 100 _2)" indicates the distance signal _{D 13} The distance is “3 ₁₀ (= 010 ₂ )”. Further, distance signals D _21, D ₂₂ , and D ₂₃ are input to the counter match detection circuits DE ₂₁ , DE ₂₂ , and DE ₂₃ from the distance calculation circuits DP ₂₁ , DP ₂₂ , and DP _{23 ,} respectively. In this example, the distance indicated by the distance signal D ₂₁ is “7 ₁₀ (= 111 ₂ )”, the distance indicated by the distance signal D ₂₂ is “0 ₁₀ (= 000 ₂ )”, and the distance signal D ₂₃ indicates The distance is “2 ₁₀ (= 010 ₂ )”. Each counter coincidence detection circuit in the distance / clock number conversion circuits DE ₁ and DE ₂ has a BAS signal (BAS <1> = 1, BAS <2> = 0, BAS <) indicating the most significant bit as an initial value. 3> = 0) is preset.

When a signal SB indicating a search start is input from a control circuit (not shown) of the associative memory 110, the counter match detection circuits DE ₁₁ and DE ₁₂ respectively divide the frequency corresponding to the most significant bit at the 0th clock. The counter value “0” of the device 312 d is output to the EXNOR circuit 313 a of the coincidence detection circuit 313. In the example of FIG. 10A, when BAS “1” and clock “0”, the counter value “ 0 00” of the most significant bit indicated by the underline in the counter match detection circuit DE ₁₁ does not match the distance “ 1 01”. Similarly, the counter match detection circuit DE _21, do not match the counter value of the most significant bit is underlined and "0 00" and the distance "1 11". Therefore, in the counter coincidence detection circuit DE ₁₁ and the counter coincidence detection circuit DE ₂₁ , detection signals indicating “0” are output from the EXNOR circuit 313 a to the AND circuit 313 d. Then, the coincidence detection signal m ₁₁ _ 1 (= 0) is output from the counter coincidence detection circuit DE ₁₁ to the counter coincidence detection circuit DE ₁₂ , and the coincidence detection signal m ₂₁ _1 is output from the counter coincidence detection circuit DE ₂₁ to the counter coincidence detection circuit DE _22. (= 0) is output.

Since the coincidence detection signal corresponding to the most significant bit of the distance / clock number conversion circuits DE ₁ and DE ₂ has not risen at the 0th clock, the valid bit setting unit 40 uses the CLK_ACT signal (= 1) as an AND circuit. 6 is output. As a result, the clock signal CLK is input to the counter coincidence detection circuits DE ₁₁ and DE ₂₁ .

The counter coincidence detection circuits DE ₁₁ and DE ₂₁ input the clock signal CLK to the respective selectors 312a. Divider 312d in the counter coincidence detection circuit _{DE 11} was ^{2 0} times the frequency of the clock signal CLK, and outputs the counter value at t1 shown in FIG. 10B "1" to EXNOR circuit 313a, indicating "1" from the EXNOR circuit 313a The detection signal is output to the AND circuit 313d. Then, the coincidence detection signal m ₁₁ _1 (= 1) is output to the counter coincidence detection circuit DE ₁₂ and the buffer 22.

When the match detection signal m ₁₁ _ 1 (= 1) is input to the counter match detection circuit DE ₁₂ , the match detection circuit 313 matches the counter value of the frequency divider 312 d corresponding to the most significant bit with the distance D _12. Start detecting. Counter match detection circuit _DE divider in ₁₂ 312d is a clock signal CLK to ^{2 0} times division and outputs the counter value at t1 shown in FIG. 10B to "0" to the EXNOR circuit 313a. Since the counter value “0” corresponding to the most significant bit does not match the distance D ₁₂ “ 1 00”, the detection signal indicating “0” is output from the EXNOR circuit 313a to the AND circuit 313d, and the match detection signal m ₁₂ _1. (= 0) is output. Therefore, the coincidence detection signal m ₁₃ _1 (= 1) is not output for the reference data 1 at the first clock from the search start.

On the other hand, as shown in FIG. 10B, the frequency divider 312d in the counter coincidence detection circuit _{DE 21} is a clock signal CLK to ^{2 0} times circumferential outputs the counter values at t1 shown in FIG. 10B "1" to EXNOR circuit 313a, A detection signal indicating “1” is output from the EXNOR circuit 313a to the AND circuit 313d. Then, the coincidence detection signal m ₂₁ _ 1 (= 1) is output to the counter coincidence detection circuit DE ₁₂ and the buffer 22.

When the coincidence detection signal m ₂₁ _ 1 (= 1) is input to the counter coincidence detection circuit DE ₂₂ , the coincidence detection circuit 313 matches the counter value of the frequency divider 312 d corresponding to the most significant bit with the distance D _22. Start detecting. As shown in FIG. 10B, the frequency divider 312d in the counter coincidence detection circuit _{DE 22} is a clock signal CLK to ^{2 0} times division and outputs the counter value at t1 shown in FIG. 10B to "0" to the EXNOR circuit 313a. To match the counter value "0" and the distance "0 00" corresponding to the most significant bit, a detection signal indicating "1" from the EXNOR circuit 313a is output to the AND circuit 313d, a counter coincidence detecting circuit _{DE 23} Buffer 23, the coincidence detection signal m ₂₂ _1 (= 1) is output.

When the coincidence detection signal m ₂₂ _ 1 (= 1) is input to the counter coincidence detection circuit DE ₂₃ , the coincidence detection circuit 313 matches the counter value of the frequency divider 312 d corresponding to the most significant bit with the distance D _23. Start detecting. As shown in FIG. 10B, the frequency divider 312d in the counter coincidence detecting circuit _{DE 23} was ^{2 0} times the frequency of the clock signal CLK, the counter value in the coincidence detection signal _m 22 _1 (= 1) is input timing "0" Is output to the EXNOR circuit 313a. Since the counter value “0” corresponding to the most significant bit matches the distance D ₂₃ “ 0 10”, the detection signal indicating “1” is output from the EXNOR circuit 313a to the AND circuit 313d, and the effective bit is set from the multiplexer 314. The coincidence detection signal m ₂₃ _ 1 (= 1) is output to the unit 40. Accordingly, the coincidence detection signal m ₂₃ _1 (= 1) is output for the reference data 2 at the first clock from the start of the search.

When the coincidence detection signal m ₂₃ _ 1 (= 1) for the most significant bit is input from the distance / clock number conversion circuit DE ₂ , the valid bit setting unit 40 receives the _second bit from the most significant bit at the second clock from the search start. the BAS signal indicating a bit (BAS <1> = 0, BAS <2> = 1, BAS <3> = 0), is input to the counter match detecting circuit in the distance / clock number conversion circuit DE ₁ and DE _2. As a result, the detection target bits are expanded to the upper 2 bits. The valid bit setting unit 40 outputs the CLK_ACT signal (= 0) to the AND circuit 6 so that the clock signal CLK is not input to the distance / clock number conversion circuits DE ₁ and DE ₂ .

When the counter match detection circuits DE ₁₁ and DE ₂₁ receive the BAS signal (BAS <2> = 1) in the respective counters 312, the BAS signal (BAS <2> = 1) is input to the selector 312 b corresponding to the second most significant bit. , A match between the counter value of the upper 2 bits and the distance is detected.

When BAS signal (BAS <2> = 1) is input, as shown in FIG. 10C, the frequency divider 312e in the counter coincidence detecting circuit _{DE 11,} 312d are ² 0, ^{2 1} times each minute the clock signal CLK Rotate and output a 2-bit counter value. At the first clock from the start of the search, the counter value “1” of the frequency divider 312d in the counter coincidence detection circuit DE ₁₁ and the distance D ₁₁ “ 1 01” coincide. Therefore, the frequency divider 312d, 312e of the counter match detection circuit _{DE 11,} the counter value in t1 shown in FIG. 10C-bit value "10", "1", and outputs the "0" EXNOR circuit 313a, in 313b. That is, the search for the distance “4” is cancelled. Since the counter value “10” corresponding to the upper 2 bits matches the distance D ₁₁ “ 10 1”, the EXNOR circuits 313a and 313b output detection signals indicating “1” to the AND circuits 313d and 313e, respectively, and EXNOR The coincidence detection signals m ₁₁ _1 (= 1) and m ₁₁ _2 (= 1) are output from the circuit 313a and the AND circuit 313d to the multiplexer 314, respectively. Then, the coincidence detection signal m ₁₁ _2 (= 1) is output from the multiplexer 314 to the counter coincidence detection circuit DE ₁₂ and the buffer 22.

When the coincidence detection signal m ₁₁ _2 (= 1) is input, the counter coincidence detection circuit DE ₁₂ starts the coincidence detection between the upper 2-bit counter value and the distance D ₁₂ in the coincidence detection circuit 313. When BAS signal (BAS <2> = 1) is input, as shown in FIG. 10C, the frequency divider 312e in the counter coincidence detector _{DE 12,} 312d are ² 0, ^{2 1} times each minute the clock signal CLK Rotate and output a 2-bit counter value. As shown in FIG. 10C, the bit values “0” and “0” of the counter values “00” of the frequency dividers 312d and 312e of the counter match detection circuit DE ₁₂ at t1 are output to the EXNOR circuits 313a and 313b, respectively. Since the counter value “00” corresponding to the upper 2 bits does not match the distance D ₁₂ “ 10 0”, detection signals indicating “0” and “1” are output from the EXNOR circuits 313a and 313b to the AND circuit 313d, respectively. The coincidence detection signal m ₁₂ _ 2 (= 0) is output from the multiplexer 314 to the counter coincidence detection circuit DE ₁₃ and the buffer 23.

Divider 312e in the counter coincidence detection circuit _{DE 21,} 312d, when BAS signal (BAS <2> = 1) is input, as shown in FIG. 10C, ² a clock signal CLK respectively 0, ^{2 1} times the circumferential The 2-bit counter value is output. At the first clock from the search start, the counter value “1” of the frequency divider 312d in the counter coincidence detection circuit DE ₂₁ matches the distance “ 1 11”. Therefore, the frequency dividers 312d and 312e of the counter coincidence detection circuit DE ₂₁ output the bit values “1” and “0” of the counter value “10” at t1 illustrated in FIG. 10C to the EXNOR circuits 313a and 313b, respectively. That is, the search for the distance “2” is cancelled. Since the counter value “10” corresponding to the upper 2 bits and the distance D ₂₁ “ 11 1” do not match, detection signals indicating “1” and “0” are output from the EXNOR circuits 313a and 313b to the AND circuit 313d, respectively. The multiplexer 314 outputs the coincidence detection signal m ₂₁ _ 2 (= 0) to the counter coincidence detection circuit DE ₂₂ and the buffer 22.

In the valid bit setting unit 40, none of the coincidence detection signals (m ₁₃ _2 and m ₂₃ _2) corresponding to the second most significant bit of the counter coincidence detection circuits DE ₁ and DE ₂ rises at the second clock. Therefore, by entering the CLK_ACT signal (= 1) to the aND circuit 6, the distance / clock number conversion circuit DE ₁ and DE ₂ so that the clock signal CLK is input.

In the counter coincidence detection circuit DE ₁₁ , the coincidence detection signal m ₁₁ _2 (= 1) is output at the second clock from the start of the search for the upper 2 bits. Therefore, in the third clock from the search start, to stop the operation of the coincidence detection in the counter coincidence detection circuit DE _11.

Counter match detection circuit _{DE 12} is the third clock from the search start, when the clock signal CLK via a selector 312b is input, the frequency divider 312d, 312e is, the counter value in t2 shown in FIG. 10C "01" Bit values “0” and “1” are output to the EXNOR circuits 313a and 313b, respectively. The counter value “01” of the upper 2 bits does not match the distance D ₁₂ “ 10 0”. Therefore, in the counter coincidence detection circuit DE ₁₂ , the coincidence detection signal m ₁₂ _ 2 (= 0) is output to the counter coincidence detection circuit DE ₁₃ and the buffer 23.

Likewise counter match detection circuit _{DE 21,} the third clock from the search start, when the clock signal CLK via a selector 312b is input, the frequency divider 312d, 312e is, the counter value in t2 shown in FIG. 10C "11 "1" and "1" are output to the EXNOR circuits 313a and 313b, respectively. The counter value “11” of the upper 2 bits matches the distance D ₂₁ “ 11 1”. Therefore, in the counter coincidence detection circuit DE ₂₁ , the coincidence detection signal m ₂₁ _2 (= 1) is output from the multiplexer 314 to the counter coincidence detection circuit DE ₂₂ and the buffer 22.

When the coincidence detection signal m ₂₁ _2 (= 1) is input to the counter coincidence detection circuit DE ₂₂ , the coincidence detection circuit 313 starts detecting coincidence between the counter value of the upper 2 bits and the distance D ₂₂ . As shown in FIG. 10C, the frequency divider in the counter coincidence detector _{DE 22} 312e, 312d, the counter value at t2 bit value of "00", "0", and outputs the "0" EXNOR circuit 313a, in 313b. The counter value “00” corresponding to the upper 2 bits matches the distance D ₂₂ “ 00 0”. For this reason, in the counter coincidence detection circuit DE ₂₂ , the coincidence detection signal m ₂₂ _2 (= 1) is output from the multiplexer 314 to the counter coincidence detection circuit DE ₂₃ and the buffer 23.

When the coincidence detection signal m ₂₂ _2 (= 1) is input, the counter coincidence detection circuit DE ₂₃ starts to detect coincidence between the counter value of the upper 2 bits and the distance D ₂₃ . As shown in FIG. 10C, the frequency divider in the counter coincidence detecting circuit _{DE 23} 312e, 312d, the counter value at t2 bit value of "00", "0", and outputs the "0" EXNOR circuit 313a, in 313b. The counter value “00” corresponding to the upper 2 bits does not match the distance D ₂₃ “ 01 0”. For this reason, in the counter match detection circuit DE ₂₃ , the match detection signal m ₂₃ _ 2 (= 0) is output from the multiplexer 314 to the valid bit setting unit 40.

In the third clock, neither of the distance / clock number conversion circuits DE ₁ and DE ₂ has a coincidence detection signal (m ₁₃ _2, m ₂₃ _2) corresponding to the second most significant bit. Therefore, the CLK_ACT signal (= 1) is input from the valid bit setting unit 40 to the AND circuit 6 even at the fourth clock.

In the counter coincidence detection circuit DE _11, since the upper 2 coincidence detection signal for bit m _{11 _2} (= 1) is output to the second clock from the search start, also stops the operation of the coincidence detection in the fourth clock.

Counter match detection circuit _{DE 12} is the fourth clock from the search start, when the clock signal CLK via a selector 312b is input, the frequency divider 312d, 312e is, the counter value in t3 shown in FIG. 10C "10" Bit values “1” and “0” are output to the EXNOR circuits 313a and 313b, respectively. The counter value “10” of the upper 2 bits matches the distance D ₁₂ “ 10 0”. Therefore, in the counter coincidence detection circuit DE ₁₂ , the coincidence detection signal m ₁₂ _2 (= 1) is output to the counter coincidence detection circuit DE ₁₃ and the buffer 23.

When the coincidence detection signal m ₁₂ _2 (= 1) is input, the counter coincidence detection circuit DE ₁₃ starts the coincidence detection between the upper 2-bit counter value and the distance D ₁₃ in the coincidence detection circuit 313. As shown in FIG. 10C, the frequency divider 312e, 312d in the counter coincidence detecting circuit _{DE 13,} the counter value at t3 bit value of "00", "0", and outputs the "0" EXNOR circuit 313a, in 313b. The counter value “00” corresponding to the upper 2 bits does not match the distance D ₁₃ “ 01 1”. Therefore, in the counter coincidence detection circuit DE ₁₃ , the coincidence detection signal m ₁₃ _ 2 (= 0) is output from the multiplexer 314 to the valid bit setting unit 40.

On the other hand, in the counter coincidence detection circuits DE ₂₁ and DE ₂₂ , the coincidence detection signals m ₂₁ _2 and m ₂₂ _2 (= 1) for the upper 2 bits are output at the second clock and the third clock from the search start, respectively. At the fourth clock, the counter coincidence detection circuits DE ₂₁ and DE ₂₂ stop the coincidence detection operation.

Counter match detection circuit _{DE 23} is the fourth clock from the search start, when the clock signal CLK via a selector 312b is input, the frequency divider 312d, 312e is, the counter value in t3 shown in FIG. 10C "01" Bit values “0” and “1” are output to the EXNOR circuits 313a and 313b, respectively. Since the counter value “01” of the upper 2 bits matches the distance D ₂₃ “ 01 0”, the match detection signal m ₂₃ _2 (= 1) is output from the multiplexer 314 to the valid bit setting unit 40.

When the coincidence detection signal m ₂₃ _2 (= 1) for the second bit from the most significant bit is input from the distance / clock number conversion circuit DE _{2 at} the fourth clock, the valid bit setting unit 40 receives five clocks from the start of the search. eyes, BAS signal indicating the least significant bit (BAS <1> = 0, BAS <2> = 0, BAS <3> = 1) , and the counters match detection at a distance / clock number conversion circuit DE ₁ and DE ₂ Input to the circuit. As a result, the bit subject to coincidence detection is expanded from the most significant bit to the least significant bit. The valid bit setting unit 40 inputs the CLK_ACT signal (= 0) to the AND circuit 6 so that the clock signal CLK is not input to the distance / clock number conversion circuits DE ₁ and DE ₂ .

When the counter coincidence detection circuits DE ₁₁ and DE ₂₁ receive the BAS signal (BAS <3> = 1) in the respective counters 312, the selector 312c corresponding to the least significant bit is input at the fifth clock from the start of the search. The coincidence detection circuit 313 detects coincidence between the counter values of all bits and the distance.

Counter match detection circuit _DE divider in ₁₁ 312f, 312e, 313d, when BAS signal (BAS <3> = 1) is input, as shown in FIG. 10D, the clock signal CLK ^{2 0, 2} 1, 2 ^twice in each division and outputs a 3-bit counter value. At the second clock from the start of search, the counter value “10” of the frequency dividers 312d and 312e in the counter coincidence detection circuit DE ₁₁ and the distance D ₁₁ “ 10 1” coincide. Therefore, the frequency divider 312d of counter match detection circuit _{DE 11,} 312e, 312f, the counter value in t3 shown in FIG. 10D bit value of "100", "1", "0", "0" EXNOR circuit 313a, 313b , 313c. That is, the search for the distance “4” is cancelled. Since the counter value “100” corresponding to all bits and the distance D ₁₁ “ 101 ” do not match, detection signals indicating “1” and “1” are output from the EXNOR circuits 313a and 313b to the AND circuit 313d, respectively, and EXNOR A detection signal indicating “0” is output from the circuit 313c to the AND circuit 313e. Then, the coincidence detection signal m ₁₁ — 3 (= 0) is output from the multiplexer 314 to the counter coincidence detection circuit DE ₁₂ and the buffer 22.

When the BAS signal (BAS <3> = 1) is input to the frequency dividers 312f, 312e, and 313d in the counter coincidence detection circuit DE ₂₁ , as shown in FIG. 10D, the clock signal CLK is changed to 2 ⁰ , 2 ¹ , 2 ^twice in each division and outputs a 3-bit counter value. At the third clock from the start of the search, the counter value “11” of the frequency dividers 312d and 312e in the counter coincidence detection circuit DE ₂₁ matches the distance D ₂₁ “ 11 1”. Therefore, the frequency divider 312d of counter match detection circuit _{DE 11,} 312e, 312f, the counter value of the t5 shown in FIG. 10D bit value of "110", "1", "1", "0" EXNOR circuit 313a, It outputs to 313b and 313c, respectively. That is, the search for the distance “6” is cancelled. Since the counter value “110” corresponding to all bits and the distance D ₂₁ “ 111 ” do not match, detection signals indicating “1” and “1” are output from the EXNOR circuits 313a and 313b to the AND circuit 313d, respectively, and EXNOR A detection signal indicating “0” is output from the circuit 313c to the AND circuit 313e. Then, the coincidence detection signal m ₂₁ — 3 (= 0) is output from the multiplexer 314 to the counter coincidence detection circuit DE ₂₂ and the buffer 22.

Since the counter match detection circuits DE ₁₁ and DE ₂₁ do not match the counter value of the least significant bit and the distance at the fifth clock from the start of the search, the counter match detection circuits DE ₁₁ and DE ₂₁ receive the clock signal CLK. The

Counter match detection circuit _{DE 11} is the sixth clock from the search start, when the clock signal CLK via a selector 312b is input, the frequency divider 312d, 312e, 312f, the counter value in t4 shown in FIG. 10D "101 Are output to the EXNOR circuits 313a, 313b, and 313c, respectively. Since the counter value “101” of all bits coincides with the distance D ₁₁ “ 101 ”, the counter coincidence detection circuit DE ₁₁ receives the coincidence detection signal m ₁₁ — 3 (= 1) in the counter coincidence detection circuit DE ₁₂ and the buffer 22. Is output.

When the coincidence detection signal m ₁₁ — 3 (= 1) is input to the counter coincidence detection circuit DE ₁₂ , the coincidence detection circuit 313 detects coincidence between the counter values of all bits and the distance. From the search start the fourth clock, a frequency divider 312d in the counter coincidence detector _{DE 12,} 312e, the counter value of 312f "10" and the distance _{D 11} "10 0" and the match. Therefore, the frequency divider 312d of counter match detection circuit _{DE 12,} 312e, 312f, the counter value in t4 shown in FIG. 10D bit value of "100", "1", "0", "0" EXNOR circuit 313a, 313b , 313c. Since the counter value of all the bits "100" distance _{D 12} and "100" match, the counter match detection circuit _{DE 12,} the coincidence detection signal to the counter coincidence detection circuit _{DE 13} and the buffer 23 _m 12 _3 (= 1) is Is output.

When the coincidence detection signal m ₁₂ — 3 (= 1) is input, the counter coincidence detection circuit DE ₁₃ starts the coincidence detection circuit 313 to detect coincidence between the counter values of all bits and the distance. Divider 312d of counter match detection circuit _{DE 13,} 312e, 312f, the bit value "0" of the counter value "000" in the t4 shown in FIG. 10D, "0", "0" EXNOR circuit 313a, 313b, 313c Respectively. Since the counter value “000” of all bits does not match the distance D ₁₃ “ 011 ”, the match detection signal m ₁₃ — 3 (= 0) is output to the valid bit setting unit 40 in the counter match detection circuit DE ₁₃ .

On the other hand, the counter match detection circuit _{DE 21} is the sixth clock from the search start, when the clock signal CLK via the selector 312c is input, the frequency divider 312d, 312e, 312f, the counter value in t6 shown in FIG. 10D Bit values “1”, “1”, and “1” of “111” are output to the EXNOR circuits 313a, 313b, and 313c, respectively. Since the counter value “111” of all bits and the distance D ₂₁ “ 111 ” coincide, the counter coincidence detection circuit DE ₂₁ receives the coincidence detection signal m ₂₁ _3 (= 1) in the counter coincidence detection circuit DE ₂₂ and the buffer 22. Is output.

When the coincidence detection signal m ₂₁ — 3 (= 1) is input, the counter coincidence detection circuit DE ₂₂ starts the coincidence detection circuit 313 to detect coincidence between the counter values of all bits and the distance. At the third clock from the start of the search, the counter values “00” of the frequency dividers 312d and 312e in the counter coincidence detection circuit DE ₂₂ coincide with the distance D ₂₂ “ 00 0”. Therefore, the frequency dividers 312d, 312e, and 312f of the counter coincidence detection circuit DE ₂₂ change the bit values “0”, “0”, and “0” of the counter value “000” at t6 illustrated in FIG. 10D to the EXNOR circuits 313a and 313b. , 313c. Since the counter value of all the bits "000" and the distance _{D 22} "000" match, the counter match detection circuit _{DE 22,} counter match detection circuit _{DE 23} and coincidence detection signal _m 22 to the buffer 23 _3 (= 1) Is output.

When the coincidence detection signal m ₂₂ — 3 (= 1) is input, the counter coincidence detection circuit DE ₂₃ starts the coincidence detection circuit 313 to detect coincidence between the counter values of all bits and the distance. At the fourth clock from the start of the search, the counter values “01” of the frequency dividers 312d and 312e in the counter match detection circuit DE ₂₃ and the distance D ₂₃ “ 01 0” match. Therefore, the frequency dividers 312d, 312e, and 312f of the counter match detection circuit DE ₂₃ change the bit values “0”, “1”, and “0” of the counter value “010” at t6 illustrated in FIG. 10D to the EXNOR circuits 313a and 313b. , 313c. Since the counter value “010” of all bits matches the distance D ₂₃ “ 010 ”, the counter match detection circuit DE ₂₃ outputs a match detection signal m ₂₃ — 3 (= 1) to the valid bit setting unit 40.

When the valid bit setting unit 40 receives the coincidence detection signal m ₂₃ — 3 (= 1) for the least significant bit from the distance / clock number conversion circuit DE ₂ , the valid bit setting unit 40 receives the coincidence detection signal at the timing of receiving the coincidence detection signal. a timing signal _{C 2} to the Winner detector 20 for DE _2.

Thus, in the example of FIG. 10A, the timing signal C ₂ for the reference data 2 in 6 clock cycles it is output. When the method of the first embodiment is used, 9 clock cycles (= 7 + 0 + 2) are required in the case of the reference data 2, but when the method of the present embodiment is used, 3 clock cycles are reduced.

The coincidence detection circuit 313 outputs a coincidence detection signal for detecting coincidence between the distance and the counter value for the upper J bits (1 ≦ J ≦ N). When the k-th bit from the lower order is set as a target bit for coincidence detection, a coincidence detection signal indicating a coincidence of upper (N- (k-1)) bits ignoring the lower k-1 bits is output. Therefore, if the coincidence detection signal is “0” for all reference data when the k-th bit is the target bit, it means that all the reference data has a distance of 2 ^k−1 or more. In this case, the clock signal is input to the counter of the k-th bit from the lower order and counted up. This means that the k-th bit from the lower order becomes “1”, which corresponds to the distance 2 ^k−1 being canceled in one clock cycle.

On the other hand, if the coincidence detection signal output for any of the reference data is “1”, it means that the reference data has no distance of 2 ^k−1 . In this case, the target bit is set to the (k−1) th bit from the lower order, and the distance 2 ^k−2 is sequentially canceled for all the reference data.

That is, by extending the bit to be detected as a match from the most significant bit to an arbitrary bit unit and detecting a match between the counter value and the distance, the large distance is sequentially canceled. Thereby, the longest search time of one reference data in the first and second embodiments is “M × 2 ^N−1 × τ _CLK ”, whereas in this embodiment, “(M × N + N−1)”. × τ _CLK ″ can be reduced.

<Fourth embodiment>
In the first embodiment and the second embodiment, by repeating the process of converting each distance between the search data and the reference data calculated using Expression (1) into the number of clocks, the number of times matches the distance, The example in which the sum is converted to the number of clocks corresponding to the sum of the square values of the distances, that is, the sum of the Euclidean distances, has been described. In the present embodiment, each distance calculation circuit (DP ₁₁ , DP ₁₂ ,... DP _RW ) calculates the square value of each distance, and the calculated square value of each distance is converted into a distance / clock number conversion circuit (DC ₁ , DC ₂ ,... DC _R ) will be described as an example of conversion to the number of clocks.

FIG. 11 is a schematic configuration diagram illustrating a configuration example of the distance calculation circuit in the present embodiment. The distance calculation circuit DP _ij (1 ≦ i ≦ R, 1 ≦ j ≦ W) includes, for example, calculation circuits 61 to 64 when the distance is expressed by 4 bits, that is, when M = 4. A group 60, a shift register 65, and a multiplier bit shift circuit 66 are included. The shift register 65 is a 3-bit shift register, and is configured by connecting three flip-flop circuits 65a to 65c in series.

In the example of FIG. 11, the arithmetic circuits 61 to 64 and the flip-flop circuits 65a to 65c are arranged in this order from the most significant bit to the least significant bit (all 7 bits). The arithmetic circuit 61 to 64, respectively, and the reference data (Re _S) inverting the reference data obtained by inverting the _{(Re SQ),} the value of each bit of the search data (an In _S) is input. S is an integer satisfying 1 ≦ S ≦ 4.

When the signal value of the square calculation control signal SQ input from the control circuit (not shown) is “0”, the arithmetic circuits 61 to 64 have an absolute value difference (AD ₁ ) between the input inverted reference data and the search data. , AD ₂ , AD ₃ , AD ₄ ). That is, in this case, the arithmetic circuits 61 to 64 function as a subtracter.

When the signal value of the square calculation control signal SQ input from the control circuit (not shown) is “1”, the arithmetic circuits 61 to 64 function as adders. That is, the arithmetic circuit 61, the augend value M1 which will be described later is input, adds the shift operation value TE _0, and outputs the addition result as the shift operation value TE ₁ to the arithmetic circuit 62. Arithmetic circuit 62, the augend M2 inputted, adds the shift operation value TE ₁ inputted from the arithmetic circuit 61, and outputs the addition result as the shift operation value TE ₂ to the arithmetic circuit 63. Arithmetic circuit 63, the augend M3 input, adds the shift operation value TE ₂ inputted from the arithmetic circuit 62, and outputs the addition result as the shift operation value TE ₃ to the arithmetic circuit 64. Arithmetic circuit 64, the augend M4 inputted, adds the shift operation value TE ₃ inputted from the arithmetic circuit 63, the addition result, the flip-flop circuit 65a of the shift register 65 as the shift operation value TE ₄ Output.

In addition, the arithmetic circuits 61 to 64 receive a control signal indicating a Manhattan distance (MD) or a Euclidean distance (ED) from a control circuit (not shown). In the present embodiment, the signal value in the case of the Manhattan distance (MD) is “1”, and the signal value in the case of the Euclidean distance (ED) is “0”. Arithmetic circuits 61 to 64 outputs _{DOUT k (0 ≦ k ≦ 4} ) indicating the absolute value difference AD _S or sum above distance / clock number conversion circuit DC _i in response to a control signal.

Flip-flop circuit 65a is a shift operation value TE ₄ inputted from the arithmetic circuit 64, in synchronization with the clock signal CLK, and outputs to the flip-flop circuit 65b as the shift operation value TE _5, showing a shift operation value TE ₅ It outputs an output value DOUT ₅ distance / clock number conversion circuit DC _i.

Flip-flop circuit 65b is a shift operation value TE ₅ inputted from the flip-flop circuit 65a, in synchronization with the clock signal CLK, and outputs to the flip-flop circuit 65c as a shift operation value TE _6, the shift operation value TE ₆ the outputs an output value DOUT ₆ distance / clock number conversion circuit DC _i shown.

Flip-flop circuit 65c is output shift operation value TE ₆ inputted from the flip-flop circuit 65b, in synchronization with the clock signal CLK, and the shift operation value TE ₇ as an output value DOUT ₇ to distance / clock number conversion circuit DC _i To do.

That is, when the square calculation control signal SQ (= 1) is inputted, the arithmetic circuit calculates a shift operation value TE _S at 61 to 64, the arithmetic circuit 61 to 64 and the shift register 65, every clock, each shift A process of shifting the calculated value by 1 bit in the lower direction is performed. This process is performed until a signal indicating the end of the square calculation is input from a control circuit (not shown).

  Here, the circuit configuration of the arithmetic circuits 61 to 64 will be described. FIG. 12 is a diagram illustrating a circuit configuration example of the arithmetic circuits 61 to 64. In the example of FIG. 12, the arithmetic circuits 61 to 64 include multiplexers 71, 72, and 78, a full adder 73, a D flip-flop circuit 74, an inversion control circuit 75, a latch circuit 76, and an AND circuit 77. Have.

The multiplexer 71 receives the search data In _S (S is an integer satisfying 1 ≦ S ≦ 4) and the shift operation value TE _S−1 . Multiplexer 72 receives the reference data RE _S inversion reference data _{Re SQ} obtained by inverting, the augend _{M S} inputted from the AND circuit 77.

The multiplexers 71 and 72 receive a square calculation control signal SQ from a control circuit (not shown). In the present embodiment, when the signal value of the square calculation control signal SQ is “1”, the distance calculation circuit DP _ij performs a square calculation of the distance, and when the signal value is “0”, the distance calculation circuit In DP _ij , the absolute value (absolute value difference) of the difference between the reference data and the search data is calculated.

The multiplexer 71 outputs the search data In _S to the full adder 73 when the signal value of the square calculation control signal SQ is “0”, and the shift operation value TE _S−1 when the signal value is “1”. Is output to the full adder 73. The multiplexer 72 outputs the inverted reference data Re _SQ to the full adder 73 when the signal value of the square calculation control signal SQ is “0”, and the added value M _S when the signal value is “1”. Output to full adder 73.

The full adder 73 has a terminal CB that receives the carry value from the lower bits and a terminal CN or CA ₁ that outputs the carry value to the upper bits. Note that the terminal CB in the arithmetic circuit 64 receives the carry value in the arithmetic circuit 61 instead of the carry value from the lower bits. The arithmetic circuit 61 to correspond to the most significant bit, and outputs a carry value in the arithmetic circuit 61 from the terminal CA ₁ to the arithmetic circuit 64.

The terminal CB in the arithmetic circuit 64 is connected to the AND circuit 64a (see FIG. 11). The AND circuit 64a, a control signal from a control circuit (not shown) and (MD or ED), the carry value output from the terminal CA ₁ of the arithmetic circuit 61 is inputted, the signal value of the control signal and column The result of calculating the logical product of the raised values is output.

That is, the full adder 73 in the arithmetic circuits 61 to 64 includes the search data In _S or the shift operation value TE _S-1 output from the multiplexer 71 and the inverted reference data Re _SQ or the added value M output from the multiplexer 72. _S and the carry value to be input are added. Hereinafter, more specific processing of the full adder 73 in the arithmetic circuits 61 to 64 will be described.

Since the arithmetic circuit 61 corresponds to the most significant bit, the shift arithmetic value in the upper bit is not input to the multiplexer 71. Therefore, when the square calculation control signal SQ indicating the signal value “1” is output from the control circuit (not shown), the arithmetic circuit 61 inputs “0” as the shift arithmetic value TE ₀ . Therefore, the full adder 73 in the arithmetic circuit 61 uses the added value M ₁ output from the multiplexer 72, the carry value of the arithmetic circuit 62 input from the terminal CB, and the shift operation value TE ₀ (= 0). Addition is performed, and the addition result is output to the D flip-flop circuit 74.

When the square calculation control signal SQ indicating the signal value “1” is output from the control circuit, the full adders 73 in the arithmetic circuits 62 and 63 are added values M ₂ and M ₃ output from the multiplexer 72, respectively. Then, the carry values of the arithmetic circuits 63 and 64 input from the terminal CB and the shift arithmetic values TE ₁ and TE ₂ input from the arithmetic circuits 61 and 62 are added, and the addition result is sent to the D flip-flop circuit 74. Output.

When the square calculation control signal SQ indicating the signal value “1” is output from the control circuit, the full adder 73 in the arithmetic circuit 64 ANDs the added value M ₄ output from the multiplexer 72 and the terminal CB. The value input from the circuit 64 a and the shift operation value TE ₃ input from the arithmetic circuit 63 are added, and the addition result is output to the D flip-flop circuit 74. That is, a control signal (= 1) indicating the Manhattan distance (MD) is input to an AND circuit (not shown), and the carry value “1” from the terminal CA ₁ of the arithmetic circuit 61 is an AND circuit (not shown). Then, “1” is input to the terminal CB of the arithmetic circuit 64 and added.

Next, the inversion control circuit 75 in the arithmetic circuit 61 to 64, has a terminal CA ₂ receiving a signal indicating a carry value of the most significant bits from the arithmetic circuit 61, arithmetic circuit input via the terminal CA ₂ When the carry value of 61 = “0”, the calculation result output from the full adder 73 is inverted, and the inverted value (absolute value difference AD _S ) is output to the latch circuit 76. When the carry value of the arithmetic circuit 61 is “1”, the calculation result output from the full adder 73 is output to the latch circuit 76 without being inverted.

The latch circuit 76 in the arithmetic circuits 61 to 64 receives the square calculation control signal SQ. The latch circuit 76 stores the absolute value difference (AD _S ) output from the inversion control circuit 75 at the timing when the signal value of the square calculation control signal SQ changes from “0” to “1”. Then, the absolute value difference (AD _S ) is output to the AND circuit 77, the multiplier bit shift circuit 66, and the multiplexer 78.

The AND circuit 77 in the arithmetic circuits 61 to 64 outputs a logical product value of the multiplier bit MB input from the multiplier bit shift circuit 66 and the absolute value difference (AD _S ) input from the latch circuit 76 to the multiplexer 72. To do.

After the absolute value difference AD _S is calculated by the control circuit (not shown), the clock signal CLK is input to the D flip-flop circuit 74 in the arithmetic circuit 61 to 64. The D flip-flop circuit 74 in the arithmetic circuits 61 to 64 inputs the addition result output from the full adder 73 at the timing when the clock of the clock signal CLK rises. Then, at the timing when the clock falls, the addition result is output as a shift operation value (TE _S ) to the multiplexer 71 or the shift register 65 in the lower bit arithmetic circuit.

The multiplexer 78 in the arithmetic circuits 61 to 64 receives a control signal indicating a Manhattan distance (MD) or a Euclidean distance (ED) from a control circuit (not shown). For example, in this example, the signal value in the case of Manhattan distance (MD) is “1”, and the signal value in the case of Euclidean distance (ED) is “0”. When the control signal (= 1) indicating the Manhattan distance (MD) is input, the multiplexer 78 outputs the calculation result (absolute value difference AD _S ) output from each latch circuit 76 in the arithmetic circuits 61 to 64. Further, when the control signal (= 0) indicating the Euclidean distance (ED) is input, the multiplexer 78 outputs the calculation result (TE _S ) output from each D flip-flop circuit 74 in the arithmetic circuits 61 to 64. .

Multiplier bit shift circuit 66 in synchronism with the clock signal CLK, receives the value of the absolute value difference AD _S outputted from the latch circuit 76 in the arithmetic circuit 61 to 64. The multiplier bit shift circuit 66 outputs the absolute value difference to the AND circuit 77 as a multiplier bit MB in order from the lower bits, that is, in the order of the absolute value difference AD ₄ → AD ₃ → AD ₂ → AD ₁ . When the multiplier bit shift circuit 66 outputs the value of the absolute value difference (AD ₁ ) of the most significant bit, it outputs a signal indicating the end of the square calculation to the control circuit (not shown).

The AND circuit 77 outputs a logical product value of the multiplier bit MB input from the multiplier bit shift circuit 66 and the absolute value difference AD _S input from the latch circuit 76 to the multiplexer 72 as an added value M _S. .

FIG. 13 is a diagram illustrating a process of square calculation in the distance calculation circuit DP _ij . This example shows a case where the absolute value difference AD _S = 7 ₁₀ = 0111 ₂ between the search data and the reference data. In the example of FIG. 13, each AND circuit 77 of the arithmetic circuits 61 to 64 has a multiplier bit MB in the order of “1 → 1 → 1 → 0” from the lower bit of the absolute value difference in synchronization with the clock signal CLK. It is input by a multiplier bit shift circuit 66. In addition, an initial value “0” is set as the shift operation value TE _{S−1 in} the multiplexer 71 of the arithmetic circuits 61 to 64.

The distance calculation circuit DP _ij starts the square calculation when the square calculation control signal SQ (= 1) is input from the control circuit. In the arithmetic circuits 61 to 64, the shift arithmetic value TE _S-1 “0000” set in each multiplexer 71 is input to the full adder 73 (step S1). In addition, an added value M _S “0111” indicating a logical product of the multiplier bit “1” and the absolute value difference AD _S “0111” is input to each multiplexer 72 from the AND circuit 77 of the arithmetic circuits 61 to 64. The added value M _S “0111” is input from the multiplexer 72 to the full adder 73 (step S2). In the full adders 73 of the arithmetic circuits 61 to 64, the shift operation value TE _S-1 “0000” and the added value M _S “0111” are added and output. The addition result “0111” is input to the D flip-flop circuits 74 of the arithmetic circuits 61 to 64 at the timing when the first clock rises, and is held until the first clock falls (step S3).

When the first clock falls, the added values M _S “0111” indicating the logical product of the multiplier bit “1” and the absolute value difference AD _S “0111” are output from the AND circuits 77 of the arithmetic circuits 61 to 64 to the multiplexers 72. The added value M _S “0111” is input from each multiplexer 72 to the full adder 73 (step S4). Further, in step S3, addition result held in the D flip-flop circuit 74 of the arithmetic circuit 61 to 64 "0111", as the shift operation value TE _S, a multiplexer 71 of the arithmetic circuit 62 to 64, the shift register 65 The data is output to the flip-flop circuit 65a (step S5).

From the fall of the first clock to the rise of the second clock, the full adder 73 of the arithmetic circuits 61 to 64 adds the added value M _S “0111” and the shift operation value TE _S−1 “0111”. Is output. The addition result “1010” is input to the D flip-flop circuit 74 of the arithmetic circuits 61 to 64 at the timing when the second clock rises, and is held until the second clock falls. Further, the shift operation value TE ₄ “1” input to the flip-flop circuit 65a of the shift register 65 is held until the second clock falls (step S6).

When the second clock falls, the AND circuit 77 of the arithmetic circuits 61 to 64 inputs the added value M _S “0111” indicating the logical product of the multiplier bit “1” and the absolute value difference “0111” to each multiplexer 72. Then, the added value M _S “0111” is input from each multiplexer 72 to each full adder 73 (step S7).

Further, when the second clock falls, in step S6, the results summed held in the D flip-flop circuit 74 of the arithmetic circuit 61 to 64 "1010", as the shift operation value TE _S, the arithmetic circuit 62 to 64 It is output to the multiplexer 71 and the flip-flop circuit 65a. The multiplexer 71 of the arithmetic circuits 61 to 64 inputs “ ₀ , ₁ , ₀ , ₁ ” to the full adder 73 as the shift arithmetic values TE ₀ , TE ₁ , TE ₂ , TE ₃ . The flip-flop circuit 65a outputs the held shift operation value TE ₄ “1” as the shift operation value TE ₅ (= DOUT ₅ ) to the flip-flop circuit 65b, and the shift operation value TE ₄ output from the operation circuit 64. “0” is input (step S8).

From the falling edge of the second clock to the rising edge of the third clock, the full adder 73 of the arithmetic circuits 61 to 64 adds the added value M _S “0111” and the shift operation value TE _S−1 “0101”. Is output. The addition result “1100” is input to the D flip-flop circuit 74 of the arithmetic circuits 61 to 64 at the timing when the third clock rises, and is held until the third clock falls. Further, in the flip-flop circuit 65a, the shift operation value TE ₄ “0” from the arithmetic circuit 64 is held until the third clock falls. In the flip-flop circuit 65b, the shift operation value TE ₅ “1” from the flip-flop circuit 65a is held until the third clock falls (step S9).

When the third clock falls, the added value M _S “0000” indicating the logical product of the multiplier bit “0” and the absolute value difference “0111” is input to each multiplexer 72 from the AND circuit 77 of the arithmetic circuits 61 to 64. The added value M _S “0000” is input from each multiplexer 72 to the full adder 73 (step S10).

Further, in step S9, the result summed held in the D flip-flop circuit 74 of the arithmetic circuit 61 to 64 "1100" is 3 when the clock cycle falls, the shift operation value TE _S, the arithmetic circuit 62 to 64 It is output to the multiplexer 71 and the flip-flop circuit 65a. The multiplexer 71 of the arithmetic circuits 61 to 64 inputs “ ₀ , ₁ , ₁ , ₀ ” to the full adder 73 as the shift arithmetic values TE ₀ , TE ₁ , TE ₂ , TE ₃ . The flip-flop circuit 65 a outputs the held shift operation value TE ₄ “0” as the shift operation value TE ₅ , and receives the shift operation value TE ₄ “0” output from the operation circuit 64. The flip-flop circuit 65b outputs the held shift operation value TE ₅ “1” as the shift operation value TE ₆ (= DOUT ₆ ), and uses the shift operation value TE ₅ “0” output from the flip-flop circuit 65a. input. The flip-flop circuit 65c receives the shift operation value TE ₆ “1” output from the flip-flop circuit 65b (step S11).

When the multiplier bit shift circuit 66 outputs the multiplier bit MB “0” to each of the arithmetic circuits 61 to 64 while the third clock is falling, a signal indicating the end of the square calculation is sent to the control circuit (not shown). Is output. The adder value M _S “0000” and the shift operation value TE _S-1 “0110” are added in the full adder 73 of the arithmetic circuits 61 to 64 until the fourth clock rises from the fall of the third clock. Is output. When the fourth clock rises, the addition result “0110” is output to the D flip-flop circuit 74 as the shift operation values TE ₁ , TE ₂ , TE ₃ , TE ₄ (step S12). In the shift register 65, the values (0, 0, 1) of the shift operation values TE ₄ , TE ₅ , TE ₆ input in step S11 are held as shift operation values TE ₅ , TE ₆ , TE _7. .

When the fourth clock falls, the shift calculation values TE ₁ , TE ₂ , TE ₃ , TE ₄ held in the respective D flip-flop circuits 74 are output to the respective multiplexers 78 in the arithmetic circuits 61 to 64. , DOUT ₀ = 0, DOUT ₁ = 0, DOUT ₂ = 1, DOUT ₃ = 1, and DOUT ₄ = 0 are output to the distance / clock number conversion circuit DC _i . Further, in the shift register 65, the shift operation values TE ₅ “0”, TE ₆ “0”, and TE ₇ “1” held in the flip-flop circuits 65a to 65c are respectively decreased when the fourth clock falls. , DOUT ₅ = 0, DOUT ₆ = 0, and DOUT ₇ = 1 are output to the distance / clock number conversion circuit DC _i . That is, DOUT _{0 to} DOUT ₇ are output to the distance / clock number conversion circuit DC _i as the distance signal D _ij indicating the square value (= 49 ₁₀ ) of the absolute value difference (= 7 ₁₀ ).

The distance / clock number conversion circuit DC _i converts the square value of the absolute value difference output from the distance calculation circuit DP _ij into a clock number. Figure 14 is a diagram showing a schematic configuration of a counter coincidence detection circuit 31 at a distance / clock number conversion circuit DC ₁ shown in Figure 2A. As shown in FIG. 14, the counter coincidence detection circuit 31 includes a counter 311 and a coincidence detection circuit 3121.

The counter 311 receives a clock signal CLK from the buffer 21 and a reset signal RST from a control circuit (not shown) of the associative memory 100. Upon receiving the reset signal RST, the counter 311 resets the counter value, and counts up the M-bit bit value in ascending order in synchronization with the clock signal CLK. The counter 311 sequentially outputs the counter value CV ₁₁ to the coincidence detection circuit 3121 in synchronization with the clock signal CLK.

Match detection circuit 3121 receives clock signal CLK from buffer 21 and receives search start signal SB from a control circuit (not shown). The coincidence detection circuit 3121 receives the counter value CV ₁₁ from the counter 311 and the distance signal D ₁₁ from the distance calculation circuit DP ₁₁ . Coincidence detecting circuit 3121, rises the search start signal SB, and counts the number of clocks of the clock signal CLK when the counter value _{CV 11} matching the distance signal _{D 11} is obtained. Then, the coincidence detection circuit 3121 outputs a coincidence signal MTH1 indicating the timing of counting the number of clocks to the counter coincidence detection circuit 32. When the coincidence detection circuit 3121 outputs the coincidence signal MTH1, the operation is stopped.

  Note that each of the counter coincidence detection circuits 32 to 3W shown in FIG. 2A has the same configuration as the counter coincidence detection circuit 31 shown in FIG. Counter match detection circuits 32 to 3W stop operating until they receive match signals MTH1 to MTHW-1 from match detection circuits 3121 of counter match detection circuits 31 to 3W-1, and receive match signals MTH1 to MTHW-1. To start operation.

At the timing when the coincidence signal MTHW is outputted from the counter coincidence detection circuit 3W, the timing signal C _i for the distance / clock number conversion circuit DC _i is outputted to the Winner detector 20. That is, the timing signal C _i is a clock corresponding to the sum of square values of the absolute value differences indicated by the distance signals D _{i1 to} D _iW input to the distance / clock number conversion circuit DC _i , that is, the sum of the Euclidean distance values. It is output when the number is obtained.

In the above example, the example of performing the search using the Euclidean distance has been described. However, the control signal (MD) indicating the Manhattan distance is supplied to the multiplexer 78 of the arithmetic circuits 61 to 64 shown in FIG. Are input from each multiplexer 78, a distance signal D _ij represented by an absolute value difference (AD _{1 to} AD ₄ ) between the search data and the reference data is output. In this case also, similar to the Euclidean distance, the distance / clock number conversion circuit DC _i, may be counted the number of clocks of the clock signal CLK when the counter value CV _ij matching distance signal D _ij is obtained.

  In the fourth embodiment described above, the distance calculation circuit can calculate the absolute value difference between the search data and the reference data, and can also perform the square calculation of the absolute value difference. Therefore, the circuit area can be reduced as compared with the case where the absolute value difference calculation and the absolute value difference square calculation are realized by separate circuits. It can also be applied to searches using either the Manhattan distance or the Euclidean distance.

<Modification>

(1) In the first embodiment described above, an example of performing a search using the Euclidean distance has been described. However, the search may be performed using any of the Manhattan distance and the Euclidean distance. FIG. 15 is a schematic diagram illustrating a configuration example of a counter coincidence detection circuit in the present modification. The counter match detection circuit 31 includes a demultiplexer 31x, and the counter match detection circuit 32 includes a demultiplexer 32x.

A control signal SL indicating a Manhattan distance or an Euclidean distance is input to the demultiplexers 31x and 32x from a control circuit (not shown). The clock number conversion circuit 31a, the distance signal D ₁₁ and the clock count and matches, outputs the H level coincidence detection signal to the demultiplexer 31x. When the input control signal indicates a Manhattan distance, the demultiplexer 31x outputs the coincidence detection signal output from the clock number conversion circuit 31a to the buffer 22 and the clock number conversion circuit 31a and stops its operation.

When the coincidence detection signal is output from the counter coincidence detection circuit 31, the clock signal CLK is input from the buffer 22 to the clock number conversion circuit 32a. The clock number conversion circuit 32a, the distance signal D ₁₂ and the clock count and matches, outputs the H level coincidence detection signal to the demultiplexer 32x. Demultiplexer 32x is inputted control signal to indicate Manhattan distance, and outputs a timing signal C ₁ to Winner detector 20 at the timing when the coincidence detection signal of H level from the clock number conversion circuit 32a is input Stop operation.

When a control signal indicating the Euclidean distance is input to the demultiplexers 31x and 32x, the multiplexers 31x and 32x respectively receive the H level coincidence detection signals from the clock number conversion circuits 31a and 32a to the counters 31b and 32b. outputs, as with the first embodiment described above, and repeats the operation until the counter 31b, and the 32b counter value and the distance signal _{D 11, D 12} of matching.

(2) In the third embodiment described above, the example in which the target bit is expanded one bit at a time from the most significant bit to the lower direction when detecting the coincidence between the distance and the counter value has been described. It may be expanded. Further, the number of bits to be expanded may be different every time the target bit is expanded. For example, when the distance and the counter value are 6 bits long, a match search is performed for the most significant bit, and when the match detection signal for any reference data rises, the second and third two bits Is extended to the upper 3 bits. For any reference data, when the match detection signal for the upper 3 bits rises, the fourth to sixth bits are set as the next search target bits, and the target bits are extended to all bits.

  The present invention is applied to an associative memory.

DESCRIPTION OF SYMBOLS 1 ... Memory part, 2 ... Row decoder, 3 ... Column decoder, 4 ... Read / write circuit, 5 ... Search data storage circuit, 6, 77, 64a, 300c, 313d, 313e ... AND circuit, 10 ... Memory array part 20 ... Winner detector, 21-2W ... buffer, 31-3W, ... counter coincidence detection circuit, 31a, 32a ... clock number conversion circuit, 31b, 32b, 300b, 311, 312 ... counter, 31c, 31c ', 32c 32c ', 313, 3121 ... coincidence detection circuit, 40 ... effective bit setting unit, 61-64 ... arithmetic circuit, 65 ... shift register, 65a, 65b, 65c ... flip-flop circuit, 66 ... multiplier bit shift circuit, 71, 72, 78, 31d, 32d, 300a, 314 ... multiplexer, 73 ... full adder, 74 ... D flip-flop circuit, 5 ... Inversion control circuit, 76 ... Latch circuit, 300 ... Counter coincidence detection unit, 310, 320 ... Distance / clock number conversion unit, 312a-312c ... Selector, 312d-312f ... Frequency divider, 313a-313c ... EXNOR circuit, DC _{1 to} DC _R , DE _{1 to} DE _R ... Distance / clock number conversion circuit, DE _{11 to} DE _1W ... Counter coincidence detection circuit, DP _{11 to} DP _RW .

Claims (5)

Reference data storage means for storing R (R is an integer of 2 or more) reference data each having a bit length of M × W (M is an integer of 1 or more, W is an integer of 2 or more) bits;
R × W absolute value differences representing absolute values of differences between the search data to be searched and the reference data provided corresponding to the R reference data and having a bit length of M × W bits, First distance calculating means for calculating the distance between the search data and the reference data;
A timing signal that outputs a timing signal indicating the timing at which the number of clocks matching the Euclidean distance between the reference data and the search data is detected for each reference data using the distance calculated by the first distance calculating unit Timing signal output means for performing output processing on the R reference data;
Based on R timing signals output from the timing signal output means, k timing signals (k is an integer satisfying 1 ≦ k <R) are detected in order of output of the timing signals, and detected. Match signal output means for outputting the k timing signals as match signals indicating the similarity between the search data and the reference data;
Associative memory.   The timing signal output means repeats a process of detecting the number of clocks matching the absolute value difference as many times as the timing signal output process matches each of the W absolute value differences for each reference data. The associative memory according to claim 1, wherein the associative memory outputs the timing signal indicating the timing at which the number of clocks matching the Euclidean distance between the reference data and the search data is detected. By calculating the square value of each of the W absolute value differences calculated by the first distance calculation means for each reference data, the distance between the search target search data and the reference data is A second distance calculating means for calculating a square value of W absolute value differences;
The timing signal output means detects, as the timing signal output process, the number of clocks that matches the sum of the squares of the W absolute value differences calculated by the second distance calculation means for each reference data. The associative memory according to claim 1, wherein the timing signal indicating the timing at which the number of clocks matching the Euclidean distance between the reference data and the search data is detected is output. A selection means for selecting either the Manhattan distance or the Euclidean distance;
The timing signal output means, when the Manhattan distance is selected by the selection means, the timing indicating the timing at which the number of clocks matching the sum of the W absolute value differences is detected for each reference data 4. The associative memory according to claim 1, wherein a signal is output, and when the Euclidean distance is selected by the selection unit, the timing signal output process is performed on each reference data. 5. . Reference data storage means for storing R (R is an integer of 2 or more) reference data each having a bit length of M × W (M is an integer of 1 or more, W is an integer of 2 or more) bits;
Distance calculating means provided corresponding to the R reference data and calculating R × W distances between search data to be searched having a bit length of M × W bits and the reference data;
For each of the reference data, among the bits representing the distance calculated by the distance calculating means, a coincidence detecting means for outputting a coincidence detection signal at a timing at which the number of clocks that matches the set target bit value is detected,
The target bits are set in predetermined bit units in order from the most significant bit representing the distance calculated for each reference data, and the coincidence detection signal for the target bits is output for any of the reference data Bit setting means for extending the target bit each time,
A timing signal output means for performing a process of outputting a timing signal indicating a timing at which the coincidence detection signal is output for all the bits representing the distance for each of the reference data;
Based on R timing signals output from the timing signal output means, k timing signals (k is an integer satisfying 1 ≦ k <R) are detected in order of output of the timing signals, and detected. Match signal output means for outputting the k timing signals as match signals indicating the similarity between the search data and the reference data;
Associative memory.

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