JP6212728B2 - Random number generator and mapping operation circuit - Google Patents

Description

  The present invention relates to a random number generation device and a mapping operation circuit that can be used in the random number generation device.

  Strictly speaking, pseudo-random numbers created by a computer are generated according to certain rules, and are not strictly random numbers. Also, with the software-like pseudo-random number generation method, there is a risk that the pseudo-random number generation program will leak if the key issuing server is hacked. In this case, there is a risk that an encryption key issue (random number generation) pattern will be grasped.

  A well-known linear shift register system is known as pseudorandom number generation. These can be easily made into an electronic circuit and can be provided at high speed, but can be fundamentally reproduced by software. Therefore, an (analog) effect such as “difficult to reproduce with software” cannot be obtained.

  True random number generation generally has a problem that its generation speed is slower than that of a pseudo-random number generation method. In addition, there are those that use thermoelectrons as true random numbers, but they are biased at 1/0 and require a mechanism for correcting them. Even if an attempt is made to use a true random number as a random number to be used in computer simulation, the generation of the true random number is slow, and it is not in time for the high-speed processing of today's computers. Therefore, there is a problem that the total processing time becomes longer due to the generation of genuine random numbers as a bottleneck. For this, it is conceivable to increase the throughput by introducing a large number of true random number generators in parallel. However, when this method is used, there is a problem that the system becomes large.

  Patent Document 1 discloses a method of A / D converting an analog chaotic signal, acquiring a random number after data compression processing, and acquiring a random value from the analog chaotic signal. In the method of Patent Document 1, only analog chaos is digitized, and random numbers that are difficult to reproduce are not obtained by adding an indeterminate element to the chaos digital arithmetic circuit.

  Moreover, according to the random number generation circuit that generates an analog chaotic signal with a simple LRC closed circuit and outputs it as random number data after A / D conversion, an output that looks like a random number can be obtained. Correlation may be discovered by measuring performance quantitatively, and a device for removing the correlation is required.

  Patent Document 2 discloses a circuit that performs analog-to-digital conversion of analog chaotic signals to extract high-quality random values. However, the amount of data to be extracted is only 1 bit per clock pulse, and the random number generation speed depends on the frequency of the optimum external periodic signal (sine wave) that generates an analog chaotic signal, I can't expect that much speed.

  On the other hand, it is theoretically known that a logistic map takes a short period with a certain initial value. There are 0.25, 0.5, and 0.75 values for period 1, and care must be taken when selecting the initial value.

  There are some other parameters that take a short period, and it is reported that these parameters have these period bands even if they are implemented by fixed operations. For this reason, it is necessary to set an initial value with care and to avoid entering into a short loop. However, in a fixed operation, there is a concern that these parameters may coincide with a rounding error in the process of mapping.

When a chaotic map is implemented with a fixed calculation, there is a mechanism that eventually falls into a considerably shorter period than the maximum calculation accuracy.
When the calculation accuracy is N = 6 [bit] according to the integer calculation logistic map (7) described later, the mapping from the initial value X ₀ = 25 is
25 → 60 → 15 → 45 → 53 → 36 → 63 → 3 → 11 → 36
It can be seen that a transition occurs and falls into a period band of period length 4 of 36 → 63 → 3 → 11.
In addition, in the initial value X ₀ = 51
51 → 58 → 21 → 56 → 28 → 63 → 3 → 11 → 36 → 63
It can be seen that the transition occurs and falls into a period band of 36 → 63 → 3 → 11 with a period length of 4 similarly.

  For example, the maximum value of the calculation accuracy N = 6 [bit] is 64, but the cycle is considerably short for the calculation accuracy. Since this has the same mechanism even when the calculation accuracy is increased, there is a problem that the random number performance is deteriorated when random number generation is performed by mounting a chaotic mapping digitally. For this reason, the idea which does not fall into a period is fundamentally required.

  Further, Patent Document 3 discloses a logistic map for performing a fixed operation. However, this mapping has a definite presence of random number generation patterns and periods due to the nature of digital finite precision arithmetic.

  Further, Patent Document 4 and Patent Document 5 propose that the random number performance is statistically improved by means of extending the period for the problem of a short period due to fixed arithmetic implementation. However, when a device for extending the cycle is used, adding a register, a control circuit, or the like increases the circuit scale and processing steps, and increases the cost at the design stage.

  Moreover, there is a concern that it is difficult to scale up / down the processing performance and circuit area flexibly by adding the function into the arithmetic processing process and making it complicated. In addition, even if a mechanism for extending the period is added, there is a possibility that a short period band may exist in the map sequence, but there is a problem that it is not known unless a full search is performed for the period band. is there.

  Furthermore, if random number generation by logistic mapping is to be implemented by software, as will be described later, in order to pass the NIST random number test, the calculation accuracy must be 64 bits or more, and the maximum calculation width is 128 bits or more. It becomes. The current personal computer has a maximum calculation accuracy width of 64 bits, and if it is intended to create a random number with good randomness, it is necessary to use a multiple length arithmetic library, and the speed of random number generation is reduced. For this reason, it is desirable to use a dedicated circuit.

  Patent Document 6 discloses a one-dimensional mapping circuit using a CMOS electronic circuit. However, the internal state determined by the analog electronic circuit of the logistic map needs to be A / D converted and taken out as a random number.

  Also, in the implementation of one-dimensional mapping digital operations, if the configuration is such that the upper bits of the mapping are extracted, the randomness is statistically poor, so it is necessary to devise a method such as extracting the lower bits from the middle. is there. It is desirable to conduct a random number test in advance at the design stage, and to obtain a statistical grasp in advance.

  Further, in Cited Document 7, randomness is improved so as to promote the high speed of digital computation and the irregularity of analog by combining thermal noise with a feedback shift register generally known as a random number generator. The proposal which aimed at is made.

  The feedback shift register used in the cited document 7 is ideally made in frequency and period, and a pattern once generated is not generated twice in the period. For this reason, even if the sequence is fluctuated by an irregular signal, the same pattern is returned to the original, and there is a concern that a random number that is patterned in one direction is repeatedly output.

  Moreover, there is a concern that thermal noise repeats a periodic pattern depending on physical conditions, and it also depends on the quality after manufacture. For this reason, it is more desirable that a random number test is performed in advance at the design stage so that statistical grasping can be performed in advance.

  Further, Patent Document 8 discloses a random number generation circuit for a logistic map in which a 32-bit operation is put in a separate register to extend the operation accuracy. However, it remains a logistic map, and it seems inevitable that periodicity will occur.

Japanese Patent No. 3036698 specification JP 2008-123374 A JP 2004-93756 A JP 2005-228169 A Japanese Patent Laid-Open No. 9-292978 JP-A-7-262159 Japanese Patent Laid-Open No. 51-224165 JP 2005-228169 A

  In general, a logistic map is known as a mathematically generated chaotic phenomenon that is said to have unpredictability. Since the mathematical formula is simple, it can be used as a pseudo-random number generation circuit with a small circuit scale. And the logistic map has the feature that the unpredictability is promoted only by giving a slight error to the initial value or the calculated value due to its chaotic behavior known as the butterfly effect.

  The present invention has been made in view of the characteristics of such a logistic map and the current state of the random number generation technology as described above, and its purpose is that it can be reduced in size and speed, and the sequence is unpredictable. To provide a random number generator capable of generating a high-quality random number sequence that cannot be reproduced. It is another object of the present invention to provide a mapping operation circuit that can be used in this random number generation device.

The random number generation device according to the present invention includes an analog chaos generation circuit that generates an analog chaos signal by an analog chaos generation circuit, and converts the analog chaos signal to a digital value of 1 or 0 using different reference voltages. Using n differential amplifier circuits, n-bit data in which 1 bit out of n bits is a selection instruction signal is obtained, and one of n registers is selected based on the n-bit data selection instruction signal. In the mapping operation circuit based on the variation data, a variation data generation unit including a bit extraction / A / D conversion circuit that obtains variation data by digital conversion by extracting the data, a map operation circuit that performs logistic mapping, Data variation means for causing variation in mapping, and random value acquisition for acquiring a random value based on the mapping result by the mapping operation circuit Characterized by comprising a stage.

  In the random number generation device according to the present invention, the fluctuation data generation unit is characterized in that a part of the data obtained by digitizing the chaotic signal is used as the fluctuation data as it is or by performing a predetermined calculation.

  In the random number generation device according to the present invention, the data variation means replaces the variation data with a part of the mapping data.

  In the random number generation device according to the present invention, the data changing means generates the change in the mapping based on the calculation of the fluctuation data and at least a part of the mapping data.

  The random number generation device according to the present invention is characterized in that the random value acquisition means uses the mapping result obtained by the mapping calculation circuit as it is or performs a predetermined calculation to obtain a random value.

  In the random number generation device according to the present invention, the analog chaos generation circuit changes a circuit constant at a predetermined timing.

Mapping operation circuit according to the present invention, and the multiplier X _i, the multiplication result of the multiplicand is the result of subtracting the multiplier X _i from _{^{2 N (2 N -X i)}} , defined by the equation multiplying the constant a that the mapping operation circuit for performing a logistic map by using the logistic equation, multiplication that multiplies a subtraction unit for subtracting the multiplier X _i from 2 ^N as the operation of obtaining the multiplicand, the multiplicand and the multiplier obtained by the subtraction unit And a shift operation unit that performs a shift operation corresponding to a constant a with respect to the result obtained by the multiplication unit, and rejects the lower N bits from the result obtained by the shift operation unit and performs the subtraction as the next multiplier And a first processing unit to be sent to the unit.

  The mapping operation circuit according to the present invention includes a multiplier register for placing a multiplier, a multiplicand register for placing a multiplicand, an adder, and a single supply source for supplying 1; An inverter that inverts the multiplier set in the multiplier register to obtain a complement, a first path that leads 1 to the adder from the output of the inverter and the one supply source, and the lead that is led to the adder It is characterized by comprising an output of the inverter and a second path for guiding the result of adding 1 from the one supply source to the multiplicand register.

  In the mapping operation circuit according to the present invention, one bit is extracted in order from the lower bits of the multiplier set in the shift register and the multiplier register, and the logical product of the one bit and the multiplicand set in the multiplicand register is obtained. Is obtained by an AND circuit, and the result is output to the adder, the initial data or the data obtained by shifting the output of the previous adder by the shift register using the adder, and the second And a third processing unit that outputs to the shift register and outputs the shift register until the processing is performed for all the bits of the multiplier placed in the multiplier register. The processing by the second processing unit and the third processing unit is repeatedly executed.

  According to the present invention, it is possible to reduce the size and increase the speed, and it is possible to generate a high-quality random number sequence whose sequence is unpredictable and cannot be reproduced.

The block diagram which shows embodiment of the random number generator of this invention. The block diagram which shows the analog chaos generation circuit used for embodiment of the random number generator of this invention. The block diagram which shows the circuit which is an analog chaos generating circuit used for embodiment of the random number generator of this invention, and can change a parameter automatically. The block diagram which shows the bit extraction and A / D conversion circuit used for embodiment of the random number generator of this invention. The block diagram which shows the change of an analog chaos voltage at the time of changing a parameter in the analog chaos generation circuit used for embodiment of the random number generator of this invention. The figure which shows the return map corresponding to the time series of a logistic map. The flowchart which shows operation | movement of the logistic map calculating part which concerns on embodiment of this invention. The flowchart which shows the operation | movement of the logistic map calculating part which concerns on embodiment of this invention in detail. The circuit diagram which shows the structure of the mapping arithmetic circuit used for embodiment of the random number generator of this invention. The circuit diagram which shows the structure of the control circuit used for embodiment of the random number generator of this invention. The specific wave form diagram which carried out the circuit simulation of the control circuit used for embodiment of the random number generator of this invention. The circuit diagram which shows the structure of the selector used for embodiment of the random number generator of this invention. The circuit diagram which shows the structure of the multiplier register | resistor used for embodiment of the random number generator of this invention. The circuit diagram which shows the structure of the multiplicand register used for embodiment of the random number generator of this invention. The circuit diagram which shows the structure of the adder used for embodiment of the random number generator of this invention. The circuit diagram which shows the structure of the shift register used for embodiment of the random number generator of this invention. The circuit diagram which shows the structure of the 1-bit shift circuit used for the shift register of embodiment of the random number generator based on this invention. The wave form diagram which carried out the circuit simulation of the logistic map calculating part used for embodiment of the random number generator of this invention. The flowchart of the bit multiplication by embodiment of the random number generator of this invention. The bit arrangement | sequence flow figure of the logistic mapping operation until random value extraction performed in Example 1 and Example 2 is performed. The figure which shows the Poincare plot of a negative resistance circuit. The figure which shows the time series when not changing the time series when changing 1 bit compulsorily in a logistic map.

  Embodiments of a random number generation device according to the present invention and a mapping operation circuit used therein will be described below with reference to the accompanying drawings. In each figure, the same components are denoted by the same reference numerals, and redundant description is omitted. FIG. 1 shows a configuration diagram of an embodiment of a random number generation device according to the present invention. The embodiment of the random number generation device includes a variation data generation unit 10 and a mapping operation circuit 21 that performs logistic mapping.

  The fluctuation data generation unit 10 generates an analog chaos signal by an analog chaos generation circuit and digitally converts the signal to obtain fluctuation data. The variation data generation unit 10 includes an analog chaos generation circuit 11 and a bit extraction / A / D conversion circuit 12.

  The map operation circuit 21 is included in the logistic map operation unit 20, and the logistic map operation unit 20 includes a map operation circuit 21, an initial value register 22, and a random number output circuit 23.

  The random number generation device includes a control circuit 30, which controls the outputs of the bit extraction / A / D conversion circuit 12, the mapping operation circuit 21, and the random number output circuit 23. Further, a clock signal is given from the outside to the control circuit 30 and the bit extraction / A / D conversion circuit 12, and a periodic signal is given to the analog chaos generation circuit 11 from the outside. The random number output circuit 23 functions as a random value acquisition unit that acquires a random value based on the mapping result obtained by the mapping operation circuit 21. The random value acquisition means can use the mapping result obtained by the mapping calculation circuit 21 as it is or perform a predetermined calculation to obtain a random value.

  In the present embodiment, a chaos signal is generated using an electronic circuit as the analog chaos generation circuit 11. The electronic circuit as the analog chaos generation circuit 11 may be any of a negative oscillation circuit, a series resonance circuit with a nonlinear inductance, a double scroll circuit, and the like, and an electronic circuit that generates analog chaos with another configuration. It may be.

  In the present embodiment, a negative resistance oscillation circuit as shown in FIG. 2 can be employed as the analog chaos generation circuit 11. That is, a parallel circuit of a capacitor C and a negative resistance MR is connected to the RL series circuit, and a signal of Ecos (ωt) is given to this circuit as a periodic signal from the outside.

In the present embodiment, the circuit of FIG. 2 is used as the analog chaos generation circuit 11, but the circuit shown in FIG. 3 may be used. In the circuit of FIG. 3, a capacitor C ₀ is connected instead of the capacitor C of FIG. 2, and a series circuit including capacitors (C _{1 to} C ₈ ) and switches (SW ₁ to SW ₈ ) is connected in parallel to the capacitor C _0. It is a thing. The opening and closing of the switch can be configured to be controlled by a random number (for example, 8 bits among them) obtained by a random number generator. That is, the analog chaos generation circuit can be configured to change the circuit constant at a predetermined timing.

  The bit extraction / A / D conversion circuit 12 can be configured as shown in FIG. 4, for example. The bit extraction / A / D conversion circuit 12 has a configuration for extracting one bit, and a basic circuit for one bit is configured by circuit elements arranged in a group in the horizontal direction in the figure. Therefore, the basic circuit is provided corresponding to the number of bits for dividing the chaotic signal. This bit extraction / A / D conversion circuit 12 is an A / D conversion circuit diagram for extracting bits from an analog chaotic signal, and is of a generally used high-speed A / D converter system.

  Here, the input analog chaotic signal is divided by a resistance element, and the divided signal is compared with a reference voltage by each differential amplifier circuit and converted to 1/0. The output of each differential amplifier circuit converted to 1/0 is transferred to the latch circuit at the next stage. In the latch circuit, the clock signal CLK is set to the H level at a desired cycle timing at which the random bit value is to be read from the analog chaos signal, and data is transferred to the exclusive OR circuit (Exclusive OR) in the next stage.

  Since the reference voltage of each differential amplifier circuit is set lower in order as it is closer to the GND voltage, the output group 2 of the latch circuit whose neighbors are “1” or “0” depending on each reference voltage when sampling the analog chaos voltage. Only one exclusive OR circuit at the 1/0 boundary outputs “1”.

  The 1/0 register is selected by the output of the exclusive OR circuit, and the selected 1/0 register outputs stored 1-bit data. Here, data 1/0 is alternately stored in the 1/0 register as shown in FIG. By this operation, the analog chaotic signal is converted into a digital signal, and 1-bit extraction is performed at every sampling period (clock signal CLK is at H level).

  Further, the 1/0 register is also inverted by 1 → 0 or 0 → 1 by the clock counter circuit every arbitrary number of clocks (number of acquired bits). This is performed to correct the 1/0 frequency shift by the amplitude value and to improve the random performance. As described above, the present embodiment includes a variation data generation unit that generates an analog chaos signal by the analog chaos generation circuit and digitally converts the signal to obtain variation data. The fluctuation data generation unit can use a part of the data obtained by digitizing the chaos signal as it is or perform a predetermined calculation to obtain the fluctuation data.

  For an analog chaos signal, the random number bit signal generated by the bit extraction / A / D conversion circuit 12 affects the quality of the entire random number generated by the random number generation device of the present embodiment. It is preferable to use one that has passed the correlation and average test as shown in 2008-123374.

  Here, the advantage of using the analog chaos generation circuit 11 that slightly changes the parameter C at a certain point in time by the LRC circuit as shown in FIG. 3 will be described. FIG. 5 shows the time series voltage value V1 and the parameter C value when the value of the parameter C of the LRC circuit causing the chaotic oscillation is slightly changed at a certain time (C = 0.3 [μF] → 0.3005 [μF]). It is the graph which compared the fluctuation | variation of the time-sequential voltage value V2 when not changing (C = 0.3 [micro F] fixed). As can be seen in FIG. 5, chaos is a system that is gradually different after a certain period of time only by changing various parameters such as L / R / C slightly due to initial sensitivity. It can be seen that it has the characteristic of behaving. From this, it is clear that the sequence is changed by changing the L / R / C value by a method such as using a random number value that has already been output, and therefore it is desirable to promote unpredictability.

  In the map calculation circuit 21 of the logistic map calculation unit 20, the logistic map is realized as follows. The mathematical formula for the logistic map is defined below.

Range of logistic map behaves like take any value of [0,1] interval, and a property that does not return in the past calculated X _i possibly infinite precision arithmetic. Although any value can be selected as the initial value X ₀ , for example, when X ₀ = 0.25, 0.5, 0.75, the solution converges, so these initial values cannot be adopted, and the initial value is Must carefully select values that do not converge. FIG. 6 (a) shows the time series for the horizontal axis “i” of the sequence {X _i } in which X ₀ = 0.4 is assigned to the initial value and takes values irregularly, and FIG. 6 (b) shows its geometry. The structure (return map) is shown. A logistic map obtained by converting it to an integer is expressed as follows. In the following, the number of bits of calculation accuracy is “N”. The digital arithmetic implementation of the logistic map is based on equation (7).

In the map calculation circuit 21 of the logistic map calculation unit 20 according to the present embodiment, the logistic map calculation is started using the initial value X ₀ set in the initial value register 22. As the initial value X ₀ , a fixed value that does not fall within a short cycle is obtained and stored in the initial value register 22 in advance. Alternatively, the analog chaos signal generated in the analog chaos generation circuit 11 may be A / D converted to extract a digital value that does not fall within a short period, and stored in the initial value register 22 in advance.

  The logistic map calculation unit 20 according to the present embodiment includes data changing means for causing a change in the mapping in the map calculation circuit 21 based on the change data. For this reason, the number of mappings RN to be subjected to random number extraction and the number of random number extractions AN to be used to cause fluctuation in the logistic mapping result using the uncertain bit by the bit extraction / A / D conversion circuit 12 are set. In this embodiment, the data changing means replaces the changing data with a part of the mapping data. That is, a predetermined bit of the logistic mapping result is replaced with the output of the bit extraction / A / D conversion circuit 12. However, the data changing means may change the mapping based on the calculation of the fluctuation data and at least a part of the mapping data. The calculation performed here may be any calculation such as addition / subtraction / division / division or an appropriate function.

The logistic map computing unit 20 according to the present embodiment as described above operates as shown in the flowchart shown in FIG. From the initial value register 22 fetches the initial value X ₀ (S11), performs a logistic mapping operation using this (S12). In step S12, the number of calculations i of 0 is incremented by 1 in the initial state. Next, it is detected whether the number of computations has reached the number of mappings RN that should be subjected to random number extraction (S13). If the number has not reached RN, the process returns to step S12 to continue the processing.

  On the other hand, if it is detected in step S13 that the number of operations i has reached RN, the random number output circuit 23 extracts a random value from the result calculated by the mapping operation circuit 21, and increments the random number extraction number j by one. (S14). Next, it is detected whether the random number extraction number j has reached the random number extraction number AN that should cause a change in the logistic mapping result (S15). If it has not reached AN, the process returns to step S12 and continues.

When the random number extraction count j reaches AN in step S15, the logistic mapping result is changed by the error bit that is the changing data generated by the changing data generation unit 10, and a new mapping result X is generated. _i [k] is determined and then processed to be used in step S12 (S16). Note that k indicates a lower-order bit digit in the mapping result X _i into which error bits that are data for variation are inserted.

More specifically, the logistic mapping operation unit 20 according to the present embodiment includes a subtraction unit (S21), a multiplication unit (S22), a shift operation unit (S23), and a processing unit (S24) as shown in the flowchart of FIG. The logistic mapping of the expression (7) is executed by the operation according to the above. First, the initial value X ₀ [N] is extracted from the initial value register 22 which is an initial value supply source (S20), and a logistic mapping operation is performed using this. In FIG. 8, N indicates the calculation accuracy, X _i [N] indicates the bit arrangement of the mapping, MINUS [N] indicates the bit arrangement of the subtraction result, and MULTI [N] indicates the bit arrangement of the multiplication result. Show.

The subtraction unit (S21), the next subtracting the 2 multiplier from ^N _{X i} as the operation to obtain the multiplicand, the multiplier unit (S22), a multiplier to the result of the subtraction (2 ^N -X _{i) X i} To obtain a 2N-bit solution. Further, in the shift operation unit (S23), the result of the multiplication is left-shifted by 2 bits, and an operation corresponding to four times the equation (7) is performed. In the processing unit (S24), the lower N bits corresponding to the division by 2 ^N are deleted (rejected) to obtain a mapping result X _i for N bits. Thereafter, steps S21 to S24 are repeatedly executed to perform the set finite precision calculation.

The above is the processing by the map calculation circuit 21 of the logistic map calculation unit 20 according to the present embodiment. As a result, a register array X _i [N] for storing N bits in one mapping operation is obtained. In the random number generation device of the present embodiment, the data changing means is a predetermined position of the register array X _i [N]. Can be replaced with an indeterminate bit (1 bit in this embodiment) extracted by the bit extraction / A / D conversion circuit 12 to promote unpredictability.

  In order to realize the processing by the map calculation circuit 21, the detailed configuration of the map calculation circuit 21 in the logistic map calculation unit 20 can be as shown in FIG. In the logistic map calculation unit 20, the control circuit 30 takes in a clock signal from the outside, and performs control by applying pulses Pulse1 to Pulse3 generated based on this clock to the required units.

  FIG. 10 shows a specific configuration diagram of the control circuit 30. As apparent from FIG. 10, the control circuit 30 includes three D flip-flop circuits 31 to 33 connected in cascade, an inverter 34, AND circuits 35 and 36, an EX-OR (exclusive OR) circuit 37, 38. The D flip-flop circuits 31 to 33 receive the signal at the D input terminal using the high edge of the signal input to the clock terminal as a trigger, and from the D input terminal until the next high edge is input to the clock terminal. The captured signal is held and output is continued from the Q output terminal. The three D flip-flop circuits 31 to 33 constitute an octal counter.

  The AND circuit 35 performs an AND operation with the clock signal CLK input to the clock terminal of the D flip-flop circuit 31 and the output signals (CNT2, CNT4, CNT8) of the D terminal of the D flip-flop circuits 31 to 33 as inputs. The AND circuit 36 directly inputs the clock signal CLK input to the clock terminal of the D flip-flop circuit 31 and the output signals (CNT4 and CNT8) of the D terminal of the D flip-flop circuits 32 and 33, and also the D flip-flop The output signal (CNT2) at the D terminal of the circuit 31 is input via the inverter 34, and the logical product operation of these signals is performed. The output signal of the AND circuit 35 is a pulse Pulse1, and the output signal of the AND circuit 36 is a pulse Pulse2.

  The EX-OR circuit 37 performs an exclusive OR operation using the signal input to the clock terminal of the D flip-flop circuit 31 and the output signal of the AND circuit 35 as inputs. The EX-OR circuit 38 performs an exclusive OR operation on the output signal of the EX-OR circuit 37 and the output signal of the AND circuit 36. The output signal of the EX-OR circuit 38 is a pulse Pulse3.

  FIG. 11 shows a specific waveform diagram obtained by circuit simulation of the control circuit 30. As described above, the pulse Pulse1 is one pulse logically calculated by the clock signal CLK and the output signal (CNT2, CNT4, CNT8) of the D terminal, and the pulse Pulse2 is the output signal of the clock signal CLK and the D terminal. This is one pulse logically operated by (CNT4, CNT8) and the inverted signal of the output signal (CNT2) of the D terminal. Also. Pulse Pulse3 is the result of performing an OR operation between this result and pulse Pulse2, using the result of the exclusive OR operation between pulse Pulse2 and clock signal CLK, and corresponds to an operation accuracy of N = 6 [bit] 6 pulses. In this example, since N = 6 [bit], one pulse uses Pulse 1 and Pulse 2 in one mapping, and Pulse Pulse 3 uses 6 pulses corresponding to the calculation accuracy N [bit], for a total of Eight pulses (clock) will be used. That is, the number of clocks required for one mapping calculation is N + 2.

The roles of the pulses Pulse1, Pulse2, and Pulse3 are as follows. In the pulse Pulse 1, the initial value X ₀ set in the initial value register 22 is read by the first pulse, and X is a result of mapping for each time to the multiplier register 221 by the second and subsequent pulses. _i is set. Further, the random number value is output from the random number output circuit 23 by the pulse Pulse1. Further, in the pulse Pulse2, the logistic map subtraction (2 ^N −X _i ) is performed by the pulse.

Further, in the pulse Pulse3, the pulse is composed of N pulses with the calculation accuracy N [bit], and logistic multiplication X _i (2 ^N −X _i ) is performed by the pulse. There are multiple pulses, which is equivalent to N for calculation accuracy of N [bit]. The above-described pulses Pulse1, Pulse2, and Pulse3 are used in that order in one mapping, and the required number of mappings determined by the user are repeated, thereby making it possible to sequentially calculate the logistic mapping of equation (7).

The logistic map calculation unit 20 shown in FIG. 9 includes a map calculation circuit 21, an initial value register 22, and a random number output circuit 23. The initial value register 22 is the initial value X ₀ is set, the initial value X ₀ is supplied to the mapping operation circuit 21. The random number output circuit 23 outputs a random value from the mapping operation circuit 21. In the present embodiment, an AND circuit is used as the random number output circuit 23, and output control is performed by the pulse Pulse 1 output from the control circuit 30.

The mapping operation circuit 21, and the multiplier X _i, the multiplication result of the multiplicand is the result of subtracting the multiplier X _i from _{^{2 N (2 N -X i)}} , logistic equation defined by formula multiplying the constant a Can be used as a mapping operation circuit for performing logistic mapping. In the present embodiment, constant a = 4 is set so that the mapping is a chaotic region having no periodicity. The mapping operation circuit 21 can include a subtraction unit, a multiplication unit, a shift operation unit, and a processing unit.

The subtracting unit subtracts the multiplier X _i from 2 ^N as an operation for obtaining the multiplicand. The multiplication unit multiplies the multiplicand obtained by the subtraction unit and the multiplier. The shift operation unit performs a shift operation corresponding to the constant a for the result obtained by the multiplication unit. Further, the processing unit rejects the lower N bits from the result obtained by the shift calculation unit and sends it to the subtraction unit as the next multiplier.

  The mapping operation circuit 21 includes a multiplier register 221 for placing a multiplier, a multiplicand register 222 for placing a multiplicand, an adder 223, and a 1 supply source 224 for supplying 1. Further, the mapping operation circuit 21 includes an inverter 225, a first path, and a second path so as to constitute the subtracting unit.

  The inverter 225 inverts the multiplier placed in the multiplier register 221 to obtain a complement. The first path is a path for leading 1 from the output of the inverter 225 and the one supply source 224 to the adder 223, and includes a selector 252 and a selector 253. The second path is a path for leading the result of adding the output of the inverter 225 led to the adder 223 and 1 from the one supply source 224 to the multiplicand register 222 and includes an AND circuit 263. .

  The mapping operation circuit 21 further includes a shift register 226, an AND circuit 262, a second processing unit, and a third processing unit. The second processing unit sequentially extracts one bit from the lower bits of the multiplier set in the multiplier register 221, and ANDs the 1 bit and the multiplicand set in the multiplicand register 222 by the AND circuit 262. The result is obtained and the result is output to the adder 223.

  The third processing unit uses the adder 223 to add the initial data or the data obtained by shifting the output of the previous adder 223 by the shift register 226 and the output of the second processing unit. The data is output to the shift register 226 via the circuit 264.

  The processing by the second processing unit and the third processing unit is repeatedly executed until processing is performed for all the bits of the multipliers placed in the multiplier register 221. Details of processing by the second processing unit and the third processing unit will be described later.

Further, the mapping operation circuit 21 is provided with a selector 251 for controlling whether the initial value X ₀ or the output of the shift register 226 is selected. The selector 251 is controlled by a direct output of the 1-bit shift register 271 or an output via the inverter 272. In the 1-bit shift register 271, the source voltage VDD is supplied to the D terminal, the source voltage VSS is supplied to the clear terminal CLR, and the pulse Pulse1 and the pulse Pulse2 are supplied to the clock terminal CLK via the OR circuit 273.

  Further, the pulse Pulse 1 is given to the DW terminal of the multiplier register 221, and the pulse Pulse 1 and the pulse Pulse 3 are given to the clock terminal CLK via the OR circuit 274.

  The selectors 251, 252, and 253 provided in the mapping arithmetic circuit 21 have the same configuration and are circuit diagrams as shown in FIG. In this embodiment, since N = 6 bits, the logic circuit block 250 of 6 blocks is provided. Each logic circuit block 250 includes an AND circuit that controls passage of input data from the A terminal by a control signal to the SA terminal, an AND circuit that controls passage of input data from the B terminal by a control signal to the SB terminal, and the above-described circuit. An OR circuit that receives the output signals of the two AND circuits and outputs a logical sum operation result from the S terminal. Therefore, one of the input terminals A and B on the side where the H level is given to either the SA terminal or the SB terminal is selected, and N bits are output.

  Further, the multiplier register 221 provided in the above mapping operation circuit 21 has a circuit diagram configuration of a parallel input serial output shift register as shown in FIG. The multiplier register 221 includes six D flip-flops 130 that hold input data, and one D flip-flop 130A that is connected to the least significant side of the D flip-flop 130 to hold the right-shifted result. And six logic circuit blocks 140 for controlling data writing to the D terminals of the six D flip-flops 130.

  The logic circuit block 140 allows the input of the PD terminal to pass through the D terminal of the D flip-flop 130 when the pulse Pulse1 is at the H level, and takes in the clock, and arrives at the clock terminal CLK when the pulse Pulse1 is at the L level. This is a circuit that performs control so that the shift by the pulse Pulse3 is performed. In the present embodiment, the output terminal of the AND circuit 261 is connected to one of the input terminals PD1 to PD6, and the output of the selector 251 is not given to this input terminal (any one of PD1 to PD6).

  Further, the multiplicand register 222 provided in the mapping operation circuit 21 is configured as shown in FIG. The multiplicand register 222 includes six D flip-flops 150 provided in parallel for inputting a pulse Pulse2 as a common clock to the clock terminal CLK.

  Further, the adder 223 provided in the mapping calculation circuit 21 is configured as shown in FIG. The adder 223 is configured such that a half adder 160 is provided at the lowest position, and five cascaded full adders 170 are connected to the half adder 160.

  Further, the shift register 226 provided in the mapping arithmetic circuit 21 has a circuit diagram configuration of a parallel input parallel output shift register as shown in FIG. That is, the shift register 226 is composed of N + 1 1-bit shift registers 180 as shown in FIG. 16, and the data input to the D terminal of the N + 1 1-bit shift registers 180 is shifted by 1 bit and the SFT terminal Output from.

  Each 1-bit shift register 180 is composed of two cascaded D flip-flops 190 as shown in FIG. By the first clock (pulse Pulse 3) input to the clock terminal CLK, data is fetched and held from the D terminal in the first stage D flip-flop 190 and becomes the output of the LTC (Q) terminal. The output from the LTC (Q) terminal of the first stage D flip-flop 190 is taken into the second stage D flip-flop 190 from the D terminal by the first clock (pulse Pulse 3) input to the clock terminal CLK. By being held, a right shift is executed. The configuration of the 1-bit shift register 271 in FIG. 9 is also equivalent to the circuit shown in FIG. 17 and operates in the same manner.

The mapping operation circuit 21 configured as described above operates as follows. The calculation is started by the output of the pulse Pulse1, and the signal of the pulse Pulse1 is clocked via the selector 251 and the DW terminal of the multiplier register 221 and the OR circuit 274 from the initial value register 22 in which the initial value X ₀ is stored in advance. Input to terminal CLK. As a result, the initial value X ₀ is stored in advance in the multiplier register 221 via the selector 251 from the initial value register 22.

  In the multiplier register 221, while the DW terminal is at the H level, the data supplied to the terminal PD <1: 6> is taken into the internal D flip-flop 130 at the timing when the signal applied to the clock terminal CLK is at the H level. That is, data is transferred to the terminals PD <1: 6> when the pulse Pulse1 is at the H level.

The selector 251 during operation start only, executes input selection of to read the initial value X _0. In the 1-bit shift register 271 configured as shown in FIG. 17, the output terminal SFT is at the L level in the initial stage, and the H level is given to the SA terminal of the selector 251 via the inverter 272. The initial value X ₀ coming from the terminal A is selected. By inputting the first two pulses composed of the pulse Pulse1 and the pulse Pulse2 to the OR circuit 273, H level data of the source voltage VDD connected to the D terminal of the 1-bit shift register 271 is captured. since the signal of the permanently H level is output to the output terminal SFT Te, via the inverter 272 to the SA terminal of the selector 251 is as given is L level, the second and subsequent from mapping X _1, selector 251 The SB terminal is given an H level, and each time the mapping X _i is transferred to the multiplier register 221.

In the present embodiment, the initial value X ₀ is fetched from the initial value register 22. However, as the initial value X ₀ , an A / D conversion value of an analog chaotic signal may be fetched into the register and used. . When the initial value X ₀ selected in advance is used, the source voltage (VDD / VSS) may be connected to the selector 251 as a fixed value. In the case of adopting this configuration, the initial value register 22 is not necessary, and the circuit area can be suppressed correspondingly, thereby reducing the size of the apparatus.

Next, subtraction (2 ^N −X ₀ ) is executed by the pulse Pulse 2. In the present embodiment, the subtraction is performed by adding 1 to the one's complement. In the state where the pulse Pulse2 is at the H level, the selector 252 selects the B input terminal. At this time, the output data of the terminal PO <1: 6> of the multiplier register 221 is inverted by the inverter 225 so as to be a one's complement.

On the other hand, the selector 253 selects the fixed value 1 (00... 001) ₂ connected to the source voltage (VDD / VSS) when the pulse Pulse2 is at the H level. As a result, the inverted data (1's complement) selected by the selector 252 and the fixed value (00..001) ₂ for addition of 1 are aligned in the adder 223, and the adder 223 performs subtraction (2 ^N -X ₀₎ is executed. The calculation result (2 ^N −X ₀ ) reaches the multiplicand register 222 via the AND circuit 263 that is allowed to pass by the pulse Pulse2, and is synchronized at the timing when the H level by the pulse Pulse2 is given to the clock terminal CLK of the multiplicand register 222. And stored in the multiplicand register 222.

Next, multiplication X ₀ (2 ^N −X ₀ ) by the pulse Pulse3 is executed. This multiplication is performed by using an adder 223 and a shift register 226. Here, the adder 223 is used for the above subtraction. However, by using the adder 223 for multiplication, the number of circuit parts can be reduced and the entire apparatus can be reduced in size and cost.

In the selector 252 and the selector 253, data from the A input terminal is selected by the pulse Pulse3. The shift register 226 serving as a register for storing X _i (2 ^N −X _i ), which is the product as the operation result, is cleared to zero by the immediately preceding pulse Pulse2. When the multiplier X _i by the multiplier register 221, the pulse Pulse3 is given in a state where the multiplicand (2 ^N -X ₀₎ is stored in the multiplicand register 222, and the least significant bit of the multiplier X _i multiplier register 221 sequentially Multiplication is performed in circuit 262. If the bit of the multiplier X _i sent from the multiplier register 221 is 0, the AND circuit 262 sends 0 to the A input terminal of the adder 223, and if the bit of the multiplier X _i sent from the multiplier register 221 is 1. The AND circuit 262 sends the contents of the multiplicand register 222 to the A input terminal of the adder 223. In the adder 223, the data of the A input terminal and the data of the upper bit group (B input terminal) of the shift register 226 are added, and the addition result is recursively stored in the shift register 226. The

I will explain in order. First pulse by the pulse Pulse3 is inputted to a clock terminal CLK of the multiplier register 221 via the OR circuit 274, data stored in the multiplier register 221 is shifted one bit right at the beginning, the lower one of the multiplier X _i The bit is input to the AND circuit 262, and based on this, the multiplicand (2 ^N −X _i ) is input to the A input terminal of the adder 223.

  The initial 0 data (data at the SFT terminal of the 1-bit shift register 180 in the shift register 226) is input from the shift register 226 to the B input terminal of the adder 223, and the addition result is simultaneously shifted in synchronization with the pulse Pulse3. It is stored in the register 226 (the LTC terminal of the 1-bit shift register 180 in the shift register 226).

Next, the second pulse by the pulse Pulse3 is inputted to a clock terminal CLK of the multiplier register 221 via the OR circuit 274, the contents of the multiplier X _i stored in the multiplier register 221 is shifted one bit to the right. As a result, the lower-order second bit of the multiplier is input to the AND circuit 262 from the multiplier register 221. At the same time, the data stored in the shift register 226 is shifted to the right by one bit by the second pulse of the pulse Pulse3. That is, the data of the LTC terminal in the 1-bit shift register 180 in the shift register 226 is transferred to the SFT terminal.

  The data shifted right by 1 bit is transferred to the adder 223 and added. This calculation is equivalent to a process in which the previous calculation result is shifted left by one bit by writing to perform addition. The calculation result on the way is sent to the shift register 226 through the AND circuit 264 in which data can be passed by the pulse Pulse3. Further, data obtained by shifting the calculation result to the right by 1 bit is sequentially sent from the shift register 226 to the adder 223 for each pulse of the pulse Pulse3 via the selector 253 in a state where data can be passed by the pulse Pulse3. In this shift register 226, N = 6 [bit] in the present embodiment, so that the signal to be supplied to the adder 223 for the next addition is the seven 1-bit shift registers 180 shown in FIG. Output signals “SC”, “S6”, “S5”, “S4”, “S3”, “S2” (SC is an overflow [carry out]) from the SFT terminal of the upper bit group.

Finally, the calculation “4X _i (2 ^N −X _i )” and the division “4X _i (2 ^N −X _i ) / 2 ^N ” to be multiplied by 4 with respect to the multiplication result remain as operations of the logistic map. . First, the quadruple operation can be realized by shifting the multiplication result to the left by 2 bits. The division can be realized by shifting the left 2 bits, and then shifting N bits to the right (rejecting the lower N bits from 2 ^N bits). However, this shift processing is equivalent to performing “X _i (2 ^N −X _i ) / 2 ^N−2 ”. Therefore, the calculation result is shifted N-2 bits to the right (the lower “N-2” bits are discarded), and the lower N bits of the remaining N + 2 bits are mapped to the next mapping X. Transfer as _i .

Therefore, in the shift register 226, plus 2 bits may be stocked on the lower side of the calculation result N bits. Since N = 6 [bit] in this embodiment, the output signals “L5”, “L4”, “L3”, “L2” from the LTC terminals in the seven 1-bit shift registers 180 shown in FIG. "," L1 "," as the data using the S1 "to the next mapping X _i, is transferred to the PD terminal pins of the multiplier register 221 in synchronism with the pulse Pulse1 (L1, S1 is a stock lower 2 bits ). For this purpose, as shown in FIG. 16, the shift register 226 may prepare N + 1 1-bit shift registers 180 as a minimum number.

FIG. 18 shows a waveform of a simulation result when logistic mapping is performed with the initial value X ₀ being 25 (011001). At this time, the multiplicand 2 ^N -X ₀ is obtained as 39 (100111) by subtraction from the initial value. The multiplication by the pulse Pulse3 is performed as shown in FIG. This will be explained. First, (100111) is obtained by adding (000000) and (100111) by the first pulse of the pulse Pulse3.

  Depending on the second pulse of pulse Pulse3, the following processing is performed. The result (010011) obtained by shifting the calculation result (100111) by the first pulse to the right by 1 bit and the output (000000) of the next AND circuit 262 are added.

  Depending on the third pulse of the pulse Pulse3, the following processing is performed. The result (001001) obtained by shifting the calculation result (010011) by the second pulse to the right by 1 bit and the output (000000) of the next AND circuit 262 are added. The following processing is performed depending on the fourth pulse of the pulse Pulse3. The result (000100) obtained by shifting the calculation result (001001) by the third pulse to the right by 1 bit and the output (100111) of the next AND circuit 262 are added. Thereafter, processing is performed in the same manner. In the first mapping, the addition result is finally shifted to the right by 4 bits, and the lower 6 bits (111100) = 60 are sent to the multiplier register 221 as a multiplier of the next mapping.

  Then, as shown in FIG. 18, (111100) = 60 is obtained in the first mapping, (001111) = 15 is obtained in the second mapping, and (101101) = 45 is obtained in the third mapping. As random numbers, in the example of FIG. 18, 3 bits from the upper 3rd bit to the 5th bit are obtained as (110), (111), and (110), respectively.

  In the circuit of the embodiment shown in FIG. 9, random bit extraction and irregular bit write timing from analog chaos are synchronized with the pulse Pulse1 via the AND circuit 261 for each mapping. However, the random number extraction performed in the random number output circuit 23 may be performed when the pulse Pulse1 is counted and a predetermined number of mappings are performed, or an irregular bit obtained from the analog chaos signal. This writing may also be performed at a timing when a predetermined number of random numbers are acquired.

In addition, the random number generation device according to the embodiment uses the bit extraction / A / D conversion circuit 12 that performs analog chaos A / D conversion and extracts one bit. In the bit extraction / A / D conversion circuit 12, the data amount of the irregular signal for forcibly changing the mapping X _i is only 1 bit. Even if the bit extraction / A / D conversion circuit 12 is used and the number of times of mapping is set to a predetermined number of times to change the signal of the logistic mapping, it is effective to improve the random number performance. This was clarified by Example 2 described later. For this reason, it is expected that the random number generation speed can be increased by increasing the clock frequency applied to the logistic map calculation unit 20 as much as possible, and the random number performance can be improved even with a small amount of bit information from analog chaos.

  Further, since the circuit configuration is simple as shown in the embodiment, the connection in the circuit can be changed relatively easily. For example, it is possible to increase the random number pattern by changing the calculation accuracy from 6 bits to 5 bits (at the same time, changing the number of pulses of Pulse Pulse 3 from 6 to 5). The effect of improving randomness can be expected. In the design stage by simulation, an effect of suppressing the mounting cost can be expected by performing the tuning after optimal tuning is performed in advance on the random number performance, the circuit area, and the random number generation speed.

(1) Example 1
By the process according to the flowchart showing the operation of the logistic map operation unit 20 shown in FIG. 7, random numbers are extracted using only the logistic map operation, and the NIST random number test is performed.
Two types of operation accuracy N = 64 and N = 56 bits long are prepared, and the random number extraction method uses the calculated logistic map X _i as shown in FIG. 20 as 8 bits from the lower 5 bits to 12 bits in the array. Then, 8 bits from the lower 21 bits to 28 bits were taken out, and 8 bits of the result obtained by exclusive ORing each 8 bits was output as a random value.

The initial value of the mapping was a fixed value of 0.125 (0.0010000 ...) ₂ and a random number of 8 bits was extracted every time the mapping was calculated three times.
The obtained random numbers were evaluated by performing a NIST random number test. Here, an outline of the NIST random number test will be described.

<NIST random number test>
It is one of the most widely used random number test methods at present and is published by the National Institute of Standards and Technology (NIST) and consists of 15 test methods.
For the test data, it is recommended that one series is 1,000,000 [bit], and that 1,000 series are prepared for a total of 1,000,000,000 [bit].
P-value is calculated for each series, and randomness is evaluated from the viewpoint of UNIFORMITY (uniformity) and PROPORTION (whether it is in 3σ range with a rejection rate of 1%) for a total of 1,000 p-values doing.
A total of 1,000,000,000 [bits] of random values were acquired by the above method, and the test was performed using the NIST random number test tool. The results at each calculation accuracy are shown in Table 1 below.

As a result of Example 1, as shown in Table 1, when the calculation accuracy is 56 bits, PROPORTION has a total of 10 errors, and UNIFORMITY has a total of 8 errors, but the calculation accuracy is 64 bits. Then, both PROPORTION and UNIFORMITY passed.
From the above, it can be seen that when the random number value is obtained only by the operation of the logistic map of the above method and the NIST random number test is performed, the NIST random number test is passed with a calculation accuracy width of about 64 bits.

(2) Example 2
Next, a digital value extraction of an analog chaotic signal was performed as an uncertain element of this embodiment, a random number was obtained by a method of transferring the bit value to a logistic mapping arithmetic circuit, and a NIST random number test was performed.

The random number is obtained by a process corresponding to the flowchart shown in FIG. 7, and the logistic map X _i calculated as shown in FIG. 20 is converted into the 8 bits from the lower 5 bits to the 12 bits in the array as in the first embodiment. Eight bits from the lower 21 bits to 28 bits were taken out, and each 8 bits were subjected to an exclusive OR operation, and the resulting 8 bits were output as a random value. Random number extraction is performed by extracting 8-bit random numbers every time mapping is performed three times, and extracting the random number values for 100 times by performing A / D conversion from analog chaos signals as uncertain bits. One bit is forcibly incorporated into the lower 2 bits of the register array of mapping X _i .

  The parameter band of the analog chaotic signal corresponding to the equation (5) used as the theoretical simulation is as shown in Table 2 below.

In the second embodiment, the voltage value of the chaotic signal is boosted by 0.5 [V] and is input to the A / D conversion circuit, and the resolution of the voltage value is 32.
FIG. 21 shows a graph in which the horizontal axis dV / dt obtained by differentiating V per cycle of the external input signal with time under the above parameter conditions and the vertical axis V plotted (Poincare plot). The strange attractor, a characteristic of chaos, can be observed.

  The timing of bit extraction after analog chaos signal digital conversion was acquired for each cycle of the external cycle input voltage in the analog chaos generation circuit. As in the first embodiment, two types of logistic map calculation accuracy, N = 56 and N = 64 bits, were prepared, a total of 1,000,000,000 [bits] of random values were obtained, and a test was performed using the NIST random number test tool. The results at each accuracy are shown in Table 3 below.

As a result, as shown in Table 3, both 56-bit and 64-bit calculation accuracy passed both PROPORTION and UNIFORMITY.
In the first embodiment, the random number test with the calculation accuracy of 56 bits resulted in a plurality of errors. However, the mapping system was changed by digitally extracting the 1-bit error from the unpredictable analog chaotic signal and transferring it. It is estimated that the random number performance has improved. Therefore, by incorporating an uncertain element even with a small bit amount, it is possible to obtain a high-quality random number performance with non-reproducibility even if the calculation accuracy is lowered.

  In the present embodiment, the position of the bit to be forcibly changed is limited to the lower 2 bits, but the mapping pattern is limited only at the same position. For this reason, it can be expected that the random number performance is further improved by changing the position of the bit to be changed and increasing the number of patterns.

Also, take the timing convolving unpredictable bits extracted from the analog chaos short, not only one bit takes the more bits, by force change the mapping X _i, computation precision constraints It is assumed that the value of the map X _i that could not be obtained will be spread by the above. From this, it is presumed that even if the calculation accuracy (circuit scale) of the logistic map calculation circuit is further reduced, a good random number performance can be obtained.

  As described above, the embodiment of the present invention has an effect that random number performance is improved and a random number generation speed is increased by introducing an unpredictable bit value in a predetermined loop at the time of pseudo random number generation by logistic mapping. Can be obtained. This is extremely advantageous in comparison with the problem that the generation speed of intrinsic random numbers is generally slow. In addition, it is suitable for generating a relatively short random number sequence for use as a security random number seed. In other words, the embodiment of the present invention can provide a random number for security use by incorporating unpredictable bits from an analog chaos circuit in a short cycle into an arithmetic circuit of a logistic map. Have

  As shown in the examples, the chaos generation circuit used in the embodiment according to the present invention is expressed as an LRC equivalent circuit. By performing computer simulation on the mathematical formula, tuning for estimating the random number performance at the design stage is possible, and the effect of reducing the development cost of the random number generation device having the desired random number performance can be expected.

  The embodiment according to the present invention uses a pseudo random number generation method as a main configuration. The embodiment according to the present invention uses an analog chaos output that cannot be predicted for each predetermined loop at the time of pseudo-random number generation, and changes the internal state of the pseudo-random number generation method. As a result, the embodiment according to the present invention as a whole makes it possible to generate a random number that does not grasp the generation rule (without reproducibility). Since the embodiment according to the present invention employs the pseudo random number generation method as a main configuration, the generation rule cannot be grasped (there is no reproducibility) while the processing speed is equal to that of general pseudo random number generation. It is characterized by enabling random number generation.

Here, the characteristics or effects inherent in analog chaos are as follows.
(1) I cannot grasp the context and rules of the random numbers to be generated.
(2) The generated random number sequence cannot be reproduced again.
(3) It is impossible to reproduce (analyze) faithfully using any computer simulation method by using analog implementation.
Since the embodiment according to the present invention uses the output of the above-mentioned analog chaos, the characteristics or effects are inherited as they are.

  Today, the importance of information security is screamed, and random numbers are used as seeds for generating cryptographic keys, particularly in cryptographic techniques. Therefore, for example, when the embodiment according to the present invention is implemented in the encryption key issuing server, there is no need to worry about the encryption key generation sequence due to outflow of the random number generation algorithm even if the server is hacked. .

  In general needs where a random number sequence is required, by using the embodiment according to the present invention, in particular, the relevance of random numbers generated around time is not grasped in principle (the random number sequence generation sequence is Can not be grasped).

  In recent years, the amount of data to be distributed has increased dramatically as the IT adaptation area has expanded. In such an environment, a scene where data identification management is applied by applying a universal unique ID (UUID) of 128 bits to each data, a scene where home appliance mutual challenge response authentication is performed, and safety of data stored in a ubiquitous terminal Needs such as random number writing and erasing. The embodiment according to the present invention is suitable when a high-speed random number generator capable of generating high-quality random numbers is mounted on a small scale for such scenes and needs.

  Further, when a chaotic map is implemented by digital calculation, there is a fundamental problem of short period, and therefore some proposals have been made to extend the period. However, in order to extend the period, new problems such as complicated control are required, and the size and cost of the apparatus are increased due to an increase in the mounting area of the memory and the like required for the structure for extending the period. To do.

  In addition, there is an example in which a measure for avoiding a short cycle problem is provided by providing a mechanism for detecting an abnormal value when entering a periodic band, but a mechanism for realizing this is required. The random number generation circuit according to the embodiment of the present invention uses a technique of taking a true random number based on an analog chaotic signal, so that no mechanism or device for detecting a periodic band is required.

  The logistic map used by the embodiment according to the present invention “has only one bit fluctuate” as apparent from the description of FIG. 22 and the following FIG. 22 from the initial sensitivity (butterfly effect) of chaos. An extremely large effect can be obtained with a small amount of control.

FIG. 22 shows the time series IM1 of the mapping when the calculation accuracy is set to N = 16 bits and the initial value X ₀ = 26214 in the logistic map converted to the integer calculation by the equation (7), and 1 bit is rewritten at a certain time. The time series IM2 of the mapping at the time of shooting is shown. When the number of mappings is the 10th time, the lower third bit is forcibly changed from “0” to “1” from X ₁₀ = 18977 (= (0100101000100001) ₂ ) to X ₁₀ = 18981 (= (0100101000100101) ₂ ) The trajectory when changed to is shown. It was confirmed even in finite arithmetic accuracy that the system was completely separated in terms of time development by forcibly changing only 1 bit for the sequence, and it was possible to obtain a sequence with different behavior. did it.

Generally, the larger the calculation accuracy range, the better the random number performance. The embodiment according to the present invention uses a bit of an irregular signal from the analog chaos to vary the mapping sequence so as to reach a value of the mapping X _{i that} cannot be obtained due to a rounding error due to calculation accuracy. Thereby, by employing the embodiment according to the present invention, it is possible to reduce the calculation accuracy width (circuit scale) and to obtain a good random number performance.

  Since the digital circuit that performs the operation of the logistic map adopting the embodiment according to the present invention is configured only with the clock signal from the external input, the embodiment according to the present invention is easy only by adjusting the frequency of the clock signal. Has the advantage that the random number generation speed can be changed. In addition, since the embodiment according to the present invention has a simple circuit configuration, the random number sequence can be changed relatively easily by incorporating a mechanism for autonomously changing the wiring connection.

  Further, a feedback shift register is known as a random number generation logic, and according to this, a sequence of random numbers having an ideal frequency and cycle can be obtained. However, according to this feedback shift register, the generation pattern is limited in one direction such that the pattern generated once is not generated again. On the other hand, in the embodiment according to the present invention, since analog chaos having a merit in random performance that makes it difficult to predict a sequence is adopted, there is no disadvantage that the generation pattern is limited, and random number generation in various fields is performed. It has the advantage of being suitable for.

DESCRIPTION OF SYMBOLS 10 Fluctuation data production | generation part 11 Analog chaos production | generation circuit 12 1 bit extraction and A / D conversion circuit 20 Logistic map operation part 21 Mapping operation circuit 22 Initial value register 23 Random number output circuit 30 Control circuit 221 Multiplier register 222 Multiplicand register 223 Adder 226 Shift register 224 1 supply source

Claims (9)

An analog chaos generation circuit that generates an analog chaos signal by an analog chaos generation circuit, and n differential amplification circuits that convert the analog chaos signal to a digital value of 1 or 0 using different reference voltages, respectively, n N-bit data in which 1 bit of the bit is a selection instruction signal is obtained, and digital conversion is performed by selecting one of the n registers based on the n-bit data selection instruction signal and extracting the data. A fluctuation data generation unit comprising a bit extraction / A / D conversion circuit for obtaining fluctuation data;
A mapping operation circuit that performs logistic mapping using the variation data;
Data variation means for causing a variation in the mapping in the mapping operation circuit based on the variation data;
A random number generation device, comprising: random number acquisition means for acquiring a random value based on a mapping result obtained by the mapping operation circuit.   2. The random number generation device according to claim 1, wherein the variation data generation unit converts the data obtained by digitizing the chaotic signal into the variation data as it is or by performing a predetermined calculation.   3. The random number generation device according to claim 1, wherein the data changing unit replaces the changed data with a part of the mapping data.   The random number generation device according to claim 1 or 2, wherein the data changing means changes the mapping based on the calculation of the fluctuation data and at least a part of the mapping data.   5. The random number generation device according to claim 1, wherein the random value acquisition unit uses the mapping result obtained by the mapping calculation circuit as it is or performs a predetermined calculation to obtain a random value. 6. 6. The random number generation device according to claim 1 , wherein the analog chaos generation circuit changes a circuit constant at a predetermined timing. In a mapping operation circuit that performs logistic mapping using a logistic equation defined by a formula obtained by multiplying the multiplier Xi and the multiplicand (2N−Xi), which is the result of subtracting the multiplier Xi from 2N, by a constant a ,
A subtractor for subtracting a multiplier Xi from 2N as an operation for obtaining the multiplicand;
A multiplier that multiplies the multiplicand and multiplier obtained by the subtractor;
A shift operation unit that performs a shift operation corresponding to a constant a with respect to the result obtained by the multiplication unit, and rejects the lower N bits from the result obtained by the shift operation unit and sends the result to the subtraction unit as the next multiplier. A mapping operation circuit comprising: a first processing unit. A multiplier register for placing a multiplier; a multiplicand register for placing a multiplicand; an adder;
The subtracting unit is
An inverter for inverting a multiplier placed in the multiplier register to obtain a complement;
A first path for leading 1 to the adder from the output of the inverter and the one supply source,
According to claim 7, characterized in that it is constituted by a second path leading to the result 1 is added from the first supply source and the output of the inverter guided to the adder to the multiplicand register Mapping operation circuit. Further, one bit is extracted in order from the lower bits of the multiplier placed in the shift register and the multiplier register, the logical product of this 1 bit and the multiplicand placed in the multiplicand register is obtained by an AND circuit, and the result is obtained. A second processing unit for outputting to the adder;
A third processing unit that uses the adder to add initial data or data obtained by shifting the output of the previous adder by the shift register and the output of the second processing unit, and outputs the result to the shift register And
Until said processing of all bits of the numeral been multiplier multiplier register is performed, a shift register, to claim 8, characterized in that repeatedly executes the processing by the second processing unit and the third processing unit The mapping operation circuit described.

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