JP2014149322A - Liquid crystal display panel and electronic apparatus - Google Patents

Abstract

Provided are a liquid crystal display panel and an electronic device that suppress parasitic capacitance generated in a capacitance at a crossing portion of a signal line and a scanning line and a capacitance in a channel of a transistor.
A liquid crystal display panel is a single gate transistor having a thin film transistor channel region Ntft. The semiconductor layer of the thin film transistor is disposed in a plane between the scanning line 24 and the signal line 25 in a direction perpendicular to the surface of the substrate, and the channel region Ntft is bent to be the end of the channel region near the contact portion 25a. The part PD is in a position where it overlaps with the signal line 25, and the channel region end PS near the contact part 90 a is not in a position where it overlaps with the signal line 25.
[Selection] Figure 4

Description

  The present disclosure relates to a liquid crystal display panel including a liquid crystal. Moreover, this indication is related with the electronic device provided with the liquid crystal display panel provided with a liquid crystal.

  In recent years, the demand for display devices for mobile devices such as mobile phones and electronic paper has increased. Such a display device includes a display area unit in which pixels are arranged in a matrix, a vertical drive circuit that selects each pixel in the display area unit in units of rows, and each pixel in a row selected by the vertical drive circuit. And a horizontal drive circuit for supplying an image signal.

  In the display device, wirings connected to the vertical drive circuit and the horizontal drive circuit are arranged in the display area portion. In the display device, a parasitic capacitance acting between the wiring and the pixel is generated. As the definition of the display area increases, the area of the pixel decreases, and the parasitic capacitance acting between the wiring and the pixel increases.

  In the technique described in Patent Document 1, pixel electrodes that are connected to a thin film transistor on a transparent substrate and have a predetermined number that is linearly continuous in the column or row direction are arranged in half in adjacent columns or rows. In a liquid crystal display element arranged at a pitch shift, one of a drain line and a gate line connected to a thin film transistor has a linear portion along a row or a column direction between adjacent pixel electrodes in a predetermined column or row, and a phase. There is described a liquid crystal display element having an oblique straight line portion that obliquely connects adjacent straight line portions and having a channel length direction of a thin film transistor different from a column or row direction.

Japanese Patent Laid-Open No. 9-022026

  However, in the technique described in Patent Document 1, there is a possibility that the capacitance at the intersection of the signal line and the scanning line and the capacitance at the channel of the transistor are generated in multiple times regardless of the delta arrangement, and the parasitic capacitance is increased. large.

  The present disclosure has been made in view of such problems, and an object of the present disclosure is to provide a liquid crystal display panel and an electronic device that suppress parasitic capacitance generated in the capacitance at the intersection of the signal line and the scanning line and the capacitance in the channel of the transistor. To provide equipment.

  A liquid crystal display panel according to the present disclosure includes a first substrate, a second substrate disposed to face the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. In the display panel, the first substrate includes a plurality of pixel electrodes arranged in a matrix, a thin film transistor connected to the pixel electrode by a first contact portion, and a direction perpendicular to the surface of the first substrate. A plurality of first metal wirings that are in a layer different from the semiconductor layer of the thin film transistor and that are partly crossed to form a scanning line so that a part of the semiconductor layer serves as a channel region, and a first metal wiring extending from the first metal wiring A plurality of second metal wirings that are three-dimensionally crossed with the first metal wiring by extending in the second direction, which is different from the one direction, and that are connected to the semiconductor layer at the second contact portion and serve as signal lines. Including the thin film transistor In the star, the channel region is a single gate transistor, the semiconductor layer is disposed in a plane between the first metal wiring and the second metal wiring, and the channel region is bent, The end of the channel region near the second contact portion is in a position overlapping the second metal wiring, and the end of the channel region near the first contact portion is not in a position overlapping with the second metal wiring.

  An electronic device according to the present disclosure includes the liquid crystal display panel.

  According to the liquid crystal display panel and the electronic device according to the present disclosure, it is possible to provide a liquid crystal display panel and an electronic device in which parasitic capacitance is suppressed.

FIG. 1 is an explanatory diagram illustrating an example of a configuration of a liquid crystal display panel according to the present embodiment and a modification. FIG. 2 is a block diagram illustrating a system configuration example of the liquid crystal display panel of FIG. FIG. 3 is a circuit diagram illustrating an example of a drive circuit for driving a pixel. FIG. 4 is a schematic diagram for explaining a circuit pattern of the liquid crystal display panel according to the first embodiment. 5 is a cross-sectional view taken along line VV in FIG. FIG. 6 is a schematic diagram for explaining a circuit pattern of the liquid crystal display panel when the thin film transistor is a double gate transistor. FIG. 7 is a schematic diagram of a section taken along line VII-VII in FIG. FIG. 8 is a schematic diagram for explaining a circuit pattern of a liquid crystal display panel according to a first modification of the first embodiment. FIG. 9 is a schematic diagram showing a main part of a cross section taken along line IX-IX in FIG. FIG. 10 is a schematic diagram for explaining a circuit pattern of a liquid crystal display panel according to a second modification of the first embodiment. FIG. 11 is a schematic diagram illustrating a main part of a cross section taken along line XI-XI in FIG. FIG. 12 is a schematic diagram for explaining a circuit pattern of a liquid crystal display panel according to a third modification of the present embodiment. FIG. 13 is a schematic diagram for explaining a circuit pattern of a liquid crystal display panel according to a fourth modification of the present embodiment. FIG. 14 is a schematic diagram illustrating a main part of a cross section taken along line XIV-XIV in FIG. 13. FIG. 15 is a schematic diagram for explaining a circuit pattern of a liquid crystal display panel according to a fifth modification of the present embodiment. FIG. 16 is an explanatory diagram for explaining an evaluation result of the evaluation example. FIG. 17 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to the present embodiment and the modification is applied. FIG. 18 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to the present embodiment and the modification is applied. FIG. 19 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to the present embodiment and the modification is applied. FIG. 20 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to the present embodiment and the modification is applied. FIG. 21 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to this embodiment and the modification is applied. FIG. 22 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to this embodiment and the modification is applied. FIG. 23 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to this embodiment and the modification is applied. FIG. 24 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to the present embodiment and the modification is applied. FIG. 25 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to this embodiment and the modification is applied. FIG. 26 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to the present embodiment and the modification is applied. FIG. 27 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to this embodiment and the modification is applied. FIG. 28 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to the present embodiment and the modification is applied. FIG. 29 is a diagram illustrating an example of an electronic apparatus to which the liquid crystal display panel according to the present embodiment and the modification is applied.

A mode (embodiment) for carrying out the present disclosure will be described in detail with reference to the drawings. The present disclosure is not limited by the contents described in the following embodiments. The constituent elements described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the constituent elements described below can be appropriately combined. The description will be given in the following order.
1. This embodiment (liquid crystal display panel)
2. Evaluation example 3. Application example (electronic equipment)
3. Example in which the liquid crystal display panel according to the above embodiment is applied to an electronic device. Composition of this disclosure

<1. Embodiment (Liquid Crystal Display Panel)>
FIG. 1 is an explanatory diagram illustrating an example of a configuration of a liquid crystal display panel according to the present embodiment and a modification. FIG. 2 is a block diagram illustrating a system configuration example of the liquid crystal display panel of FIG. FIG. 1 is a schematic representation and is not necessarily the same as the actual size and shape. The display device 1 corresponds to a specific example of a “liquid crystal display panel” of the present disclosure.

  The display device 1 is a transmissive or transflective display device, and includes a liquid crystal display panel 2, a driver IC 3, and a backlight 6. The display device 1 may be a reflective display device that does not include the backlight 6. An unillustrated flexible printed circuit board (FPC (Flexible Printed Circuits)) transmits an external signal to the driver IC 3 or driving power for driving the driver IC 3. The liquid crystal display panel 2 includes a transparent insulating substrate, for example, a glass substrate 11, a display area unit 21 on the surface of the glass substrate 11, in which a large number of pixels including liquid crystal cells are arranged in a matrix (matrix), and a horizontal driver (Horizontal drive circuit) 23 and vertical drivers (vertical drive circuits) 22A and 22B. The vertical drivers (vertical drive circuits) 22A and 22B are arranged so as to sandwich the display area portion 21 as the first vertical driver 22A and the second vertical driver 22B. The glass substrate 11 includes a first substrate on which a large number of pixel circuits including active elements (for example, transistors) are arranged and formed in a matrix, and a second substrate arranged to face the first substrate with a predetermined gap. Including. The glass substrate 11 has a liquid crystal layer in which liquid crystal is sealed between the first substrate and the second substrate.

  The picture frames 11gr and 11gl of the liquid crystal display panel 2 are non-display areas on the surface of the glass substrate 11 and without the display area portion 21 in which a large number of pixels including liquid crystal cells are arranged in a matrix (matrix). The vertical drivers 22A and 22B are arranged on the frames 11gr and 11gl.

  The backlight 6 is disposed on the back side of the liquid crystal display panel 2 (the surface on the side opposite to the surface on which images are displayed). The backlight 6 irradiates the liquid crystal display panel 2 with light and makes the light incident on the entire surface of the display area 21. The backlight 6 includes, for example, a light source and a light guide plate that guides light output from the light source and emits the light toward the back surface of the liquid crystal display panel 2.

(Example of system configuration of display device)
The liquid crystal display panel 2 includes a display area unit 21, a driver IC 3 having functions of an interface (I / F) and a timing generator, a first vertical driver 22A, a second vertical driver 22B, and a horizontal driver 23 on a glass substrate 11. And.

The display area unit 21 has a matrix (matrix) structure in which pixels Vpix including a liquid crystal layer are arranged in m rows × n columns of units constituting one pixel on the display. In this specification, a row means a pixel row having n pixels Vpix arranged in one direction. A column refers to a pixel column having m pixels Vpix arranged in a direction orthogonal to the direction in which rows are arranged. The values of m and n are determined according to the vertical display resolution and the horizontal display resolution. In the display area section 21, scanning lines 24 ₁ , 24 ₂ , 24 ₃ ... 24 _m are wired for each row with respect to an array of m rows and n columns of pixels Vpix, and signal lines 25 ₁ , 25 ₂ are provided for each column. , 25 ₃ ... 25 _n are wired. Hereinafter, in the present embodiment, the scanning lines 24 ₁ , 24 ₂ , 24 ₃ ... 24 _m are represented as scanning lines 24 or scanning lines 24 _m , and signal lines 25 ₁ , 25 ₂ , 25 are represented. ₃ ... 25 _n may be represented as a signal line 25 or a signal line 25 _n . In the present embodiment, the scanning lines _{24 1, 24 2, 24 3} ··· 24 m and on behalf expressed as scanning lines _{24 m + 1, 24 m +} 2, 24 m + 3 ···, the signal lines 25 ₁ 25 ₂ , 25 ₃ ... 25 _n may be represented as signal lines 25 _{n + 1} , 25 _{n + 2} , 25 _{n + 3} . The display area 21 is arranged in a region where the scanning lines 24 and the signal lines 25 overlap with the black matrix of the color filter when viewed from the direction orthogonal to the front. In addition, the display area portion 21 has an opening in a region where no black matrix is arranged.

  The liquid crystal display panel 2 is supplied with a master clock, a horizontal synchronizing signal, and a vertical synchronizing signal, which are external signals from the outside, and are supplied to the driver IC 3. The driver IC 3 converts (boosts) the level of the master clock, the horizontal synchronization signal, and the vertical synchronization signal of the voltage amplitude of the external power source into the voltage amplitude of the internal power source necessary for driving the liquid crystal, and the master clock, the horizontal synchronization signal, and the vertical synchronization signal. Generate a signal. The driver IC 3 supplies the generated master clock, horizontal synchronization signal, and vertical synchronization signal to the first vertical driver 22A, the second vertical driver 22B, and the horizontal driver 23, respectively. The driver IC 3 generates a common potential (counter electrode potential) Vcom that is commonly applied to each pixel with respect to the pixel electrode for each pixel Vpix, and supplies the common potential to the display area unit 21.

The first vertical driver 22A and the second vertical driver 22B include a shift register described later, and further include a latch circuit and the like. In the first vertical driver 22A and the second vertical driver 22B, the latch circuit sequentially samples and latches display data output from the driver IC 3 in one horizontal period in synchronization with the vertical clock pulse. The first vertical driver 22A and the second vertical driver 22B sequentially output the digital data for one line latched in the latch circuit as vertical scanning pulses, and scan lines 24 _{m + 1} , 24 _{m + 2} , 24 _{m + 3.} ... Sequentially select pixels Vpix in units of rows. The first vertical driver 22A and the second vertical driver 22B are arranged so as to sandwich the scanning lines 24 _{m + 1} , 24 _{m + 2} , 24 _{m + 3} ... In the extending direction of the scanning lines 24 _{m + 1} , 24 _{m + 2} , 24 _{m + 3.} ing. For example, the first vertical driver 22A and the second vertical driver 22B are located above the display area 21 of the scanning lines 24 _{m + 1} , 24 _{m + 2} , 24 _{m + 3.} The digital data is output in order in the vertical scanning downward direction. Further, the first vertical driver 22A and the second vertical driver 22B are located below the display area 21 of the scanning lines 24 _{m + 1} , 24 _{m + 2} , 24 _{m + 3.} The digital data can also be output in order in the vertical scanning upward direction.

  For example, 6-bit R (red), G (green), and B (blue) digital video data Vsig is supplied to the horizontal driver 23. For each pixel Vpix in the row selected by the vertical scanning by the first vertical driver 22A and the second vertical driver 22B, the horizontal driver 23 is a signal line for each pixel, for every plurality of pixels, or for all the pixels at once. The display data is written via 25.

(Liquid crystal display panel drive method)
FIG. 3 is a circuit diagram illustrating an example of a drive circuit for driving a pixel. In the display area unit 21, signal lines 25 _{n + 1} , 25 _{n + 2} , 25 _{n + 3} for supplying pixel signals as display data to the thin film transistors (TFT) of each pixel Vpix shown in FIG. 3 and the thin film transistors Tr are driven. Wiring lines such as scanning lines 24 _{m + 1} , 24 _{m + 2} , 24 _{m + 3} are formed. As described above, the signal lines 25 _{n + 1} , 25 _{n + 2} , and 25 _{n + 3} extend in a plane parallel to the surface of the glass substrate 11 described above, and supply pixel signals for displaying an image to the pixels Vpix. The pixel Vpix includes a thin film transistor Tr and a liquid crystal element LC. In this example, the thin film transistor Tr is composed of an n-channel MOS (Metal Oxide Semiconductor) TFT. One of the source and drain of the thin film transistor Tr is connected to the signal lines 25 _{n + 1} , 25 _{n + 2} and 25 _{n + 3} , the gate is connected to the scanning lines 24 _{m + 1} , 24 _{m + 2} and 24 _{m + 3} , and the other of the source and drain is the liquid crystal element LC. It is connected to one end. The liquid crystal element LC has one end connected to the thin film transistor Tr and the other end connected to the common potential Vcom of the common electrode COML.

The pixel Vpix is connected to other pixels Vpix belonging to the same row of the display area unit 21 by scanning lines 24 _{m + 1} , 24 _{m + 2} and 24 _{m + 3} . Of the scanning lines 24 _{m + 1} , 24 _{m + 2} and 24 _{m + 3} , the odd scanning lines 24 _{m + 1} and 24 _{m + 3} are connected to the first vertical driver 22A, and a vertical scanning pulse Vgate of a scanning signal described later is supplied from the first vertical driver 22A. The Of the scanning lines 24 _{m + 1} , 24 _{m + 2} and 24 _{m + 3} , the even scanning lines 24 _{m + 2} and 24 _{m + 4} are connected to the second vertical driver 22B, and a vertical scanning pulse Vgate of a scanning signal to be described later is supplied from the second vertical driver 22B. Is done. As described above, the first vertical driver 22A and the second vertical driver 22B alternately apply the vertical scanning pulse Vgate to the scanning lines 24 _{m + 1} , 24 _{m + 2} , and 24 _{m + 3} in the scanning direction. The pixel Vpix is connected to other pixels Vpix belonging to the same column of the display area unit 21 by signal lines 25 _{n + 1} , 25 _{n + 2} , and 25 _{n + 3} . The signal lines 25 _{n + 1} , 25 _{n + 2} , 25 _{n + 3} are connected to the horizontal driver 23, and pixel signals are supplied from the horizontal driver 23. The common potential Vcom of the common electrode COML is connected to a drive electrode driver (not shown), and a voltage is supplied from the drive electrode driver. Further, the pixel Vpix is connected to another pixel Vpix belonging to the same column of the display area unit 21 by the common potential Vcom of the common electrode COML.

The first vertical driver 22A and the second vertical driver 22B shown in FIGS. 1 and 2 send the vertical scanning pulse Vgate to the thin film transistor Tr of the pixel Vpix via the scanning lines 24 _{m + 1} , 24 _{m + 2} , and 24 _{m + 3} shown in FIG. By applying to the gate, one row (one horizontal line) of the pixels Vpix formed in a matrix in the display area 21 is sequentially selected as a display driving target. The horizontal driver 23 shown in FIGS. 1 and 2 sequentially selects pixel signals by the first vertical driver 22A and the second vertical driver 22B via the signal lines 25 _{n + 1} , 25 _{n + 2} and 25 _{n + 3 shown} in FIG. Each pixel Vpix including one horizontal line is supplied. In these pixels Vpix, display of one horizontal line is performed in accordance with the supplied pixel signal.

As described above, in the display device 1, one horizontal line is sequentially selected by driving the first vertical driver 22 _{</ b > A} and the second vertical driver 22 _{</ b >} B so that the scanning lines 24 _{m + 1} , 24 _{m + 2} , and 24 _{m + 3} are sequentially scanned. The In the display device 1, the horizontal driver 23 supplies a pixel signal to the pixels Vpix belonging to one horizontal line, so that display is performed for each horizontal line. When performing this display operation, the drive electrode driver applies the common potential Vcom of the common electrode COML corresponding to the one horizontal line.

  In the display device 1, there is a possibility that the specific resistance (resistance value specific to the substance) of the liquid crystal and the like deteriorate due to the continuous application of the direct current DC voltage to the liquid crystal element LC. The display device 1 employs a driving method in which the polarity of the video signal is inverted at a predetermined period with reference to the common potential Vcom of the driving signal in order to prevent deterioration of the specific resistance (substance specific to the substance) of the liquid crystal.

  As driving methods for this liquid crystal display panel, driving methods such as column inversion, line inversion, dot inversion, and frame inversion are known. Column inversion is a driving method in which the polarity of a video signal is inverted in a time period of 1 V (V is a vertical period) corresponding to one column (one pixel column). Line inversion is a driving method in which the polarity of a video signal is inverted at a time period of 1H (H is a horizontal period) corresponding to one line (one pixel row). The dot inversion is a driving method in which the polarity of the video signal is alternately inverted for each of the upper, lower, left and right adjacent pixels. Frame inversion is a driving method that inverts video signals to be written to all pixels for each frame corresponding to one screen at the same polarity. The display device 1 can employ any of the above driving methods.

  Next, the configuration of the display area unit 21 will be described in detail. FIG. 4 is a schematic diagram for explaining a circuit pattern of the liquid crystal display panel according to the present embodiment. FIG. 5 is a schematic diagram of a cross-sectional view taken along line VV in FIG. As shown in FIG. 5, the display area unit 21 includes a pixel substrate 70A, a counter substrate 70B disposed in a direction perpendicular to the surface of the pixel substrate 70A, and the pixel substrate 70A and the counter substrate 70B. A liquid crystal layer 70C inserted in In the pixel substrate 70A, the backlight 6 is disposed on the surface opposite to the liquid crystal layer 70C.

  The liquid crystal layer 70C modulates light passing therethrough according to the state of the electric field, and a liquid crystal display device using a liquid crystal in a transverse electric field mode such as FFS (fringe field switching) or IPS (in-plane switching). Used. The liquid crystal layer 70C may be a liquid crystal of various modes such as TN (Twisted Nematic), VA (Vertical Alignment), ECB (Electrically Controlled Birefringence). Note that alignment films may be provided between the liquid crystal layer 70C and the pixel substrate 70A and between the liquid crystal layer 70C and the counter substrate 70B shown in FIG.

  The counter substrate 70 </ b> B includes a glass substrate 75 and a color filter 76 formed on one surface of the glass substrate 75. The color filter 76 includes, for example, a color region colored in three colors of red (R), green (G), and blue (B). The color filter 76 periodically arranges, for example, color regions colored in three colors of red (R), green (G), and blue (B) in the opening 76b, and R is applied to each pixel Vpix shown in FIG. , G, and B are associated with each other as a pixel Pix. The color filter 76 faces the liquid crystal layer 70 </ b> C in a direction perpendicular to the TFT substrate 71. The color filter 76 may be a combination of other colors as long as it is colored in a different color. In general, in the color filter 76, the luminance of the green (G) color region is higher than the luminance of the red (R) color region and the blue (B) color region. The black matrix 76a may be formed so as to cover the outer periphery of the pixel Vpix shown in FIG. The black matrix 76a has a lattice shape by being arranged at the boundary between the two-dimensionally arranged pixels Vpix and the pixels Vpix. The black matrix 76a is formed of a material having a high light absorption rate.

  The pixel substrate 70A includes a TFT substrate 71 as a circuit substrate, a plurality of pixel electrodes 72 arranged in a matrix on the TFT substrate 71, and a common electrode COML formed between the TFT substrate 71 and the pixel electrode 72. And an insulating layer 74 that insulates the pixel electrode 72 from the common electrode COML. The common electrode COML is a transparent electrode formed of a transparent conductive material (transparent conductive oxide) such as ITO (Indium Tin Oxide).

On the TFT substrate 71, wirings such as the semiconductor layer 92 in which the thin film transistor Tr of each pixel Vpix is formed, the signal line 25 that supplies a pixel signal to each pixel electrode 72, the scanning line 24 that drives the thin film transistor Tr, and the like are insulating layers. 74 are stacked. The insulating layer 74 includes, for example, an insulating film 741 between the scanning line 24 and the semiconductor layer 92, an insulating film 742 between the semiconductor layer 92 and the signal line 25, and between the signal line 25 and the common electrode COML. An insulating film 743 and an insulating film 744 between the common electrode COML and the pixel electrode 72 are stacked. The insulating films 741, 742, 743, and 744 may be the same insulating material, or any of them may be different insulating materials. For example, the insulating film 743 is formed of an organic insulating material such as polyimide resin, and the other insulating films (the insulating film 741, the insulating film 742, and the insulating film 744) are inorganic insulating materials such as SiN and SiO _2. It is formed with.

  The signal line 25 extends in a plane parallel to the surface 71f of the TFT substrate 71, and supplies a pixel signal for displaying an image on the pixel. The semiconductor layer 92 is made of, for example, low-temperature polysilicon or amorphous silicon. A part of the semiconductor layer 92 is in contact with the signal line 25 and the other part is in contact with a base wiring 90 formed in the same layer as the signal line 25. In the present disclosure, the scanning line 24 is a first metal wiring that is a metal wiring such as molybdenum (Mo) and aluminum (Al), and the signal line 25 is a second metal wiring that is a metal wiring such as aluminum. The pedestal wiring 90 is a third metal wiring that is a metal wiring such as aluminum. The insulating layer 74 insulates the scanning line 24, the second metal wiring, and the semiconductor layer 92 except for the second contact portion 25 a and the first contact portion 90 a (contact hole) where the wiring contacts.

  The semiconductor layer 92, the signal line 25, and the scanning line 24 are formed in different layers in a direction (Z direction) perpendicular to the surface 71f of the TFT substrate 71. The signal line 25 and the pedestal wiring 90 are formed in the same layer in the direction (Z direction) perpendicular to the surface 71 f of the TFT substrate 71. The scanning line 24 crosses a part of the semiconductor layer 92 and acts as a gate of the thin film transistor Tr. In the present disclosure, there is one place where the scanning line 24 and a part of the semiconductor layer 92 are three-dimensionally crossed, and the thin film transistor Tr is a single gate transistor including an n-channel channel Ntft. In addition, the semiconductor layer 92 is bent in the middle of the semiconductor layer 92 that extends in parallel to the Y direction within a range overlapping the signal line 25. With this structure, a part of the channel Ntft is located at a position where the signal line 25 and the scanning line 24 are three-dimensionally crossed, a cross capacitance acting between the signal line 25 and the scanning line 24, and a capacitance of the channel Ntft. And operate in the same area. For this reason, the liquid crystal display panel 2 of the present embodiment can suppress the parasitic capacitance rather than the cross capacitance and the channel Ntft capacitance acting separately.

  In recent years, there has been a demand for higher definition display devices. As the display device has higher definition, the number of pixels increases, so that the number of wirings increases and the space for arranging the wirings increases. For this reason, the occupation ratio of the wiring on the liquid crystal display panel is increased, and the ratio of the aperture, that is, the aperture ratio, which is a range through which light is transmitted, is decreased. When the aperture ratio is small, the amount of light that can pass through the liquid crystal display panel is reduced with respect to the amount of light emitted from the light source. The liquid crystal display panel of the present embodiment shields light by overlapping the channel Ntft in which the scanning line 24 and a part of the semiconductor layer 92 are three-dimensionally intersected with the region in which the signal line 25 and the scanning line 24 are three-dimensionally intersected. The area is reduced and the aperture ratio is improved.

  The second contact portion 25a connected to the signal line 25 serves as, for example, the drain electrode of the thin film transistor Tr in the semiconductor layer 92. Further, the first contact portion 90 a of the semiconductor layer 92 is connected to the pixel electrode 72 through the base wiring 90. The first contact portion 90 a connected to the base wiring 90 is, for example, a source electrode of the thin film transistor Tr in the semiconductor layer 92. For example, when the second contact portion 25a is the source electrode of the thin film transistor Tr in the semiconductor layer 92, the first contact portion 90a is the drain electrode of the thin film transistor Tr in the semiconductor layer 92, for example. As shown in FIG. 3, the scanning line 24 becomes a gate of the thin film transistor Tr in the semiconductor layer 92.

  Here, as described above, the scanning line 24 and the signal line 25 are linear metal wirings, and are arranged so as to three-dimensionally intersect in a direction substantially orthogonal to each other. As shown in FIG. 4, the base wiring 90 has an edge of a region surrounded by a first direction (X direction) along the scanning line 24 and a second direction (Y direction) along the signal line 25 in the Z direction. It is arranged in the part.

  5, the display area unit 21 according to this embodiment is stacked in the Z direction in the order of the TFT substrate 71, the scanning line 24, the semiconductor layer 92, the signal line 25, the common electrode COML, and the pixel electrode 72. The display area unit 21 according to the present embodiment has a bottom gate structure in which the semiconductor layer 92 is disposed on a plane between the scanning line 24 and the signal line 25 in the Z direction. The extending portion 24A of the scanning line 24 is a metal wiring provided on the same plane as the plane parallel to the surface 71f of the TFT substrate 71 in which the scanning line 24 extends in the X direction. In the extending portion 24A, a part of the conductive metal of the scanning line 24 extends in the Y direction. For this reason, the extended portion 24 </ b> A is electrically connected to the scanning line 24 and has the same potential as the scanning line 24. Thereby, the extending part 24A can serve as both electric field shielding and the gate electrode of the thin film transistor Tr. The extending portion 24A has an area overlapping with the signal line 25 and overlapping with the channel region end PS near the first contact portion 90a. A part of the extending portion 24 </ b> A overlaps with the signal line 25. A boundary line 24a at a part of the edge of the extending portion 24A that does not overlap the signal line 25 extends in a direction different from the X direction and the Y direction. Further, as described above, the semiconductor layer 92 is bent in the middle of the semiconductor layer 92 that extends in parallel with the Y direction within a range overlapping the signal line 25. The semiconductor layer 92 extends toward the first contact portion 90a after being bent. The semiconductor layer 92 includes an extension direction of the semiconductor layer 92 extending toward the first contact portion 90a after bending, and a plane parallel to the Z direction including the line 24a of a part of the edge of the extension portion 24A. It is bent so that the angle formed is about 90 degrees. For this reason, the line segment length of the channel region end PS is minimized. As a result, the possibility of leakage current generated in the semiconductor layer 92 is suppressed. Here, about 90 degrees includes a manufacturing error of 85 degrees or more and 95 degrees or less.

  As shown in FIG. 4, there is a gap Sp between the base wiring 90 and the signal line 25 in the Z direction. The gap Sp is on both sides of the base wiring 90 in the X direction. The area | region which does not have the base wiring 90 between the adjacent signal lines 25 shown in FIG. 4 is the opening area | region Op. If the length 24y exceeds the end 90t of the pedestal wiring 90 on the side farther than the scanning line 24, the extended portion 24A overlaps the opening region Op. For this reason, the extending portion 24A shields the opening region Op, and the extending portion 24A may reduce the aperture ratio. In the extending portion 24A according to the present embodiment, the length 24y protruding from the scanning line 24 is a length that does not exceed the end portion 90t of the base wiring 90 on the side farther from the scanning line 24. Thereby, the extending part 24A according to the present embodiment can avoid overlapping the opening region Op in the Z direction. The extending portion 24A has a width 24x that overlaps the signal line 25 in the Z direction and protrudes into the gap Sp. That is, the width 24x in the X direction of the extending portion 24A is wider than the width 25x in the X direction of the signal line 25. Thus, the extending portion 24A partially overlaps the gap Sp in the Z direction. The extending portion 24 </ b> A according to the present embodiment can suppress a decrease in the aperture ratio by avoiding overlapping with the opening region Op in the Z direction. In this way, the extending portion 24A partially overlaps the gap Sp in the Z direction, but does not overlap the opening region Op.

  The extending portion 24A of the present embodiment is necessary for one of the two intervals of the base wiring 90 and the signal line 25, but is not necessary for the other. For this reason, the display area unit 21 according to the present embodiment can narrow the space between the signal lines 25 to reduce the pixel pitch (hereinafter also referred to as “narrow pitch correspondence”), thereby achieving high definition.

  As shown in FIGS. 4 and 5, the channel region Ntft is bent so that the channel region end PD on the signal line 25 side and close to the second contact portion 25 a overlaps the signal line 25. As shown in FIGS. 4 and 5, the channel region Ntft is not at the position where the channel region end PS on the pixel electrode 72 side and near the first contact portion 90 a overlaps the signal line 25. Thereby, in the direction perpendicular to the surface 71f of the TFT substrate 71, the virtual line extending the edge of the channel region end PD, the second channel end line PDL, and the virtual line extending the edge of the channel region end PS, The one channel end line PSL is not parallel to the positional relationship. That is, the angle formed by the first channel end line PSL and the second channel end line PDL has an angle θ and is not parallel. When the thin film transistor Tr is a single gate transistor and has a bottom gate structure, if the channel region end PD and the channel region end PS are covered with the signal line 25 having the same potential, the gate voltage is controlled. Even if the channel region Ntft is made non-conductive, there is a possibility that a phenomenon called back channel leakage occurs in which a leak current flows to the channel region Ntft through the back surface side of the semiconductor layer 92. In the channel region Ntft of the present embodiment, one of the channel region end PD and the channel region end PS is covered by the signal line 25, but the other is not covered by the signal line 25, and back channel leakage occurs. The possibility of occurring can be suppressed.

  The semiconductor layer 92 formed of low-temperature polysilicon preferably has a sufficiently low on-resistance as compared to the semiconductor layer 92 formed of amorphous silicon, and it is preferable to suppress leakage current at the time of off. Therefore, the semiconductor layer 92 formed of low-temperature polysilicon can reduce the line segment length of the channel region end PS and the channel region end PD compared to the semiconductor layer 92 formed of amorphous silicon. For example, in the semiconductor layer 92 formed of amorphous silicon, when the line segment length of the channel region end PS and the channel region end PD is large, the first channel end line PSL and the second channel end line PDL are parallel to each other. It is easier to manufacture. On the other hand, the semiconductor layer 92 formed of low-temperature polysilicon is set so that the first channel end line PSL and the second channel end line PDL are non-parallel to the semiconductor layer 92 formed of amorphous silicon. Is easy.

  FIG. 6 is a schematic diagram for explaining a circuit pattern of the liquid crystal display panel when the thin film transistor is a double gate transistor. FIG. 7 is a schematic diagram illustrating a cross section taken along line VII-VII in FIG. 6. The display area unit 21 illustrated in FIG. 6 does not include the extended portion 24A like the display area unit 21 according to the present embodiment. Further, the scanning line 24 shown in FIG. 6 crosses a part of the semiconductor layer 92 and acts as a gate of the thin film transistor Tr. As shown in FIGS. 6 and 7, there are two places where the scanning line 24 and a part of the semiconductor layer 92 intersect three-dimensionally, and the thin film transistor Tr includes an n-channel first channel Ntft1 and an n-channel. It is a double gate transistor provided with a certain second channel Ntft2. The semiconductor layer 92 is integrally formed by bending the ends of two thin wires extending in parallel to the Y direction. The first channel Ntft1 and the second channel Ntft2 are parallel and extend in the Y direction, and are connected in series. In the thin film transistor Tr, there is a possibility that the semiconductor layer 92 between the first channel Ntft1 and the second channel Ntft2 may reduce the aperture ratio. Since the display area unit 21 according to the present embodiment is a single gate, the semiconductor layer 92 between the first channel Ntft1 and the second channel Ntft2 is unnecessary. The display area unit 21 according to the present embodiment can have an aperture ratio higher than that of the display area 21 shown in FIG.

(First modification of this embodiment)
FIG. 8 is a schematic diagram for explaining a circuit pattern of a liquid crystal display panel according to a first modification of the present embodiment. FIG. 9 is a schematic diagram showing a main part of a cross section taken along line IX-IX in FIG. The same components as those described in the above-described embodiment are denoted by the same reference numerals, and redundant description is omitted.

  The display area unit 21 according to the first modification of the present embodiment has a bottom gate structure in which the semiconductor layer 92 is disposed on a plane between the scanning line 24 and the signal line 25 in the Z direction. In the first modification example of the present embodiment, the scanning line 24 and a part of the semiconductor layer 92 have a single intersection, and the thin film transistor Tr is a single gate transistor having an n-channel channel Ntft. In addition, the semiconductor layer 92 is bent in the middle of the semiconductor layer 92 that extends in parallel to the Y direction within a range overlapping the signal line 25. Thereby, in the direction perpendicular to the surface 71f of the TFT substrate 71, the second channel end line PDL indicating the edge of the channel region end PD and the first channel end line PSL indicating the edge of the channel region end PS are formed. The positional relationship is not parallel. With this structure, a part of the channel Ntft is located at a position where the signal line 25 and the scanning line 24 are three-dimensionally crossed, a cross capacitance acting between the signal line 25 and the scanning line 24, and a capacitance of the channel Ntft. And operate in the same area. For this reason, the liquid crystal display panel of the present embodiment can suppress the parasitic capacitance rather than the cross capacitance and the channel Ntft capacitance acting separately.

  As shown in FIG. 8, in the direction perpendicular to the surface 71f of the TFT substrate 71, the imaginary line extending the edge of the channel region end PD, the second channel end line PDL, and the edge of the channel region end PS are extended. An angle θ formed by the virtual line and the first channel end line PSL is about 90 degrees. Here, about 90 degrees includes a manufacturing error of 85 degrees or more and 95 degrees or less. As described above, the edge of the channel region end PD and the edge of the channel region end PS are non-parallel. When comparing the display area part 21 shown in FIG. 4 with the display area part 21 shown in FIG. 8, the display area part 21 shown in FIG. 4 described above is a channel region in a direction perpendicular to the surface 71f of the TFT substrate 71. The angle θ formed by the second channel end line PDL indicating the edge of the end PD and the first channel end line PSL indicating the edge of the channel region end PS does not include about 90 degrees. Therefore, the length of the semiconductor layer 92 shown in FIG. 4 is shorter than the length of the semiconductor layer 92 shown in FIG. 8, and the capacitance of the channel region Ntft is reduced, so that the parasitic capacitance can be reduced.

  The display area unit 21 according to the first modification example of the present embodiment illustrated in FIG. 9 includes the TFT substrate 71, the scanning line 24, the semiconductor layer 92, the signal line 25, the common electrode COML, and the pixel electrode 72 in the Z direction in this order. Are stacked. The extending portion 24B of the scanning line 24 is a metal wiring provided on the same plane as the plane parallel to the surface 71f of the TFT substrate 71 in which the scanning line 24 extends in the X direction. In the extending portion 24B, a part of the conductive metal of the scanning line 24 extends in the Y direction. For this reason, the extending portion 24 </ b> B is electrically connected to the scanning line 24 and has the same potential as the scanning line 24. Thereby, the extension part 24B can serve as both the electric field shielding and the gate electrode of the thin film transistor Tr.

  The extended portion 24B of the present embodiment is necessary for one of the two intervals of the base wiring 90 and the signal line 25, but is not necessary for the other. For this reason, the display area unit 21 according to the present embodiment can narrow the space between the signal lines 25 to reduce the pixel pitch (hereinafter also referred to as “narrow pitch correspondence”), thereby achieving high definition.

  As shown in FIGS. 8 and 9, the channel region Ntft is bent so that the channel region end PD on the signal line 25 side and near the second contact portion 25 a overlaps the signal line 25. Further, as shown in FIGS. 8 and 9, the channel region Ntft is not at the position where the channel region end PS on the pixel electrode 72 side and the first contact portion 90 a overlaps the signal line 25. In the channel region Ntft of the first modification example of the present embodiment, one of the channel region end PD and the channel region end PS is covered with the signal line 25, but the other is not covered with the signal line 25. The possibility of back channel leakage can be suppressed.

(Second modification of this embodiment)
FIG. 10 is a schematic diagram for explaining a circuit pattern of a liquid crystal display panel according to a second modification of the present embodiment. FIG. 11 is a schematic diagram illustrating a main part of a cross section taken along line XI-XI in FIG. The same components as those described in the above-described embodiment are denoted by the same reference numerals, and redundant description is omitted.

  The display area unit 21 according to the second modification of the present embodiment has a bottom gate structure in which the semiconductor layer 92 is disposed on a plane between the scanning line 24 and the signal line 25 in the Z direction. In the second modified example of the present embodiment, the scanning line 24 and a part of the semiconductor layer 92 have one place where the three-dimensional crossing occurs, and the thin film transistor Tr is a single gate transistor including an n-channel channel Ntft.

  The display area unit 21 according to the second modification of the present embodiment shown in FIG. 10 includes a TFT substrate 71, a scanning line 24, a semiconductor layer 92, a signal line 25, a common electrode COML, and a pixel electrode 72 in this order in the Z direction. Are stacked. The extending portion 24C of the scanning line 24 is a metal wiring provided on the same plane as the plane parallel to the surface 71f of the TFT substrate 71 in which the scanning line 24 extends in the X direction. In the extending portion 24C, a part of the conductive metal of the scanning line 24 extends in the Y direction. For this reason, the extended portion 24 </ b> C is electrically connected to the scanning line 24 and has the same potential as the scanning line 24. Thereby, the extending part 24C can serve as both the electric field shielding and the gate electrode of the thin film transistor Tr. In addition, the semiconductor layer 92 is bent in the middle of the semiconductor layer 92 extending in parallel with the Y direction in a range where it overlaps with the signal line 25, but the channel Ntft is only in the extending portion 24 </ b> C and overlaps with the signal line 25. Not in range. With this structure, the channel Ntft is not at a position where the signal line 25 and the scanning line 24 are three-dimensionally crossed, and the cross capacitance Cq acting between the signal line 25 and the scanning line 24 and the capacitance of the channel Ntft are Acts in different areas.

  The extending portion 24 </ b> C of this embodiment is necessary for one of the two intervals of the base wiring 90 and the signal line 25, but is not necessary for the other. However, the display area unit 21 according to the present embodiment is an arrangement in which the channel region Ntft extends in the X direction. For this reason, manufacturing errors in the manufacturing process of the semiconductor layer 92, the extended portion 24C of the scanning line 24, the signal line 25, and the base wiring 90, which determine the length of the channel region Ntft in the X direction, are overlapped. As a result, the arrangement margin of the semiconductor layer 92, the extending portion 24C of the scanning line 24, the signal line 25, and the pedestal wiring 90 needs to be large, so that the interval between the signal lines 25 is limited. As a result, the display area unit 21 according to the second modification example of the present embodiment is limited to support a narrow pitch.

  As shown in FIGS. 10 and 11, the channel region Ntft is not at the position where the channel region end PD on the signal line 25 side and near the second contact portion 25 a overlaps the signal line 25. Further, as shown in FIGS. 10 and 11, the channel region Ntft is not at a position where the channel region end PS on the pixel electrode 72 side and near the first contact portion 90 a overlaps the signal line 25. The channel region Ntft of the second modification example of the present embodiment suppresses the possibility that back channel leakage occurs because both of the channel region end PD and the channel region end PS are not covered by the signal line 25. Can do.

(Third Modification of this Embodiment)
FIG. 12 is a schematic diagram for explaining a circuit pattern of a liquid crystal display panel according to a third modification of the present embodiment. The same components as those described in the above-described embodiment are denoted by the same reference numerals, and redundant description is omitted. The schematic diagram of the cross section taken along line XI-XI shown in FIG. 12 is the same as the schematic diagram of the cross section shown in FIG.

  The display area unit 21 according to the third modification of the present embodiment has a bottom gate structure in which the semiconductor layer 92 is disposed on a plane between the scanning line 24 and the signal line 25 in the Z direction. In the third modified example of the present embodiment, the scanning line 24 and a part of the semiconductor layer 92 have one place where the three-dimensional crossing occurs, and the thin film transistor Tr is a single gate transistor having an n-channel channel Ntft.

  The display area part 21 according to the third modification of the present embodiment does not have the above-described extending parts 24A, 24B, and 24C. For this reason, the display area unit 21 according to the present embodiment can narrow the space between the signal lines 25 to reduce the pixel pitch (hereinafter also referred to as “narrow pitch correspondence”), thereby achieving high definition.

  Further, the semiconductor layer 92 is out of the range overlapping with the signal line 25, and the semiconductor layer 92 itself extending in parallel with the X direction in the opening region Op is bent in the Y direction in the middle. With this structure, the semiconductor layer 92 may cause a decrease in the aperture ratio. Further, a part of the channel Ntft is not located at the position where the signal line 25 and the scanning line 24 are three-dimensionally crossed, and the cross capacitance Cq acting between the signal line 25 and the scanning line 24 and the capacitance of the channel Ntft Works in different areas.

  As shown in FIG. 12, the channel region Ntft is not at the position where the channel region end PD on the signal line 25 side and near the second contact portion 25 a overlaps the signal line 25. As shown in FIG. 12, the channel region Ntft is not on the pixel electrode 72 side and the channel region end PS near the first contact portion 90a does not overlap the signal line 25. The channel region Ntft of the third modification example of the present embodiment suppresses the possibility that back channel leakage occurs because both the channel region end PD and the channel region end PS are not covered by the signal line 25. Can do.

(Fourth modification of the present embodiment)
FIG. 13 is a schematic diagram for explaining a circuit pattern of a liquid crystal display panel according to a fourth modification of the present embodiment. FIG. 14 is a schematic diagram illustrating a main part of a cross section taken along line XIV-XIV in FIG. 13. The same components as those described in the above-described embodiment are denoted by the same reference numerals, and redundant description is omitted.

  The display area unit 21 according to the fourth modification of the present embodiment has a bottom gate structure in which the semiconductor layer 92 is disposed on a plane between the scanning line 24 and the signal line 25 in the Z direction. In the fourth modification example of the present embodiment, the scanning line 24 and a part of the semiconductor layer 92 have a single intersection, and the thin film transistor Tr is a single gate transistor having an n-channel channel Ntft.

  The display area unit 21 according to the fourth modification example of the present embodiment does not include the above-described extending portions 24A, 24B, and 24C. For this reason, the display area unit 21 according to the present embodiment can narrow the space between the signal lines 25 to reduce the pixel pitch (hereinafter also referred to as “narrow pitch correspondence”), thereby achieving high definition.

  In addition, the semiconductor layer 92 is bent in the middle of the semiconductor layer 92 extending in parallel with the Y direction in a range where it overlaps with the signal line 25, but the channel Ntft exists only in a range where it overlaps with the signal line 25. With this structure, the channel Ntft is at a position where the signal line 25 and the scanning line 24 are three-dimensionally crossed, and the cross capacitance acting between the signal line 25 and the scanning line 24 is the same as the capacitance of the channel Ntft. Act in the area. For this reason, the liquid crystal display panel according to the fourth modification example of the present embodiment can suppress the parasitic capacitance rather than the cross capacitance and the capacitance of the channel Ntft acting separately. However, as shown in FIGS. 13 and 14, the channel region Ntft is in a position where the channel region end PD on the signal line 25 side and close to the second contact portion 25 a overlaps the signal line 25. As shown in FIGS. 13 and 14, the channel region Ntft is located on the pixel electrode 72 side and at the position where the channel region end PS near the first contact portion 90a overlaps the signal line 25. As a result, in the channel region Ntft of the fourth modification example of the present embodiment, both the channel region end PD and the channel region end PS are covered with the signal line 25, and there is a possibility that back channel leakage occurs. .

(Fifth modification of this embodiment)
FIG. 15 is a schematic diagram for explaining a circuit pattern of a liquid crystal display panel according to a fifth modification of the present embodiment. The same components as those described in the above-described embodiment are denoted by the same reference numerals, and redundant description is omitted. The schematic diagram of the IX-IX line section shown in FIG. 15 is the same as the schematic diagram of the line section shown in FIG.

  The display area unit 21 according to the fifth modification of the present embodiment has a bottom gate structure in which the semiconductor layer 92 is disposed on a plane between the scanning line 24 and the signal line 25 in the Z direction. In the fifth modified example of the present embodiment, the scanning line 24 and a part of the semiconductor layer 92 have one place where the three-dimensional crossing occurs, and the thin film transistor Tr is a single gate transistor including an n-channel channel Ntft.

  The display area part 21 according to the fifth modification of the present embodiment does not have the above-described extending parts 24A, 24B, and 24C. However, the scanning line 24 is bent so that the position in the Y direction where the signal line 25 and the scanning line 24 cross each other is different from the position in the Y direction extending in the X direction between the signal lines 25. Meandering. For this reason, the meandering portion of the signal line 24 passes through both of the two intervals of the pedestal wiring 90 and the signal line 25 instead of the above-described extending portions 24A, 24B, and 24C. For this reason, the display area part 21 shown in FIG. 15 has restrictions on the space | interval which narrows between the signal lines 25. FIG.

  In addition, the semiconductor layer 92 is bent in the middle of the semiconductor layer 92 that extends in parallel to the Y direction within a range overlapping the signal line 25. With this structure, a part of the channel Ntft is located at a position where the signal line 25 and the scanning line 24 are three-dimensionally crossed, a cross capacitance acting between the signal line 25 and the scanning line 24, and a capacitance of the channel Ntft. And operate in the same area. For this reason, the liquid crystal display panel of the present embodiment can suppress the parasitic capacitance rather than the cross capacitance and the channel Ntft capacitance acting separately.

  As shown in FIG. 15, the channel region Ntft is bent so that the channel region end PD on the signal line 25 side and close to the second contact portion 25 a overlaps the signal line 25. As shown in FIG. 15, the channel region Ntft is not at the position where the channel region end PS on the pixel electrode 72 side and near the first contact portion 90 a overlaps the signal line 25. In the channel region Ntft of the fifth modification example of the present embodiment, one of the channel region end PD and the channel region end PS is covered by the signal line 25, but the other is not covered by the signal line 25. The possibility of back channel leakage can be suppressed.

<2. Evaluation example>
FIG. 16 is an explanatory diagram for explaining an evaluation result of the evaluation example. In order to examine the operational effects of the present embodiment and the modification described above, the manufacturing apparatus manufactured Evaluation Examples 1 to 6. The manufacturing apparatus manufactured a liquid crystal display panel having the display area unit 21 according to the present embodiment shown in FIG. The manufacturing apparatus manufactured a liquid crystal display panel having the display area portion 21 according to the first modification of the present embodiment shown in FIG. The manufacturing apparatus manufactured a liquid crystal display panel having the display area portion 21 according to the second modified example of the present embodiment shown in FIG. The manufacturing apparatus manufactured a liquid crystal display panel having the display area portion 21 according to the third modification of the present embodiment shown in FIG. The manufacturing apparatus manufactured a liquid crystal display panel having the display area portion 21 according to the fourth modification of the present embodiment shown in FIG. The manufacturing apparatus manufactured a liquid crystal display panel having the display area portion 21 according to the fifth modification example of the present embodiment shown in FIG. The evaluation results are the results of evaluating the narrow pitch correspondence, the aperture ratio, the parasitic capacitance, and the back channel leakage in the evaluation examples 1 to 6, and are shown in FIG.

  For the narrow pitch correspondence shown in FIG. 16, for example, compared with the circuit pattern of the liquid crystal display panel when the thin film transistor shown in FIG. As shown in FIG. 16, Evaluation Example 1, Evaluation Example 2, Evaluation Example 4 and Evaluation Example 5 were evaluated as “good”. Moreover, the evaluation example 3 and the evaluation example 6 were evaluation of x.

  For example, when the aperture ratio shown in FIG. 6 is a double gate transistor shown in FIG. The equivalent or lower was evaluated as x. As shown in FIG. 16, Evaluation Example 1, Evaluation Example 2, Evaluation Example 3, and Evaluation Example 5 were evaluated as “good”. Moreover, the evaluation example 6 was evaluation of (triangle | delta). Evaluation example 4 was evaluation of x.

  As for the parasitic capacitance shown in FIG. 16, for example, the case where the parasitic capacitance of the circuit pattern of the liquid crystal display panel when the thin film transistor shown in FIG. As shown in FIG. 16, Evaluation Example 1 and Evaluation Example 5 were evaluations of “◯”. Moreover, Evaluation Example 2, Evaluation Example 3, Evaluation Example 4, and Evaluation Example 6 were evaluated as Δ.

  The back channel leak shown in FIG. 16 was evaluated as “x” when the back channel leak occurred in the evaluation examples, and “◯” when the back channel leak did not occur. As shown in FIG. 16, Evaluation Example 1, Evaluation Example 2, Evaluation Example 3, Evaluation Example 4 and Evaluation Example 6 were evaluated as “good”. Moreover, the evaluation example 5 was evaluation of x.

<3. Application example>
Next, an application example of the display device 1 described in the embodiment will be described with reference to FIGS. FIGS. 17 to 29 are diagrams illustrating examples of electronic apparatuses to which the liquid crystal display panel according to the present embodiment and the modification are applied. The display device 1 according to the present embodiment can be applied to electronic devices in various fields such as a television device, a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, or a video camera. In other words, the display device 1 according to the present embodiment can be applied to electronic devices in various fields that display an externally input video signal or an internally generated video signal as an image or video. The electronic device includes a control device that supplies a video signal to the liquid crystal display panel and controls the operation of the liquid crystal display panel.

(Application example 1)
The electronic device shown in FIG. 17 is a television device to which the display device 1 according to the present embodiment is applied. The television apparatus includes, for example, a video display screen unit 510 including a front panel 511 and a filter glass 512, and the video display screen unit 510 is a liquid crystal display panel according to this embodiment and a modification. .

(Application example 2)
The electronic device shown in FIGS. 18 and 19 is a digital camera to which the display device 1 according to this embodiment is applied. The digital camera includes, for example, a flash light emitting unit 521, a display unit 522, a menu switch 523, and a shutter button 524, and the display unit 522 is a liquid crystal display panel according to the present embodiment and the modification. .

(Application example 3)
The electronic device shown in FIG. 20 represents the appearance of a video camera to which the display device 1 according to this embodiment is applied. This video camera has, for example, a main body 531, a subject photographing lens 532 provided on the front side surface of the main body 531, a start / stop switch 533 during photographing, and a display 534. The display unit 534 is a liquid crystal display panel according to the present embodiment and the modification.

(Application example 4)
The electronic apparatus shown in FIG. 21 is a notebook personal computer to which the display device 1 according to this embodiment is applied. The notebook personal computer has, for example, a main body 541, a keyboard 542 for inputting characters and the like, and a display unit 543 for displaying an image. The display unit 543 is a liquid crystal according to the present embodiment and the modification. It is a display panel.

(Application example 5)
The electronic apparatus shown in FIGS. 22 to 28 is a mobile phone to which the display device 1 according to this embodiment is applied. This mobile phone is, for example, a structure in which an upper housing 551 and a lower housing 552 are connected by a connecting portion (hinge portion) 553 and includes a display 554, a sub display 555, a picture light 556, and a camera 557. Yes. The display 554 or the sub display 555 is a liquid crystal display panel according to the present embodiment and the modification.

(Application example 6)
The electronic device illustrated in FIG. 29 is an information portable terminal that operates as a portable computer, a multifunctional portable phone, a portable computer capable of voice communication, or a portable computer capable of communication, and is sometimes referred to as a so-called smartphone or tablet terminal. . This information portable terminal has a display unit 562 on the surface of a housing 561, for example. The display unit 562 is a liquid crystal display panel according to this embodiment and a modification. The display unit 562 includes a so-called touch panel that detects an object close to the liquid crystal display panel.

<4. Configuration of the present disclosure>
In addition, the present disclosure can take the following configurations.

(1) A liquid crystal display panel comprising: a first substrate; a second substrate disposed opposite to the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate. ,
The first substrate is
A plurality of pixel electrodes arranged in a matrix;
A thin film transistor connected to the pixel electrode at a first contact portion;
A plurality of first metal wirings which are in a layer different from the semiconductor layer of the thin film transistor in a direction perpendicular to the surface of the first substrate and which intersect with each other to form a scanning line in order to make a part of the semiconductor layer a channel region When,
A signal line connected to the semiconductor layer by a second contact portion and three-dimensionally intersecting the first metal wiring by extending in a second direction different from the first direction in which the first metal wiring extends. A plurality of second metal wirings,
The thin film transistor is a liquid crystal display panel in which the channel region is a single gate transistor.

(2) The semiconductor layer is disposed in a plane between the first metal wiring and the second metal wiring, and the channel region is bent, so that the end of the channel region near the second contact portion is The liquid crystal display panel according to (1), wherein the liquid crystal display panel is located at a position overlapping with the second metal wiring, and an end portion of the channel region near the first contact portion is not located at a position overlapping with the second metal wiring.

(3) The liquid crystal display panel according to (2), wherein a part of the channel region is at a position where the first metal wiring and the second metal wiring are three-dimensionally crossed.

(4) A part of the metal of the first metal wiring further includes an extending part that protrudes and extends in the second direction, and the part of the extending part overlaps the second metal wiring and extends. The liquid crystal display panel according to any one of (1) to (3), wherein an edge portion that does not overlap the second metal wiring is different from the first direction.

(5) The extending portion overlaps the second metal wiring in a direction perpendicular to the surface of the first substrate, and has a width that protrudes from the second metal wiring toward the first contact portion. The liquid crystal display panel according to (4).

(6) In a direction perpendicular to the surface of the first substrate, a first channel end line indicating an edge of the end of the channel region near the first contact portion; and a channel region near the second contact portion. The liquid crystal display panel according to any one of (1) to (5), wherein the liquid crystal display panel is not parallel to a second channel end line indicating an edge of the end.

(7) The liquid crystal display panel according to (6), wherein an angle formed by the first channel end line and the second channel end line does not include 90 degrees.

(8) The liquid crystal display panel according to any one of (4) to (7), wherein the extending portion has the same potential as the scanning line.

(9) An electronic device comprising the liquid crystal display panel according to any one of (1) to (8).

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 Liquid crystal display panel 6 Backlight 11 Glass substrate 11gr, 11gl Frame 21 Display area part 22A 1st vertical driver 22B 2nd vertical driver 24 Scan line 24A, 24B, 24C Extension part 25 Signal line 71 TFT substrate 72 Pixel Electrode 75 Glass substrate 76 Color filter 90 Base wiring 92 Semiconductor layer LC Liquid crystal element Tr Thin film transistor COML Common electrode Vpix Pixel

Claims (8)

A liquid crystal display panel comprising: a first substrate; a second substrate disposed opposite to the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate,
The first substrate is
A plurality of pixel electrodes arranged in a matrix;
A thin film transistor connected to the pixel electrode at a first contact portion;
A plurality of first metal wirings which are in a layer different from the semiconductor layer of the thin film transistor in a direction perpendicular to the surface of the first substrate and which intersect with each other to form a scanning line in order to make a part of the semiconductor layer a channel region When,
A signal line connected to the semiconductor layer by a second contact portion and three-dimensionally intersecting the first metal wiring by extending in a second direction different from the first direction in which the first metal wiring extends. A plurality of second metal wirings,
In the thin film transistor, the channel region is a single gate transistor,
The semiconductor layer is disposed in a plane between the first metal wiring and the second metal wiring;
Since the channel region is bent, the end of the channel region near the second contact portion overlaps the second metal wiring, and the end of the channel region near the first contact portion is A liquid crystal display panel that does not overlap with two metal lines.   2. The liquid crystal display panel according to claim 1, wherein a part of the channel region is located at a position where the first metal wiring and the second metal wiring are three-dimensionally crossed. An extension portion in which a part of the metal of the first metal wiring protrudes in the second direction and extends;
The part of the extended portion overlaps with the second metal wiring, and an edge portion that does not overlap with the second metal wiring in the extended portion is different from the first direction. LCD display panel.   The extension portion overlaps with the second metal wiring in a direction perpendicular to the surface of the first substrate and has a width that protrudes from the second metal wiring toward the first contact portion. 3. A liquid crystal display panel according to 3.   In a direction perpendicular to the surface of the first substrate, a first channel end line indicating an edge of the end of the channel region near the first contact portion, and an end of the channel region near the second contact portion 5. The liquid crystal display panel according to claim 1, wherein the liquid crystal display panel is not parallel to a second channel end line indicating an edge. 6.   The liquid crystal display panel according to claim 5, wherein an angle formed by the first channel end line and the second channel end line does not include 90 degrees.   The liquid crystal display panel according to claim 3, wherein the extended portion has the same potential as the scanning line. An electronic apparatus having a liquid crystal display panel comprising: a first substrate; a second substrate disposed opposite to the first substrate; and a liquid crystal layer disposed between the first substrate and the second substrate. And
The first substrate of the liquid crystal display panel is:
A plurality of pixel electrodes arranged in a matrix;
A thin film transistor connected to the pixel electrode at a first contact portion;
A plurality of first metal wirings which are in a layer different from the semiconductor layer of the thin film transistor in a direction perpendicular to the surface of the first substrate and which intersect with each other to form a scanning line in order to make a part of the semiconductor layer a channel region When,
A signal line connected to the semiconductor layer by a second contact portion and three-dimensionally intersecting the first metal wiring by extending in a second direction different from the first direction in which the first metal wiring extends. A plurality of second metal wirings,
In the thin film transistor, the channel region is a single gate transistor,
The semiconductor layer is disposed in a plane between the first metal wiring and the second metal wiring;
Since the channel region is bent, the end of the channel region near the second contact portion overlaps the second metal wiring, and the end of the channel region near the first contact portion is Electronic equipment that does not overlap with 2 metal wiring.

Images