JP2014147000A - Modulation signal processing circuit and modulation signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a modulation signal processing circuit and a modulation signal processing method capable of reducing a circuit scale in QPSK-IFDM, and also capable of reducing power consumption without performing a plurality of complex multiplications.SOLUTION: Provided is a modulation signal processing circuit in an OFDM-based communication system, the modulation signal processing circuit comprising: a QPSK phase modulator 31 for converting user data into a real number sequence representing a phase; a pre-stage IFDM modulator 32 for repeatedly rearranging the real number sequence from the QPSK phase modulator 31; a post-stage IFDM modulator 33 for performing a conversion process by address addition and sign inversion arithmetic on the real number sequence rearranged by the pre-stage IFDM modulator 32; and a phase IQ modulator 34 for converting the output from the post-stage IFDM modulator 33 into a complex series by using a waveform invoked from a LUT 35.

Description

  The present invention relates to a modulation signal processing circuit and a modulation signal processing method in a system that performs communication using subcarriers of orthogonal frequency division multiplexing (OFDM).

  Conventional interleaved frequency domain multiplexing (IFDM) and block IFDM modulation signal processing circuits use a first-stage modulation unit that performs modulation so that subcarriers are interleaved at fixed intervals, and a complex multiplication of the first-stage signal. And a post-stage modulation unit that shifts on the frequency axis by a detector (see Non-Patent Document 1, for example).

  Here, the pre-modulation part (4 blocks up to Insert cyclic prefix in FIG. 4) of Non-Patent Document 1 replaces the input signal with iterative rearrangement of the time series signal by modifying the arithmetic expression, thereby performing discrete Fourier transform. Multiplication processing such as (DFT: Discrete Fourier Transform) can be dispensed with and can be implemented with a simple signal processing circuit.

  On the other hand, since the post-modulation unit of NPL 1 (four blocks after the Insert cyclic prefix in FIG. 4) needs to perform complex multiplication for each sample, a large-scale signal processing circuit is required. Necessary and power consumption increases.

  Further, even when this IFDM modulation signal processing circuit is applied to quadrature phase shift keying (QPSK), generally, a signal obtained by repeatedly converting user data into a complex sequence and reordering the user data is 1 Since complex multiplication is required for each sample, a large-scale signal processing circuit is required, and power consumption is increased.

E. P. Simon, D.C. P. Gaillot, V.M. Degardin, “Synchronization sensitivity of block-IFDMA systems”, IEEE Trans. Wirel. Commun. , Vol. 9, no. 1,256-267, 2010

However, the prior art has the following problems.
That is, in the conventional QPSK-IFDM modulation signal processing circuit, as described above, since complex multiplication needs to be performed for each sample, a large-scale signal processing circuit is required, and power consumption increases. .

  The present invention has been made to solve the above-described problems. In QPSK-IFDM, the circuit scale can be reduced and power consumption can be reduced without performing a plurality of complex multiplications. An object of the present invention is to provide a modulation signal processing circuit and a modulation signal processing method capable of performing the above.

  A modulation signal processing circuit according to the present invention is a modulation signal processing circuit in an OFDM communication system, and converts a QPSK phase modulator that converts user data into a real number sequence representing a phase, and a real number sequence from the QPSK phase modulator. A pre-stage IFDM modulator that performs repetitive rearrangement, a post-stage IFDM modulator that performs conversion processing by addition of addresses and sign inversion on a real number sequence that is repetitively rearranged by the pre-stage IFDM modulator, and a post-stage IFDM modulator A phase IQ modulator that converts an output into a complex sequence using a waveform called from an LUT.

  A modulation signal processing method according to the present invention is a modulation signal processing method executed by a modulation signal processing circuit in a communication system using OFDM, and includes a QPSK phase modulation step for converting user data into a real number sequence representing a phase; , The former IFDM modulation step for iteratively rearranging the real number sequence converted in the QPSK phase modulation step, and the real number sequence repeatedly rearranged in the previous IFDM modulation step are subjected to conversion processing by address addition and sign inversion operation A post-stage IFDM modulation step and a phase IQ modulation step for converting the output of the post-stage IFDM modulation step into a complex sequence using a waveform called from the LUT.

According to the modulation signal processing circuit and the modulation signal processing method of the present invention, the QPSK phase modulator (step) converts the user data into a real number sequence representing the phase, and the preceding IFDM modulator (step) The real number sequence from the modulator is repetitively rearranged, and the rear-stage IFDM modulator (step) performs conversion processing by addition of addresses and sign inversion operation on the real number sequence repeatedly rearranged by the front-stage IFDM modulator, The phase IQ modulator (step) converts the output from the post-stage IFDM modulator into a complex sequence using the waveform called from the LUT.
Therefore, in QPSK-IFDM, it is possible to obtain a modulation signal processing circuit and a modulation signal processing method capable of reducing the circuit scale and reducing power consumption without performing a plurality of complex multiplications.

It is a block diagram which shows a general QPSK-IFDM modulation signal processing circuit. It is a block diagram showing an IFDMA modulation signal processing circuit with a frame length excluding CP of 64 points and QPSK as a primary modulation scheme. (A), (b) is explanatory drawing which shows the reduction | restoration description example of the vector width which used the moving average filter circuit as an example, and the word length. (A), (b) is explanatory drawing which shows the reduction notation example of a 2's complement or a sign inversion arithmetic circuit. (A)-(c) is explanatory drawing which shows the contraction description example of a complex multiplication circuit. (A), (b) is explanatory drawing which shows the example of a fixed-point reduction notation in a bit shift divider. (A), (b) is explanatory drawing which shows the example of contraction notation of the signed fixed point in the bit shift multiplier with a clip process. It is a block diagram which shows the QPSK-IFDMA modulation signal processing circuit based on Embodiment 1 of this invention. It is a block diagram which shows the IFDMA modulation signal processing circuit which uses QPSK as a primary modulation system with a frame length excluding CP of 64 points according to Embodiment 2 of the present invention. It is a block diagram which shows the IFDMA modulation signal processing circuit which uses QPSK as a primary modulation system with a frame length excluding CP of 64 points according to Embodiment 3 of the present invention. It is a block diagram which shows the circuit which combined the 64 point 8PSK-IFDMA modulation signal processing circuit based on Embodiment 4 of this invention with 8fold Tweedle LUT. It is a block diagram which shows the QPSK-Block IFDMA modulation circuit at the time of 64 points | pieces and 4CP concerning Embodiment 5 of this invention.

  Hereinafter, preferred embodiments of a modulation signal processing circuit and a modulation signal processing method according to the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts will be described with the same reference numerals. .

  First, a general QPSK-IFDM modulation signal processing circuit will be described with reference to FIG. In FIG. 1, the QPSK-IFDM modulation signal processing circuit includes a QPSK IQ modulator 11, a front IFDM modulator 12, a rear IFDM modulator 13, a LUT (Look Up Table) 14, and a complex multiplier 15.

  The QPSK IQ modulator 11 converts user data into a complex sequence. The front IFDM modulator 12 reorders the complex sequence from the QPSK IQ modulator 11. The post-stage IFDM modulator 13 multiplies the complex sequence repeatedly rearranged by the pre-stage IFDM modulator 12 and the waveform called from the LUT 14 using the complex multiplier 15 for each sample.

  That is, according to the configuration of the QPSK-IFDM modulation signal processing circuit shown in FIG. 1, it is necessary to perform a plurality of complex multiplications as described above, so that a large-scale signal processing circuit is required and power consumption is large. There is a problem of becoming.

  Next, a more specific configuration will be described with reference to FIG. In FIG. 2, contracted symbols are used to simplify the description. These contracted symbols will be described later.

  FIG. 2 shows an interleaved frequency domain multiplexing (IFDMA) modulation signal processing with a frame length of 64 points excluding a cyclic prefix (CP) and QPSK as a primary modulation scheme. It is a block diagram at the time of mounting a circuit in a form faithful to the principle formula.

  In FIG. 2, this IFDMA modulation signal processing circuit includes a PN (Pseudo-random Noise) sequence generation circuit, an IFDMA modulation processing circuit, a PA (Preamble) and CP generation / insertion circuit, a carrier frequency offset (CFO: Carrier Frequency Offset). A compensator, a DC (Direct Current) offset circuit, and a DAC (Digital Analog Converter) / Serdes (SERializer / DESerizer) interface circuit are included.

  A PN generator 21 (PN Gen in the figure) constituting the PN sequence generation circuit generates a 32 parallel expanded PN sequence and outputs it as 16 parallel 2-bit words. This 2-bit word is converted into a 16 × 2 parallel complex Gray code corresponding to Gray mapping on the IQ plane by the subsequent LUT 22 constituting the IFDMA modulation processing circuit.

  Also, this complex Gray code is expanded in parallel by 64 × 2 by being multiplied by 4 for each code by the fan-out 23 that also forms the IFDMA modulation processing circuit, and processing corresponding to repetitive repetition in the time domain is performed. That is, this is a pre-modulation process of IFDM modulation. Here, the Gray code mapping LUT 22 needs to store an address width of 2 bits / word width of 10 bits in parallel with 16 × 2 and has a capacity of 1.25 kbit (= 4 × 10 × 16 × 2/1024).

  A selector 24 constituting a generation / insertion circuit is arranged at the subsequent stage of the IFDMA modulation processing circuit, and processing for time-multiplexing PA and Pilot symbols stored in the LUT 25 also constituting the generation / insertion circuit according to a desired burst frame format is performed. Done. Thereafter, the first four sample portions of the multiplexed signal are added to the tail as a CP by the fan-out 26 that also forms the generation / insertion circuit, and 68 × 2 parallel 10-bit words are obtained.

  In parallel with the above circuit, a circuit that generates a Tweedle waveform for frequency shift is required as a CFO compensator. This circuit increments the read pointer value of the LUT 27 that accommodates the Tweedle waveform. It is realized by.

  Note that the basic capacity of the Tweedle waveform accommodation LUT 27 is 1,360 kbit (= 1024 × 10 × 68 × 2/1024) when the address bit width is approximately equal to the data bit width. However, the required capacity can be reduced to 1/8 at the maximum by folding accommodation.

  The address generation circuit 28 is supplied with a Map signal indicating which subcarriers are allocated to the user and a CSI (Carrier State Information) signal indicating the CFO value, the polarity of the LN, and the like, and derives an address. . Here, the Map information of the Map signal and the polarity information of the CSI signal are given from the system so as not to cause subcarrier collision for each transmitter, and are updated synchronously in units of bursts.

  The CSI signal is updated as needed by detecting the CFO of the transmitter by the pilot unit at the receiver. Therefore, a good carrier synchronization characteristic can be obtained by updating the value related to the CFO of the CSI signal as needed in symbol units.

  The operations of the complex multiplier 29, the DC offset circuit 30, and the DAC / Serdes interface circuit 31 constituting the CFO compensator are the same as those of the post-stage IFDM modulator 13, the LUT 14, and the complex multiplier 15 shown in FIG. Is omitted.

  Here, with reference to FIG. 2 described above, symbols contracted to simplify the description will be described. Note that these contracted symbols are similarly applied to the following embodiments. The contracted symbols that appear for the first time in the following embodiments will also be described together.

(1) Reduced Notation of Vector Width and Word Length FIGS. 3A and 3B are explanatory diagrams showing reduced notation examples of vector width and word length taking a moving average filter circuit as an example. In FIG. 3, (b) represents the signal processing circuit of (a) in a more reduced form.

  The moving average filter circuit shown in FIG. 3 defines a word length m obtained by replacing a real or complex signal having originally infinite precision with a fixed-point signal having mbit finite precision, and this fixed-point word signal. Is defined as the vector width. Note that the word length of Boolean is 1, and when the vector width or the word length is 1, abbreviations can also be made.

(2) Reduced Notation of 2's Complement or Sign Inversion Operation Circuit FIGS. 4A and 4B are explanatory diagrams showing an example of reduced notation of a 2's complement or sign inversion operation circuit. In FIG. 4, since this circuit represents a complement operation, the main signal represented by the black arrow that passes from the left to the right is not Boolean, but the word length notation is omitted.

  In addition, the inverter naturally represents the number of bit computing units that are parallelized by a number equal to the word length. In this circuit example, an unsigned signal and a signed signal are defined, a conversion circuit between them is shown, and a Boolean signal instructing sign inversion is indicated by being outlined.

  Note that FIG. 4B is an example in which the circuit of FIG. 4A is further reduced, but the Boolean signal is further omitted as an extension.

(3) Reduced Notation of Complex Multiplier Circuit FIGS. 5A to 5C are explanatory diagrams showing reduced notation examples of the complex multiplier circuit. FIG. 5A shows a schematic configuration of the complex multiplication circuit, and it is understood that the complex multiplication circuit includes four multipliers, one adder, and one subtracter. The subtracter has a circuit configuration similar to that of the subtracter in the two's complement arithmetic circuit, and the same symbol is used here.

  In addition, an adder that receives a real variable having a word length m as two inputs can be constituted by the same number of bit operation unit circuits as the word length m, whereas a multiplier is basically equal to the cube of the word length m. It is composed of a number of bit operation unit circuits. In an actual adder or multiplier circuit, the situation is more complicated because the circuit can be optimized according to the input word length and allowable processing time, but if the word length is somewhat long, the multiplier becomes a bottleneck for circuit resources. Is basically possible.

  In view of these points, only the number of multipliers may be indicated as shown in FIG. 5B, and may be abbreviated as shown in FIG. 5C.

(4) Fixed-Point Reduction Notation in Bit Shift Divider FIGS. 6A and 6B are explanatory diagrams showing examples of fixed-point reduction notation in the bit shift divider. As shown in FIG. 6, the fraction length is expressed with respect to the word length, and the decimal point position is changed as a result even if the circuit is not accompanied by an actual operation such as a bit shift circuit or is merely a change in signal interpretation. The accompanying part and the part in which the word length is changed but the decimal point position is not changed are shown separately as shown in the figure.

  In addition, if the decimal point position is not changed, the replica branch of the signal, the merging and branching of the vector, the change of the vector width associated therewith, the truncation of the most significant bit (MSB: Most Significant Bit) ignoring carryover, and the least significant bit The same notation can be used for truncation of a bit (LSB: Least Significant Bit).

  In addition, regarding the handling of the word length, when processing such as ignoring the carry-over signal at the output part of the adder, this notation is not particularly used, and the fixed-point position or word in the input / output is simply not used. Sometimes expressed as a transition of length.

(5) Signed Fixed-Point Reduction Notation in Bit Shift Multiplier with Clip Processing FIGS. 7A and 7B are examples of signed fixed-point reduction notation in a bit shift multiplier with clip processing. It is explanatory drawing shown. As shown in FIG. 7, generally, even in a bit shift multiplication, when a clip process or a code process is involved, an actual operation may be involved. As described above, when the actual operation is involved, not the conversion notation based only on the wiring definition as described above but the circuit notation based on the arithmetic unit type symbol.

Embodiment 1 FIG.
FIG. 8 is a block diagram showing a QPSK-IFDMA modulation signal processing circuit according to Embodiment 1 of the present invention. In FIG. 8, the QPSK-IFDMA modulation signal processing circuit includes a QPSK phase modulator 31, a front-stage IFDM modulator 32, a rear-stage IFDM modulator 33, a phase IQ modulator 34, and an LUT 35.

  Here, the QPSK-IFDMA modulation signal processing circuit according to the first embodiment of the present invention is different from the general QPSK-IFDM modulation signal processing circuit shown in FIG. 1 in that a QPSK phase modulator 31 and a post-stage IFDM modulator 33 are used. And the phase IQ modulator 34 is different.

  The QPSK phase modulator 31 converts user data into a real number sequence representing a phase. The pre-stage IFDM modulator 32 repeatedly rearranges the real number sequence from the QPSK phase modulator 31. The post-stage IFDM modulator 33 performs a conversion process (a process corresponding to a frequency shift) by addition of an address (real number) and a sign inversion operation on the real number sequence reordered by the pre-stage IFDM modulator 12. The phase IQ modulator 34 converts the output from the post-stage IFDM modulator 33 into a complex sequence using the waveform called from the LUT 35.

  Specifically, it can be seen that this QPSK-IFDMA modulation signal processing circuit can perform modulation signal processing without using a complex multiplier by expanding the equation as follows. Here, a modulation calculation process in the case of performing 25% bandwidth allocation in 64-point QPSK-IFDMA will be described as an example.

First, assuming that the k-th code consisting of 64 sample points is _l x _k and the word in the l-th IFDM symbol is _l D, _l x _k and _l D are expressed by the following equations (1) and (2), respectively. It is represented by

  Further, the interleave modulation calculation when the CP length is 4 points is expressed by the following equation (3).

  Further, the IFDMA subcarrier mapping calculation is represented by the following equation (4).

  The transmission frequency compensation calculation based on CSI is expressed by the following equation (5).

  Similarly, IFDMA modulation calculation is expressed by the following equation (7) by incorporating the initial phase of the l-th symbol based on CSI as the following equation (6).

  The subcarrier mapping calculation and the transmission frequency compensation calculation can be integrated by the following expressions (8) and (9), and further rearranged, the following expression (10) is obtained.

  Here, as an example, when an LUT having a depth of 1024 (= 10-bit addressing) represented by the following equation (11) is introduced, the read pointer value can be developed in parallel as represented by the following equation (12). It can be obtained by addition and increment operations and LSB truncation operations.

  In addition, regarding the IFDMA modulation calculation, it can be seen that the approximation calculation is established with an arbitrary accuracy according to the depth of the LUT, as represented by the following equation (13).

  The initial phase for each symbol is updated by the following equation (14), which can be continuously obtained without any computation overhead by continuously performing the above-described increment operation.

  Thereby, it is possible to perform processing using an adder without performing a plurality of complex multiplications (without using a complex multiplier).

As described above, according to the first embodiment, the QPSK phase modulator converts user data into a real number sequence representing a phase, and the preceding IFDM modulator repeatedly rearranges the real number sequence from the QPSK phase modulator. The post-stage IFDM modulator performs an address addition and a conversion process by sign inversion operation on the real number sequence repeatedly rearranged by the pre-stage IFDM modulator, and the phase IQ modulator outputs an output from the post-stage IFDM modulator. Is converted into a complex sequence using the waveform called from the LUT.
Therefore, in QPSK-IFDM, the circuit scale can be reduced and the power consumption can be reduced without performing a plurality of complex multiplications.

Embodiment 2. FIG.
FIG. 9 is a configuration diagram showing an IFDMA modulation signal processing circuit according to Embodiment 2 of the present invention, in which the frame length excluding the CP is 64 points and QPSK is the primary modulation scheme.

  In FIG. 9, the primary conversion process is equalized with the reference address of the LUT that accommodates Tweedle, and the DC offset circuit is woven into this LUT to further reduce the capacity of this LUT to half of the basic configuration. Thus, a configuration incorporating an address folding conversion circuit is shown.

  Since the circuit shown in FIG. 9 is performed in the address area of the Tweedle LUT including the calculation of the CP unit, a multiplier is not necessary and the configuration is efficient in terms of circuit scale.

Embodiment 3 FIG.
FIG. 10 is a configuration diagram illustrating an IFDMA modulation signal processing circuit according to Embodiment 3 of the present invention in which the frame length excluding the CP is 64 points and QPSK is the primary modulation scheme.

  FIG. 10 shows a configuration in which the LUT capacity is reduced by combining the address folding conversion circuit and the folding release circuit as compared with the second embodiment shown in FIG. The circuit shown in FIG. 10 compresses the Tweedle LUT in the form of folding it eight times, so the LUT capacity is compressed to 1/9 including the compression effect of the code bit, and the configuration is more efficient. .

  At the same time, the address depth per page of the individual LUTs developed in parallel is also 1/8 and 128, and the number of fan-ins in the LUT selector circuit is sufficiently small. The scale can be reduced and the power consumption can be reduced.

Embodiment 4 FIG.
FIG. 11 is a configuration diagram showing a circuit in which a 64-point 8PSK-IFDMA modulation signal processing circuit according to Embodiment 4 of the present invention is combined with an 8fold Tweedle LUT.

  In FIG. 11, the circuit is exactly the same as the 64-point QPSK-IFDMA modulation signal processing circuit according to the third embodiment shown in FIG. 10 except that the Gray code mapping unit is expanded to 3 bit words.

  That is, the circuit shown in FIG. 11 has an efficient configuration in terms of circuit scale, and the multilevel can be dynamically changed between QPSK and 8PSK. It has a high affinity.

Embodiment 5 FIG.
FIG. 12 is a block diagram showing a QPSK-Block IFDMA modulation circuit in the case of 64 points and 4 CPs according to Embodiment 5 of the present invention. In FIG. 12, this circuit is assumed to be applied to a Block IFDMA-PON (Passive Optical Network) system.

  Block IFDMA is a method of obtaining multiple signals by mapping the IFDMA modulation described above to different subcarriers, performing parallel processing, and taking the sum at the final stage.

  In the Block IFDMA-PON system, CSI information common to each optical network unit (ONU: Optical Network Unit) is given to each IFDMA modulation processing circuit, and mapping information is assigned to each IFDMA modulation processing circuit of each ONU. A value corresponding to each is assigned.

  In the summing circuit that receives the IFDMA modulation processing circuit, a DC offset (usually 0x100 in the configuration shown in FIG. 12) is simultaneously added, and a value exceeding the upper limit (+ 0x200 or more) and a value exceeding the lower limit ( -0x001 or less), the clipping process is performed and the code signal is omitted. Thus, the modulation circuit converts the signed signal into an unsigned signal corresponding to the DAC input specification.

  Furthermore, the Tweedle LUT Unfold processing circuit unit performs polarity conversion processing and rewrites the LUT value to adjust the gain balance between the modulation gain and I-ch and Q-ch. Here, the value stored in the Tweedle LUT may normally be the same value in all IFDMA modulation processing circuits.

  As a result, as shown in FIG. 12, the circuit can be configured without using a multiplier, which can be realized with a circuit-saving scale. In particular, in the PON system, an ONU transmitter having a large number of components has a remarkable effect in reducing the circuit scale and power consumption.

  In FIG. 8, a single subcarrier modulator is obtained by removing the previous IFDM modulator 32, a plurality of single subcarrier modulators are arranged in parallel, and the sum of these single subcarrier modulation signals is obtained at the final stage. It may be an m-PSK-IFDM modulator.

  Further, in FIG. 8, by adding a 1-bit shift function of the absolute value to the phase IQ modulator 34 to have an intensity modulation function, it is made to correspond to PAM (Pulse Amplitude Modulation) -IFDM and PAM-Block IFDM. Also good.

  11 IQ modulator, 12 Pre-stage IFDM modulator, 13 Post-stage IFDM modulator, 14 LUT, 15 Complex multiplier, 21 PN generator, 22 LUT, 23 Fan out, 24 Selector, 25 LUT, 26 Fan out, 27 LUT, 28 address generation circuit, 29 complex multiplier, 30 DC offset circuit, 31 DAC / Serdes interface circuit, 31 QPSK phase modulator, 32 upstream IFDM modulator, 33 downstream IFDM modulator, 34 phase IQ modulator, 35 LUT .

Claims (6)

A modulation signal processing circuit in a communication system using OFDM,
A QPSK phase modulator that converts user data into a real sequence representing a phase;
A pre-stage IFDM modulator that iteratively reorders the real number sequence from the QPSK phase modulator;
A rear-stage IFDM modulator that performs conversion processing by addition of an address and a sign inversion operation on the real number sequence repeatedly rearranged by the front-stage IFDM modulator;
A phase IQ modulator that converts an output from the latter-stage IFDM modulator into a complex sequence using a waveform called from an LUT;
A modulation signal processing circuit comprising: The modulation signal processing circuit according to claim 1, wherein the QPSK phase modulator is an m-PSK phase modulator having a multilevel m. The modulation signal processing circuit according to claim 2, wherein a plurality of m-PSK-IFDMs are arranged in parallel, and a sum of these modulation signals is taken in the final stage to form an m-PSK-Block-IFDM modulator. The one obtained by removing the previous IFDM modulator is a single subcarrier modulator,
4. The modulated signal processing according to claim 2, wherein a plurality of the single subcarrier modulators are arranged in parallel, and a sum total of the single subcarrier modulated signals is obtained in a final stage to obtain an m-PSK-IFDM modulator. circuit. The phase IQ modulator is made compatible with PAM-IFDM and PAM-Block IFDM by adding an absolute value 1-bit shift function to have an intensity modulation function. The modulated signal processing circuit according to Item. A modulation signal processing method executed by a modulation signal processing circuit in a communication system using OFDM,
A QPSK phase modulation step for converting user data into a real number sequence representing a phase;
A previous IFDM modulation step of iteratively rearranging the real number sequence converted in the QPSK phase modulation step;
A post-stage IFDM modulation step that performs conversion processing by addition of an address and a sign inversion operation on the real number sequence repeatedly rearranged in the pre-stage IFDM modulation step;
A phase IQ modulation step for converting the output of the latter IFDM modulation step into a complex sequence using a waveform called from the LUT;
A modulation signal processing method comprising:

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