JP2014146877A - Communication system and time synchronization - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the accuracy of clock synchronization.SOLUTION: A first communication device calculates a time from when a packet for requesting a set time of day from a second communication device to when the packet is received by the second communication device, calculates a correction amount for a timepiece of the second communication device on the basis of said time and a time needed for packet transmission between the first and the second communication devices, outputs the packet and the correction amount from a first IF, and accepts a response packet as its input, with priority for the first IF given to a first virtual channel on which the packet, the correction amount and the response packet are transferred over a second virtual channel on which data is transferred. The second communication device calculates, by the timepiece, a time from when the packet is received to when a response packet is transmitted, creates a response packet including said time, corrects the timepiece on the basis of the correction amount from the first communication device, outputs the response packet from a second IF, and accepts the correction amount as its input, with priority for the second IF given to the first virtual channel on which the request for time of day, the response packet, and the correction amount are transferred over the second virtual channel on which data is transferred.

Description

  The present invention relates to a communication system.

  In a communication system in which a plurality of devices operate in conjunction with each other, processing may be performed using a clock in which each device is synchronized. Such a communication system includes a network server device for securities trading and an FA (factory automation) device. The network server device for securities trading needs to accurately record the processing execution time as a time stamp. In FA (factory automation) equipment, a plurality of processes are accurately synchronized in time, and the production process is controlled.

  If a function for receiving a reference clock signal from a GPS or standard radio wave or a primitive clock is mounted on a network server device for securities trading or an FA device, the cost becomes very high. For this reason, there is already a communication system using NTP (Network Time Protocol) technology that synchronizes the clock of a master device having a reference clock with the clock of a master device having a reference clock via a LAN such as Ethernet (registered trademark). Are known.

  In a communication system using the NTP technology, an error in clock synchronization between the clock of the master device and the clock of the slave device increases.

  Therefore, an object is to improve the accuracy of clock synchronization.

The disclosed communication system is:
A communication system having a first communication device and one or more second communication devices connected to the first communication device by a serial IF,
The first communication device is:
The first watch,
The time request is made by the one or more second communication devices after starting transmission of a time request packet for requesting the time set in the one or more second communication devices by the first clock. The time until the reception of the response packet for the packet is started is obtained, and transmission of the time request packet is required between the time and the first communication device and the one or more second communication devices. A first time synchronization circuit that calculates a correction amount of a second timepiece of the one or more second communication devices based on time,
A first interface that outputs the time request packet and the correction amount, and inputs the response packet to the first time synchronization circuit;
In the first interface, a first virtual channel for transferring the time request packet, the correction amount, and the response packet, and a second virtual channel for transferring data are set, and the second virtual channel is set. The time request packet transferred on the first virtual channel and the time stamp of the correction amount are given priority over the data transferred on the first virtual channel, and the output of the data transmitted on the second virtual channel is prioritized. Preferentially select the response packet to be output on the virtual channel;
Each of the one or more second communication devices includes:
A second watch,
Obtaining a time from the start of reception of the time request packet by the second clock to the start of transmission of the response packet, creating the response packet including the time, from the first communication device A second time synchronization circuit for correcting the second timepiece based on the correction amount;
A second interface for outputting the response packet and inputting the correction amount to the second time synchronization circuit;
In the second interface, a third virtual channel for transferring the time request packet, the response packet, and the correction amount, and a fourth virtual channel for transferring data are set, and the fourth virtual channel is set. Giving priority to the time stamp of the response packet transferred on the third virtual channel over the data transferred on the first virtual channel, and outputting on the third virtual channel over the output of the data transmitted on the fourth virtual channel The time request packet and the correction amount are preferentially selected.

  According to the disclosed embodiment, the accuracy of clock synchronization can be improved.

It is a figure which shows one Example of a communication system. It is a figure which shows one Example of the calculation method of the correction amount of a slave clock. It is a functional block diagram which shows one Example of the master time synchronizing circuit of a 1st communication apparatus. It is a functional block diagram which shows one Example of the slave time synchronizing circuit of a 2nd communication apparatus. It is a figure which shows one Example of IF of a 1st communication apparatus. It is a figure which shows one Example of a switch. It is a figure which shows one Example of IF of a 2nd communication apparatus. It is a flowchart which shows one Example of operation | movement of a 1st communication apparatus. It is a flowchart which shows one Example of operation | movement of a 2nd communication apparatus. It is a figure which shows the comparison with one Example of a communication system, and the conventional communication system. It is a figure which shows the modification of a communication system. It is a figure which shows the modification of a communication system. It is a figure which shows the modification of a communication system. It is a figure which shows the modification of a communication system.

Next, the form for implementing this invention is demonstrated, referring drawings based on the following Examples.
In all the drawings for explaining the embodiments, the same reference numerals are used for those having the same function, and repeated explanation is omitted.

<Example>
<Communication system>
FIG. 1 shows an embodiment of a communication system.

  The communication system includes a first communication device 100 and a second communication device 200. FIG. 1 mainly shows the hardware configuration of the first communication device 100 and the second communication device 200.

  The first communication device 100 functions as a master in time synchronization, and the second communication device 200 functions as a slave in time synchronization. That is, the second communication device 200 as a slave has a clock (slave clock (slave clock) 202) of its own device in addition to a clock (master clock (master clock) 102) of the first communication device 100 as a master. Execute the process to synchronize.

  The first communication device 100 and the second communication device 200 are connected by a high-speed serial interface (IF). In one embodiment of the communication system, a PCIe cable interface is used for the high-speed serial interface.

<First communication apparatus 100>
The first communication device 100 includes a master clock (master clock) 102, a master time synchronization circuit 104, a data transfer circuit 106, and an IF 108. The IF card 110 is connected to the first communication device 100 via the IF 108. In addition, a transceiver 114 is connected to the IF card 110.

  The IF 108 is an interface (InterFace) between the first communication device 100 and the IF card 110. The IF 108 is connected to the master time synchronization circuit 104. For example, the IF 108 includes a PCIe IF. PCIe IF implements multiple virtual channels (VCs) that share serial transmission paths with multiple traffics in a time-sharing manner. In one embodiment of the first communication device 100, two virtual channels are implemented. Specifically, the IF 108 implements two virtual channels, VC0 and VC1.

  The IF card 110 has a switch 112. The switch 112 performs packet transfer between the IF 108 and the IF card 110. That is, the switch 112 functions as a bridge that processes packet transfer between the IF 108 and the IF card 110. The IF card 110 includes a PCIe cable IF card. The switch 112 includes a PCIe switch. The switch 112 implements two virtual channels, VC0 and VC1.

  The transceiver 114 transmits and receives signals to and from the second communication device 200 via the transmission path 300. The transceiver 114 includes an optical transceiver. The transmission line 300 includes an optical fiber.

  The master clock 102 is a reference clock in the communication system.

  The master time synchronization circuit 104 is connected to the master clock 102. The master time synchronization circuit 104 receives the first time information from the master clock 102. The master time synchronization circuit 104 outputs a time request packet for requesting the time from the second communication device 200 to the VC 1 of the IF 108. The master time synchronization circuit 104 receives the time response packet from the second communication device 200 for the time request packet from the VC 1 of the IF 108. The master time synchronization circuit 104 calculates a correction amount for synchronizing the slave clock 202 of the second communication device 200 with the master clock 102. The master time synchronization circuit 104 outputs a correction amount signal including a correction amount to VC1 of the IF 108.

  Data transfer circuit 106 is connected to IF 108. The data transfer circuit 106 performs data transfer between the first communication device 100 and the second communication device 200. The data transfer circuit 106 inputs data to be transferred to the second communication device 200 to the VC0 of the IF 108. The data transfer circuit 106 receives the data transferred by the second communication device 200 from the VC0 of the IF 108.

<Second communication apparatus 200>
The second communication device 200 includes a slave clock (slave clock) 202, a slave time synchronization circuit 204, a data transfer circuit 206, and an IF 208. The IF card 210 is connected to the second communication device 200 via the IF 208. In addition, a transceiver 214 is connected to the IF card 210.

  The IF 208 is an interface (InterFace) between the second communication device 200 and the IF card 210. IF 208 is connected to slave time synchronization circuit 204. For example, the IF 208 includes a PCIe IF. In one embodiment of the second communication device 200, two virtual channels are implemented. Specifically, the IF 208 implements two virtual channels, VC0 and VC1.

  The IF card 210 has a switch 212. The switch 212 performs packet transfer between the IF 208 and the IF card 210. That is, the switch 212 functions as a bridge that processes packet transfer between the IF 208 and the IF card 210. The IF card 210 includes a PCIe cable IF card. The switch 212 includes a PCIe switch. The switch 212 implements two virtual channels, VC0 and VC1.

  The transceiver 214 transmits and receives signals to and from the first communication device 100 via the transmission path 300. The transceiver 214 includes an optical transceiver.

  The slave clock 202 is a clock in the second communication device 200.

  Slave time synchronization circuit 204 is connected to slave clock 202. The slave time synchronization circuit 204 receives the second time information from the slave clock 202. The slave time synchronization circuit 204 receives the time request packet from the first communication device 100 from the IF 208. The slave time synchronization circuit 204 outputs a time response packet corresponding to the time request packet to the VC 1 of the IF 208. The slave time synchronization circuit 204 receives the correction amount signal from VC1 of the IF 208. The slave time synchronization circuit 204 inputs the correction amount included in the correction amount signal to the slave clock 202. The slave clock 202 corrects the clock based on the correction amount from the slave time synchronization circuit 204.

  Data transfer circuit 206 is connected to IF 208. The data transfer circuit 206 executes data transfer between the first communication device 100 and the second communication device 200. The data transfer circuit 206 inputs data to be transferred to the first communication device 100 to VC0 of the IF 208. The data transfer circuit 206 receives the data transferred by the first communication device 100 from the VC0 of the IF 208.

<Calculation method of correction amount of slave clock 202>
FIG. 2 shows a method for calculating the correction amount of the slave clock 202. In FIG. 2, “delay time T1” indicates that the first communication apparatus 200 receives the time response packet from the second communication apparatus 200 after the first communication apparatus 100 starts transmitting the time request packet. Time to start. The “delay time T2” is a period from when the second communication apparatus 200 starts receiving the time request packet from the first communication apparatus 100 to when the second communication apparatus 200 starts transmitting the time response packet. It's time. “Delay time T3” is the time required for the packet to be transferred from the first communication apparatus 100 to the second communication apparatus 200. “Delay time T4” is the time required for a packet to be transferred from the second communication apparatus 200 to the first communication apparatus 100.

  FIG. 3 shows an embodiment of the first communication device 100. FIG. 3 shows a functional block diagram of the master time synchronization circuit 104. Each functional block may be executed by a CPU (not shown) included in the master time synchronization circuit 104.

  The CPU functions as a first time information acquisition unit 302, a time request packet creation unit 304, a correction amount calculation unit 306, and a correction amount signal creation unit 308.

  The first time information acquisition unit 302 acquires time M from the master clock 102.

  After the first time information acquisition unit 302 acquires the time M, the time request packet generation unit 304 generates a time request packet for the second communication device 200 and inputs it to the VC 1 of the IF 108. The time request packet is transmitted to the second communication device 200 via the IF 108, the IF card 110, and the transceiver 114. The time request packet creation unit 304 records the time when the time request packet is transmitted. For example, the time request packet creation unit 304 preferably records the time when the time request packet is input to the VC 1 of the IF 108.

  The time request packet is input to the slave time synchronization circuit 204 via the transmission path 300, the transceiver 214 of the second communication device 200, the IF card 210, and the IF 208.

  The delay time from when the time request packet is transmitted (transferred) from the first communication apparatus 100 to when the time request packet is received by the second communication apparatus 200 is T3.

  FIG. 4 shows an example of the second communication device 200. FIG. 4 shows a functional block diagram of the slave time synchronization circuit 204. Each functional block may be executed by a CPU (not shown) included in the slave time synchronization circuit 204.

  The CPU functions as a second time information acquisition unit 402, a time response packet creation unit 404, and a time correction processing unit 406.

  When the time request packet is received by the slave time synchronization circuit 204, the second time information acquisition unit 402 acquires the time S from the slave clock 202.

  The time response packet creation unit 404 creates a time response packet including the time S acquired by the second time information acquisition unit 402 and inputs the time response packet to the IF 208. When the time response packet creation unit 404 transmits the time response packet to the first communication apparatus 100, the time response packet includes the delay time T2 from the time when reception of the time request packet is started. When the time response packet creation unit 404 inputs the time response packet to the IF 208, the time response packet preferably includes a delay time T2 from the time when reception of the time request packet is started. A system clock is input to the time response packet creation unit 404. The system clock is preferably a circuit that generates pulses having a constant period. For example, the time response packet creation unit 404 uses the clock counter or the like to measure the number of pulses output by the system clock from when the slave clock 202 is inquired about the time until the time returns. Is preferably calculated and included in the time response packet.

  The time response packet is transmitted to the first communication device 100 via the IF 208, the IF card 210, and the transceiver 214. Further, the time response packet is input to the correction amount calculation unit 306 of the master time synchronization circuit 104 via the transmission path 300, the transceiver 114 of the first communication device 100, the IF card 110, and the IF 108.

  When the time response packet is input, the correction amount calculation unit 306 calculates a delay time T1 required from the time M recorded when the time request packet is transmitted until the reception of the time response packet is started. When calculating the delay time T1, the correction amount calculation unit 306 calculates the elapsed time from the time M recorded when transmitting the time request packet until the time response packet is input to the master time synchronization circuit 104. preferable.

  The correction amount calculation unit 306 acquires the time S included in the time response packet and the delay time T2.

  The correction amount calculation unit 306 uses the delay time T1 to the delay time T2, and the time required for the packet (time request packet, time response packet) to travel between the first communication device 100 and the second communication device 200 Is calculated. In an embodiment of the communication system, since PCIe is applied, the transfer rate when the time request packet is transmitted from the first communication apparatus 100 to the second communication apparatus 200, and the second communication apparatus 200 to the second communication apparatus It is assumed that there is almost no difference in the transfer rate when the time response packet is transmitted to one communication apparatus 100. Therefore, the delay time T3 required for the packet to be transferred from the first communication device 100 to the second communication device 200 and the packet are transferred from the second communication device 200 to the first communication device 100. The delay time T4 required for the calculation can be calculated by (delay time T1−delay time T2) / 2.

  The correction amount calculation unit 306 calculates a correction amount for correcting the slave clock in order to synchronize the slave clock 202 with the master clock 102 by (time S) − (time M) −T3.

  The correction amount signal creation unit 308 creates a correction amount packet including the correction amount and inputs it to the VC 1 of the IF 108. The correction amount packet is transferred to the second communication device 200.

  The correction amount packet is transferred to the second communication device 200 via the IF 108, the IF card 110, and the transceiver 114.

  The correction amount packet is input to the slave time synchronization circuit 204 of the second communication device 200 via the transmission path 300, the transceiver 214, the IF card 210, and the IF 208.

  The time correction processing unit 406 corrects the slave clock 202 based on the correction amount included in the correction amount packet.

  By correcting the slave clock 202, the slave clock 202 of the second communication device 200 can be synchronized with the master clock 102 of the first communication device 100.

<IF108>
FIG. 5 shows an example of the IF 108.

  One embodiment of the IF 108 implements two virtual channels. The two virtual channels are called VC1 and VC2. The IF 108 may implement three or more virtual channels. When a PCIe IF is applied to the IF 108, the PCIe IF can include two or more virtual channel interfaces.

  The IF 108 includes a VC1 transmission buffer 502, a VC0 transmission buffer 504, an arbiter 506, a VC1 reception buffer 508, a VC0 reception buffer 510, and a selector 512.

  Each VC has a reception buffer and a transmission buffer. That is, VC0 has a VC0 reception buffer 510 and a VC0 transmission buffer 504. VC1 has a VC1 reception buffer 508 and a VC1 transmission buffer 502.

  VC1 is used for communication with the master time synchronization circuit 104. The size of the VC1 reception buffer 508 is preferably such that one packet can be stored. The size of the VC1 transmission buffer 502 is preferably such that one packet can be stored. The size of the VC1 transmission buffer 502 is preferably set in advance.

  VC0 is used for communication with the data transfer circuit 106. The size of the VC0 reception buffer 510 is preferably such that a plurality of packets can be stored. More preferably, the size of the VC0 reception buffer 510 is increased as much as the circuit size and cost allow so that as many packets as possible can be stored so as not to lower the data transfer rate. The size of the VC0 reception buffer 510 is preferably set in advance.

  The size of the VC0 transmission buffer 504 is preferably such that a plurality of packets can be stored. More preferably, the size of the VC0 transmission buffer 504 is increased as much as the circuit size and cost allow so that as many packets as possible can be stored so as not to lower the data transfer rate. The size of the VC0 transmission buffer 504 is preferably set in advance.

  In one embodiment of the IF 108, the size of the VC0 reception buffer 510 is set to a size that can store 30 PCIe packets with a 128-byte payload, and the size of the VC0 transmission buffer 504 is set to a size that can store 30 PCIe packets with a 128-byte payload. To do.

  The packet input to VC1 from the master time synchronization circuit 104 and the packet input to VC0 from the data transfer circuit 106 are transferred as they are to the serial interface as long as no conflict occurs on the output side.

  If packets are stored in the VC1 transmission buffer 502 and the VC0 transmission buffer 504 and a conflict occurs, the arbiter 506 performs arbitration between the VC1 transmission buffer 502 and the VC0 transmission buffer 504. The arbiter 506 selects and transfers either the packet stored in the VC1 transmission buffer 502 or the packet stored in the VC0 transmission buffer 504. In one embodiment of the IF 108, the arbiter 506 preferentially selects and forwards the packet stored in the VC1 transmission buffer 502. That is, when the PCIe IF is applied to the IF 108, the packet stored in the VC1 transmission buffer 502 is set to be preferentially selected using the strict mode defined in the PCIe standard. By using the strict mode, packets can be issued in a fixed priority order for each virtual channel. In this way, time synchronization packets such as time request packets and correction amount packets can be transmitted with priority over data packets from the data transfer circuit 106.

  Even if a conflict occurs between the packet stored in the VC1 transmission buffer 502 and the packet stored in the VC0 transmission buffer 504, the size of the VC1 transmission buffer 502 is such that one packet can be stored. Packets stored in the VC1 transmission buffer 502 are not continuously input by flow control defined by the PCIe standard. Therefore, the time synchronization packet is not continuously transferred in priority to the data packet from the data transfer circuit 106. For this reason, it can suppress that a data transfer rate falls by continuing transferring a time synchronous packet.

  A packet from the second communication device 200 is input from the switch 112 to the selector 512.

  The selector 512 refers to the header information of the packet and determines whether the packet is stored in the VC1 reception buffer 508 or the data stored in the VC0 reception buffer 510.

  The selector 512 transfers the packet stored in the VC1 reception buffer 508 to the VC1 reception buffer 508. The VC1 reception buffer 508 is connected to the master time synchronization circuit 104.

  The selector 512 transfers the packet stored in the VC0 reception buffer 510 to the VC0 reception buffer 510. The VC0 reception buffer 510 is connected to the data transfer circuit 106.

  VC0 and VC1 are time-divided in the serial interface. The selector 512 sequentially distributes the packets from the serial interface to the VC1 reception buffer 508 and the VC0 reception buffer 510 in the order of arrival.

<Switch 112>
FIG. 6 shows an embodiment of the switch 112.

  The switch 112 includes a first IF 602, a crossbar switch 616, and a second IF 618.

  The first IF 602 includes an arbiter 604, a VC1 transmission buffer 606, a VC0 transmission buffer 608, a selector 610, a VC1 reception buffer 612, and a VC0 reception buffer 614.

  The second IF 618 includes a VC1 reception buffer 620, a VC0 reception buffer 622, a selector 624, a VC1 transmission buffer 626, a VC0 transmission buffer 628, and an arbiter 630.

  The switch 112 has the same kind of IF as the external port. For example, the switch 112 includes a first IF 602 of the same type as the IF 108 and a second IF 618 of the same type as the transceiver 114. When a PCIe IF circuit is applied to the first IF 602, the PCIe IF circuit can include two or more VC interfaces. One embodiment of the first IF 602 implements two VCs. When a PCIe IF circuit is applied to the second IF 618, the PCIe IF circuit can include two or more VC interfaces. One embodiment of the second IF 618 implements two VCs.

  In the example shown in FIG. 6, the first IF 602 is connected to the IF 108, and the second IF 618 is connected to the transceiver 114.

  The first IF 602 is connected to the second IF 618 via the crossbar switch 616. More specifically, the VC1 transmission buffer 606 of the first IF 602 is connected to the VC1 reception buffer 620 of the second IF 618 via the crossbar switch 616. The VC0 transmission buffer 608 of the first IF 602 is connected to the VC0 reception buffer 622 of the second IF 618 via the crossbar switch 616. The VC1 reception buffer 612 of the first IF 602 is connected to the VC1 transmission buffer 626 of the second IF 618 via the crossbar switch 616. The VC0 reception buffer 614 of the first IF 602 is connected to the VC0 transmission buffer 628 of the second IF 618 via the crossbar switch 616.

  The first IF 602 will be described.

  Each VC has a reception buffer and a transmission buffer. That is, VC0 has a VC0 transmission buffer 608 and a VC0 reception buffer 614. The VC 1 includes a VC 1 transmission buffer 606 and a VC 1 reception buffer 612.

  The size of the VC1 transmission buffer 606 is preferably such that one packet can be stored. The size of the VC1 reception buffer 612 is preferably such that one packet can be stored. The size of the VC0 transmission buffer 608 is preferably such that a plurality of packets can be stored. More preferably, the size of the VC0 transmission buffer 608 is increased as much as the circuit cost allows so that as many packets as possible can be stored so as not to lower the data transfer rate. The size of the VC0 reception buffer 614 is preferably such that a plurality of packets can be stored. More preferably, the size of the VC0 reception buffer 614 is made as large as the circuit cost allows so that as many packets as possible can be stored so as not to lower the data transfer rate.

  The second IF 618 will be described.

  Each VC has a reception buffer and a transmission buffer. That is, VC0 includes a VC0 reception buffer 622 and a VC0 transmission buffer 628. VC1 has a VC1 reception buffer 620 and a VC1 transmission buffer 626.

  The size of the VC1 reception buffer 620 is preferably such that one packet can be stored. The size of the VC1 transmission buffer 626 is preferably such that one packet can be stored. The size of the VC0 reception buffer 622 is preferably such that a plurality of packets can be stored. More preferably, the size of the VC0 reception buffer 622 is increased as much as the circuit cost allows so that as many packets as possible can be stored so that the data transfer rate does not decrease. The size of the VC0 transmission buffer 628 is preferably such that a plurality of packets can be stored. More preferably, the size of the VC0 transmission buffer 628 is increased as much as the circuit cost allows so that as many packets as possible can be stored so as not to lower the data transfer rate.

  The packet input from the IF 108 to the VC 1 and the packet input from the IF 108 to the VC 0 are transferred to the transceiver 114 as long as no conflict occurs on the output side.

  If packets are stored in the VC1 transmission buffer 626 and the VC0 transmission buffer 628, and a conflict occurs, the arbiter 630 arbitrates between the VC1 transmission buffer 626 and the VC0 transmission buffer 628. The arbiter 630 selects and transfers either the packet stored in the VC1 transmission buffer 626 or the packet stored in the VC0 transmission buffer 628. In one embodiment of switch 112, arbiter 630 preferentially selects and forwards packets stored in VC1 transmit buffer 626. That is, when the PCIe switch is applied to the switch 112, the packet stored in the VC1 transmission buffer 626 is set to be preferentially selected using the strict mode defined in the PCIe standard. By using the strict mode, packets can be issued in a fixed priority order for each virtual channel. By doing so, time synchronization packets such as time request packets and correction amount packets can be transmitted with priority over data packets.

  Even if a conflict occurs between the packet stored in the VC1 transmission buffer 626 and the packet stored in the VC0 transmission buffer 628, the size of the VC1 transmission buffer 626 is such that one packet can be stored. Packets stored in the VC1 transmission buffer 626 are not continuously input by flow control defined by the PCIe standard. Therefore, the time synchronization packet is not continuously transferred to the data packet with priority. For this reason, it can suppress that a data transfer rate falls by continuing transferring a time synchronous packet.

  The selector 610 refers to the header information of the packet and determines whether the packet is stored in the VC1 reception buffer 612 or the data stored in the VC0 reception buffer 614.

  The selector 610 transfers the packet stored in the VC1 reception buffer 612 to the VC1 reception buffer 612. The VC1 reception buffer 612 is connected to the VC1 transmission buffer 626.

  The selector 610 transfers the packet stored in the VC0 reception buffer 614 to the VC0 reception buffer 614. The VC0 reception buffer 614 is connected to the VC0 transmission buffer 628.

  VC0 and VC1 are time-divided in the serial interface. The selector 610 sequentially distributes the packets from the serial interface to the VC1 reception buffer 612 and the VC0 reception buffer 614 in the order of arrival.

  The packet input from the transceiver 114 to the VC1 and the packet input from the transceiver 114 to the VC0 are transferred to the IF 108 as long as no conflict occurs on the output side.

  If packets are stored in the VC1 transmission buffer 606 and the VC0 transmission buffer 608 and a conflict occurs, the arbiter 604 performs arbitration between the VC1 transmission buffer 606 and the VC0 transmission buffer 608. The arbiter 604 selects and transfers either the packet stored in the VC1 transmission buffer 606 or the packet stored in the VC0 transmission buffer 608. In one embodiment of switch 112, arbiter 604 preferentially selects and forwards packets stored in VC1 transmit buffer 606. That is, when the PCIe switch is applied to the switch 112, the packet stored in the VC1 transmission buffer 606 is set to be preferentially selected using the strict mode defined in the PCIe standard. By using the strict mode, packets can be issued in a fixed priority order for each virtual channel. In this way, time synchronization packets such as time response packets can be input with priority over data packets.

  Even if a conflict occurs between the packet stored in the VC1 transmission buffer 606 and the packet stored in the VC0 transmission buffer 608, the size of the VC1 transmission buffer 606 is such that one packet can be stored. Packets stored in the VC1 transmission buffer 606 are not continuously input by flow control defined by the PCIe standard. Therefore, the time synchronization packet is not continuously transferred to the data packet with priority. For this reason, it can suppress that a data transfer rate falls by continuing transferring a time synchronous packet.

  The selector 624 determines whether the packet is stored in the VC1 reception buffer 620 or the data stored in the VC0 reception buffer 622 with reference to the header information of the packet.

  The selector 624 transfers the packet stored in the VC1 reception buffer 620 to the VC1 reception buffer 620. The VC1 reception buffer 620 is connected to the VC1 transmission buffer 606.

  The selector 624 transfers the packet stored in the VC0 reception buffer 622 to the VC0 reception buffer 622. The VC0 reception buffer 622 is connected to the VC0 transmission buffer 608.

  VC0 and VC1 are time-divided in the internal bus. The selector 624 sequentially distributes the packets from the transceiver 114 to the VC1 reception buffer 620 and the VC0 reception buffer 622 in the order of arrival.

<IF208>
FIG. 7 shows an example of the IF 208.

  One embodiment of IF 208 implements two virtual channels. The two virtual channels are called VC1 and VC2. The IF 208 may implement three or more virtual channels. When the PCIe IF is applied to the IF 208, the PCIe IF can include two or more virtual channel interfaces.

  The IF 208 includes a VC1 transmission buffer 702, a VC0 transmission buffer 704, an arbiter 706, a VC1 reception buffer 708, a VC0 reception buffer 710, and a selector 712.

  Each VC has a reception buffer and a transmission buffer. That is, VC0 has a VC0 transmission buffer 704 and a VC0 reception buffer 710. VC1 has a VC1 transmission buffer 702 and a VC1 reception buffer 708.

  VC1 is used for communication with the slave time synchronization circuit 204. The size of the VC1 reception buffer 708 is preferably such that one packet can be stored. The size of the VC1 transmission buffer 702 is preferably such that one packet can be stored.

  VC0 is used for communication with the data transfer circuit 206. The size of the VC0 reception buffer 710 is preferably such that a plurality of packets can be stored. More preferably, the size of the VC0 reception buffer 710 is increased as much as the circuit size and cost allow so that as many packets as possible can be stored so as not to lower the data transfer rate. The size of the VC0 transmission buffer 704 is preferably such that a plurality of packets can be stored. More preferably, the size of the VC0 transmission buffer 704 is increased as much as the circuit size and cost allow so that as many packets as possible can be stored so as not to lower the data transfer rate.

  In one embodiment of the IF 208, the size of the VC0 reception buffer 710 is set to a size that can store 30 PCIe packets with a 128-byte payload, and the size of the VC0 transmission buffer 704 is set to a size that can store 30 PCIe packets with a 128-byte payload. To do.

  The packet input to the VC1 from the slave time synchronization circuit 204 and the packet input to the VC0 from the data transfer circuit 206 are transferred to the serial interface as long as no conflict occurs on the output side.

  If packets are stored in the VC1 transmission buffer 702 and the VC0 transmission buffer 704 and a conflict occurs, the arbiter 706 performs arbitration between the VC1 transmission buffer 702 and the VC0 transmission buffer 704. The arbiter 706 selects and transfers either the packet stored in the VC1 transmission buffer 702 or the packet stored in the VC0 transmission buffer 704. In one embodiment of the IF 208, the arbiter 706 preferentially selects and forwards the packet stored in the VC1 transmission buffer 702. That is, when the PCIe IF is applied to the IF 208, the packet stored in the VC1 transmission buffer 702 is set to be preferentially selected using the strict mode defined in the PCIe standard. By using the strict mode, packets can be issued in a fixed priority order for each virtual channel. In this way, the time response packet can be transmitted with priority over the data packet from the data transfer circuit 206.

  Even if a conflict occurs between the packet stored in the VC1 transmission buffer 702 and the packet stored in the VC0 transmission buffer 704, the size of the VC1 transmission buffer 702 is such that one packet can be stored. Packets stored in the VC1 transmission buffer 702 are not continuously input by flow control defined by the PCIe standard. Therefore, the time synchronization packet is not continuously transferred to the data packet from the data transfer circuit 206 with priority. For this reason, it can suppress that a data transfer rate falls by continuing transferring a time synchronous packet.

  A packet from the first communication device 100 is input from the switch 212 to the selector 712.

  The selector 712 refers to the header information of the packet and determines whether the packet is stored in the VC1 reception buffer 708 or the data stored in the VC0 reception buffer 710.

  The selector 712 transfers the packet stored in the VC1 reception buffer 708 to the VC1 reception buffer 708. The VC1 reception buffer 708 is connected to the slave time synchronization circuit 204.

  The selector 712 transfers the packet stored in the VC0 reception buffer 710 to the VC0 reception buffer 710. The VC0 reception buffer 710 is connected to the data transfer circuit 206.

  VC0 and VC1 are time-divided in the serial interface. The selector 712 sequentially distributes the packets from the serial interface to the VC1 reception buffer 708 and the VC0 reception buffer 710 in the order of arrival.

<Operation of First Communication Device 100>
FIG. 8 shows an example of the operation of the first communication device 100. FIG. 6 mainly shows the operation of the master time synchronization circuit 104.

  In step S <b> 802, the first communication device 100 acquires the time M from the master clock 102.

  In step S804, the first communication device 100 inputs the time request packet to the VC 1 of the IF 108 and records the transmission start time.

  In step S806, the first communication device 100 determines whether a time response packet can be received from the VC1 of the IF 108. If the time response packet is not receivable, the process returns to step S806.

  In step S808, when it is determined that the time response packet can be received, the reception start time of the time response packet is recorded.

  In step S810, the first communication device 100 calculates a delay time T1. The master time synchronization circuit 104 calculates the delay time T1 by subtracting the reception start time from the transmission start time.

  In step S812, the first communication device 100 reads and records the slave time S from the time response packet.

  In step S814, the first communication device 100 calculates a packet transmission delay time T3 (T4). The master time synchronization circuit 104 calculates the delay time T3 by dividing the delay time T1 by subtracting the delay time T2 by 2. That is, the master time synchronization circuit 104 calculates (delay time T1−delay time T2) / 2.

  In step S816, the first communication device 100 calculates the slave clock correction amount. The master time synchronization circuit 104 calculates the correction amount of the slave clock by subtracting the delay time T3 from the subtraction of the time M from the time S. That is, the master time synchronization circuit 104 calculates time S−time M−delay time T3.

  In step S <b> 818, the first communication device 100 inputs a correction amount packet in which the correction amount is recorded to the IF 108.

  In step S820, the first communication device 100 stands by until the next time correction time. The time correction may be executed at a predetermined cycle. If the next time correction time is reached, the process returns to step S802.

  Time correction may be performed periodically or constantly.

<Operation of Second Communication Device 200>
FIG. 9 shows an example of the operation of the second communication device 200. FIG. 9 mainly shows the operation of the slave time synchronization circuit 204.

  In step S <b> 902, second communication apparatus 200 determines whether or not a time request packet can be received from IF 208. If the time request packet cannot be received, the process returns to step S902.

  In Step S904, when it is determined that the time request packet can be received, the second communication device 200 records the reception start time of the time request packet.

  In step S906, the second communication device 200 acquires the time S from the slave clock 202.

  In step S908, the second communication device 200 calculates a delay time T2. The slave time synchronization circuit 204 calculates the delay time T2 by subtracting the transmission start time from the reception start time.

  In step S910, second communication apparatus 200 inputs a time response packet including delay time T2 and time S to IF 208.

  In step S <b> 912, the second communication device 200 determines whether the correction amount packet can be received from the IF 208. If the correction amount packet cannot be received, the process returns to step S912.

  In step S914, the second communication device 200 reads and records the correction amount of the slave time S from the correction amount packet.

  In step S916, the second communication device 200 corrects the slave clock 202. The slave time synchronization circuit 204 obtains the corrected time by subtracting the correction amount from the time S. The slave time synchronization circuit 204 sets the corrected time in the slave clock 202.

<Effect of one embodiment of communication system>
FIG. 10 shows the effect of an embodiment of the communication system.

  FIG. 10 shows a comparison of delay times when time synchronization packets (time request packet, time response packet, correction amount packet) are waited by the arbiter 506 of the IF 108 and the arbiter 706 of the IF 208. The first communication device 100 and the second communication device 200 have a packet buffer for data transfer having a size capable of storing 30 128-byte payload packets. FIG. 10 shows a case where (1) there is no data transfer, (2) when a plurality of VCs are not used, and (3) a time synchronization packet is preferentially transferred by VC1. (2) The case where a plurality of VCs are not used corresponds to the conventional method. (3) The case where the time synchronization packet is preferentially transferred by VC1 corresponds to an embodiment of the communication system.

  In order to improve the synchronization accuracy between the master clock 102 and the slave clock 202, an error in the delay time caused by the time synchronization packet such as the time request packet, the time response packet, and the correction amount packet transmitted through the high-speed serial interface. Smaller is preferable.

  This delay time error does not occur when there is no competition between the time synchronization packet and the data transfer packet. However, as shown in (2), in a communication system in which a data packet and a time synchronization packet use a common buffer, when a conflict occurs between the time synchronization packet and the data transfer, a large error occurs. Occurs.

(1) When there is no data transfer Since the time synchronization packet is not disturbed by the transfer of the data packet, no delay occurs.

(2) When a plurality of VCs are not used Even if an attempt is made to transfer a time synchronization packet after 30 data packets are stored in the buffer, the time synchronization packet is transferred until the transfer of the 30 stored data packets is completed. Is delayed because it is not transferred.

  If the high-speed serial IF is PCIe Gen1 (2.5GT / s) x4, it takes about 152 ns to transmit one 128-byte payload data packet. Therefore, a delay of 152 ns × 30 = 4560 ns occurs until the transfer of 30 packets ends, resulting in a measurement error.

  Therefore, when a plurality of VCs are not used, the synchronization accuracy on the order of μs to ms is limited.

(3) When the time synchronization packet is preferentially transferred by the VC1 Since the time synchronization packet is preferentially transferred by using a plurality of VCs, the waiting time is limited to the transfer of one data packet. This is about 152 ns. In other words, the maximum delay is guaranteed to be one data packet or less. Therefore, time correction in the ns order is possible.

  Since the maximum delay is about 152 ns, clock synchronization with an accuracy of ns order is possible between the master and the slave.

  Furthermore, since data transfer and time synchronization packet transfer can be executed by the same interface, a dedicated LAN connection is not required to transfer the time synchronization packet. Therefore, it can be realized easily and the cost can be reduced.

  Furthermore, since there is almost no adverse effect that the data transfer rate is lowered by transferring the time synchronization packet, it is possible to achieve both high-speed serial data transfer and highly accurate clock synchronization processing.

  In one embodiment of the communication system, clock synchronization at the nsec level can be realized.

  In the communication system using the NTP technology, the communication delay time of the LAN and the communication delay are long because the processing is executed as software. In addition, the clock synchronization error is large, and the clock synchronization at the maximum msec level is the limit.

  In the standard of IEEE 1588 that synchronizes clocks with high accuracy, the accuracy of clock synchronization is on the order of μsec. For this reason, the accuracy is insufficient to obtain highly accurate nsec order synchronization.

In one embodiment of the communication system, the accuracy of time synchronization can be improved without using a separate LAN for clock synchronization. When high-speed data transfer is required between a plurality of devices, a plurality of devices may be connected by a high-speed interface such as PCIe having a data transfer band faster than a LAN. In this case, a separate LAN connection was required for clock synchronization, leading to an increase in cost.
<Modification (Part 1)>
In a variation of the communication system, the first communication device 100 has a root complex, and the second communication device 200 has an endpoint.

  FIG. 11 shows a modification of the communication system.

  In the example illustrated in FIG. 11, the first communication device 100 includes a route complex 116 instead of the IF 108 of the first communication device 100 described with reference to FIG. 1. The route complex 116 is connected to the master time synchronization circuit 104, the data transfer circuit 106, and the switch 112. The second communication apparatus 200 includes an endpoint 216 instead of the IF 208 of the second communication apparatus 200 described with reference to FIG. The end point 216 is connected to the slave time synchronization circuit 204, the data transfer circuit 206, and the switch 212.

In a modification of the communication system, nsec level clock synchronization can be realized.
<Modification (Part 2)>
In one variation of the communication system, the first communication device 100 has a root complex 116 and the second communication device 200 has an endpoint 216.

  FIG. 12 shows a modification of the communication system.

  In the example shown in FIG. 12, a plurality of second communication devices described with reference to FIG. 11 are prepared. The first communication device 100 and a plurality of second communication devices 200n (n is an integer of n> 0) are connected via the switch 600. In other words, the switch 600 is disposed between the root complex 116 and the endpoint 216. FIG. 12 shows the case where n = 2. The same applies to the case where n is 3 or more.

  Between the first communication device 100 and the plurality of second communication devices 200n, the time synchronization packet can be transferred and the data can be transferred via the switch 600.

In a modification of the communication system, nsec level clock synchronization can be realized.
<Modification (Part 3)>
In a modification of the communication system, the first communication device 100 described with reference to FIG. 11 and the second communication device 200 are daisy-chain connected via a third communication device.

  FIG. 13 shows a modification of the communication system.

  In the example shown in FIG. 13, the first communication device 100 and the second communication device 200 described with reference to FIG. 11 are prepared. The first communication device 100 and the second communication device 200 are daisy chain connected via the third communication device 100.

  The third communication apparatus 1000 includes a common clock 1002, a slave time synchronization circuit 1004, a data transfer circuit 1006, an endpoint 1016, a master time synchronization circuit 1018, and a route complex 1026. The IF card 1010 is connected to the third communication apparatus 1000 via the end point 1016. In addition, a transceiver 1014 is connected to the IF card 1010. The IF card 1020 is connected to the third communication apparatus 1000 via the route complex 1026. In addition, the transceiver 1024 is connected to the IF card 1020.

The slave time synchronization circuit 1004 is similar to the slave time synchronization circuit 204, the data transfer circuit 1006 is similar to the data transfer circuit 206, and the endpoint 1016 is similar to the endpoint 216. The master time synchronization circuit 1018 is the same as the master time synchronization circuit 104, and the root complex 1026 is the same as the root complex 116. The IF card 1010 is similar to the IF card 210, the switch 1012 is similar to the switch 212, and the transceiver 1014 is similar to the transceiver 214.
The IF card 1020 is similar to the IF card 110, the switch 1022 is similar to the switch 112, and the transceiver 1024 is similar to the transceiver 114.

  The third communication device 1000 functions as a slave with respect to the first communication device 100 in time synchronization. In addition, the third communication device 1000 functions as a master in time synchronization with respect to the second communication device 200.

  The second communication apparatus 1000 executes a process of synchronizing the clock (common clock 1002) of its own apparatus with the clock (master clock 102) of the first communication apparatus 100 as a master.

  Slave time synchronization circuit 1004 is connected to common clock 1002. The slave time synchronization circuit 1004 receives time information from the common clock 1002. The slave time synchronization circuit 1004 receives the time request packet from the first communication device 100 from the endpoint 1016. The slave time synchronization circuit 1004 outputs a time response packet corresponding to the time request packet to the VC 1 of the endpoint 1016. The slave time synchronization circuit 1004 receives the correction amount signal from VC1 of the endpoint 1016. The slave time synchronization circuit 1004 inputs the correction amount included in the correction amount signal to the common clock 1002. The common clock 1002 corrects the clock based on the correction amount from the slave time synchronization circuit 1004.

  Master time synchronization circuit 1018 is connected to common clock 1002. The master time synchronization circuit 1018 receives time information from the common clock 1002. The master time synchronization circuit 1018 outputs a time request packet for requesting the time to the second communication device 200 to VC1 of the route complex 1026. The master time synchronization circuit 1018 receives the time response packet from the second communication device 200 for the time request packet from the VC 1 of the route complex 1026. The master time synchronization circuit 1018 calculates a correction amount for synchronizing the slave clock 202 of the second communication device 200 with the common clock 1002. The master time synchronization circuit 1018 outputs a correction amount signal including a correction amount to VC1 of the root complex 1026.

  In FIG. 13, a plurality of third communication apparatuses 1000 may be daisy chain connected.

  In this case, the other third communication device connected to the third communication device is connected to the third communication device when the third communication device is directly or indirectly connected to the first communication device 100. The communication device functions as a slave in time synchronization.

  In addition, when the other third communication apparatus is connected to the third communication apparatus that is directly or indirectly connected to the second communication apparatus 200, the time is compared with the third communication apparatus. Act as master in synchronization.

  The third communication device executes processing for synchronizing the clock (common clock) of the third communication device with the clock (common clock) of the other third communication device as a slave.

  The slave time synchronization circuit 1004 of the other third communication device is connected to the common clock 1002 of the other third communication device. The slave time synchronization circuit 1004 of the other third communication device receives time information from the common clock 1002 of the other third communication device. The slave time synchronization circuit 1004 of the other third communication device receives the time request packet from the third communication device from the endpoint 1016 of the other third communication device. The slave time synchronization circuit 1004 of the other third communication device outputs a time response packet corresponding to the time request packet to the VC1 of the endpoint 1016 of the other third communication device. The slave time synchronization circuit 1004 of the other third communication device receives the correction amount signal from the VC1 of the endpoint 1016 of the other third communication device. The slave time synchronization circuit 1004 of the other third communication device inputs the correction amount included in the correction amount signal to the common clock 1002 of the other third communication device. The common clock 1002 of the other third communication device corrects the clock based on the correction amount from the slave time synchronization circuit 1004 of the other third communication device.

  The master time synchronization circuit 1018 of the other third communication device is connected to the common clock 1002 of the other third communication device. The master time synchronization circuit 1018 of the other third communication device receives time information from the common clock 1002 of the other third communication device. The master time synchronization circuit 1018 of the other third communication device is connected to the VC1 of the route complex 1026 of the other third communication device to the third communication device that functions as a slave to the other third communication device. A time request packet for requesting time is output. The master time synchronization circuit 1018 of the other third communication device receives the time response packet from the second communication device 200 for the time request packet from VC1 of the route complex 1026 of the other third communication device. The master time synchronization circuit 1018 of the other third communication device uses the common clock of the third communication device that functions as a slave to the other third communication device to the common clock 1002 of the other third communication device. A correction amount for synchronization is calculated. The master time synchronization circuit 1018 of the other third communication device outputs a correction amount signal including the correction amount to VC1 of the route complex 1026 of the other third communication device.

  In a modification of the communication system, the common clock 1002 of one or more third communication devices 1000 can be synchronized with the master clock 102 of the first communication device 100, and the one or more third communication devices 1000, the slave clock 202 of the second communication device 200 can be synchronized with the common clock 1002 of one third communication device connected to the second communication device 200. That is, the common clock 1002 of the third communication device 1000 and the slave clock 202 of the second communication device 200 can be synchronized with the master clock 102 of the first communication device 100 at the nsec level.

<Modification (Part 4)>
A modification of the communication system shows an application example to an image forming apparatus.

  FIG. 13 shows a modification of the communication system.

  The communication system includes a digital front end (DFE) 700 and a printer 800.

  The digital front end 700 includes a RIP (Raster Image Processing) processing unit 904, a first communication device 100, an IF card 110, and a transceiver 114.

  The RIP processing unit 904 includes a CPU 906, a rendering processing unit 908, a compression processing unit 910, an expansion processing unit 912, an HDD 914, a network processing unit 916, and a memory 918.

  The printer 800 includes a transceiver 214, an IF card 210, a second communication device 200, a print controller 802, and a print engine 816.

  The print controller 802 includes a CPU 804, a write control unit 806, and a DMAC (Direct Memory Access Controller) 808. The print engine 816 has a printing unit 812.

  The RIP processing unit 904 expands the print job transmitted from the client PC 902 from PDL (Page Description Language) format to image data in a raster format for printing.

  The print controller 802 controls the print engine 816. The print controller 802 executes control for transferring image data from the second communication apparatus 200 to the print engine 816.

  The print engine 816 prints image data by a predetermined method. The predetermined method includes an electrophotographic method and an ink jet method.

<Operation of communication system>
The operation when a print job is executed by the client according to the numbers shown in FIG. 13 will be described.

  (1) A print job is transmitted from the client PC 902 to the network processing unit 916 of the RIP processing unit 904 via the LAN. The print job format is preferably a PDL format.

  (2) The print job received by the network processing unit 916 is temporarily stored in the memory 918.

  (3) The rendering processing unit 908 reads the print job stored in the memory 918 and develops it into print image data by performing a rendering process. The print image data is preferably in a raster format.

  (4) The compression processing unit 910 compresses the image data expanded by the rendering processing unit 908 and stores it in the HDD 914.

  (5) The expansion processing unit 912 sequentially expands the compressed data stored in the HDD 914 and expands it in the memory 918.

  (6) The data transfer circuit 106 reads the image data developed in the memory 918 and inputs it to the IF 108.

  (7) The image data input to the IF 108 is transferred to the data transfer circuit 206 of the second communication device 200 via the switch 112, the transceiver 114, the transmission path 300, the transceiver 214, the switch 212, and the IF 208.

  (8) The write control unit 806 of the print controller 802 instructs the print processing to the DMAC 808 of the print controller 802 and the printing unit 812 of the print engine 816. The DMAC 806 reads the image data from the data transfer circuit 206 and transfers it to the printing unit 812. The printing unit 812 prints the image data transferred from the data transfer circuit 206.

  The data transfer process (8) is performed simultaneously in parallel for each print job, for each page, or for the band data constituting the page and the line data constituting the band data. The printing process can be executed by performing the data transfer process in a predetermined unit with simultaneous changes.

  When the digital front end 700 and the printer 800 execute print processing, in order to obtain various job controls and log data that can be referred to when a failure occurs, the digital front end 700 and the printer 800 manage time stamps at times that are accurately synchronized. Must be done.

  By applying an embodiment of the communication system to the image forming apparatus, a serial interface capable of high-speed data transfer can be used for time synchronization when performing high-speed printer raster image transfer. Furthermore, assuming that the DFE is the master and the printer is the slave, accurate time stamp management can be realized by synchronizing the time.

  Although the present invention has been described with reference to particular embodiments, each embodiment is merely illustrative, and those skilled in the art will appreciate various variations, modifications, alternatives, substitutions, and the like. . For convenience of explanation, an apparatus according to an embodiment of the present invention has been described using a functional block diagram, but such an apparatus may be implemented in hardware, software, or a combination thereof. The present invention is not limited to the above-described embodiments, and various variations, modifications, alternatives, substitutions, and the like are included without departing from the spirit of the present invention.

100 First communication device 102 Master clock 104 Master time synchronization circuit 106 Data transfer circuit 108 IF
110 IF card 112 switch 114 transceiver 300 transmission line 200 second communication device 202 master clock 204 master time synchronization circuit 206 data transfer circuit 208 IF
210 IF card 212 Switch 214 Transceiver

JP 2007-27985 A

Claims (8)

A communication system having a first communication device and one or more second communication devices connected to the first communication device by a serial IF,
The first communication device is:
The first watch,
The time request is made by the one or more second communication devices after starting transmission of a time request packet for requesting the time set in the one or more second communication devices by the first clock. The time until the reception of the response packet for the packet is started is obtained, and transmission of the time request packet is required between the time and the first communication device and the one or more second communication devices. A first time synchronization circuit that calculates a correction amount of a second timepiece of the one or more second communication devices based on time,
A first interface that outputs the time request packet and the correction amount, and inputs the response packet to the first time synchronization circuit;
In the first interface, a first virtual channel for transferring the time request packet, the correction amount, and the response packet, and a second virtual channel for transferring data are set, and the second virtual channel is set. The time request packet transferred on the first virtual channel and the time stamp of the correction amount are given priority over the data transferred on the first virtual channel, and the output of the data transmitted on the second virtual channel is prioritized. Preferentially select the response packet to be output on the virtual channel;
Each of the one or more second communication devices includes:
A second watch,
Obtaining a time from the start of reception of the time request packet by the second clock to the start of transmission of the response packet, creating the response packet including the time, from the first communication device A second time synchronization circuit for correcting the second timepiece based on the correction amount;
A second interface for outputting the response packet and inputting the correction amount to the second time synchronization circuit;
In the second interface, a third virtual channel for transferring the time request packet, the response packet, and the correction amount, and a fourth virtual channel for transferring data are set, and the fourth virtual channel is set. Giving priority to the time stamp of the response packet transferred on the third virtual channel over the data transferred on the first virtual channel, and outputting on the third virtual channel over the output of the data transmitted on the fourth virtual channel A communication system that preferentially selects the time request packet and the correction amount. The first time synchronization circuit includes:
A first time required from the start of transmission of the time request packet to reception of a response packet to the time request packet from the one or more second communication devices is obtained, and the first time and Based on the second time from when the one or more second communication devices start to receive the time request packet to when the response packet starts to be transmitted, the first communication device and the first communication device Alternatively, a third time required for transmission of the time request packet with a plurality of second communication devices is predicted, and transmission of the time request packet is started after the third time is started. 2. The communication according to claim 1, wherein a correction amount of a second clock of the one or more second communication devices is calculated based on a time until reception of the time request packet is started by the communication device. system. The first interface includes a first buffer for storing the time request packet to be transferred in the first virtual channel and the correction amount;
2. The communication according to claim 1, further comprising: a second buffer that stores the data to be transferred through the second virtual channel, wherein a size of the first buffer is substantially the same as a size of the time request packet. system. The first interface includes a first root complex;
The communication system according to any one of claims 1 to 3, wherein the second interface includes a second root complex or an endpoint. The communication system according to claim 4, further comprising a switch arranged between the first root complex and the endpoint or the second root complex. The first communication device is mounted on a digital front end;
The communication system according to claim 1, wherein the second communication device is mounted on a printer. A first communication device, one or more third communication devices sequentially connected to the first communication device via a serial IF, and one of the one or more third communication devices and a serial IF. A communication system having a connected second communication device,
The first communication device is:
The first watch,
The first communication starts after transmission of a first time request packet for requesting a time set in a third communication device connected to the first communication device by the first clock. A time until reception of the first response packet for the first time request packet from the third communication device connected to the device is started, and the time, the first communication device, and the Based on the time required for transmission of the first time request packet to and from the third communication device connected to the first communication device, the third connected to the first communication device. A first time synchronization circuit for calculating a first correction amount of a third watch of the communication device;
A first interface for outputting the first time request packet and the first correction amount and inputting the first response packet to the first time synchronization circuit;
The first interface includes a first virtual channel that transfers the first time request packet, the first correction amount, and the first response packet, and a second virtual that transfers first data. The first time request packet transferred through the first virtual channel and the first correction amount time stamp are given priority over the first data transferred through the second virtual channel. And preferentially selecting the first response packet to be output on the first virtual channel over the output of the first data to be transmitted on the second virtual channel,
Each of the one or more third communication devices includes:
The third watch;
The first response packet or the second time request from the start of reception of the first time request packet or the second time request packet from the connected third communication device by the third clock A time until the start of transmission of a second response packet to the packet is obtained, the first response packet including the time or the second response packet is created, and the first communication device receives the first response packet from the first communication device. A third time synchronization circuit that corrects the third clock based on a second correction amount or a second correction amount from a third communication device that transmits the second time request packet;
A third interface for outputting the first response packet or the second response packet and inputting the first correction amount or the second correction amount to the third time synchronization circuit;
A third time requesting the time set in the connected third communication device among the third communication devices other than the third communication device transmitting the second time request packet by the third clock. The third communication device that is the transmission destination of the third time request packet after starting the transmission of the fourth time request packet that requests the time set packet of the first time request packet or the time set in the second communication device To obtain a time until reception of a third response packet for the third time request packet or a fourth response packet for the fourth time request packet by the second communication device is started, and The transmission of the third time request packet is required between the third communication device that transmits the third time request packet and the third communication device that is the transmission destination of the third time request packet. Time Based on the time required for transmission of the fourth time request packet between the third communication device that transmits the fourth time request packet and the second communication device, the third time request packet A fourth time synchronization circuit for calculating a third correction amount of the third timepiece of the third communication device that is a transmission destination of the second timepiece or a fourth correction amount of the second timepiece of the second communication device;
The third time request packet and the third correction amount or the fourth time request packet and the fourth correction amount are output, and the third response packet or the fourth time synchronization circuit is output to the fourth time synchronization circuit. A fourth interface for inputting a fourth response packet;
The third interface includes the first time request packet, the first response packet, the first correction amount, or the second time request packet, the second response packet, and the second correction. A fifth virtual channel for transferring the amount and a sixth virtual channel for transferring the first data are set, and the fifth virtual channel is set to be higher than the first data transferred on the sixth virtual channel. Give priority to the time stamp of the first response packet or the second response packet transferred on the channel, and output on the fifth virtual channel over the output of the first data transmitted on the sixth virtual channel Preferentially select the first time request packet and the first correction amount or the second time request packet and the second correction amount,
The fourth interface includes the third time request packet, the third response packet, the third correction amount, or the fourth time request packet, the fourth response packet, and the fourth correction. A seventh virtual channel for transferring the amount of data and an eighth virtual channel for transferring the second data are set, and the seventh virtual channel is more than the second data transferred by the eighth virtual channel. Giving priority to the third time request packet and the third correction amount or the fourth time request packet and the fourth correction amount time stamp transferred in step 8, and transmitting on the eighth virtual channel. Preferentially selecting the third response packet or the fourth response packet to be output on the seventh virtual channel over the output of the data of 2;
The second communication device is:
The second watch;
The time from the start of reception of the fourth time request packet by the second clock to the start of transmission of the fourth response packet is obtained, and the fourth response packet including the time is created. A second time synchronization circuit that corrects the second clock based on the fourth correction amount from the third communication device that has transmitted the fourth time request packet;
A second interface for outputting the fourth response packet and inputting the fourth correction amount to the second time synchronization circuit;
A third virtual channel for transferring the fourth time request packet, the fourth response packet, and the fourth correction amount to the second interface, and a fourth virtual channel for transferring the second data. A virtual channel is set, and the time stamp of the fourth response packet transferred on the third virtual channel is prioritized over the second data transferred on the fourth virtual channel, and the fourth virtual channel is prioritized. A communication system that preferentially selects the fourth time request packet and the fourth correction amount output by the third virtual channel over the output of the second data transmitted by the channel. A time synchronization method in a communication system having a first communication device and one or more second communication devices connected to the first communication device via a serial IF,
The first communication device is:
The time request packet is transmitted by the one or more second communication devices after starting transmission of the time request packet for requesting the time set in the one or more second communication devices by the first clock. Based on the time required to transmit the time request packet between the first communication device and the one or more second communication devices. Calculating the correction amount of the second timepiece of the second communication device,
The first interface outputs the time request packet and the correction amount, and inputs the response packet to the first time synchronization circuit,
In the first interface, a first virtual channel for transferring the time request packet, the correction amount, and the response packet, and a second virtual channel for transferring data are set, and the second virtual channel is set. The time request packet transferred on the first virtual channel and the time stamp of the correction amount are given priority over the data transferred on the first virtual channel, and the output of the data transmitted on the second virtual channel is prioritized. Preferentially select the response packet to be output on the virtual channel;
Each of the one or more second communication devices includes:
A time from when reception of the time request packet is started by a second clock until transmission of the response packet is obtained, the response packet including the time is created, and the response from the first communication device is generated. Correcting the second clock based on the correction amount;
The second interface outputs the response packet, and inputs the correction amount to the second time synchronization circuit,
In the second interface, a first virtual channel for transferring the time request packet, the response packet, and the correction amount, and a second virtual channel for transferring data are set, and the second virtual channel is set. Giving priority to the time stamp of the response packet transferred on the first virtual channel over the data transferred on the first virtual channel, and outputting on the first virtual channel over the output of the data transmitted on the second virtual channel A time synchronization method for preferentially selecting the time request packet and the correction amount.

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