JP2014146774A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2014146774A
JP2014146774A JP2013016137A JP2013016137A JP2014146774A JP 2014146774 A JP2014146774 A JP 2014146774A JP 2013016137 A JP2013016137 A JP 2013016137A JP 2013016137 A JP2013016137 A JP 2013016137A JP 2014146774 A JP2014146774 A JP 2014146774A
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sealing material
semiconductor device
substrate
semiconductor chip
sealing
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JP6167535B2 (en
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Katsuhiko Yanagawa
克彦 柳川
Yoshinari Ikeda
良成 池田
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is highly reliable and can be inexpensively provided, and a method of manufacturing the semiconductor device.SOLUTION: An SiC semiconductor device 10 comprises an insulating substrate 1, a semiconductor chip 6, a printed circuit board 9, and external electrode terminals 11 and 12. The rear surface of the semiconductor chip 6 is bonded to a first copper block 3 on the front surface side of the insulating substrate 1. A front surface electrode of the semiconductor chip 6 is bonded to an implant pin 8 of the printed circuit board 9 disposed on the front surface side of the semiconductor chip 6. A first sealing body 21 is filled between the insulating substrate 1 and the printed circuit board 9, and the semiconductor chip 6 and the implant pin 8 are sealed with the first sealing body 21. The whole front surface side of the insulating substrate 1 is sealed with a second sealing body 22. The second sealing body 22 covers the first sealing body 21, the insulating substrate 1, and the printed circuit board 9. The outer periphery of the second sealing body 22 is covered with a third sealing body 23 for preventing the second sealing body 22 from being oxidized.

Description

この発明は、半導体装置および半導体装置の製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

従来、パワー半導体モジュールなどのパワー半導体装置では、インプラントピンなどの導電性ポストを有するインプラント方式のプリント基板を介して半導体チップの表面電極と外部電極用端子とを接続した構造が公知である。このような従来の半導体装置について、シリコン（Ｓｉ）からなるＳｉ半導体素子を備えたＳｉ半導体装置の例について説明する。図７は、従来のＳｉ半導体装置の構成を示す断面図である。図７に示すように、従来のＳｉ半導体装置１１０は、絶縁基板１０１、Ｓｉ半導体素子を有する半導体チップ１０６、インプラントピン１０８などの導電性ポストを有するプリント基板１０９、および外部電極用端子１１１，１１２を備える。   2. Description of the Related Art Conventionally, a power semiconductor device such as a power semiconductor module has a known structure in which a surface electrode of a semiconductor chip and an external electrode terminal are connected via an implant type printed circuit board having conductive posts such as implant pins. As such a conventional semiconductor device, an example of a Si semiconductor device including a Si semiconductor element made of silicon (Si) will be described. FIG. 7 is a cross-sectional view showing a configuration of a conventional Si semiconductor device. As shown in FIG. 7, a conventional Si semiconductor device 110 includes an insulating substrate 101, a semiconductor chip 106 having Si semiconductor elements, a printed circuit board 109 having conductive posts such as implant pins 108, and external electrode terminals 111 and 112. Is provided.

絶縁基板１０１は、絶縁層１０２の両面にそれぞれ第１，２銅（Ｃｕ）ブロック１０３，１０４が接合されてなる。半導体チップ１０６の裏面は、導電性材料からなる接合層（以下、導電接合層とする）１０５を介して絶縁基板１０１のおもて面側の第１銅ブロック１０３に接合されている。半導体チップ１０６のおもて面側には、プリント基板１０９が配置されている。プリント基板１０９の半導体チップ１０６側の面には、インプラントピン１０８が配置されている。半導体チップ１０６のおもて面電極（不図示）は、導電接合層１０７を介してインプラントピン１０８に接合されている。   The insulating substrate 101 is formed by bonding first and second copper (Cu) blocks 103 and 104 to both surfaces of an insulating layer 102, respectively. The back surface of the semiconductor chip 106 is bonded to the first copper block 103 on the front surface side of the insulating substrate 101 via a bonding layer (hereinafter referred to as a conductive bonding layer) 105 made of a conductive material. A printed circuit board 109 is disposed on the front surface side of the semiconductor chip 106. Implant pins 108 are arranged on the surface of the printed circuit board 109 on the semiconductor chip 106 side. A front surface electrode (not shown) of the semiconductor chip 106 is bonded to the implant pin 108 via a conductive bonding layer 107.

外部電極用端子１１１は、絶縁基板１０１のおもて面側の第１銅ブロック１０３に接合されている。外部電極用端子１１２は、プリント基板１０９の回路パターン（不図示）に接合されている。これら絶縁基板１０１、半導体チップ１０６、インプラントピン１０８、プリント基板１０９および外部電極用端子１１１，１１２は、金型を用いて封入された封止材１１３によって封止されＳｉ半導体装置１１０が構成されている。絶縁基板１０１の裏面側の第２銅ブロック１０４は、熱伝導ペーストを介して冷却器（不図示）に接合されている。   The external electrode terminal 111 is joined to the first copper block 103 on the front surface side of the insulating substrate 101. The external electrode terminal 112 is bonded to a circuit pattern (not shown) of the printed circuit board 109. The insulating substrate 101, the semiconductor chip 106, the implant pin 108, the printed circuit board 109, and the external electrode terminals 111 and 112 are sealed by a sealing material 113 encapsulated using a mold to form the Si semiconductor device 110. Yes. The second copper block 104 on the back surface side of the insulating substrate 101 is joined to a cooler (not shown) via a heat conductive paste.

封止材１１３の内部にはＳｉ半導体装置１１０を冷却器に固定するためのボルト（不図示）の挿入孔である取付け金具１１４が埋め込まれている。この取付け金具１１４に挿入されるボルトによってＳｉ半導体装置１１０が冷却器に固定される。Ｓｉ半導体装置１１０の動作時、半導体チップ１０６や回路パターンには大電流が流れる。このため、半導体チップ１０６やプリント基板１０９の回路パターンで発生した熱を絶縁基板１０１から冷却器へ伝導して放熱し、半導体チップ１０６やプリント基板１０９を冷却することが重要となる。   Inside the sealing material 113, a mounting bracket 114, which is an insertion hole for a bolt (not shown) for fixing the Si semiconductor device 110 to the cooler, is embedded. The Si semiconductor device 110 is fixed to the cooler by bolts inserted into the mounting bracket 114. During the operation of the Si semiconductor device 110, a large current flows through the semiconductor chip 106 and the circuit pattern. For this reason, it is important to cool the semiconductor chip 106 and the printed circuit board 109 by transferring the heat generated in the circuit pattern of the semiconductor chip 106 and the printed circuit board 109 from the insulating substrate 101 to the cooler to dissipate the heat.

このような半導体装置として、次の装置が提案されている。絶縁板の第１の主面に金属箔が形成され、絶縁板の第２の主面に、少なくとも一つの別の金属箔が形成される。また、別の金属箔上に接合された少なくとも一つの半導体素子と、半導体素子が配置された絶縁板の主面に対向するようにプリント基板が配置される。そして、プリント基板の第１の主面に形成された金属箔またはプリント基板の第２の主面に形成された別の金属箔と、半導体素子の主電極とが複数のポスト電極により電気的に接続される（例えば、下記特許文献１参照。）。   The following devices have been proposed as such semiconductor devices. A metal foil is formed on the first main surface of the insulating plate, and at least one other metal foil is formed on the second main surface of the insulating plate. In addition, the printed circuit board is disposed so as to face at least one semiconductor element bonded on another metal foil and the main surface of the insulating plate on which the semiconductor element is disposed. The metal foil formed on the first main surface of the printed circuit board or another metal foil formed on the second main surface of the printed circuit board and the main electrode of the semiconductor element are electrically connected by a plurality of post electrodes. (For example, refer to Patent Document 1 below.)

また、別の装置として、封止材層が第１封止材層と第２封止材層をこの順に積層したものであり、半導体チップと、リードフレームと、半導体チップの周囲の銅ベース基板とが第１封止材層で覆われており、当該第１封止材層が第２封止材層で覆われており、第１封止材層の熱膨張係数が銅ベース基板の熱膨張係数付近の所定の値である装置が提案されている（例えば、下記特許文献２参照。）。また、別の装置として、半導体素体を電圧印加特性を向上させる樹脂で覆い、その上を耐湿性を向上させる樹脂で覆った装置が提案されている（例えば、下記特許文献３参照。）。   As another device, a sealing material layer is a stack of a first sealing material layer and a second sealing material layer in this order. A semiconductor chip, a lead frame, and a copper base substrate around the semiconductor chip Are covered with the first sealing material layer, the first sealing material layer is covered with the second sealing material layer, and the thermal expansion coefficient of the first sealing material layer is the heat of the copper base substrate. An apparatus having a predetermined value near the expansion coefficient has been proposed (for example, see Patent Document 2 below). As another device, there has been proposed a device in which a semiconductor element body is covered with a resin that improves voltage application characteristics and is covered with a resin that improves moisture resistance (see, for example, Patent Document 3 below).

また、別の装置として、次の装置が提案されている。半導体素子を被覆する充填手段を複数層構造とする。半導体素子に直接接触する絶縁性の第１充填層部を、半導体素子の最高温度以上の耐熱温度の材料で形成する。その周囲の第２充填層部を、低耐熱性の安価な材料で構成する。第１充填層部の熱伝導性を低くし、裏面への放熱を増やし、第２充填層部の温度上昇を防止する（例えば、下記特許文献４参照。）。   As another apparatus, the following apparatus has been proposed. The filling means for covering the semiconductor element has a multi-layer structure. The insulating first filling layer portion that is in direct contact with the semiconductor element is formed of a material having a heat resistant temperature equal to or higher than the maximum temperature of the semiconductor element. The surrounding 2nd filling layer part is comprised with an inexpensive material with low heat resistance. The thermal conductivity of the first filling layer portion is lowered, the heat radiation to the back surface is increased, and the temperature rise of the second filling layer portion is prevented (for example, see Patent Document 4 below).

また、別の装置として、次の装置が提案されている。半導体素子の回路形成面を封止する封止樹脂とを設けており、実装側面、背面および側面を有する半導体装置において、半導体装置の背面および側面に補強材として機能する有機材層が形成されている。有機材層はポリパラキシリレンからなる。（例えば、下記特許文献５参照。）。また、別の装置として、センサ素体を包囲して注型された透明樹脂の表面にポリパラキシリレンを蒸着してセンサ素体表面の凹凸を埋めて平坦にすることで光学特性を向上させた装置が提案されている（例えば、下記特許文献６参照。）。   As another apparatus, the following apparatus has been proposed. A sealing resin for sealing a circuit forming surface of a semiconductor element is provided, and in a semiconductor device having a mounting side surface, a back surface, and a side surface, an organic material layer that functions as a reinforcing material is formed on the back surface and the side surface of the semiconductor device. Yes. The organic material layer is made of polyparaxylylene. (For example, see Patent Document 5 below.) As another device, the optical properties are improved by depositing polyparaxylylene on the surface of the transparent resin that is cast around the sensor element to fill the unevenness of the sensor element surface and flatten it. Have been proposed (see, for example, Patent Document 6 below).

また、別の装置として、次の装置が提案されている。集積回路の基板の上の半導体素子およびリード細線の端部を含むようにポリイミド樹脂からなる第１の保護樹脂層を設ける。この第１の保護樹脂層の表面上にリード細線を覆わないようにシリコーンラバーからなる第２の保護樹脂層を設ける。最後にエポキシ樹脂からなる樹脂封止体を設ける（例えば、下記特許文献７参照。）。   As another apparatus, the following apparatus has been proposed. A first protective resin layer made of polyimide resin is provided so as to include the semiconductor element on the substrate of the integrated circuit and the ends of the fine lead wires. A second protective resin layer made of silicone rubber is provided on the surface of the first protective resin layer so as not to cover the fine lead wires. Finally, a resin sealing body made of an epoxy resin is provided (see, for example, Patent Document 7 below).

また、半導体装置を封止材によって封止する方法として、次の方法が提案されている。フリップチップと回路基板との隙間に、液状エポキシ樹脂を注入し、１５分以下の加熱によってエポキシ基が初期の３０％以上残っている半硬化状態にし、フリップチップ全体を覆うように液状エポキシ樹脂を配置し、２時間の加熱によって積層した両樹脂を完全硬化させる。その結果、フリップチップと回路基板との隙間に下層側封止樹脂が配置されるとともに、フリップチップ全体が上層側封止樹脂にて覆われる（例えば、下記特許文献８参照。）。   Moreover, the following method is proposed as a method of sealing a semiconductor device with a sealing material. Liquid epoxy resin is injected into the gap between the flip chip and the circuit board, heated to 15 minutes or less to make it a semi-cured state in which more than 30% of the epoxy groups remain, and the liquid epoxy resin is applied to cover the entire flip chip. Place and fully cure both resins laminated by heating for 2 hours. As a result, the lower layer side sealing resin is disposed in the gap between the flip chip and the circuit board, and the entire flip chip is covered with the upper layer side sealing resin (see, for example, Patent Document 8 below).

このような半導体装置に内蔵される半導体素子の構成材料は、将来的に、炭化珪素（ＳｉＣ）や窒化ガリウム（ＧａＮ）に置き換えられることが想定されている。その理由は、ＳｉＣやＧａＮがＳｉに比べて優れた電気的特性を有するため、ＳｉＣやＧａＮからなる半導体素子はＳｉ半導体素子に比べて高温環境下での動作特性が優れているからである。したがって、半導体素子を構成する材料にＳｉＣやＧａＮを用いた場合、半導体素子の電流密度を高めることができる。   It is assumed that the constituent material of the semiconductor element incorporated in such a semiconductor device will be replaced with silicon carbide (SiC) or gallium nitride (GaN) in the future. The reason is that since SiC and GaN have superior electrical characteristics compared to Si, a semiconductor element made of SiC or GaN has superior operating characteristics under a high temperature environment as compared to a Si semiconductor element. Therefore, when SiC or GaN is used as the material constituting the semiconductor element, the current density of the semiconductor element can be increased.

特開２００９−０６４８５２号公報JP 2009-064852 特開２０１０−２１９４２０号公報JP 2010-219420 A 特開平５−１３６２３号公報JP-A-5-13623 特開２００６−３１３７７５号公報JP 2006-313775 A 特開２００２−２７０７２１号公報JP 2002-270721 A 特開平３−６８７５７号公報Japanese Patent Laid-Open No. 3-68757 特開平８−８８２９８号公報JP-A-8-88298 特開平９−２４６３００号公報JP-A-9-246300

しかしながら、半導体素子を高電流密度にするほど発熱量が増大して、半導体装置の内部の半導体素子付近の温度が高くなる。このため、半導体装置の信頼性を維持するために封止材の耐熱性を向上させる必要があるが、耐熱性の高い封止材は高価であるため、コストが増大するという問題がある。一方、半導体装置の外周部（半導体素子から離れた部分）では、半導体素子付近に比べて半導体素子の発熱による温度上昇は小さい。しかしながら、半導体装置の外周部では、封止材が外部に露出されており、この露出された部分で空気に接する。このため、空気中の酸素によって封止材が酸化して劣化し、封止材の材料物性に基づく性能が低下するという問題がある。   However, as the semiconductor element has a higher current density, the amount of heat generation increases, and the temperature near the semiconductor element inside the semiconductor device increases. For this reason, in order to maintain the reliability of the semiconductor device, it is necessary to improve the heat resistance of the sealing material. However, since the sealing material having high heat resistance is expensive, there is a problem that the cost increases. On the other hand, the temperature rise due to heat generation of the semiconductor element is small in the outer peripheral portion (a part away from the semiconductor element) of the semiconductor device as compared with the vicinity of the semiconductor element. However, at the outer peripheral portion of the semiconductor device, the sealing material is exposed to the outside, and the exposed portion is in contact with air. For this reason, there exists a problem that the performance based on the physical property of a sealing material falls by oxidizing and degrading a sealing material with the oxygen in air.

この発明は、上述した従来技術による問題点を解消するため、信頼性が高くかつ安価な半導体装置および半導体装置の製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable and inexpensive semiconductor device and a method for manufacturing the semiconductor device in order to solve the above-described problems caused by the prior art.

上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置は、半導体チップの裏面に接合された第１基板と、前記半導体チップのおもて面に接合された第２基板と、前記第１基板と前記第２基板との間に封入され前記半導体チップを封止する第１封止材と、第２封止材によって前記第１基板、前記第２基板および前記第１封止材を封止してなる成形体と、前記成形体の表面を覆う第３封止材と、を備え、前記第１封止材は、前記半導体チップの発熱に耐え得る耐熱性を有し、前記第２封止材は、前記第１封止材および前記第３封止材よりも耐熱性が低く、前記第３封止材は、耐酸化性を有することを特徴とする。   In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device according to the present invention includes a first substrate bonded to the back surface of a semiconductor chip and a first substrate bonded to the front surface of the semiconductor chip. Two substrates, a first sealing material sealed between the first substrate and the second substrate and sealing the semiconductor chip, and the first substrate, the second substrate, and the second sealing material by a second sealing material A molded body formed by sealing the first sealing material; and a third sealing material that covers a surface of the molded body, wherein the first sealing material is heat resistant to withstand heat generation of the semiconductor chip. The second sealing material has lower heat resistance than the first sealing material and the third sealing material, and the third sealing material has oxidation resistance. .

また、この発明にかかる半導体装置は、上述した発明において、前記第１基板の前記半導体チップ側に対して反対側の面は前記成形体の表面に露出されており、前記第３封止材は、前記成形体の、前記第１基板の前記半導体チップ側に対して反対側の面以外の表面を覆うことを特徴とする。   In the semiconductor device according to the present invention, in the above-described invention, a surface of the first substrate opposite to the semiconductor chip side is exposed on a surface of the molded body, and the third sealing material is The molded body covers a surface other than the surface opposite to the semiconductor chip side of the first substrate.

また、この発明にかかる半導体装置は、上述した発明において、前記第３封止材は、ポリパラキシリレンからなることを特徴とする。   In the semiconductor device according to the present invention as set forth in the invention described above, the third sealing material is made of polyparaxylylene.

また、この発明にかかる半導体装置は、上述した発明において、前記半導体チップに電気的に接続される外部電極用端子をさらに備え、前記外部電極用端子の外部接続される側の端部は露出されていることを特徴とする。   The semiconductor device according to the present invention further includes an external electrode terminal electrically connected to the semiconductor chip in the above-described invention, and an end of the external electrode terminal on the side to be externally connected is exposed. It is characterized by.

また、この発明にかかる半導体装置は、上述した発明において、前記第１封止材の熱変形温度は２００℃以上であることを特徴とする。   The semiconductor device according to the present invention is characterized in that, in the above-described invention, the thermal deformation temperature of the first sealing material is 200 ° C. or higher.

また、この発明にかかる半導体装置は、上述した発明において、前記第１封止材の前記第１基板に対する接着強さは１０ＭＰａ以上３０ＭＰａ以下であることを特徴とする。   The semiconductor device according to the present invention is characterized in that, in the above-described invention, the adhesive strength of the first sealing material to the first substrate is 10 MPa or more and 30 MPa or less.

また、この発明にかかる半導体装置は、上述した発明において、前記第１封止材の熱膨張係数は１０×１０-6／℃以上１８×１０-6／℃以下であることを特徴とする。 In the semiconductor device according to the present invention, the thermal expansion coefficient of the first sealing material is 10 × 10 −6 / ° C. or more and 18 × 10 −6 / ° C. or less in the above-described invention.

また、この発明にかかる半導体装置は、上述した発明において、前記第１封止材は、エポキシ樹脂系材料からなることを特徴とする。   In the semiconductor device according to the present invention as set forth in the invention described above, the first sealing material is made of an epoxy resin material.

また、この発明にかかる半導体装置は、上述した発明において、前記第２封止材の熱変形温度が１００℃以上２００℃以下であることを特徴とする。   The semiconductor device according to the present invention is characterized in that, in the above-described invention, a heat deformation temperature of the second sealing material is 100 ° C. or higher and 200 ° C. or lower.

また、この発明にかかる半導体装置は、上述した発明において、前記第２封止材の熱膨張係数が１０×１０-6／℃以上１８×１０-6／℃以下であることを特徴とする。 The semiconductor device according to the present invention is characterized in that, in the above-described invention, the second sealing material has a thermal expansion coefficient of 10 × 10 −6 / ° C. or more and 18 × 10 −6 / ° C. or less.

また、この発明にかかる半導体装置は、上述した発明において、前記第２封止材の前記第１基板に対する接着強さは１０ＭＰａ以上３０ＭＰａ以下であることを特徴とする。   The semiconductor device according to the present invention is characterized in that, in the above-described invention, the adhesion strength of the second sealing material to the first substrate is 10 MPa or more and 30 MPa or less.

また、この発明にかかる半導体装置は、上述した発明において、前記第２封止材は、エポキシ樹脂系材料からなることを特徴とする。   In the semiconductor device according to the present invention as set forth in the invention described above, the second sealing material is made of an epoxy resin material.

また、上述した課題を解決し、本発明の目的を達成するため、この発明にかかる半導体装置の製造方法は、半導体チップの裏面を第１基板に接合する第１接合工程と、前記第１基板の前記半導体チップ側の面に対向するように第２基板を配置し、前記第２基板に前記半導体チップのおもて面を接合する第２接合工程と、前記第１基板と前記第２基板との間に第１封止材を封入し、前記第１封止材によって前記半導体チップを封止する第１封止工程と、第２封止材によって前記第１基板、前記第２基板および前記第１封止材を封止してなる成形体を形成する第２封止工程と、第３封止材によって前記成形体を覆う第３封止工程と、を含み、前記第１封止材は、前記半導体チップの発熱に耐え得る耐熱性を有し、前記第２封止材は、前記第１封止材および前記第３封止材よりも耐熱性が低く、前記第３封止材は、耐酸化性を有することを特徴とする。   In order to solve the above-described problems and achieve the object of the present invention, a semiconductor device manufacturing method according to the present invention includes a first bonding step of bonding a back surface of a semiconductor chip to a first substrate, and the first substrate. A second bonding step of disposing a second substrate so as to face the surface of the semiconductor chip, bonding a front surface of the semiconductor chip to the second substrate, and the first substrate and the second substrate And a first sealing step of sealing the semiconductor chip with the first sealing material, and the first substrate, the second substrate, and the second sealing material. A second sealing step of forming a molded body formed by sealing the first sealing material; and a third sealing step of covering the molded body with a third sealing material, wherein the first sealing The material has heat resistance that can withstand the heat generation of the semiconductor chip, and the second sealing material is the first sealing material. And the third low heat resistance than the sealing material, the third sealing member is characterized to have oxidation resistance.

また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記第３封止材は、ポリパラキシリレンからなることを特徴とする。   In the semiconductor device manufacturing method according to the present invention as set forth in the invention described above, the third sealing material is made of polyparaxylylene.

また、この発明にかかる半導体装置の製造方法は、上述した発明において、前記第１封止工程では、前記第１基板の前記半導体チップ側に対して反対側の面が露出されるように前記成形体を形成し、前記第３封止工程では、前記第１基板の前記半導体チップ側に対して反対側の面以外の前記成形体の表面を前記第３封止材によって覆うことを特徴とする。   In the semiconductor device manufacturing method according to the present invention, in the above-described invention, in the first sealing step, the molding is performed so that a surface opposite to the semiconductor chip side of the first substrate is exposed. Forming a body, and in the third sealing step, the surface of the molded body other than the surface opposite to the semiconductor chip side of the first substrate is covered with the third sealing material. .

上述した発明によれば、半導体チップの発熱に耐え得る耐熱性を有する第１封止材で半導体チップを封止して動作時に最も温度上昇が大きい半導体チップ付近の耐熱性能を確保しつつ、第１封止材の外周を第１封止材よりも安価な第２封止材で封止することにより、Ｓｉ半導体素子よりも電流密度の高いＳｉＣ半導体素子を搭載した場合でも高耐熱性能で安価な半導体装置を提供することができる。また、上述した発明によれば、第２封止材によって第１基板、第２基板および第１封止材を封止してなる成形体の表面を第３封止材で覆うことで、第２封止材が空気に接触しない。このため、第２封止材が酸化して劣化することを防止することができる。   According to the above-described invention, the semiconductor chip is sealed with the first sealing material having heat resistance that can withstand the heat generation of the semiconductor chip, and the heat resistance performance in the vicinity of the semiconductor chip having the largest temperature increase during operation is secured. By sealing the outer periphery of one sealing material with a second sealing material that is cheaper than the first sealing material, even when a SiC semiconductor element having a higher current density than the Si semiconductor element is mounted, the heat resistance performance is inexpensive. A semiconductor device can be provided. Further, according to the above-described invention, the surface of the molded body formed by sealing the first substrate, the second substrate, and the first sealing material with the second sealing material is covered with the third sealing material. 2 Sealing material does not contact air. For this reason, it can prevent that a 2nd sealing material oxidizes and deteriorates.

また、上述した発明によれば、第１封止材および第２封止材の第１基板に対する接着強さを１０ＭＰａ〜３０ＭＰａ程度にすることにより、半導体チップの第１基板に対する接合強度、および第２封止材の第１基板や第１封止材に対する接合強度を向上させることができる。また、第１封止材の熱膨張係数を１０×１０-6／℃〜１８×１０-6／℃程度とすることにより、第１封止材と第１基板との熱膨張係数差を小さくすることができ、半導体装置にかかる熱応力を低減することができる。また、第２封止材の熱膨張係数を１０×１０-6／℃〜１８×１０-6／℃程度とすることにより、第１封止材と第２封止材との熱膨張係数差を小さくすることができ、半導体装置にかかる熱応力を低減することができる。これらの効果により、半導体装置全体の強度を向上させることができる。 In addition, according to the above-described invention, the bonding strength of the semiconductor chip to the first substrate, and the first sealing material and the second sealing material are bonded to the first substrate by about 10 MPa to 30 MPa. The bonding strength of the two sealing materials to the first substrate and the first sealing material can be improved. Further, by setting the thermal expansion coefficient of the first sealing material to about 10 × 10 −6 / ° C. to 18 × 10 −6 / ° C., the difference in thermal expansion coefficient between the first sealing material and the first substrate is reduced. The thermal stress applied to the semiconductor device can be reduced. Moreover, the thermal expansion coefficient difference of a 1st sealing material and a 2nd sealing material is made into the thermal expansion coefficient of a 2nd sealing material by about 10 * 10 < -6 > / degreeC-18 * 10 < -6 > / degreeC. The thermal stress applied to the semiconductor device can be reduced. With these effects, the strength of the entire semiconductor device can be improved.

また、上述した発明によれば、第１封止材によって半導体チップを封止した後に、一次硬化後の第１封止材を液状の第２封止材を用いて封止することにより、第１封止材の外周に容易に第２封止材を充填することができ、かつ第１封止材との高い接着性を保持した第２封止材によって半導体装置を短時間で成形することができる。   Further, according to the above-described invention, after the semiconductor chip is sealed with the first sealing material, the first sealing material after the primary curing is sealed with the liquid second sealing material. Forming the semiconductor device in a short time with the second sealing material that can be easily filled with the second sealing material on the outer periphery of the first sealing material and that maintains high adhesion to the first sealing material. Can do.

本発明にかかる半導体装置および半導体装置の製造方法によれば、信頼性が高くかつ安価な半導体装置を提供することができるという効果を奏する。   According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to provide a highly reliable and inexpensive semiconductor device.

実施の形態にかかる半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造途中の状態を示す断面図である。It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造途中の状態を示す断面図である。It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造途中の状態を示す断面図である。It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造途中の状態を示す断面図である。It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. 実施の形態にかかる半導体装置の製造途中の状態を示す断面図である。It is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning embodiment. 従来のＳｉ半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the conventional Si semiconductor device.

以下に添付図面を参照して、この発明にかかる半導体装置および半導体装置の製造方法の好適な実施の形態を詳細に説明する。なお、以下の実施の形態の説明および添付図面において、同様の構成には同一の符号を付し、重複する説明を省略する。   Exemplary embodiments of a semiconductor device and a method for manufacturing the semiconductor device according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

（実施の形態）
実施の形態にかかる半導体装置の構成について、炭化珪素（ＳｉＣ）からなるＳｉＣ半導体素子を備えたＳｉＣ半導体装置を例に説明する。図１は、実施の形態にかかる半導体装置の構成を示す断面図である。図１に示すように、ＳｉＣ半導体装置１０は、絶縁基板（第１基板）１、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）やＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）などのＳｉＣ半導体素子を有する半導体チップ６、インプラントピン８などの導電性ポストを有するインプラント方式のプリント基板（第２基板）９、および外部電極用端子１１，１２を備える。絶縁基板１は、絶縁層２の両面にそれぞれ例えば略直方体状の第１，２銅ブロック３，４が接合されてなる。 (Embodiment)
The configuration of the semiconductor device according to the embodiment will be described by taking a SiC semiconductor device including a SiC semiconductor element made of silicon carbide (SiC) as an example. FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device according to an embodiment. As shown in FIG. 1, an SiC semiconductor device 10 includes an insulating substrate (first substrate) 1, a semiconductor chip 6 having SiC semiconductor elements such as an IGBT (insulated gate bipolar transistor) and a MOSFET (insulated gate field effect transistor). And an implant-type printed circuit board (second substrate) 9 having conductive posts such as implant pins 8 and external electrode terminals 11 and 12. The insulating substrate 1 is formed by bonding, for example, approximately rectangular parallelepiped first and second copper blocks 3 and 4 to both surfaces of the insulating layer 2.

半導体チップ６の裏面は、導電性材料からなる接合層（導電接合層）５を介して絶縁基板１のおもて面側の第１銅ブロック３に接合されている。半導体チップ６は、例えば１つの絶縁基板１上に複数配置されていてもよい。また、このように１つ以上の半導体チップ６が接合された絶縁基板１がＳｉＣ半導体装置１０内に複数配置されていてもよい。半導体チップ６のおもて面側には、図示省略する外部回路と接続用のプリント基板９が配置されている。プリント基板９は、表面に回路パターン（不図示、図３〜６についても同様）が形成された絶縁基板である。プリント基板９の半導体チップ６側の面にはインプラントピン８が配置されている。インプラントピン８は、プリント基板９の回路パターンに接続されている。半導体チップ６のおもて面電極（不図示、図２〜６においても同様）は、導電接合層７を介してインプラントピン８に接合されている。   The back surface of the semiconductor chip 6 is bonded to the first copper block 3 on the front surface side of the insulating substrate 1 via a bonding layer (conductive bonding layer) 5 made of a conductive material. For example, a plurality of semiconductor chips 6 may be arranged on one insulating substrate 1. In addition, a plurality of insulating substrates 1 to which one or more semiconductor chips 6 are bonded in this way may be arranged in the SiC semiconductor device 10. An external circuit (not shown) and a printed circuit board 9 for connection are disposed on the front surface side of the semiconductor chip 6. The printed circuit board 9 is an insulating substrate having a circuit pattern (not shown; the same applies to FIGS. 3 to 6) formed on the surface. Implant pins 8 are arranged on the surface of the printed circuit board 9 on the semiconductor chip 6 side. The implant pin 8 is connected to the circuit pattern of the printed circuit board 9. A front surface electrode (not shown, the same applies to FIGS. 2 to 6) of the semiconductor chip 6 is bonded to the implant pin 8 via the conductive bonding layer 7.

外部電極用端子１１は、導電接合層を介して絶縁基板１のおもて面側の第１銅ブロック３に接合されており、第１銅ブロック３を介して半導体チップ６の裏面電極（不図示、図２〜６においても同様）に電気的に接続されている。外部電極用端子１１は、プリント基板９に形成された貫通孔を貫通して、プリント基板９の半導体チップ６側に対して反対側に突出している。外部電極用端子１２は、導電接合層を介してプリント基板９の半導体チップ６側に対して反対側の面に接合される。外部電極用端子１２は、プリント基板９の回路パターンに接続されており、この回路パターンおよびインプラントピン８を介して半導体チップ６のおもて面電極に電気的に接続されている。絶縁基板１とプリント基板９との間には第１封止材２１が封入されており、第１封止材２１によって半導体チップ６、インプラントピン８、および外部電極用端子１１の第１銅ブロック３との接合端部が封止されている。   The external electrode terminal 11 is bonded to the first copper block 3 on the front surface side of the insulating substrate 1 through a conductive bonding layer, and the back electrode (non-conductive) of the semiconductor chip 6 is connected through the first copper block 3. It is electrically connected in the same way as shown in FIGS. The external electrode terminal 11 passes through a through hole formed in the printed circuit board 9 and protrudes to the opposite side of the printed circuit board 9 with respect to the semiconductor chip 6 side. The external electrode terminal 12 is bonded to the surface opposite to the semiconductor chip 6 side of the printed circuit board 9 through the conductive bonding layer. The external electrode terminal 12 is connected to the circuit pattern of the printed circuit board 9, and is electrically connected to the front surface electrode of the semiconductor chip 6 through this circuit pattern and the implant pin 8. A first sealing material 21 is enclosed between the insulating substrate 1 and the printed circuit board 9, and the first copper block of the semiconductor chip 6, the implant pin 8, and the external electrode terminal 11 is sealed by the first sealing material 21. 3 is sealed at the joint end.

絶縁基板１のおもて面側全体は第２封止材２２によって封止され、第２封止材２２によって第１封止材２１、絶縁基板１、プリント基板９、および外部電極用端子１２のプリント基板９との接合端部が封止されてなる成形体が形成されている。絶縁基板１の裏面側の第２銅ブロック４の表面４ａは、第２封止材２２によって覆われておらず露出されている。第２封止材２２の外周、すなわち第２封止材２２によって封止されてなる成形体の、第２銅ブロック４の表面４ａを除く表面は、第３封止材２３で覆われている。図１では図示を省略するが、第２封止材２２の、絶縁基板１の裏面側の当該裏面（第２銅ブロック４の表面）に平行な部分も第３封止材２３によって覆われている。第２封止材２２は、第３封止材２３によって覆われることで空気に接触しない構成となっている。このように、ＳｉＣ半導体装置１０は、第１〜３封止材２１〜２３による３層構造の封止材によって封止されてなる。第１〜３封止材２１〜２３について詳細な説明は後述する。   The entire front surface side of the insulating substrate 1 is sealed by the second sealing material 22, and the first sealing material 21, the insulating substrate 1, the printed circuit board 9, and the external electrode terminals 12 are sealed by the second sealing material 22. The molded body formed by sealing the joint end with the printed circuit board 9 is formed. The surface 4 a of the second copper block 4 on the back surface side of the insulating substrate 1 is not covered with the second sealing material 22 and is exposed. The outer surface of the second sealing material 22, that is, the surface excluding the surface 4 a of the second copper block 4 of the molded body sealed by the second sealing material 22 is covered with the third sealing material 23. . Although not shown in FIG. 1, a portion of the second sealing material 22 parallel to the back surface (the surface of the second copper block 4) on the back surface side of the insulating substrate 1 is also covered with the third sealing material 23. Yes. The second sealing material 22 is covered with the third sealing material 23 so as not to come into contact with air. As described above, the SiC semiconductor device 10 is sealed with the three-layer structure sealing material including the first to third sealing materials 21 to 23. Detailed description of the first to third sealing materials 21 to 23 will be described later.

第２封止材２２の内部には、後述する冷却器（不図示）にＳｉＣ半導体装置１０を固定するためのボルト（不図示）の挿入孔である取付け金具２４が埋め込まれている。取付け金具２４の開口部は第３封止材２３によって覆われていない。取付け金具２４の、絶縁基板１おもて面側の開口部から挿入されるボルトによってＳｉＣ半導体装置１０が冷却器に固定される。取付け金具２４の配置は、絶縁基板１やプリント基板９の配置によって種々変更可能である。図１では、例えば第２封止材２２の外周部付近に配置され、絶縁基板１の主面に垂直な方向に第２封止材２２を貫通する取付け金具２４を図示している。   Inside the second sealing material 22, a mounting bracket 24 that is an insertion hole for a bolt (not shown) for fixing the SiC semiconductor device 10 to a cooler (not shown) to be described later is embedded. The opening of the mounting bracket 24 is not covered with the third sealing material 23. SiC semiconductor device 10 is fixed to the cooler by a bolt inserted from the opening on the front surface side of insulating substrate 1 of mounting bracket 24. The arrangement of the mounting bracket 24 can be variously changed depending on the arrangement of the insulating substrate 1 and the printed board 9. In FIG. 1, for example, a mounting bracket 24 that is disposed near the outer periphery of the second sealing material 22 and penetrates the second sealing material 22 in a direction perpendicular to the main surface of the insulating substrate 1 is illustrated.

外部電極用端子１１の第１銅ブロック３との接合端部に対して反対側の端部１１ａ、および外部電極用端子１２のプリント基板９との接合端部に対して反対側の端部１２ａは、第２，３封止材２２，２３に覆われておらず、外部に露出している。具体的には、外部電極用端子１１は、第１銅ブロック３との接合端部に対して反対側の端部１１ａが第１〜３封止材２１〜２３の外部に露出されており、半導体チップ６の裏面電極を外部へ引き出している。外部電極用端子１２は、プリント基板９との接合端部に対して反対側の端部１２ａが第２，３封止材２２，２３の外部に露出されており、半導体チップ６のおもて面電極を外部へ引き出している。   An end 11a opposite to the joint end of the external electrode terminal 11 with the first copper block 3 and an end 12a opposite to the joint end of the external electrode terminal 12 with the printed circuit board 9. Is not covered with the second and third sealing materials 22 and 23 and is exposed to the outside. Specifically, the external electrode terminal 11 is exposed to the outside of the first to third sealing materials 21 to 23 at the end 11a opposite to the joint end with the first copper block 3. The back electrode of the semiconductor chip 6 is drawn out to the outside. The external electrode terminal 12 is exposed to the outside of the second and third sealing materials 22, 23 at the end 12 a opposite to the joint end with the printed circuit board 9. The surface electrode is pulled out.

絶縁基板１の裏面側の第２銅ブロック４は、熱伝導ペーストを介して冷却器（不図示）に接合されている。冷却器は、冷却ベース部と、放熱フィン部とを有する。冷却ベース部には、熱伝導ペーストを介して絶縁基板１の裏面側の第２銅ブロック４が接合される。冷却ベース部は、半導体チップ６やプリント基板９の回路パターン（不図示）で発生し、絶縁基板１から熱伝導ペーストを介して伝わる熱を放熱フィン部へ伝導する。放熱フィン部は、複数の放熱フィンを有し、冷却ベース部から伝導された熱を放散する。   The second copper block 4 on the back side of the insulating substrate 1 is joined to a cooler (not shown) via a heat conductive paste. The cooler has a cooling base portion and a heat radiating fin portion. The second copper block 4 on the back surface side of the insulating substrate 1 is joined to the cooling base portion via a heat conductive paste. The cooling base portion is generated in a circuit pattern (not shown) of the semiconductor chip 6 or the printed board 9 and conducts heat transferred from the insulating substrate 1 through the heat conductive paste to the heat radiating fin portion. The heat radiating fin portion has a plurality of heat radiating fins, and dissipates heat conducted from the cooling base portion.

次に、第１〜３封止材２１〜２３について詳細に説明する。第１封止材２１は、半導体チップ６の発熱に耐え得る耐熱性を有し、半導体チップ６付近の高い耐熱性を実現する機能を有する。具体的には、第１封止材２１は、例えばエポキシ樹脂系封止材である。より具体的には、第１封止材２１は、例えば、環状脂肪族系エポキシ樹脂と酸無水物硬化剤との混合組成物であり、シリカ充填材を８０ｗｔ％の割合で含む耐熱封止材であってもよい。硬化後の第１封止材２１は、例えば、熱変形温度が２００℃以上であり、熱膨張係数が１０×１０-6／℃〜１８×１０-6／℃程度であり、絶縁基板１に対する接着強さが１０ＭＰａ〜３０ＭＰａ程度の材料物性を有する。 Next, the first to third sealing materials 21 to 23 will be described in detail. The first sealing material 21 has heat resistance that can withstand the heat generation of the semiconductor chip 6, and has a function of realizing high heat resistance near the semiconductor chip 6. Specifically, the first sealing material 21 is, for example, an epoxy resin sealing material. More specifically, the first sealing material 21 is, for example, a mixed composition of a cyclic aliphatic epoxy resin and an acid anhydride curing agent, and includes a heat-resistant sealing material containing a silica filler at a ratio of 80 wt%. It may be. The first sealing material 21 after curing has, for example, a thermal deformation temperature of 200 ° C. or higher, a thermal expansion coefficient of about 10 × 10 −6 / ° C. to 18 × 10 −6 / ° C. Adhesive strength has material properties of about 10 MPa to 30 MPa.

第２封止材２２は、第１封止材２１よりも成形しやすい成形封止材料を用いるのが好ましい。その理由は、第１封止材２１よりも広範囲の領域を第２封止材２２によって封止するからである。第２封止材２２は、第１封止材２１や後述する第３封止材２３よりも安価で耐熱性が低くてもよい。その理由は、第２封止材２２が第１封止材２１よりも半導体チップ６の発熱による悪影響を受けにくいからである。具体的には、第２封止材２２として、例えば液状のエポキシ樹脂系封止材を用いる。より具体的には、第２封止材２２は、例えば、環状脂肪族系エポキシ樹脂と酸無水物硬化剤との混合組成物であり、シリカ充填材を８５ｗｔ％の割合で含む液状の成形封止材であってもよい。   For the second sealing material 22, it is preferable to use a molding sealing material that is easier to mold than the first sealing material 21. The reason is that a wider area than the first sealing material 21 is sealed by the second sealing material 22. The second sealing material 22 may be cheaper and lower in heat resistance than the first sealing material 21 and the third sealing material 23 described later. The reason is that the second sealing material 22 is less likely to be adversely affected by the heat generation of the semiconductor chip 6 than the first sealing material 21. Specifically, for example, a liquid epoxy resin-based sealing material is used as the second sealing material 22. More specifically, the second sealing material 22 is, for example, a mixed composition of a cycloaliphatic epoxy resin and an acid anhydride curing agent, and is a liquid molded seal containing a silica filler at a ratio of 85 wt%. It may be a stop material.

硬化後の第２封止材２２は、例えば、熱変形温度が１００℃〜２００℃程度であり、熱膨張係数が１０×１０-6／℃〜１８×１０-6／℃程度であり、絶縁基板１に対する接着強さが１０ＭＰａ〜３０ＭＰａ程度の材料物性を有する。硬化後の第２封止材２２の熱膨張係数は、硬化後の第１封止材２１の熱膨張係数と等しいのがよい。その理由は、第１封止材２１と第２封止材２２との接着強度を高くすることで、ＳｉＣ半導体装置１０全体の補強効果を向上させることができるからである。第３封止材２３は、第２封止材２２の外周部の酸化劣化を防止する機能を有する。具体的には、第３封止材２３は、第２封止材２２の外周に例えばポリパラキシリレンが蒸着されてなる蒸着膜である。第３封止材２３は、例えば３００℃程度の耐熱性を有する。 The second sealing material 22 after curing has, for example, a thermal deformation temperature of about 100 ° C. to 200 ° C., a thermal expansion coefficient of about 10 × 10 −6 / ° C. to 18 × 10 −6 / ° C., and insulation. Adhesive strength to the substrate 1 has material properties of about 10 MPa to 30 MPa. The thermal expansion coefficient of the second sealing material 22 after curing is preferably equal to the thermal expansion coefficient of the first sealing material 21 after curing. The reason is that the reinforcing effect of the entire SiC semiconductor device 10 can be improved by increasing the adhesive strength between the first sealing material 21 and the second sealing material 22. The third sealing material 23 has a function of preventing oxidative deterioration of the outer peripheral portion of the second sealing material 22. Specifically, the third sealing material 23 is a deposited film in which, for example, polyparaxylylene is deposited on the outer periphery of the second sealing material 22. The third sealing material 23 has a heat resistance of about 300 ° C., for example.

次に、実施の形態にかかる半導体装置の製造方法について説明する。図２〜６は、実施の形態にかかる半導体装置の製造途中の状態を示す断面図である。まず、図２に示すように、絶縁層２の両面にそれぞれ第１，２銅ブロック３，４を接合して絶縁基板１を形成する。このとき、絶縁層２に第１，２銅ブロック３，４を順に接合してもよいし、第２銅ブロック４、絶縁層２および銅ブロックを順に積層した後にこれらを一括して接合してもよい。   Next, a method for manufacturing the semiconductor device according to the embodiment will be described. 2-6 is sectional drawing which shows the state in the middle of manufacture of the semiconductor device concerning Embodiment. First, as shown in FIG. 2, first and second copper blocks 3 and 4 are bonded to both surfaces of the insulating layer 2 to form an insulating substrate 1. At this time, the first and second copper blocks 3 and 4 may be joined to the insulating layer 2 in order, or after the second copper block 4, the insulating layer 2 and the copper block are sequentially laminated, these are joined together. Also good.

次に、絶縁基板１のおもて面側の第１銅ブロック３上に、導電接合層５によって半導体チップ６の裏面を接合する。半導体チップ６の個数は、設計条件に合わせて種々変更可能である。さらに、絶縁基板１のおもて面側の第１銅ブロック３上の所定の位置に導電接合層を介して外部電極用端子１１を接合する。半導体チップ６および外部電極用端子１１の絶縁基板１のおもて面側の第１銅ブロック３上への接合は、それぞれ行ってもよいし、同時に行ってもよい。このように１つ以上の半導体チップ６が配置された１つ以上の絶縁基板１を用意する。   Next, the back surface of the semiconductor chip 6 is bonded to the first copper block 3 on the front surface side of the insulating substrate 1 by the conductive bonding layer 5. The number of semiconductor chips 6 can be variously changed according to design conditions. Further, the external electrode terminal 11 is bonded to a predetermined position on the first copper block 3 on the front surface side of the insulating substrate 1 through a conductive bonding layer. The semiconductor chip 6 and the external electrode terminal 11 may be joined to the first copper block 3 on the front surface side of the insulating substrate 1 or simultaneously. Thus, one or more insulating substrates 1 on which one or more semiconductor chips 6 are arranged are prepared.

次に、図３に示すように、プリント基板９の回路パターンに複数のインプラントピン８を接合し、一方の面にインプラントピン８が配置されたプリント基板９を用意する。次に、半導体チップ６のおもて面側に接合材７ａを塗布したのち、インプラントピン８側を下にして、プリント基板９の貫通孔に外部電極用端子１１を通してプリント基板９を配置する。そして、図４に示すように、加熱等により接合材７ａを硬化させて導電接合層７を形成し、半導体チップ６のおもて面電極とインプラントピン８とを接合する。これにより、すべての半導体チップ６に対向するようにプリント基板９が配置される。なお、プリント基板９の半導体チップ６側に対して反対側の面の所定の位置に外部電極用端子１２をあとから接合してもよいし、予め外部電極用端子１２を実装済みのプリント基板９を用いてもよい。   Next, as shown in FIG. 3, a plurality of implant pins 8 are joined to the circuit pattern of the printed circuit board 9, and a printed circuit board 9 in which the implant pins 8 are arranged on one surface is prepared. Next, after applying the bonding material 7 a to the front surface side of the semiconductor chip 6, the printed circuit board 9 is disposed through the external electrode terminal 11 in the through hole of the printed circuit board 9 with the implant pin 8 side down. Then, as shown in FIG. 4, the bonding material 7 a is cured by heating or the like to form the conductive bonding layer 7, and the front electrode of the semiconductor chip 6 and the implant pin 8 are bonded. Thereby, the printed circuit board 9 is disposed so as to face all the semiconductor chips 6. The external electrode terminal 12 may be joined later to a predetermined position on the surface opposite to the semiconductor chip 6 side of the printed circuit board 9, or the printed circuit board 9 on which the external electrode terminal 12 has been mounted in advance. May be used.

次に、図５に示すように、ディスペンサー（不図示）によって絶縁基板１とプリント基板９との間に第１封止材２１を注入し、第１封止材２１によってすべての半導体チップ６およびインプラントピン８を覆う。次に、例えば１２０℃の温度で１時間の熱処理により第１封止材２１を一次硬化する。これにより、すべての半導体チップ６およびインプラントピン８が第１封止材２１によって封止される。その後、第１封止材２１は、第２封止材２２が成型された後に、２次硬化条件として例えば２００℃の温度で２時間熱処理される。第１封止材２１として上述した環状脂肪族系エポキシ樹脂と酸無水物硬化剤との混合組成物（シリカ充填材を８０ｗｔ％の割合で含む）を用いた場合、硬化後の第１封止材２１は、例えば、熱変形温度が２２５℃程度で、熱膨張係数が１８×１０-6／℃程度で、絶縁基板１に対する接着強さが２３ＭＰａ程度となる。 Next, as shown in FIG. 5, a first sealing material 21 is injected between the insulating substrate 1 and the printed circuit board 9 by a dispenser (not shown), and all the semiconductor chips 6 and the first sealing material 21 are injected by the first sealing material 21. The implant pin 8 is covered. Next, the first sealing material 21 is primarily cured by a heat treatment for 1 hour at a temperature of 120 ° C., for example. Thereby, all the semiconductor chips 6 and the implant pins 8 are sealed by the first sealing material 21. Then, after the 2nd sealing material 22 is shape | molded, the 1st sealing material 21 is heat-processed for 2 hours at the temperature of 200 degreeC as secondary curing conditions, for example. When the above-described mixed composition of the cycloaliphatic epoxy resin and the acid anhydride curing agent (including silica filler at a ratio of 80 wt%) is used as the first sealing material 21, the first sealing after curing is performed. For example, the material 21 has a thermal deformation temperature of about 225 ° C., a thermal expansion coefficient of about 18 × 10 −6 / ° C., and an adhesive strength to the insulating substrate 1 of about 23 MPa.

次に、図６に示すように、例えばトランスファー成形法を用いて、第１封止材２１の外周を第２封止材２２によって封止する。このとき、外部電極用端子１１の第１銅ブロック３との接合端部に対して反対側の端部１１ａ、外部電極用端子１２のプリント基板９との接合端部に対して反対側の端部１２ａ、および絶縁基板１の裏面側の第２銅ブロック４の表面４ａが露出するように樹脂封止を行う。具体的には、トランスファー成形用の上下金型（不図示）によって所定形状の空間を形成するキャビティー内に、絶縁基板１、第１封止材２１に封止された半導体チップ６およびプリント基板９が接合されてなる部材を載置する。そして、キャビティー内の温度を所定の成形温度（例えば１６０℃程度）に上昇させた状態で保温する。   Next, as shown in FIG. 6, the outer periphery of the first sealing material 21 is sealed with the second sealing material 22 using, for example, a transfer molding method. At this time, the end 11a opposite to the joint end of the external electrode terminal 11 with the first copper block 3 and the end opposite to the joint end of the external electrode terminal 12 to the printed circuit board 9 Resin sealing is performed such that the portion 12a and the surface 4a of the second copper block 4 on the back side of the insulating substrate 1 are exposed. Specifically, the insulating substrate 1, the semiconductor chip 6 sealed with the first sealing material 21, and the printed circuit board are formed in a cavity that forms a predetermined shape space by upper and lower molds (not shown) for transfer molding. A member formed by joining 9 is placed. Then, the temperature in the cavity is kept at a predetermined molding temperature (for example, about 160 ° C.).

トランスファー成形用の上下金型には、第２封止材２２が収納されるポット部と、ポット部の第２封止材２２をキャビティーに注入する際の第２封止材２２の流動経路となるランナー部とが設けられている。第２封止材２２には液状の成形封止材料を用い、第２封止材２２は例えば予め０．１Ｔｏｒｒ程度の真空内での１０分間の１次脱泡を行った後にシリンダー容器（不図示）に注入される。シリンダー容器内の第２封止材２２が、上下金型のポット部に所定量注入される。キャビティーには、上下金型の型締めにより例えば１５０ｋｇ／ｃｍ2の圧力がかけられる。この状態で、ランナー部を介してポット部の第２封止材２２をキャビティー内に注入し、加熱しながら圧力をかけることで第２封止材２２を硬化させる。 In the upper and lower molds for transfer molding, a pot portion in which the second sealing material 22 is stored, and a flow path of the second sealing material 22 when the second sealing material 22 of the pot portion is injected into the cavity. And a runner part. A liquid molding sealing material is used for the second sealing material 22, and the second sealing material 22 is subjected to, for example, primary defoaming for 10 minutes in a vacuum of about 0.1 Torr in advance, and then a cylinder container (not used). Injected). A predetermined amount of the second sealing material 22 in the cylinder container is injected into the pot portions of the upper and lower molds. For example, a pressure of 150 kg / cm 2 is applied to the cavity by clamping the upper and lower molds. In this state, the second sealing material 22 of the pot part is injected into the cavity through the runner part, and the second sealing material 22 is cured by applying pressure while heating.

例えば、第２封止材２２として上述した環状脂肪族系エポキシ樹脂と酸無水物硬化剤との混合組成物（シリカ充填材を８５ｗｔ％の割合で含む）を用い、１６０℃の温度で加熱しながら第２封止材２２に１５０ｋｇ／ｃｍ2の圧力をかけた場合、第２封止材２２は１分間でゲル化し、３分間で一次硬化する。その後、第２封止材２２は、２次硬化条件として例えば２００℃の温度で２時間熱処理される。硬化後の第２封止材２２は、例えば、熱変形温度が１７５℃程度で、熱膨張係数が１６×１０-6／℃程度で、絶縁基板１に対する接着強さが２５ＭＰａ程度となる。また、例えば、上下金型による第２封止材２２の成形時に取付け金具２４を挿入するための孔を第２封止材２２に形成し、第２封止材２２の硬化後に当該孔に取付け金具２４を挿入することで、第２封止材２２の内部に取付け金具２４が配置される。 For example, the above-described mixed composition of the cycloaliphatic epoxy resin and the acid anhydride curing agent (including silica filler at a ratio of 85 wt%) is used as the second sealing material 22 and heated at a temperature of 160 ° C. However, when a pressure of 150 kg / cm 2 is applied to the second sealing material 22, the second sealing material 22 gels in 1 minute and is primarily cured in 3 minutes. Thereafter, the second sealing material 22 is heat-treated at a temperature of, for example, 200 ° C. for 2 hours as a secondary curing condition. The cured second sealing material 22 has, for example, a thermal deformation temperature of about 175 ° C., a thermal expansion coefficient of about 16 × 10 −6 / ° C., and an adhesive strength to the insulating substrate 1 of about 25 MPa. Further, for example, a hole for inserting the mounting bracket 24 is formed in the second sealing material 22 when the second sealing material 22 is molded by the upper and lower molds, and the hole is attached to the hole after the second sealing material 22 is cured. By inserting the metal fitting 24, the attachment metal fitting 24 is arranged inside the second sealing material 22.

次に、例えばパラキシリレン気相蒸着装置（不図示）を用いて、第２封止材２２によって封止されてなる成形体（第２封止材２２によって絶縁基板１、プリント基板９および第１封止材２１を封止してなる成形体、以下単に成形体とする）の表面を覆う第３封止材２３を形成する。具体的には、パラキシリレン気相蒸着装置は、気化槽、分解槽および蒸着槽の３槽が連結されてなる。まず、室温（例えば２５℃程度）で０．１Ｔｏｒｒ程度に減圧された蒸着槽に成形体を挿入する。次に、気化槽に固体状のジパラキシリレンを投入し、例えば１Ｔｏｒｒ程度の減圧雰囲気において１５０℃の温度で加熱して気化させる。   Next, using a paraxylylene vapor deposition apparatus (not shown), for example, a molded body sealed with the second sealing material 22 (the insulating substrate 1, the printed circuit board 9 and the first sealing material by the second sealing material 22). A third sealing material 23 that covers the surface of a molded body formed by sealing the stopper 21 (hereinafter simply referred to as a molded body) is formed. Specifically, the paraxylylene vapor deposition apparatus is formed by connecting three tanks, a vaporization tank, a decomposition tank, and a vapor deposition tank. First, the formed body is inserted into a vapor deposition tank that is decompressed to about 0.1 Torr at room temperature (for example, about 25 ° C.). Next, solid diparaxylylene is charged into the vaporization tank and vaporized by heating at a temperature of 150 ° C. in a reduced-pressure atmosphere of about 1 Torr, for example.

次に、気化させたジパラキシリレンを分解槽に導入し、例えば０．５Ｔｏｒｒ程度の減圧雰囲気において１５０℃〜６８０℃程度の温度で熱分解してポリパラキシリレンのモノマーガスを生成する。次に、減圧雰囲気（例えば０．５Ｔｏｒｒ程度）で室温の蒸着槽に導入したモノマーガスを成形体の表面に接触させて反応重合させることで、成形体の表面にポリパラキシリレンを蒸着する。これよって、ポリパラキシリレン膜からなる第３封止材２３が形成される。ポリパラキシリレン膜の膜厚は蒸着時間によって制御し、例えば数μｍ〜数１０μｍ程度にする。また、成形体表面のポリパラキシリレンを蒸着しない部分には、成形体を蒸着槽に収納する前にマスキングテープ（不図示）を貼り付ければよい。   Next, the vaporized diparaxylylene is introduced into a decomposition tank and thermally decomposed at a temperature of about 150 ° C. to 680 ° C. in a reduced pressure atmosphere of about 0.5 Torr, for example, to generate a polyparaxylylene monomer gas. Next, polyparaxylylene is vapor-deposited on the surface of the molded body by reacting the monomer gas introduced into the vapor deposition tank at room temperature in a reduced pressure atmosphere (for example, about 0.5 Torr) by contacting the surface of the molded body. Thus, the third sealing material 23 made of a polyparaxylylene film is formed. The film thickness of the polyparaxylylene film is controlled by the vapor deposition time, for example, about several μm to several tens of μm. Moreover, what is necessary is just to affix a masking tape (not shown) to the part which does not vapor-deposit polyparaxylylene on the surface of a molded object, before accommodating a molded object in a vapor deposition tank.

ポリパラキシリレンを蒸着しない部分とは、外部電極用端子１１の第１銅ブロック３との接合端部に対して反対側の端部１１ａ、外部電極用端子１２のプリント基板９との接合端部に対して反対側の端部１２ａ、および絶縁基板１の裏面側の第２銅ブロック４の表面４ａである。外部電極用端子１１，１２の端部１１ａ，１２ａには、例えば外部電極用端子１１，１２の端部１１ａ，１２ａの径よりも若干広い内径を有するチューブ状のマスキングテープを被せればよい。このようにマスキングテープを用いることにより、ポリパラキシリレンの蒸着後にマスキングテープを剥離するだけで、ポリパラキシリレンを蒸着しない部分におけるポリパラキシリレン膜を容易に除去することができる。これによって、図１に示す半導体装置が完成する。   The portions where polyparaxylylene is not deposited are the end portion 11a opposite to the bonding end portion of the external electrode terminal 11 with the first copper block 3, and the bonding end of the external electrode terminal 12 with the printed circuit board 9. These are the end portion 12 a opposite to the portion and the surface 4 a of the second copper block 4 on the back surface side of the insulating substrate 1. The end portions 11a and 12a of the external electrode terminals 11 and 12 may be covered with, for example, a tubular masking tape having an inner diameter slightly larger than the diameter of the end portions 11a and 12a of the external electrode terminals 11 and 12. By using the masking tape in this way, the polyparaxylylene film in the portion where the polyparaxylylene is not deposited can be easily removed only by peeling the masking tape after the polyparaxylylene is deposited. Thereby, the semiconductor device shown in FIG. 1 is completed.

以上、説明したように、実施の形態によれば、２００℃以上の耐熱性を有する第１封止材で半導体チップを封止して動作時に最も温度上昇が大きい半導体チップ付近の耐熱性能を確保しつつ、第１封止材の外周を第１封止材よりも安価な第２封止材で封止することにより、Ｓｉ半導体素子よりも電流密度の高いＳｉＣ半導体素子を搭載した場合でも高耐熱性能で安価な半導体装置を提供することができる。また、実施の形態によれば、第２封止材によって絶縁基板、プリント基板および第１封止材を封止してなる成形体の表面を第３封止材で覆うことで、第２封止材が空気に接触しない。このため、第２封止材が酸化して劣化することを防止することができる。   As described above, according to the embodiment, the semiconductor chip is sealed with the first sealing material having a heat resistance of 200 ° C. or higher to ensure the heat resistance performance in the vicinity of the semiconductor chip where the temperature rise is greatest during operation. However, by sealing the outer periphery of the first sealing material with the second sealing material that is cheaper than the first sealing material, even when a SiC semiconductor element having a higher current density than the Si semiconductor element is mounted, An inexpensive semiconductor device with high heat resistance can be provided. Further, according to the embodiment, the second sealing material covers the surface of the molded body formed by sealing the insulating substrate, the printed circuit board, and the first sealing material with the third sealing material. Stop material does not come into contact with air. For this reason, it can prevent that a 2nd sealing material oxidizes and deteriorates.

また、実施の形態によれば、第１封止材の絶縁基板に対する接着強さを１０ＭＰａ〜３０ＭＰａ程度にすることにより、半導体チップの絶縁基板に対する接合強度を向上させることができ、半導体チップと絶縁基板とを強固に接着することができる。これにより、半導体装置全体の強度を向上させることができる。また、第２封止材の絶縁基板に対する接着強さを１０ＭＰａ〜３０ＭＰａ程度にすることで、第２封止材の絶縁基板や第１封止材に対する接合強度を向上させることができる。これにより、さらに半導体装置全体の強度を向上させることができる。   In addition, according to the embodiment, the bonding strength of the first sealing material to the insulating substrate can be increased to about 10 MPa to 30 MPa, so that the bonding strength of the semiconductor chip to the insulating substrate can be improved. The substrate can be firmly bonded. Thereby, the strength of the entire semiconductor device can be improved. Moreover, the bonding strength of the second sealing material to the insulating substrate and the first sealing material can be improved by setting the adhesive strength of the second sealing material to the insulating substrate to about 10 MPa to 30 MPa. Thereby, the strength of the entire semiconductor device can be further improved.

また、実施の形態によれば、第１封止材の熱膨張係数を１０×１０-6／℃〜１８×１０-6／℃程度とすることにより、第１封止材と絶縁基板との熱膨張係数差を小さくすることができ、半導体装置にかかる熱応力を低減することができる。また、第２封止材の熱膨張係数を１０×１０-6／℃〜１８×１０-6／℃程度とすることにより、第１封止材と第２封止材との熱膨張係数差を小さくすることができ、半導体装置にかかる熱応力を低減することができる。これらの効果により、半導体装置全体の強度を向上させることができる。このため、半導体チップのおもて面および裏面にそれぞれ接合される導電接合層の熱疲労による熱抵抗が増大することを防止し、信頼性の高い半導体装置を提供することができる。 In addition, according to the embodiment, by setting the thermal expansion coefficient of the first sealing material to about 10 × 10 −6 / ° C. to 18 × 10 −6 / ° C., the first sealing material and the insulating substrate The difference in thermal expansion coefficient can be reduced, and the thermal stress applied to the semiconductor device can be reduced. Moreover, the thermal expansion coefficient difference of a 1st sealing material and a 2nd sealing material is made into the thermal expansion coefficient of a 2nd sealing material by about 10 * 10 < -6 > / degreeC-18 * 10 < -6 > / degreeC. The thermal stress applied to the semiconductor device can be reduced. With these effects, the strength of the entire semiconductor device can be improved. For this reason, it is possible to prevent an increase in thermal resistance due to thermal fatigue of the conductive bonding layers bonded to the front surface and the back surface of the semiconductor chip, and to provide a highly reliable semiconductor device.

また、実施の形態によれば、第１封止材によって半導体チップを封止した後に、乾燥・硬化後の第１封止材を液状の第２封止材を用いて封止することにより、第１封止材の外周に容易に第２封止材を充填することができ、かつ第１封止材との高い接着性を保持した第２封止材によって半導体装置を短時間で成形することができる。これにより、製造コストを低減することができる。また、生産性および信頼性の高い半導体装置を提供することができる。   Moreover, according to the embodiment, after sealing the semiconductor chip with the first sealing material, the first sealing material after drying and curing is sealed with the liquid second sealing material, The semiconductor device can be formed in a short time with the second sealing material that can easily fill the outer periphery of the first sealing material with the second sealing material and retains high adhesion to the first sealing material. be able to. Thereby, manufacturing cost can be reduced. In addition, a highly productive and reliable semiconductor device can be provided.

以上において本発明は、上述した実施の形態に限らず、本発明の趣旨を逸脱しない範囲で種々変更可能である。例えば、上述した実施の形態では、ＳｉＣ半導体装置を例に説明しているが、本発明はＧａＮからなるＧａＮ半導体素子を備えたＧａＮ半導体装置や、ＳｉからなるＳｉ半導体素子を備えたＳｉ半導体装置に適用可能である。   As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above-described embodiment, the SiC semiconductor device is described as an example. However, the present invention is a GaN semiconductor device provided with a GaN semiconductor element made of GaN, or an Si semiconductor device provided with an Si semiconductor element made of Si. It is applicable to.

以上のように、本発明にかかる半導体装置および半導体装置の製造方法は、Ｓｉよりも電気的特性の優れたＳｉＣやＣａＮなどの半導体材料を用いて構成された高電流密度のパワー半導体装置に有用である。   As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a power semiconductor device having a high current density that is configured by using a semiconductor material such as SiC or CaN that has better electrical characteristics than Si. It is.

１ 絶縁基板
２ 絶縁層
３ 第１銅ブロック
４ 第２銅ブロック
４ａ 第２銅ブロックの表面
５，７ 導電接合層
６ 半導体チップ
８ インプラントピン
９ プリント基板
１０ ＳｉＣ半導体装置
１１，１２ 外部電極用端子
１１ａ 外部電極用端子の第１銅ブロックとの接合端部に対して反対側の端部
１２ａ 外部電極用端子のプリント基板との接合端部に対して反対側の端部
２１ 第１封止材
２２ 第２封止材
２３ 第３封止材
２４ 取付け金具 DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 2 Insulation layer 3 1st copper block 4 2nd copper block 4a Surface of 2nd copper block 5,7 Conductive joining layer 6 Semiconductor chip 8 Implant pin 9 Printed circuit board 10 SiC semiconductor device 11, 12 Terminal for external electrodes 11a The end 12a opposite to the joint end of the external electrode terminal with the first copper block 12a The end 21 opposite to the joint end of the external electrode terminal with the printed circuit board 21 First sealing material 22 Second sealing material 23 Third sealing material 24 Mounting bracket

Claims (15)

半導体チップの裏面に接合された第１基板と、
前記半導体チップのおもて面に接合された第２基板と、
前記第１基板と前記第２基板との間に封入され前記半導体チップを封止する第１封止材と、
第２封止材によって前記第１基板、前記第２基板および前記第１封止材を封止してなる成形体と、
前記成形体の表面を覆う第３封止材と、
を備え、
前記第１封止材は、前記半導体チップの発熱に耐え得る耐熱性を有し、
前記第２封止材は、前記第１封止材および前記第３封止材よりも耐熱性が低く、
前記第３封止材は、耐酸化性を有することを特徴とする半導体装置。 A first substrate bonded to the back surface of the semiconductor chip;
A second substrate bonded to the front surface of the semiconductor chip;
A first sealing material sealed between the first substrate and the second substrate and sealing the semiconductor chip;
A molded body formed by sealing the first substrate, the second substrate, and the first sealing material with a second sealing material;
A third sealing material covering the surface of the molded body;
With
The first sealing material has heat resistance that can withstand the heat generation of the semiconductor chip,
The second sealing material has lower heat resistance than the first sealing material and the third sealing material,
The semiconductor device, wherein the third sealing material has oxidation resistance. 前記第１基板の前記半導体チップ側に対して反対側の面は前記成形体の表面に露出されており、
前記第３封止材は、前記成形体の、前記第１基板の前記半導体チップ側に対して反対側の面以外の表面を覆うことを特徴とする請求項１に記載の半導体装置。 The surface of the first substrate opposite to the semiconductor chip side is exposed on the surface of the molded body,
The semiconductor device according to claim 1, wherein the third sealing material covers a surface of the molded body other than a surface opposite to the semiconductor chip side of the first substrate. 前記第３封止材は、ポリパラキシリレンからなることを特徴とする請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the third sealing material is made of polyparaxylylene. 前記半導体チップに電気的に接続される外部電極用端子をさらに備え、
前記外部電極用端子の外部接続される側の端部は露出されていることを特徴とする請求項１〜３のいずれか一つに記載の半導体装置。 Further comprising an external electrode terminal electrically connected to the semiconductor chip;
4. The semiconductor device according to claim 1, wherein an end portion of the external electrode terminal that is externally connected is exposed. 5. 前記第１封止材の熱変形温度は２００℃以上であることを特徴とする請求項１〜４のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the first sealing material has a heat deformation temperature of 200 ° C. or higher. 前記第１封止材の前記第１基板に対する接着強さは１０ＭＰａ以上３０ＭＰａ以下であることを特徴とする請求項１〜５のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein an adhesive strength of the first sealing material to the first substrate is 10 MPa or more and 30 MPa or less. 前記第１封止材の熱膨張係数は１０×１０-6／℃以上１８×１０-6／℃以下であることを特徴とする請求項１〜６のいずれか一つに記載の半導体装置。 The semiconductor device according to claim 1, wherein the first sealing material has a thermal expansion coefficient of 10 × 10 −6 / ° C. or more and 18 × 10 −6 / ° C. or less. 前記第１封止材は、エポキシ樹脂系材料からなることを特徴とする請求項１〜７のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the first sealing material is made of an epoxy resin material. 前記第２封止材の熱変形温度が１００℃以上２００℃以下であることを特徴とする請求項１〜８のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the second sealing material has a heat deformation temperature of 100 ° C. or more and 200 ° C. or less. 前記第２封止材の熱膨張係数が１０×１０-6／℃以上１８×１０-6／℃以下であることを特徴とする請求項１〜９のいずれか一つに記載の半導体装置。 10. The semiconductor device according to claim 1, wherein the second sealing material has a thermal expansion coefficient of 10 × 10 −6 / ° C. or more and 18 × 10 −6 / ° C. or less. 前記第２封止材の前記第１基板に対する接着強さは１０ＭＰａ以上３０ＭＰａ以下であることを特徴とする請求項１〜１０のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein an adhesive strength of the second sealing material to the first substrate is 10 MPa or more and 30 MPa or less. 前記第２封止材は、エポキシ樹脂系材料からなることを特徴とする請求項１〜１１のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the second sealing material is made of an epoxy resin material. 半導体チップの裏面を第１基板に接合する第１接合工程と、
前記第１基板の前記半導体チップ側の面に対向するように第２基板を配置し、前記第２基板に前記半導体チップのおもて面を接合する第２接合工程と、
前記第１基板と前記第２基板との間に第１封止材を封入し、前記第１封止材によって前記半導体チップを封止する第１封止工程と、
第２封止材によって前記第１基板、前記第２基板および前記第１封止材を封止してなる成形体を形成する第２封止工程と、
第３封止材によって前記成形体を覆う第３封止工程と、
を含み、
前記第１封止材は、前記半導体チップの発熱に耐え得る耐熱性を有し、
前記第２封止材は、前記第１封止材および前記第３封止材よりも耐熱性が低く、
前記第３封止材は、耐酸化性を有することを特徴とする半導体装置の製造方法。 A first bonding step of bonding the back surface of the semiconductor chip to the first substrate;
A second bonding step of disposing a second substrate so as to face a surface of the first substrate on the semiconductor chip side, and bonding a front surface of the semiconductor chip to the second substrate;
A first sealing step of sealing a first sealing material between the first substrate and the second substrate, and sealing the semiconductor chip with the first sealing material;
A second sealing step of forming a molded body formed by sealing the first substrate, the second substrate, and the first sealing material with a second sealing material;
A third sealing step of covering the molded body with a third sealing material;
Including
The first sealing material has heat resistance that can withstand the heat generation of the semiconductor chip,
The second sealing material has lower heat resistance than the first sealing material and the third sealing material,
The method for manufacturing a semiconductor device, wherein the third sealing material has oxidation resistance. 前記第３封止材は、ポリパラキシリレンからなることを特徴とする請求項１３に記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 13, wherein the third sealing material is made of polyparaxylylene. 前記第１封止工程では、前記第１基板の前記半導体チップ側に対して反対側の面が露出されるように前記成形体を形成し、
前記第３封止工程では、前記第１基板の前記半導体チップ側に対して反対側の面以外の前記成形体の表面を前記第３封止材によって覆うことを特徴とする請求項１３または１４に記載の半導体装置の製造方法。 In the first sealing step, the molded body is formed so that a surface opposite to the semiconductor chip side of the first substrate is exposed,
15. In the third sealing step, the surface of the molded body other than the surface opposite to the semiconductor chip side of the first substrate is covered with the third sealing material. The manufacturing method of the semiconductor device as described in 2.
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