JP2014146390A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform intermittent driving by power-on/off without causing a problem such as the garbling of data.SOLUTION: A semiconductor memory device 1 includes: a memory unit 10 that stores data in a nonvolatile manner; a power supply unit 20 that supplies power to the memory unit 10; and a control unit 30 that controls the memory unit 10 and power supply unit 20. The control unit 30 includes: a first instruction processing unit 31 that recognizes an access instruction and accesses the memory unit 10; and a second instruction processing unit 32 that recognizes each of a power-on instruction and a power-off instruction and permits/prohibits the power supply from the power supply unit 20 to the memory unit 10.

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  FIG. 7 is a block diagram showing a conventional example of a semiconductor memory device. The conventional semiconductor memory device 100 is equipped with a sleep mode in order to realize power saving during access standby. More specifically, the control unit 130 built in the semiconductor memory device 100 is equipped with a sleep mode transition processing unit 131, and when there is no access to the semiconductor memory device 100 for a predetermined time, When the microcomputer (not shown) is instructed to shift to the sleep mode, the semiconductor memory device 100 is in the sleep mode that consumes less power from the normal mode (power supply to other than the circuit blocks necessary for returning to the normal mode) Enters the shutdown state.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2009-99202 A

  However, in the semiconductor memory device 100 of the conventional example, the power supply voltage VCC remains turned on even in the sleep mode, and power supply to the circuit block necessary for returning to the normal mode has been continued. For this reason, even if the mode is shifted to the sleep mode, the semiconductor memory device 100 has a current consumption (generally on the order of μA).

  If the semiconductor memory device 100 itself is turned on / off as necessary, the current consumption when the power is turned off can be made completely zero. However, when such power on / off control is performed, there is a problem that the relationship between the power supply voltage VCC and the chip select signal CSB is restricted.

  FIG. 8 is a time chart for explaining the CSB timing constraint when the power is turned on / off. When the chip select signal CSB is at a low level, the semiconductor memory device 100 is in an input acceptance state (active state). If the power supply voltage VCC is raised in such a state, there is a risk of malfunction or erroneous writing due to the influence of noise or the like. In order to prevent these, it is necessary to keep the chip select signal CSB at a high level (logic level when no chip is selected) at the time of power on / off. When the chip select signal CSB is at a high level, the semiconductor memory device 100 cancels all inputs, so that no malfunction or writing due to noise or the like occurs. In FIG. 8, the solid line of the chip select signal CSB shows a good example, and the broken line shows a bad example.

  In order to frequently turn on / off the power of the semiconductor memory device 100 while observing the above restrictions, appropriate load adjustment is performed for each substrate of the set, or the rising of the power supply voltage VCC and the chip select signal CSB is performed. / A timing control circuit for establishing a falling sequence has to be provided, which causes a complicated set design and an increased cost.

  In view of the above-described problems found by the inventors of the present application, an object of the present invention is to provide a semiconductor memory device that can be intermittently driven by power on / off without causing problems such as data corruption. To do.

  In order to achieve the above object, a semiconductor memory device according to the present invention includes a memory unit that stores data in a nonvolatile manner, a power supply unit that supplies power to the memory unit, the memory unit, and the power supply unit. A control unit that controls, the control unit recognizes an access command and accesses the memory unit, and recognizes a power-on command and a power-off command, respectively, And a second command processing unit that permits / inhibits power supply from the unit to the memory unit (first configuration).

  The semiconductor memory device having the first configuration may have a configuration (second configuration) including a power-on reset unit that initializes the control unit when a power supply voltage is turned on.

  In the semiconductor memory device having the second configuration, the second instruction processing unit may be configured to start in a state in which power supply from the power supply unit to the memory unit is prohibited (third configuration). .

  Further, in the semiconductor memory device having the third configuration, the second instruction processing unit is configured to return a power supply state from the power supply unit to the memory unit in response to a status request (fourth configuration). Good.

  In the semiconductor memory device having any one of the first to fourth configurations, the control unit may have a configuration (fifth configuration) having a function of performing bidirectional serial communication with the outside of the device. .

  In the semiconductor memory device having any one of the first to fifth configurations, the memory unit includes a memory cell array in which a plurality of memory cells are arranged in an array, an X decoder and a Y decoder for driving the memory cell array, And a sense amplifier that reads data from the memory cell array (sixth configuration).

  In the semiconductor memory device having the sixth configuration, the memory cell array is an EEPROM (electrically erasable programmable read-only memory), a flash memory, or an FeRAM (ferroelectric random access memory) (seventh configuration). ).

  An electronic apparatus according to the present invention includes a semiconductor memory device having any one of the first to seventh configurations, a microcomputer that intermittently drives the semiconductor memory device by power on / off, and an instruction from the microcomputer The semiconductor memory device has a configuration (eighth configuration) having a switch for conducting / cutting off the power supply path of the semiconductor memory device.

  In the electronic apparatus having the eighth configuration, when the power of the semiconductor memory device is turned on, the microcomputer turns on the switch and then transmits a power-on command to the semiconductor memory device. When the power is turned off, it is preferable that the switch is turned off after sending a power-off command to the semiconductor memory device (ninth configuration).

  In the electronic apparatus having the ninth configuration, the microcomputer transmits a power-on command when the semiconductor memory device is powered on, and then sends a status request to the semiconductor memory device, and the power source unit performs the status request. A configuration (tenth configuration) may be employed in which normal access operation is started after confirming that power supply to the memory unit is started.

  In the electronic apparatus having the ninth or tenth configuration, the microcomputer transmits a power-off command when the semiconductor memory device is powered off, and then makes a status request to the semiconductor memory device, and the power source The switch may be turned off after confirming that power supply from the unit to the memory unit is stopped (an eleventh configuration).

  According to the present invention, it is possible to provide a semiconductor memory device that can be intermittently driven by power on / off without causing problems such as data corruption.

Block diagram showing one structural example of an electronic device Flow chart showing an example of a power-on sequence Flow chart showing an example of a power-off sequence Time chart showing an example of current consumption during intermittent drive Schematic diagram showing an example of application to a smart meter Schematic diagram showing an example of application to a biosensor Block diagram showing a conventional example of a semiconductor memory device Time chart for explaining CSB timing constraints when power is on / off

<Electronic equipment>
FIG. 1 is a block diagram illustrating a configuration example of an electronic apparatus including a semiconductor memory device. The electronic device X of this configuration example includes a semiconductor memory device 1, a microcomputer 2, and a switch 3. Examples of the electronic device X include a smart meter A (FIG. 5) that performs two-way communication with various home appliances and power companies, and various biological information (pulse wave and step count) that is always worn by the subject. Etc.) can be given as a portable biosensor B (FIG. 6).

  The semiconductor memory device 1 is a monolithic semiconductor integrated circuit device (nonvolatile memory IC) having a memory unit 10, a power supply unit 20, a control unit 30, and a power-on reset unit 40.

  The memory unit 10 includes a memory cell array 11 in which a plurality of memory cells are arranged in an array, an X decoder 12 and a Y decoder 13 that drive the memory cell array 11, and a sense amplifier 14 that reads data from the memory cell array 11. Store data in a nonvolatile manner. As the memory cell array 11, for example, an EEPROM, a flash memory, or an FeRAM can be used.

  The power supply unit 20 receives power supply voltage VCC and supplies power to the memory unit 10. Power supply from the power supply unit 20 to the memory unit 10 is permitted / prohibited by the control unit 30. This point will be described in detail later.

  The control unit 30 is a main body that controls the memory unit 10 and the power supply unit 20, and implements the first command processing unit 31 and the second command processing unit 32 by hardware or software. The first command processing unit 31 recognizes an access command (such as a read command or a write command) input from the microcomputer 2 and accesses the memory unit 10. The second command processing unit 32 recognizes each of the power-on command and the power-off command input from the microcomputer 2 and permits / inhibits power supply from the power supply unit 20 to the memory unit 10. The power-on command is a command input from the microcomputer 2 when permitting power supply to the memory unit 10, and the power-off command is input from the microcomputer 2 when prohibiting power supply to the memory unit 10. Is an instruction.

  The control unit 30 communicates with the microcomputer 2 via a serial peripheral interface (SPI) bus for bidirectional serial communication (serial clock signal SCK, chip select signal CSB, serial data input signal SDI, and serial data output signal). SDO), and operates in synchronization with the serial clock signal SCK. The above access command and power on / off command are also input via this SPI bus.

  The power-on reset unit 40 monitors the power supply voltage VCC and initializes the control unit 30 when the power supply voltage VCC is turned on (when it becomes higher than a predetermined threshold voltage).

  The microcomputer 2 is a main body that comprehensively controls the entire operation of the electronic device X. In particular, the microcomputer 2 has a power saving function for intermittently driving the semiconductor memory device 1 by on / off control of the switch 3. Note that a binary (H / L) logic signal is sufficient for the on / off control of the switch 3, and therefore a general-purpose GPIO [general purpose input / output] interface can be used.

  The switch 3 is a discrete component that conducts / cuts off the power supply path of the semiconductor memory device 1 according to an instruction from the microcomputer 2.

<Power-on sequence>
FIG. 2 is a flowchart illustrating an example of a power-on sequence. When the semiconductor memory device 1 is turned on, the microcomputer 2 first performs predetermined power-on control regardless of timing (step S201). In this power-on control, the switch 3 is turned on and the power supply path to the semiconductor memory device 1 is conducted, and the serial clock signal SCK, the chip select signal CSB, the serial data input signal SDI, and the serial data output signal SDO are Both are fixed at a high level.

  After the power supply voltage VCC is turned on, in the semiconductor memory device 1, the control unit 30 is initialized by the power-on reset unit 40 (step S101). At this time, the second command processing unit 32 is activated in a state (Pm: off) in which power supply from the power supply unit 20 to the memory unit 10 is prohibited by initialization at the time of power-on reset. Accordingly, there is no possibility of malfunction or erroneous writing due to noise or the like, and the relationship between the power supply voltage VCC and the chip select signal CSB when the semiconductor memory device 1 is powered on is not questioned.

  After performing the previous power-on control, the microcomputer 2 transmits a power-on command to the semiconductor memory device 1 (step S202). In the semiconductor memory device 1 that has received this power-on command, the second command processing unit 32 recognizes the power-on command (step S102), and permits the power supply from the power unit 20 to the memory unit 10 (Pm: off). → On) (step S103). As a result, the memory unit 10 enters a normal operation state in which access from the microcomputer 2 is accepted (step S104).

  After transmitting the previous power-on command, the microcomputer 2 transmits a status request to the semiconductor memory device 1 (step S203). In the semiconductor memory device 1 that has received this status request, the second command processing unit 32 recognizes the status request (step S105), and the power supply state (Pm: ON) from the power supply unit 20 to the memory unit 10 is used as status information. A reply is sent to the microcomputer 2 (step S106). The microcomputer 2 that has received the status information confirms that power supply from the power supply unit 20 to the memory unit 10 has started (step S204), and starts a normal access operation to the semiconductor memory device 1 (step S205). .

  Note that the status check process (steps S105, S106, S203, S204 with “*” added thereto) by the microcomputer 2 is not an essential process, and the microcomputer 2 transmits a power-on command for a predetermined time. It may be possible to shift to normal operation with a gap.

<Power-off sequence>
FIG. 3 is a flowchart illustrating an example of the power-off sequence. When powering off the semiconductor memory device 1, the microcomputer 2 first transmits a power off command to the semiconductor memory device 1 (step S211). In the semiconductor memory device 1 that has received this power-off command, the second command processing unit 32 recognizes the power-off command (step S111) and prohibits power supply from the power supply unit 20 to the memory unit 10 (Pm: ON → (Off) (Step S112).

  The microcomputer 2 transmits a status request to the semiconductor memory device 1 after transmitting the previous power-off command (step S212). In the semiconductor memory device 1 that has received the status request, the second command processing unit 32 recognizes the status request (step S113), and the power supply state (Pm: off) from the power supply unit 20 to the memory unit 10 is used as status information. A reply is sent to the microcomputer 2 (step S114). The microcomputer 2 that has received the status information confirms that power supply from the power supply unit 20 to the memory unit 10 has been stopped (step S213), and performs predetermined power-off control (step S214). In this power off control, the switch 3 is turned off to cut off the power path to the semiconductor memory device 1, and the serial clock signal SCK, chip select signal CSB, serial data input signal SDI, and serial data output signal SDO are Both are fixed at a low level. At this time, the power supply from the power supply unit 20 to the memory unit 10 has already been stopped, and the memory unit 10 is in a state in which no malfunction or erroneous writing due to noise or the like occurs. Therefore, the relationship between the power supply voltage VCC and the chip select signal CSB when the power of the semiconductor memory device 1 is turned off is not questioned.

  After the power supply voltage VCC is cut off, the semiconductor memory device 1 enters an operation stop state (step S115). At this time, since no current flows through the semiconductor memory device 1, the standby power is completely zero.

  Note that the status check process of the semiconductor memory device 1 by the microcomputer 2 (steps S113, S114, S212, and S213 with “*” attached) is not an essential process, and the microcomputer 2 transmits a power-off command for a predetermined time. The power-off control may be carried out with a gap.

<Intermittent drive>
FIG. 4 is a time chart illustrating an example of current consumption during intermittent driving. The solid line in the figure shows the behavior of the present invention (power on / off control), and the broken line shows the behavior of the prior art (operation mode switching control). As shown in the figure, in the prior art, the current consumption Isleep (generally on the order of μA) has been generated even after the transition to the sleep mode. However, according to the present invention, there is no concern about data corruption. In addition, since the power on / off control of the semiconductor memory device 1 itself can be performed, the unnecessary standby current can be made completely zero.

  Note that when the semiconductor memory device 1 is intermittently driven by power on / off periodically, the power on time t1 and the power on / off cycle t2 are preferably set as appropriate according to the application of the electronic device X. For example, if priority is given to power saving of the electronic device X, the power-on time t1 may be set to the ms order, and the power-on / off cycle t2 may be set to the s order.

  For example, in the smart meter A (FIG. 5) or the biosensor B (FIG. 6), the semiconductor memory device 1 is turned off during data acquisition or temporary storage in a register, and the semiconductor memory is stored only during nonvolatile storage of data. By intermittently driving the semiconductor memory device 1 so that the power of the device 1 is turned on, the average current consumption per unit time can be greatly reduced.

<Other variations>
The various technical features disclosed in the present specification can be variously modified within the scope of the technical creation in addition to the above-described embodiment. That is, the above-described embodiment is to be considered in all respects as illustrative and not restrictive, and the technical scope of the present invention is indicated not by the description of the above-described embodiment but by the scope of the claims. It should be understood that all modifications that fall within the meaning and range equivalent to the terms of the claims are included.

  The present invention is a power saving technique for a semiconductor memory device, and can be suitably used particularly for an electronic device that requires both high reliability and power saving of a semiconductor memory device.

DESCRIPTION OF SYMBOLS 1 Semiconductor memory device 2 Microcomputer 3 Switch 10 Memory part 11 Memory cell array 12 X decoder (row decoder)
13 Y decoder (column decoder)
14 Sense Amplifier 20 Power Supply Unit 30 Control Unit 31 First Command Processing Unit (Access Control)
32 Second command processing unit (power on / off control)
40 Power-on reset unit X Electronic device A Smart meter B Biosensor

Claims (11)

A memory unit for storing data in a nonvolatile manner;
A power supply unit for supplying power to the memory unit;
A control unit for controlling the memory unit and the power source unit;
Have
The controller is
A first command processing unit for recognizing an access command and accessing the memory unit;
A second command processing unit for recognizing a power-on command and a power-off command and permitting / prohibiting power supply from the power unit to the memory unit;
A semiconductor memory device comprising:   The semiconductor memory device according to claim 1, further comprising a power-on reset unit that initializes the control unit when a power supply voltage is turned on.   The semiconductor memory device according to claim 2, wherein the second instruction processing unit is activated in a state in which power supply from the power supply unit to the memory unit is prohibited.   4. The semiconductor memory device according to claim 3, wherein the second instruction processing unit returns a power supply state from the power supply unit to the memory unit in response to a status request.   The semiconductor memory device according to claim 1, wherein the control unit has a function of performing bidirectional serial communication with the outside of the device. The memory unit is
A memory cell array in which a plurality of memory cells are arranged in an array; and
An X decoder and a Y decoder for driving the memory cell array;
A sense amplifier for reading data from the memory cell array;
The semiconductor memory device according to claim 1, comprising:   7. The semiconductor memory device according to claim 6, wherein the memory cell array is an EEPROM (electrically erasable programmable read-only memory), a flash memory, or an FeRAM (ferroelectric random access memory). A semiconductor memory device according to any one of claims 1 to 7,
A microcomputer for intermittently driving the semiconductor memory device by power on / off;
A switch for conducting / interrupting the power path of the semiconductor memory device in accordance with an instruction from the microcomputer;
An electronic device comprising: The microcomputer is
When turning on the power of the semiconductor memory device, a power on command is transmitted to the semiconductor memory device after turning on the switch,
Upon powering off the semiconductor memory device, a power off command is transmitted to the semiconductor memory device and then the switch is turned off.
9. The electronic apparatus according to claim 8, wherein   The microcomputer transmits a power-on command when the semiconductor memory device is turned on, and then makes a status request to the semiconductor memory device to confirm that power supply from the power source unit to the memory unit is started. The electronic device according to claim 9, wherein a normal access operation is started thereafter.   The microcomputer transmits a power-off command when the semiconductor memory device is powered off, and then makes a status request to the semiconductor memory device to confirm that power supply from the power source unit to the memory unit is stopped. The electronic device according to claim 9, wherein the switch is turned off.

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