JP2014138315A - Waveform shaping circuit, system device and waveform shaping method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a waveform distortion of a signal input into a gate of a transistor accompanying a variation in a gate capacitance value.SOLUTION: A waveform shaping circuit includes: a first transistor having a gate fed with a first input signal and a drain connected to an output node; and a correction circuit including a first switch for, when the first input signal changes from a first level to a second level, connecting the gate of the first transistor to a voltage line corresponding to the second level.

Description

  The present invention relates to a waveform shaping circuit, a system device, and a waveform shaping method.

  In a circuit that handles a high voltage such as a power supply device, a transistor with a high withstand voltage such as LDMOS (Laterally Diffused Metal Oxide Semiconductor) is used (for example, see Patent Document 1).

JP 2007-215391 A

  The LDMOS has a characteristic that when the gate voltage is increased, the gate capacitance value greatly changes and has a peak value. For this reason, for example, at the rising edge of the signal input to the gate of the LDMOS, the voltage of the input signal may be distorted due to an increase in the capacitance value. Similarly, at the falling edge of the signal input to the gate of the LDMOS, the waveform of the input signal may be distorted due to an increase in the capacitance value.

  In one aspect, an object of the present invention is to suppress waveform distortion caused by a change in a gate capacitance value of a signal input to a gate of a transistor.

  A waveform shaping circuit according to one embodiment of the present invention includes a first transistor that receives a first input signal at a gate and has a drain connected to an output node, and the first input signal changes from a first level to a second level. And a correction circuit including a first switch that connects the gate of the first transistor to the voltage line corresponding to the second level.

  A system apparatus according to another aspect of the present invention includes a first transistor that receives a first input signal at a gate and has a drain connected to an output node, and the first input signal changes from a first level to a second level. And a first correction circuit including a first switch that connects the gate of the first transistor to the voltage line corresponding to the second level, and the drive unit is controlled by the output signal output from the drain. A waveform shaping circuit to be operated; and a control circuit for setting the first input signal to the first level or the second level in accordance with the control signal.

  In another form of the present invention, a waveform shaping method receives a first input signal at a gate of a first transistor having a drain connected to an output node, and the first input signal is changed from a first level to a second level. When the voltage changes to, the gate of the first transistor is connected to the voltage line corresponding to the second level, and the waveform distortion of the first input signal due to the change in the gate capacitance value due to the change in the gate voltage is corrected. To do.

  Waveform distortion accompanying fluctuations in the gate capacitance value of a signal input to the gate of the transistor can be suppressed.

It is a figure which shows the example of operation | movement of the waveform shaping circuit and waveform shaping circuit in one Embodiment. FIG. 2 is a diagram illustrating an example of capacitance characteristics with respect to a gate voltage of the transistor illustrated in FIG. 1. It is a figure which shows the example of operation | movement of the waveform shaping circuit in another embodiment, and a waveform shaping circuit. It is a figure which shows the example of operation | movement of the waveform shaping circuit and waveform shaping circuit in further another embodiment. It is a figure which shows the example of the waveform shaping circuit in another embodiment. It is a figure which shows the example of the waveform shaping circuit in another embodiment. It is a figure which shows the example of the waveform shaping circuit in another embodiment. It is a figure which shows the example of the waveform shaping circuit in another embodiment. It is a figure which shows the example of operation | movement of the waveform shaping circuit shown in FIG. FIG. 9 is a diagram illustrating an example of a system apparatus in which any one of the waveform shaping circuits illustrated in FIGS. 1 and 3 to 8 is mounted.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same reference numerals as the signal names are used for the signal lines through which signals are transmitted.

  FIG. 1 shows an example of the waveform shaping circuit and the operation of the waveform shaping circuit in one embodiment. The waveform shaping circuit WSC1 of this embodiment includes a transistor TRN and a switch SWR. For example, the transistor TRN is an n-channel type LDMOS (Laterally Diffused Metal Oxide Semiconductor) and is an example of a first transistor. The switch SWR is an example of a first switch and is included in the correction circuit CRCT1.

  Transistor TRN receives clock signal CLKN at its gate, has its drain connected to output node OUT, and its source connected to ground line VSS. The clock signal CLKN is an example of a first input signal. The switch SWR is disposed between the power supply line VDD and the gate of the transistor TRN, and is controlled by a control signal CNTR.

  The switch SWR is turned on in response to a low level pulse of the control signal CNTR generated when the clock signal CLKN changes from the low level L to the high level H, and connects the gate of the transistor TRN to the power supply line VDD. The power supply line VDD is an example of a voltage line. The low level L is an example of a first level, and the high level H is an example of a second level.

  In a transistor TRN such as an LDMOS, a gate capacitance value changes due to a change in gate voltage, and a peak appears in the capacitance value. The capacitance characteristics with respect to the gate voltage of the LDMOS are shown in FIG.

When the gate voltage of the transistor TRN is Vg, the gate capacitance value is Cgg, and the charge accumulated in the gate capacitance is Q, the relationship of Equation (1) is established from Coulomb's law. Further, when the equation (1) is differentiated with respect to time t, the relationship of the equation (2) is established.
Vg = Q / Cgg (1)

式（２）は、トランジスタＴＲＮのゲート容量値Ｃｇｇの変化が電荷Ｑの変化に対して大きいと、ゲート電圧Ｖｇが逆方向へ変化することを示す。例えば、クロック信号ＣＬＫＮの立ち上がり時に、トランジスタＴＲＮのゲート容量値Ｃｇｇが増加することによってゲート電圧Ｖｇ（この例では、クロック信号ＣＬＫＮの電圧）の上昇率は小さくなる。

Equation (2) indicates that the gate voltage Vg changes in the opposite direction when the change in the gate capacitance value Cgg of the transistor TRN is larger than the change in the charge Q. For example, the rising rate of the gate voltage Vg (in this example, the voltage of the clock signal CLKN) decreases as the gate capacitance value Cgg of the transistor TRN increases at the rising edge of the clock signal CLKN.

  When the waveform shaping circuit WSC1 does not include the correction circuit CRCT1, the voltage (= Vg) of the clock signal CLKN supplied to the gate of the transistor TRN changes according to the equation (2). As a result, as indicated by the one-dot chain line in the waveform of the clock signal CLKN shown on the right side of FIG. 1, the waveform of the clock signal CLKN is distorted in the middle of rising and changes stepwise. For example, the waveform distortion of the clock signal CLKN tends to appear when the slew rate of the clock signal CLKN is reduced in order to reduce noise due to switching of the transistor TRN.

  When the waveform of the clock signal CLKN is distorted and the current flowing between the drain and source of the transistor TRN (power supply current to the ground line VSS) changes, harmonics are generated in the power supply line and the like. The generated harmonic propagates to other circuits via the power line and the like. For this reason, when an analog circuit or the like sensitive to noise is mounted on the semiconductor chip together with the transistor TRN, the analog circuit or the like may malfunction.

  On the other hand, the waveform shaping circuit WSC1 shown in FIG. 1 has a switch SWR that connects the gate of the transistor TRN to the power supply line VDD in response to a low level pulse signal (CNTR) when the clock signal CLKN rises. Thereby, when the clock signal CLKN rises, electric charge is supplied from the power supply line VDD to the gate of the transistor TRN via the switch SWR.

  As shown by a thick solid line on the right side of FIG. 1, the waveform of the clock signal CLKN changes from the low level L to the high level H without distortion. As a result, the resistance between the source and drain of the transistor TRN decreases with a smooth change in the gate voltage, and generation of harmonics in the power supply line and the like is suppressed.

  In this embodiment, elements such as p-channel type LDMOS that change the output node OUT from the low level L to the high level H are omitted. For example, when the clock signal CLKN is supplied to the gate of a p-channel type LDMOS or the like, the falling waveform of the clock signal CLKN is distorted as shown on the right side of FIG. For example, it is preferable to apply the waveform shaping circuit WSC2 shown in FIG. 3 when harmonics are generated in the power supply line or the like when the clock signal CLKN falls and noise may be induced.

  As described above, in this embodiment, it is possible to suppress waveform distortion caused by a change in the gate capacitance value of the clock signal CLKN input to the gate of the transistor TRN. As a result, generation of harmonics in the power supply line or the like can be suppressed, and malfunction of other circuits mounted on the semiconductor integrated circuit or the like together with the waveform shaping circuit WSC1 can be avoided.

  Even when the slew rate of the clock signal CLKN is reduced in order to reduce noise due to switching of the transistor TRN, distortion of the waveform of the clock signal CLKN can be suppressed.

  FIG. 2 shows an example of capacitance characteristics with respect to the gate voltage of the transistor TRN shown in FIG. In a transistor such as an LDMOS, for example, when the gate voltage Vg is changed from 0V to 5V to 8V, or when the gate voltage Vg is changed from 5V to 8V to 0V, the gate capacitance value Cgg is changed during the change of the gate voltage Vg. A peak appears. In FIG. 2, the symbol Vd is the drain voltage (drain-source voltage) of the transistor TRN.

  FIG. 3 shows an example of the waveform shaping circuit and the operation of the waveform shaping circuit in another embodiment. Detailed description of the same or similar elements as those shown in FIG. 1 is omitted.

  The waveform shaping circuit WSC2 of this embodiment includes transistors TRP and TRN and a correction circuit CRCT2. The correction circuit CRCT2 includes switches SWR and SWF. For example, the transistor TRP is a p-channel type LDMOS, and the transistor TRN is an n-channel type LDMOS. The transistor TRP is an example of a second transistor, and the switch SWF is an example of a second switch.

  The connection relationship between the switch SWR and the transistor TRN is the same as that in FIG. However, in this embodiment, the clock signal CLKN is supplied to the gates of the transistors TRP and TRN.

  Transistor TRP has a source connected to power supply line VDD, a drain connected to output node OUT, and a gate receiving clock signal CLKN. Transistor TRN has a source connected to ground line VSS, a drain connected to output node OUT, and a gate receiving clock signal CLKN. That is, the transistors TRP and TRN function as a CMOS inverter that inverts the logic of the clock signal CLKN and outputs the inverted signal to the output node OUT.

  The switch SWF is disposed between the gates of the transistors TRP and TRN and the ground line VSS, and is controlled by a control signal CNTF. The switch SWF connects the gates of the transistors TRP and TRN to the ground line VSS in response to a high level pulse of the control signal CNTF generated when the clock signal CLKN changes from the high level H to the low level L. The power supply line VDD and the ground line VSS are examples of voltage lines.

  Of the waveforms shown on the right side of FIG. 3, the waveform at the rising edge of the clock signal CLKN is the same as that of FIG. At the rising edge of the clock signal CLKN, the low level L of the clock signal CLKN is an example of the first level, and the high level H of the clock signal CLKN is an example of the second level. Since the control signal CNTF is maintained at a low level at the rising edge of the clock signal CLKN, the switch SWF is maintained in an off state, and the gates of the transistors TRP and TRN are not connected to the ground line VSS.

  At the fall of the clock signal CLKN, the switch SWF is turned on in response to the high level pulse of the control signal CNTF generated when the clock signal CLKN changes from the high level H to the low level L. Thereby, the gates of the transistors TRP and TRN are connected to the ground line VSS via the switch SWF. At the fall of the clock signal CLKN, the high level H of the clock signal CLKN is an example of the first level, and the low level L of the clock signal CLKN is an example of the second level.

  Thereby, when the clock signal CLKN falls, the charges accumulated in the gates of the transistors TRP and TRN are extracted to the ground line VSS via the switch SWF. Then, as shown by the thick solid line on the right side of FIG. 3, the waveform of the clock signal CLKN changes from the high level H to the low level L without distortion, unlike FIG. As a result, the resistance between the source and drain of the transistor TRN decreases with a smooth change in the gate voltage, and generation of harmonics in the power supply line and the like is suppressed.

  Note that since the control signal CNTR is maintained at a high level when the clock signal CLKN falls, the switch SWR maintains an off state, and the gates of the transistors TRP and TRN are not connected to the power supply line VDD.

  As described above, also in this embodiment, similarly to the embodiment shown in FIG. 1, it is possible to suppress the waveform distortion accompanying the fluctuation of the gate capacitance value of the clock signal CLKN input to the gates of the transistors TRP and TRN. Furthermore, not only the distortion of the rising waveform of the clock signal CLKN but also the distortion of the falling waveform of the clock signal CLKN can be suppressed. As a result, generation of harmonics in the power supply line or the like can be suppressed, and malfunction of other circuits mounted on the semiconductor integrated circuit or the like together with the waveform shaping circuit WSC2 can be avoided.

  FIG. 4 shows an example of the waveform shaping circuit and the operation of the waveform shaping circuit in still another embodiment. Detailed description of the same or similar elements as those shown in FIGS. 1 and 3 is omitted.

  The waveform shaping circuit WSC3 of this embodiment includes transistors TRP and TRN and a correction circuit CRCT3. For example, the transistor TRP is a p-channel type LDMOS, and the transistor TRN is an n-channel type LDMOS.

  Transistor TRP has a source connected to power supply line VDDH, a drain connected to output node OUT, and a gate receiving clock signal CLKP. The power supply lines VDDH and VDD are examples of voltage lines. The voltage (for example, 40V) of the power supply line VDDH is higher than the voltage (for example, 5V) of the power supply line VDD. Transistor TRN has a source connected to ground line VSS, a drain connected to output node OUT, and a gate receiving clock signal CLKN.

  The clock signals CLKP and CLKN have rising edges with common timing and falling edges with common timing. That is, the clock signals CLKP and CLKN are in-phase signals. For example, the high level voltage of the clock signal CLKP is 40V, and the low level voltage of the clock signal CLKP is 35V. For example, the high level voltage of the clock signal CLKN is 5V, and the low level voltage of the clock signal CLKN is 0V. The transistors TRP and TRN function as inverters that invert the logic of the clock signals CLKP and CLKN and output them to the output node OUT.

  The correction circuit CRCT3 includes switches SWR and SWF connected to the gate of the transistor TRN, and switches SWRH and SWFH connected to the gate of the transistor TRP. The switch SWR is an example of a first switch, the switch SWF is an example of a second switch, the switch SWRH is an example of a third switch, and the switch SWFH is an example of a fourth switch.

  The switches SWRH and SWFH are connected via a clock signal line CLKP to which a clock signal CLKP is transmitted between the power supply line VDDH and the ground line VSSH. The ground line VSSH is an example of a voltage line. For example, the voltage of the ground line VSSH is 35V.

  The switch SWRH is controlled by a control signal CNTRH. Similarly to the switch SWR shown in FIG. 3, the switch SWRH supplies power to the gate of the transistor TRP in response to the low level pulse of the control signal CNTRH generated when the clock signal CLKP changes from the low level L to the high level H. Connect to line VDDH.

  The switch SWFH is controlled by a control signal CNTFH. Similar to the switch SWF shown in FIG. 3, the switch SWFH controls the gate of the transistor TRP in response to the high level pulse of the control signal CNTFH generated when the clock signal CLKP changes from the high level H to the low level L. Connect to ground line VSSH.

  The switches SWR and SWF are connected between a power supply line VDD and a ground line VSS via a clock signal line CLKN to which a clock signal CLKN is transmitted. The ground line VSS is an example of a voltage line.

  The switch SWR is controlled by a control signal CNTR. Similarly to FIG. 3, the switch SWR connects the gate of the transistor TRN to the power supply line VDD in response to a low level pulse of the control signal CNTR that is generated when the clock signal CLKN changes from the low level L to the high level H.

  The switch SWF is controlled by a control signal CNTF. Similarly to FIG. 3, the switch SWF connects the gate of the transistor TRN to the ground line VSS in response to the high level pulse of the control signal CNTF generated when the clock signal CLKN changes from the high level H to the low level L. To do.

  Also in this embodiment, as in FIG. 3, the switches SWRH and SWR respond to the low level pulses of the control signals CNTRH and CNTR that are generated when the clock signals CLKP and CLKN change from the low level L to the high level H. Turn on. Thereby, the gate of the transistor TRP is connected to the power supply line VDDH via the switch SWRH, and the gate of the transistor TRN is connected to the power supply line VDD via the switch SWR.

  The switches SWFH and SWF are turned on in response to the high level pulses of the control signals CNTFH and CNTF generated when the clock signals CLKP and CLKN change from the high level H to the low level L. Thereby, the gate of the transistor TRP is connected to the ground line VSSH via the switch SWFH, and the gate of the transistor TRN is connected to the ground line VSS via the switch SWF.

  As a result, the waveforms of the clock signals CLKP and CLKN change from the low level L to the high level H and from the high level H to the low level L without distortion, as indicated by thick solid lines on the right side of FIG. As a result, generation of harmonics in the power supply lines VDDH and VDD or the ground lines VSSH and VSS is suppressed.

  As described above, also in this embodiment, similarly to the embodiment shown in FIGS. 1 and 3, waveform distortion due to fluctuations in the gate capacitance values of the clock signals CLKP and CLKN input to the gates of the transistors TRP and TRN is suppressed. it can.

  Further, even when the gate of the p-channel type transistor and the gate of the n-channel type transistor operate by receiving clock signals CLKP and CLKN having different voltage amplitudes, distortion occurs in the clock signals CLKP and CLKN. Can be suppressed.

  As a result, generation of harmonics in the power supply line or the like can be suppressed, and malfunction of other circuits mounted on the semiconductor integrated circuit or the like together with the waveform shaping circuit WSC3 can be avoided.

  FIG. 5 shows an example of a waveform shaping circuit in another embodiment. Detailed description of the same or similar elements as those shown in FIG. 1 is omitted. The waveform shaping circuit WSC4 of this embodiment includes a buffer circuit BUF that receives the clock signal CLKIN and generates the clock signal CLKN, a transistor TRN that receives the clock signal CLKN, and a correction circuit CRCT4. For example, the transistor TRN is an n-channel type LDMOS.

  The correction circuit CRCT4 includes a waveform generation circuit WGEN, a comparison circuit CMPR, and a switch SWR. The waveform generation circuit WGEN includes a buffer circuit BUFi that receives the clock signal CLKIN and a capacitive element CAP, and is an example of a reference signal generation circuit. The buffer circuit BUFi receives the clock signal CLKIN and generates a reference clock signal CLKNi. The reference clock signal CLKNi is an example of a reference signal. The buffer circuit BUFi is an example of a second buffer circuit.

  For example, the capacitive element CAP includes an n-channel transistor whose gate is connected to the output of the buffer circuit BUFi, and whose source and drain are connected to the ground line VSS. Note that the capacitor CAP may include a p-channel transistor. For example, the wiring load from the output of the buffer circuit BUFi to the capacitive element CAP is designed to be equal to the wiring load from the output of the buffer circuit BUF to the gate of the transistor TRN. That is, the load on the signal line to which the clock signal CLKN is transmitted is the same as or equivalent to the load on the signal line to which the clock signal CLKNi is transmitted.

  For example, the buffer circuit BUFi is designed to have the same or equivalent driving capability as the buffer circuit BUF. The capacitive element CAP is designed to have a capacitance value that is the same as or equivalent to the gate capacitance value when the drain voltage Vd of the transistor TRN is 0V. Alternatively, the ratio between the drive capability of the buffer circuit BUF and the drive capability of the buffer circuit BUFi is designed to be equal to the ratio between the gate capacitance value of the transistor TRN and the capacitance value of the capacitive element CAP. Thereby, the waveform of the clock signal CLKNi is the same as the waveform of the ideal clock signal CLKN when the gate capacitance value of the transistor TRN does not depend on the gate voltage.

  The comparison circuit CMPR compares the voltages of the clock signals CLKN and CLKNi, and outputs a low-level control signal CNTR when the voltage of the clock signal CLKN is lower than the voltage of the clock signal CLKNi. The comparison circuit CMPR outputs a high-level control signal CNTR when the voltage of the clock signal CLKN is equal to or higher than the voltage of the clock signal CLKNi. When the voltages of the clock signals CLKN and CLKNi are equal to each other, an offset voltage is added to the voltage of the clock signal CLKN or the voltage of the clock signal CNKNi input to the comparison circuit CMPR in order to set the control signal CNTR to a high level. It may be added.

  For example, the switch SWR includes a p-channel type transistor having a source connected to the power supply line VDD, a drain connected to the gate of the transistor TRN, and receiving a control signal CNTR at the gate. The operation of the waveform shaping circuit WSC4 shown in FIG. 5 is the same as the operation of the waveform shaping circuit WSC1 shown in FIG. Note that the waveform of the clock signal CLKNi is the same as the waveform of the clock signal CLKN indicated by a thick line in FIG. Then, the correction circuit CRCT4 turns on the switch SWR when the clock signal CLKN rises, and supplies a charge to the gate of the transistor TRN.

  As described above, also in this embodiment, similarly to the embodiment shown in FIG. 1, waveform distortion caused by fluctuations in the gate capacitance value of the clock signal CLKN input to the gate of the transistor TRN can be suppressed, and other circuits malfunction. You can avoid doing that.

  Furthermore, the control signal CNTR can be generated inside the waveform shaping circuit WSC4 by generating the clock signal CLKNi having an ideal waveform of the clock signal CLKN by the waveform generation circuit WGEN. As a result, the load on the signal line to which the control signal CNTR for controlling the switch SWR is transmitted can be made smaller than that in FIG. 1, and the control signal CNTR can be supplied to the switch SWR without delaying the timing. As a result, even when the gate capacitance value of the transistor TRN varies, the clock signal CLKN can have an ideal waveform.

  FIG. 6 shows an example of a waveform shaping circuit in another embodiment. Detailed description of the same or similar elements as those shown in FIGS. 1, 3, and 5 will be omitted. The waveform shaping circuit WSC5 of this embodiment includes a buffer BUF that receives the clock signal CLKIN and generates the clock signal CLKN, a transistor TRN that receives the clock signal CLKN, and a correction circuit CRCT5. For example, the transistor TRN is an n-channel type LDMOS.

  The correction circuit CRCT5 includes a waveform generation circuit WGEN, a comparison circuit CMPF, and a switch SWF that are the same as or similar to those in FIG. As described with reference to FIG. 5, the waveform generation circuit WGEN generates a clock signal CLKNi having the same waveform as that of the ideal clock signal CLKN when the gate capacitance value of the transistor TRN does not depend on the gate voltage.

  The comparison circuit CMPF compares the voltages of the clock signals CLKN and CLKNi, and outputs a high-level control signal CNTF when the voltage of the clock signal CLKN is higher than the voltage of the clock signal CLKNi. The comparison circuit CMPF outputs a low level control signal CNTF when the voltage of the clock signal CLKN is equal to or lower than the voltage of the clock signal CLKNi. As in the comparison circuit CMPR shown in FIG. 5, an offset voltage may be added to the voltage of the clock signal CLKN or the voltage of the clock signal CNKNi input to the comparison circuit CMPF.

  For example, the switch SWF includes an n-channel type transistor having a source connected to the ground line VSS, a drain connected to the gate of the transistor TRN, and receiving a control signal CNTF at the gate. The operation of the waveform shaping circuit WSC5 shown in FIG. 6 is the same as the operation indicated by the waveforms of the clock signal CLKN, the control signal CNTF, and the output signal OUT of the waveform shaping circuit WSC2 shown in FIG. Note that the waveform of the clock signal CLKNi is the same as the waveform of the clock signal CLKN indicated by a thick line in FIG. Then, the correction circuit CRCT5 turns on the switch SWF when the clock signal CLKN falls, and extracts charge from the gate of the transistor TRN.

  As described above, also in this embodiment, similarly to the embodiment shown in FIGS. 1 and 3, waveform distortion due to the variation in the gate capacitance value of the clock signal CLKN input to the gate of the transistor TRN can be suppressed. It is possible to avoid malfunction of the circuit. Further, similarly to the embodiment shown in FIG. 5, the waveform generation circuit WGEN can supply the control signal CNTF to the switch SWF without delaying the timing, and the clock signal CLKN can have an ideal waveform.

  FIG. 7 shows an example of a waveform shaping circuit in another embodiment. Detailed description of elements that are the same as or similar to those shown in FIGS. 1, 3, 5, and 6 will be omitted. The waveform shaping circuit WSC6 of this embodiment includes a buffer circuit BUF that receives the clock signal CLKIN and generates the clock signal CLKN, a transistor TRN that receives the clock signal CLKN, and a correction circuit CRCT6. For example, the transistor TRN is an n-channel type LDMOS. The buffer circuit BUF is an example of a first buffer circuit.

  The correction circuit CRCT6 includes a waveform generation circuit WGEN, a comparison circuit CMPR, and a switch SWR that are the same as or similar to those in FIG. 5, and a comparison circuit CMPF and a switch SWF that are the same as or similar to those in FIG. As described with reference to FIG. 5, the waveform generation circuit WGEN generates a clock signal CLKNi having the same waveform as that of the ideal clock signal CLKN when the gate capacitance value of the transistor TRN does not depend on the gate voltage.

  The comparison circuit CMPR generates the control signal CNTR having a low level pulse in synchronization with the rising edge of the clock signal CLKN, as shown by the waveform in FIG. The comparison circuit CMPF generates a control signal CNTF having a high-level pulse in synchronization with the falling edge of the clock signal CLKN, as shown by the waveform in FIG.

  The switch SWR connects the gate of the transistor TRN to the power supply line VDD corresponding to the high level according to the control signal CNTR that is set to the low level when the clock signal CLKN changes from the low level to the high level. The switch SWF connects the gate of the transistor TRN to the ground line VSS corresponding to the low level according to the control signal CNTF set to the high level when the clock signal CLKN changes from the high level to the low level. That is, the correction circuit CRCT6 turns on the switch SWR when the clock signal CLKN rises, supplies charge to the gate of the transistor TRN, turns on the switch SWF when the clock signal CLKN falls, and pulls out the charge from the gate of the transistor TRN. . The operation waveform of the waveform shaping circuit WSC6 is the same as the operation waveform of the waveform shaping circuit WSC2 shown on the right side of FIG.

  As described above, also in this embodiment, similarly to the embodiment shown in FIGS. 1 and 3, waveform distortion due to the variation in the gate capacitance value of the clock signal CLKN input to the gate of the transistor TRN can be suppressed. It is possible to avoid malfunction of the circuit. At this time, similarly to the waveform shaping circuit WSC2 shown in FIG. 3, both the rising edge distortion and the falling edge distortion of the clock signal CLKN can be suppressed. Further, similarly to the embodiment shown in FIG. 5, the waveform generation circuit WGEN can supply the control signals CNTR and CNTF to the switches SWR and SWF without delaying the timing, and the clock signal CLKN can have an ideal waveform. Can do.

  FIG. 8 shows an example of a waveform shaping circuit in another embodiment. Detailed descriptions of elements that are the same as or similar to those shown in FIGS. 1, 4, 5, 6, and 7 are omitted. The waveform shaping circuit WSC7 of this embodiment includes buffer circuits BUF and BUFH, transistors TRP and TRN, and a correction circuit CRCT7.

  Similarly to FIG. 4, the transistor TRP has a source connected to the power supply line VDDH, a drain connected to the output node OUT, and a gate receiving the clock signal CLKP. The voltage (for example, 40V) of the power supply line VDDH is higher than the voltage (for example, 5V) of the power supply line VDD. Similarly to FIG. 4, the transistor TRN has a source connected to the ground line VSS, a drain connected to the output node OUT, and a gate receiving the clock signal CLKN.

  The clock signals CLKP and CLKN are in-phase signals with different voltages, as in FIG. The power supply lines VDDH and VDD are examples of voltage lines. The transistors TRP, TRN function as inverters that invert the logic of the clock signals CLKIN, CLKP, CLKN and output them to the output node OUT.

  The buffer circuit BUFH has a function of converting the clock signal CLKIN having an amplitude with the power supply voltage VDD and the ground voltage VSS into a clock signal CLKP having an amplitude with the power supply voltage VDDH and the ground voltage VSSH. The buffer circuit BUF outputs the clock signal CLKIN as the clock signal CLKN without changing the amplitude of the clock signal CLKIN.

  The correction circuit CRCT7 includes waveform generation circuits WGENH, WGEN, comparison circuits CMPRH, CMPFH, CMPR, CMPF, and switches SWRH, SWFH, SWR, SWF. The waveform generation circuit WGENH includes a buffer circuit BUFiH and a capacitive element CAP, as in FIG. However, unlike the buffer circuit BUFi shown in FIG. 7, the buffer circuit BUFiH has a function of converting the clock signal CLKIN having an amplitude with the power supply voltage VDD and the ground voltage VSS into a clock signal CLKPiH having an amplitude with the power supply voltage VDDH and the ground voltage VSSH. Have

  The buffer circuit BUFiH is designed to have the same or equivalent driving capability as the buffer circuit BUFH. Alternatively, the ratio between the drive capability of the buffer circuit BUFH and the drive capability of the buffer circuit BUFiH is designed to be equal to the ratio between the gate capacitance value of the transistor TRP and the capacitance value of the capacitive element CAP. Thereby, the waveform of the clock signal CLKNiH becomes the same waveform as the ideal waveform of the clock signal CLKP when the gate capacitance value of the transistor TRP does not depend on the gate voltage.

  The comparison circuit CMPRH compares the voltages of the clock signals CLKP and CLKPiH, and outputs a low-level control signal CNTRH when the voltage of the clock signal CLKP is lower than the voltage of the clock signal CLKPiH. The comparison circuit CMPRH outputs a high-level control signal CNTRH when the voltage of the clock signal CLKP is equal to or higher than the voltage of the clock signal CLKPiH. Since comparison circuit CMPRH operates in response to power supply voltage VDDH and ground voltage VSSH, the high level of control signal CNTRH is power supply voltage VDDH, and the low level of control signal CNTRH is ground voltage VSSH.

  The comparison circuit CMPFH compares the voltages of the clock signals CLKP and CLKPiH, and outputs a high level control signal CNTFH when the voltage of the clock signal CLKP is higher than the voltage of the clock signal CLKPiH. The comparison circuit CMPFH outputs a low-level control signal CNTFH when the voltage of the clock signal CLKP is equal to or lower than the voltage of the clock signal CLKPiH. Since comparison circuit CMPFH operates by receiving power supply voltage VDDH and ground voltage VSSH, the high level of control signal CNTFH is power supply voltage VDDH, and the low level of control signal CNTFH is ground voltage VSSH.

  For example, the switch SWRH includes a p-channel type transistor having a source connected to the power supply line VDDH, a drain connected to the gate of the transistor TRP, and receiving a control signal CNTRH at the gate. The switch SWRH is turned on in response to the low-level control signal CNTRH when the clock signal CLKP rises, and supplies charges to the gate of the transistor TRP.

  For example, the switch SWFH includes an n-channel type transistor having a source connected to the ground line VSSH, a drain connected to the gate of the transistor TRP, and receiving a control signal CNTFH at the gate. The switch SWFH is turned on in response to the high level control signal CNTFH at the fall of the clock signal CLKP, and draws charges from the gate of the transistor TRP.

  The waveform generation circuit WGEN, the comparison circuits CMPR and CMPF, and the switches SWR and SWF are the same as or similar to the elements in the correction circuit CRCT6 shown in FIG. 7, and the connection relationship is also the connection relationship in the correction circuit CRCT6 shown in FIG. Is the same or similar.

  FIG. 9 shows an example of the operation of the waveform shaping circuit WSC7 shown in FIG. Detailed description of waveforms similar to those shown in FIG. 4 is omitted. The waveforms of the clock signals CLKP and CLKN, the control signals CNRH, CNTR, CNTFH, CNTF, and the output signal OUT are the same as those in FIG.

  Buffer circuit BUF and buffer circuit BUFi (FIG. 7) in waveform generation circuit WGEN receive clock signal CLKIN and output clock signals CLKN and CLKNi, respectively. Buffer circuits BUFH and BUFiH receive clock signal CLKIN and output clock signals CLKP and CLKPiH, respectively. The high level voltages of the clock signals CLKN and CLKNi are different from the high level voltages of the clock signals CLKP and CLKPiH, and the low level voltages of the clock signals CLKN and CLKNi are different from the low level voltages of the clock signals CLKP and CLKPiH.

  The comparison circuit CMPR sets the control signal CNTR to the low level when the clock signal CLKN rises, and the comparison circuit CMPRH sets the control signal CNTRH to the low level when the clock signal CLKP rises. The comparison circuit CMPF sets the control signal CNTF to a high level when the clock signal CLKN falls, and the comparison circuit CMPFH sets the control signal CNTFH to a high level when the clock signal CLKP falls.

  In FIG. 9, the control signals CNRH and CNTR are shown as one waveform, but the voltage amplitude of the control signal CNTF is different from the voltage amplitude of the control signal CNTR, and the voltage amplitude of the control signal CNTFH is Different from voltage amplitude.

  As a result, the waveforms of the clock signals CLKP and CLKN change from the low level L to the high level H and from the high level H to the low level L without distortion. As a result, the generation of harmonics in the power supply lines VDDH and VDD or the ground lines VSSH and VSS is suppressed as in FIG.

  As described above, also in this embodiment, similarly to the embodiment shown in FIGS. 1 and 4, waveform distortion caused by fluctuations in the gate capacitance values of the clock signals CLKP and CLKN input to the gates of the transistors TRP and TRN is suppressed. it can. As a result, generation of harmonics in the power supply line or the like can be suppressed, and malfunction of other circuits mounted on the semiconductor integrated circuit or the like together with the waveform shaping circuit WSC7 can be avoided. Similarly to the embodiments shown in FIGS. 5, 6, and 7, the clock signals CLKNi and CLKPiH having ideal waveforms of the clock signals CLKN and CLKP can be generated by the waveform generation circuits WGEN and WGENH. Since the control signals CNTR, CNTF, CNTRH, and CNTFH can be generated inside the waveform shaping circuit WSC7, the control signals CNTR, CNTF, CNRH, and CNTFH can be supplied to the switches SWR, SWF, SWRH, and SWFH, respectively, without delaying the timing. As a result, even when the gate capacitance values of the transistors TRN and TRP change, the clock signals CLKN and CLKP can have ideal waveforms.

  FIG. 10 shows an example of a system apparatus in which any one of the waveform shaping circuits WSC (WSC1-WSC7) shown in FIGS. 1 and 3 to 8 is mounted. For example, the system device SYS includes a semiconductor integrated circuit 20 that controls a motor 10 used to open and close a window of a car and to operate a wiper. For example, the semiconductor integrated circuit 20 includes a power supply circuit 22, a monitor circuit 24, a control circuit 26, a predriver circuit 28, and an analog circuit 30. For example, the motor 10 is a stepping motor and is an example of a drive unit.

  In FIG. 10, double square marks indicate external terminals of the semiconductor integrated circuit 20. The external terminal is, for example, a pad on a semiconductor chip including the semiconductor integrated circuit 20 or a lead of a package in which the semiconductor chip is accommodated. The code of the signal supplied via the external terminal is the same as that of the terminal name.

  The power supply circuit 22 generates an internal voltage used inside the semiconductor integrated circuit 20 using a power supply voltage received via the external terminal. For example, the internal voltage is a voltage used in the power supply voltages VDD, VDDH, the ground voltage VSSH, the analog circuit 30 and the like shown in FIGS.

  The monitor circuit 24 outputs a control signal CNT to the control circuit 26 according to the monitor information MON supplied from the outside of the semiconductor integrated circuit 20. For example, the monitor information MON is an analog value indicating the rotation speed (rotation angle) and rotation direction of the motor 10 that is generated based on the operation of a switch in the vehicle by a driver of the vehicle. For example, the control signal CNT output from the monitor circuit 24 to the control circuit 26 is a digital signal. That is, the monitor circuit 24 includes an A / D converter (Analog to Digital Converter).

  The control circuit 26 generates a clock signal CLKIN based on the control signal CNT received from the monitor circuit 24 and outputs the generated clock signal CLKIN to the pre-driver circuit 28.

  The pre-driver circuit 28 includes one of the waveform shaping circuits WSC (WSC1-WSC7) shown in FIGS. The predriver circuit 28 generates an output signal OUT in response to the clock signal CLKIN received from the control circuit 26. For example, the output signal OUT is a pulse signal for operating the motor 10. That is, the control circuit 26 generates a clock signal CLKIN that is a source of a pulse signal for operating the motor 10 in response to the switch operation of the driver or the like detected by the monitor circuit 24.

  For example, the analog circuit 30 includes an A / D converter and a D / A converter (Digital to Analog Converter).

  When the pre-driver circuit 28 includes the waveform shaping circuits WSC1, WSC2, and WSC3 shown in FIGS. 1, 3, and 4, the control circuit 26 uses at least one of the clock signals CLKN and CLKP based on the control signal CNT. May be generated. In this case, the generated clock signals CLKN and CLKP are output from the control circuit 26 to the waveform shaping circuit WSC of the pre-driver circuit 28. The control circuit 26 may generate at least one of the control signals CNTR, CNTF, CNRH, and CNTFH. In this case, the generated control signals CNTR, CNTF, CNRH, CNTFH are output from the control circuit 26 to the waveform shaping circuit WSC of the pre-driver circuit 28.

  The system device SYS illustrated in FIG. 10 includes a waveform shaping circuit WSC that shapes the waveform of the clock signal CLKN (or CLKP) in the pre-driver circuit 28. For this reason, distortion of the clock signal CLKN (or CLKP) can be suppressed, harmonics generated in a power supply line or the like in the semiconductor integrated circuit SEM can be suppressed, and malfunction of an analog circuit or the like mounted on the semiconductor integrated circuit SEM can be avoided. Can do.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  DESCRIPTION OF SYMBOLS 10 ... Motor; 20 ... Semiconductor integrated circuit; 22 ... Power supply circuit; 24 ... Monitor circuit; 26 ... Control circuit; 28 ... Pre-driver circuit; 30 ... Analog circuit: BUF, BUFH, BUFi, BUFiH ... Buffer circuit; Elements: CLKN, CLKNi, CLKP, CLKPiH, clock signal; CMPF, CMPFH, CMPR, CMPRH, comparison circuit; CNT, CNTF, CNTFH, CNTR, CNRH, control signal; CRCT1, CRCT2, CRCT3, CRCT4, CRCT5, CRCT6, CRCT7 MON correction information MON monitor information OUT output node SWF, SWFH, SWR, SWRH switch SYS system device TRN TRP transistor transistor VDD VDDH power supply line VSS VSS VSS ground line WG N, WGENH ‥ waveform generating circuit; WSC1, WSC2, WSC3, WSC4, WSC5, WSC6, WSC7 ‥ waveform shaping circuit

Claims (9)

A first transistor receiving a first input signal at a gate and having a drain connected to an output node;
A correction including a first switch that connects a gate of the first transistor to a voltage line corresponding to the second level when the first input signal changes from a first level to a second level. A waveform shaping circuit comprising: a circuit. A first buffer circuit for generating the first input signal;
The correction circuit includes:
A reference signal generating circuit that receives a signal supplied to the first buffer circuit and generates a reference signal indicating an ideal waveform of the first input signal;
Comparing the voltage of the first input signal and the reference signal and indicating that the voltage of the first input signal is closer to the first level than the voltage of the reference signal; The waveform shaping circuit according to claim 1, further comprising: a comparison circuit that outputs a control signal connected to a voltage line corresponding to a level of 2 to the first switch. The reference signal generation circuit includes:
A second buffer circuit for receiving a signal supplied to the first buffer circuit;
A capacitive element connected to the output of the second buffer circuit,
The waveform shaping circuit according to claim 2, wherein the reference signal is output from the second buffer circuit. The ratio between the drive capability of the first buffer circuit and the drive capability of the second buffer circuit is equal to the ratio between the gate capacitance value of the first transistor and the capacitance value of the capacitive element. The waveform shaping circuit according to claim 3. Receiving a first input signal at a gate, having a drain connected to the output node, and a second transistor having a polarity different from that of the first transistor;
The correction circuit includes:
A second switch for connecting a gate of the second transistor to a voltage line corresponding to the first level when the first input signal changes from the second level to the first level; The waveform shaping circuit according to any one of claims 1 to 4, wherein the waveform shaping circuit is provided. A second input signal having the same polarity as the first input signal is received by a gate; a drain is connected to the output node; and a second transistor having a polarity different from that of the first transistor is provided.
The correction circuit includes:
A second switch for connecting a gate of the first transistor to a voltage line corresponding to the first level when the first input signal changes from the second level to the first level; ,
A third switch for connecting a gate of the second transistor to a voltage line corresponding to the second level when the second input signal changes from the first level to the second level; ,
A fourth switch for connecting a gate of the second transistor to a voltage line corresponding to the first level when the second input signal changes from the second level to the first level; The waveform shaping circuit according to claim 1, further comprising: A first transistor receiving a first input signal at a gate and having a drain connected to an output node;
A first switch that connects a gate of the first transistor to a voltage line corresponding to the second level when the first input signal changes from a first level to a second level; A waveform shaping circuit that operates a drive unit according to an output signal output from the drain;
And a control circuit for setting the first input signal to the first level or the second level according to a control signal. The waveform shaping circuit is
A second input signal having the same polarity as the first input signal is received by a gate; a drain is connected to the output node; and a second transistor having a polarity different from that of the first transistor is provided.
The correction circuit includes:
A second switch for connecting a gate of the first transistor to a voltage line corresponding to the first level when the first input signal changes from the second level to the first level; ,
A third switch for connecting a gate of the second transistor to a voltage line corresponding to the second level when the second input signal changes from the first level to the second level; ,
A fourth switch for connecting a gate of the second transistor to a voltage line corresponding to the first level when the second input signal changes from the second level to the first level; With
8. The control circuit according to claim 7, wherein the control circuit sets the first input signal and the second input signal to the first level or the second level according to the control signal. System unit. Receiving a first input signal at a gate of a first transistor having a drain connected to an output node;
When the first input signal changes from the first level to the second level, the gate of the first transistor is connected to the voltage line corresponding to the second level;
A waveform shaping method, wherein distortion of a waveform of the first input signal due to a change in a gate capacitance value accompanying a change in the gate voltage is corrected.

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