JP2014137451A - Video processing device, display device, semiconductor device, and video processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To upscale input video data at a higher frame frequency than a frame frequency limited by a scaler.SOLUTION: A video processing circuit 30 of a projector 1 includes: a first scaler and a second scaler that perform upscale processing of supplied video data; a first processing unit that sequentially and alternately supplies input video data having a plurality of continuous frames on the time axis, to the first scaler and second scaler according to the order of frames; and a second processing unit that when the first scaler and second scaler perform the upscale processing of the video data supplied by the first processing unit, outputs video data, which is obtained after the processing, in the order of the frames on the basis of the amount of processing delay in the first scaler and second scaler.

Description

  The present invention relates to a technique for upscaling video data.

  In a display device such as a projector or a television provided with a high-definition panel, the input video data is upscaled and then the video is displayed. Patent Document 1 discloses that a 4K2K image is reproduced using difference data between HD image data acquired from the Internet and 4K2K image data using a package medium on which HD image data is recorded. In the invention described in Patent Document 1, when generating difference data, a plurality of upscalers in different upscale processing modes are used to upscale HD image data to obtain a 4K2K resolution. And the difference between the image data from each upscaler.

JP 2010-11154 A

In a scaler that upscales video data, the frame frequency of input / output video data may be limited to a specific frame frequency. Therefore, in a display device including this type of scaler, it may be necessary to display a video based on video data having a frame frequency lower than that of input video data.
The present invention has been made in view of the above-described circumstances, and one of its purposes is to provide a technique for upscaling input video data at a frame frequency higher than a frame frequency limited by a scaler. It is.

In order to achieve the above object, a video processing apparatus according to the present invention includes a first scaler and a second scaler that perform upscaling processing of supplied video data, and input video data of a plurality of frames continuous on a time axis. The first processing unit supplies the first scaler and the second scaler sequentially and sequentially according to the order of the frames, and the video supplied from the first processing unit by the first scaler and the second scaler. A second processing unit that outputs the processed video data in the order of the frames based on processing delay amounts in the first scaler and the second scaler when the data upscaling process is performed; .
According to the present invention, input video data is alternately supplied sequentially to the first scaler and the second scaler according to the order of frames, and the video data after the upscaling processing by each scaler is the same frame as the input video data. Therefore, the input video data can be upscaled at a frame frequency higher than the frame frequency limited by the scaler.

In the video processing apparatus according to the present invention, each of the first scaler and the second scaler measures the processing delay amount in its own apparatus, and the second processing unit is configured to perform the processing measured by the first scaler. Based on the difference between the delay amount and the processing delay amount measured by the second scaler, the processed video data may be output in the order of the frames.
According to the present invention, by using a scaler having a function of measuring the processing delay amount of its own device, the order of the frames of the video data is changed based on the difference between the processing delay amounts actually measured in the first scaler and the second scaler. Can be prescribed.

The video processing apparatus according to the present invention includes a frame memory, and when the difference in the processing delay amount between the first scaler and the second scaler exceeds a threshold, the second processing unit includes the first scaler. In addition, the video data after the processing by one of the second scalers having the small processing delay amount may be stored in the frame memory, and read and output at a timing according to the difference.
According to the present invention, even when the difference in the processing delay amount between the first scaler and the second scaler exceeds a threshold, for example, the processing delay amount due to the upscaling process for one frame, it is limited by the scaler. The input video data can be upscaled at a frame frequency higher than the frame frequency.

In the video processing apparatus according to the present invention, the input video data may be 1080p video data having a frame frequency of 60 Hz.
According to the present invention, even when a scaler whose input / output frame frequency is limited to, for example, 30 Hz is used, 1080p input video data having a frame frequency of 60 Hz is upgraded to video data having a frame frequency of 60 Hz. Can be scaled.

In the video processing apparatus according to the present invention, the processed video data may be 4K2K video data.
According to the present invention, even when a scaler whose input / output frame frequency is limited to, for example, 30 Hz is used, 1080p input video data having a frame frequency of 60 Hz is converted into 4K2K video data having a frame frequency of 60 Hz. Can be upscaled.

In the display device according to the present invention, the first scaler and the second scaler that perform the upscaling process of the supplied video data, and the input video data of a plurality of frames continuous on the time axis according to the order of the frames. The upscaling process of the video data supplied by the first processing unit is performed by the first processing unit that alternately supplies the scaler and the second scaler sequentially, and the first scaler and the second scaler. A second processing unit that outputs the processed video data in the order of the frames based on processing delay amounts in the first scaler and the second scaler, and a video output by the second processing unit And a display unit that displays video based on the data.
According to the present invention, input video data is alternately supplied sequentially to the first scaler and the second scaler according to the order of frames, and the video data after the upscaling processing by each scaler is the same frame as the input video data. Therefore, it is possible to display an image obtained by up-scaling the input video data at a frame frequency higher than the frame frequency limited by the scaler.

  The present invention can be conceptualized as a semiconductor device and a video processing method in addition to a video processing device and a display device.

1 is a block diagram showing an overall configuration of a projector according to an embodiment of the invention. The block diagram which shows the hardware constitutions of the video processing circuit which concerns on the same embodiment. Explanatory drawing of operation | movement of the 1st process part which concerns on the same embodiment. Explanatory drawing of operation | movement of the 1st process part which concerns on the same embodiment. Explanatory drawing of operation | movement of the 2nd process part which concerns on the same embodiment. Explanatory drawing of the operation malfunction when a processing delay amount is large. The block diagram which shows the other example of the hardware constitutions of a video processing circuit. Explanatory drawing of operation | movement of the 2nd process part which concerns on the video processing circuit shown in FIG.

  FIG. 1 is a diagram showing an overall configuration of a projector 1 according to an embodiment of the present invention. As shown in FIG. 1, the projector 1 is a liquid crystal projector here, and is a display device that projects and displays an image based on input image data from an external device on a screen or a wall surface. The projector 1 includes an image projection unit 10, a signal input unit 20, and a video processing circuit 30.

  The image projection unit 10 is a display unit that projects an image (video) on the screen S. The image projection unit 10 includes a light source 11, a color light separation optical system 12, light valves 13 R, 13 G, and 13 B, a color light synthesis optical system 14, a projection optical system 15, and a liquid crystal drive circuit 16. When it is not necessary to particularly distinguish each of the light valves 13R, 13G, and 13B, hereinafter, they are simply referred to as “light valves 13”. The light source 11 is a light source for projection light, and includes a light source device such as an ultrahigh pressure mercury lamp or a metal halide lamp. The color light separation optical system 12 separates the light emitted from the light source 11 into a plurality of color components, here, three color components of red (R), green (G), and blue (B). The light separated into each color component is incident on the corresponding light valve 13.

  The light valve 13 is a light modulation device and includes, for example, a transmissive liquid crystal panel. In a liquid crystal panel, liquid crystal is sealed between a pair of transparent electrodes. One of the transparent electrodes is divided into a plurality of pixels arranged two-dimensionally in a matrix. The liquid crystal of each pixel exhibits optical characteristics (for example, transmittance) according to the voltage applied between the transparent electrodes. In the light valve 13, incident light can be modulated for each pixel by controlling the voltage applied to each pixel. The light separated into three color components by the color light separation optical system 12 forms an image for each color component by the light valves 13R, 13G, and 13B. The color light combining optical system 14 combines the images for each color component formed by the light valves 13R, 13G, and 13B to form a color image. The projection optical system 15 is a device that projects the color image formed by the color light combining optical system 14 onto the screen S, and has a projection lens. The liquid crystal driving circuit 16 is a device that drives the light valve 13 based on the video data input from the video processing circuit 30.

  The signal input unit 20 receives an input of a synchronization signal and input video data Vid-in from an external device (not shown), and outputs the received synchronization signal and input video data Vid-in to the video processing circuit 30. . The external device is, for example, a video playback device or a personal computer.

  The synchronization signal includes a vertical synchronization signal VS, a horizontal synchronization signal HS, and a data enable signal DE. The vertical synchronization signal VS is a signal that defines one vertical scanning period. Here, one vertical scanning period is defined by a falling edge after the vertical synchronization signal VS rises. The horizontal synchronization signal HS is a signal that defines one horizontal scanning period. Here, one horizontal scanning period is defined by a falling edge after the horizontal synchronizing signal HS rises. The data enable signal DE is a signal indicating whether or not the input video data Vid-in is valid. The input video data Vid-in when the data enable signal DE is at the H level indicates that it is valid, and the input video data Vid-in when the data enable signal DE is at the L level indicates that it is invalid.

  The input video data Vid-in is digital data (gradation data) that specifies the gradation level of each pixel of the plurality of pixels included in the light valve 13, and each pixel is composed of, for example, 3 dots. Therefore, the input video data Vid-in includes R component gradation data, G component gradation data, and B component gradation data as 8-bit digital data for each pixel. The input video data Vid-in is composed of video data of a plurality of frames continuous on the time axis (that is, video data indicating a moving image). In the present embodiment, the input video data Vid-in is 1080p video data having a frame frequency of 60 Hz. Here, “1080p” refers to an image having a resolution of 1920 pixels × 1080 pixels or 1440 pixels × 1080 pixels.

  The video processing circuit 30 performs predetermined video processing based on the synchronization signal input from the signal input unit 20 and the input video data, and outputs the processed synchronization signal and video data to the image projection unit 10 (more specifically, These are video processing devices that output to the liquid crystal driving circuit 16) shown in FIG.

FIG. 2 is a block diagram illustrating a hardware configuration of the video processing circuit 30. As shown in FIG. 2, the video processing circuit 30 includes a first processing unit 31, a first scaler 32, a second scaler 33, a CPU (Central Processing Unit) 34, and a second processing unit 35.
The first processing unit 31 alternately supplies the input video data Vid-in sequentially to the first scaler 32 and the second scaler 33 according to the frame order. The first processing unit 31 is configured by an IC (that is, a semiconductor device) exemplified by an FPGA (Field-Programmable Gate Array), for example.

  FIG. 3 is a timing chart showing time-series changes of the signals input to the first processing unit 31. As shown in FIG. 3, the vertical synchronization signal VS, the horizontal synchronization signal HS, and the data enable signal DE input to the first processing unit 31 include a period in which the signal level is “H” in each frame of a plurality of frames. It is out. For example, the vertical synchronization signal VS falls from the H level to the L level at the start timing of each vertical scanning period (frame) including the first to fourth frames. Here, the vertical synchronization signal VS falls from the H level to the L level every 1/60 seconds. The input video data Vid-in also includes a video signal representing a video of each frame of a plurality of frames.

  FIG. 4 is a timing chart showing time-series changes of each signal supplied from the first processing unit 31. As shown in FIG. 4, the first processing unit 31 converts the input synchronization signal (that is, the vertical synchronization signal VS, the horizontal synchronization signal HS, and the data enable signal DE) and the input video data Vid-in into odd frames. And signals corresponding to even frames, and the separated signals are supplied by different systems. Specifically, the first processing unit 31 supplies a vertical synchronization signal VS1, a horizontal synchronization signal HS1, a data enable signal DE1, and video data Vid1-a to the first scaler 32 as signals corresponding to odd frames. To do. The first processing unit 31 supplies the second scaler 33 with the vertical synchronization signal VS2, the horizontal synchronization signal HS2, the data enable signal DE2, and the video data Vid2-a as signals corresponding to the even frames.

  As shown in FIG. 4, the vertical synchronization signal VS1, the horizontal synchronization signal HS1, the data enable signal DE1, and the video data Vid1-a are respectively in the first, third,..., (2n-1) frames (n is 1). Including the signals corresponding to the odd numbered frames. For example, the vertical synchronization signal VS1 falls from the H level to the L level only at the start timing of the odd frame. That is, the vertical synchronization signal VS1 falls from the H level to the L level every 1/30 seconds.

On the other hand, each of the vertical synchronization signal VS2, the horizontal synchronization signal HS2, the data enable signal DE2, and the video data Vid2-a includes signals corresponding to even frames of the second, fourth,. For example, the vertical synchronization signal VS2 falls from the H level to the L level only at the start timing of the even frame. That is, the vertical synchronization signal VS2 falls from the H level to the L level every 1/30 seconds.
As described above, the first processing unit 31 time-divides a signal input at a predetermined frame frequency at the frequency, and alternately supplies the time-divided signal supply destination to the first scaler 32 and the second scaler 33. Switch to supply. Therefore, each signal supplied to the first scaler 32 or the second scaler 33 is equivalent to a signal when the frame frequency is 30 Hz.

The first scaler 32 and the second scaler 33 are each a scaler (that is, an upscaler) that performs an upscaling process on video data supplied from the first processing unit 31. Here, the input / output frame frequency is limited to 30 Hz, and the first scaler 32 and the second scaler 33 upscale 1080p video data to 4K2K video data. The first scaler 32 performs an upscaling process on the video data Vid1-a, and supplies the video data Vid1-b after the upscaling process to the second processing unit 35. The second scaler 33 performs the upscaling process on the video data Vid2-a, and supplies the video data Vid2-b after the upscaling process to the second processing unit 35.
Here, “4K2K” refers to an image having a resolution of 4096 pixels × 2043 pixels or 4096 pixels × 2160 pixels. In addition, the first scaler 32 and the second scaler 33 supply a synchronization signal including a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal to the second processing unit 35 in accordance with the upscaling process performed by itself. (Not shown). The synchronization signal supplied to the second processing unit 35 corresponds to the synchronization signal when the frame frequency is 30 Hz.

The first scaler 32 and the second scaler 33 have a function of measuring the processing delay amount in the own apparatus and supplying the measured processing delay amount to the CPU 34 in addition to the upscaling process.
The first scaler 32 and the second scaler 33 have a counter for measuring the horizontal synchronizing signal and the vertical synchronizing signal, and measure the frequency of the horizontal synchronizing signal and the vertical synchronizing signal, respectively, using this counter. Specifically, the first scaler 32 resets the count value of the counter in synchronization with the supply of the vertical synchronization signal VS1, and uses the supply timing of the vertical synchronization signal VS1 as the reference timing for measuring the delay processing amount. Then, the first scaler 32 updates the count value in synchronization with the supply of the horizontal synchronization signal HS1, and uses the count value when the upscaling process is performed for one frame of video data as the processing delay amount in its own device. . Also in the second scaler 33, the processing delay amount in the own apparatus is measured based on the vertical synchronization signal VS2 and the horizontal synchronization signal HS2 in the same manner as the first scaler 32. That is, the first scaler 32 and the second scaler 33 measure the time required for the upscaling process of the video data of one frame in the own apparatus as the processing delay amount. In the present embodiment, the processing delay amount supplied by the first scaler 32 is expressed as “delay1”, and the processing delay amount supplied by the second scaler 33 is expressed as “delay2”.
The first scaler 32 and the second scaler 33 measure the processing delay amount each time a vertical synchronization signal is supplied, for example. In this case, the first scaler 32 and the second scaler 33 measure the processing delay amount for each frame.

The CPU 34 is a control circuit that controls each part of the video processing circuit 30. For example, the CPU 34 controls the second processing unit 35 based on the difference Δd between the processing delay amount delay 1 supplied from the first scaler 32 and the processing delay amount delay 2 supplied from the second scaler 33. Details of the control performed by the CPU 34 based on the difference Δd will be described later.
The CPU 34 also supplies control signals for controlling other parts of the video processing circuit 30, but the illustration thereof is omitted in FIG. 2.

When the video data Vid1-b and Vid2-b after the upscaling process are supplied from each of the first scaler 32 and the second scaler 33, the second processing unit 35 receives the supplied video data Vid1-b and Vid2. Output processing for outputting the video data Vo obtained by combining -b to the image projection unit 10 is performed. The second processing unit 35 is configured by, for example, an IC (semiconductor device) exemplified by FPGA.
Specifically, the second processing unit 35 synthesizes the video data Vid1-b and Vid2-b based on the difference Δd supplied from the CPU 34 so as to match the frame order in the input video data Vid-in. Video data Vo is output. The frame frequency of the video data Vo is 60 Hz, which is the same as the input video data Vid-in. The second processing unit 35 outputs a vertical synchronization signal VSo, a horizontal synchronization signal HSo, and a data enable signal DEo in synchronization with the video data Vo. The vertical synchronization signal VSo, the horizontal synchronization signal HSo, and the data enable signal DEo are equivalent to signals when the frame frequency is 60 Hz. The time series changes of the vertical synchronization signal VSo, the horizontal synchronization signal HSo, the data enable signal DEo, and the video data Vo are strictly different from the vertical synchronization signal VS, the horizontal synchronization signal HS, the data enable signal DE, and the video data Vid-in, respectively. Is different, but shows a change close to the time series change shown in FIG.

  Next, the output process of the video data Vo performed by the second processing unit 35 based on the difference Δd will be described with reference to FIG. Hereinafter, the output processing of the video data Vo will be described. In synchronization with the video data Vo, the vertical processing signal VSo, the horizontal synchronization signal HSo, and the data enable signal DEo are also output by the second processing unit 35.

FIG. 5 is a timing chart showing time-series changes in the video data Vo output by the second processing unit 35. As shown in FIG. 5, here, a case is considered in which the difference Δd does not exceed the threshold, that is, the processing delay amount due to the upscaling process of one frame. The difference Δd in this case is represented as Δd1. The difference Δd1 is shorter than one frame (here, 1/30 second) in the video data Vid1-b and Vid2-b.
In this case, the video data Vid1-b from the first scaler 32 and the video data Vid2-b from the second scaler 33 are sequentially and alternately supplied to the second processing unit 35 for each frame. Therefore, the second processing unit 35 sequentially outputs the video data Vid1-b supplied from the first scaler 32 and the video data Vid2-b supplied from the second scaler 33 according to the order supplied to the own apparatus. Thus, the video data Vo can be output in the same frame order as the input video data Vid-in.

  In the video processing circuit 30, until the input video data Vid-in is changed to another video data, the difference Δd is made constant by using the frame lock function of the first scaler 32 and the second scaler 33 or the like. be able to. Therefore, the CPU 34 may obtain the difference Δd at the start of the upscaling process and continue the output process of the video data Vo based on the difference Δd. However, the video processing circuit 30 may perform the output processing of the video data Vo by obtaining the difference Δd for each frame or a plurality of frames.

  By the way, the difference Δd in the processing delay amount between the processing delay amount delay1 in the first scaler 32 and the processing delay amount delay2 in the second scaler 33 exceeds the processing delay amount due to the upscaling processing for one frame for some reason. In such a case, the following malfunction may occur in the second processing unit 35.

FIG. 6 is a diagram for explaining an operation failure when the difference Δd in the processing delay amount is large. As shown in FIG. 6, here, delay2> delay1, and the difference Δd (= Δd2) is one frame of video data Vid1-b and Vid2-b (here, 1/30 second). Consider the case of exceeding.
In this case, the video data Vid1-b from the first scaler 32 may be continuously supplied to the second processing unit 35 for two frames (in the example of FIG. 6, the (2n-1) th frame and (2n + 1) th frame). In this case, when the second processing unit 35 outputs the video data Vid1-b and the video data Vid2-b in the order supplied to the own device, the frame order in the video data Vo is (2n-1). ), (2n + 1), 2n, (2n + 3), (2n + 2), (2n + 5), (2n + 4) frames, and so on, which are different from the frame order in the input video data Vid-in. The second processing unit 35 may perform the output process of the video data Vo as follows based on the difference Δd so that this type of operation failure does not occur.

FIG. 7 is a block diagram illustrating a hardware configuration of another example of the video processing circuit 30. As shown in FIG. 7, the video processing circuit 30 includes a first processing unit 31, a first scaler 32, a second scaler 33, a CPU 34, a second processing unit 35, and a frame memory 36. The first processing unit 31, the first scaler 32, the second scaler 33, the CPU 34, and the second processing unit 35 may have the same hardware configuration as that of the video processing circuit 30 shown in FIG.
The frame memory 36 is a memory having a storage area for storing video data for one frame. The frame memory 36 stores the video data supplied from the second processing unit 35 or supplies the stored video data to the second processing unit 35 under the control of the CPU 34.

FIG. 8 is a timing chart showing time-series changes of the video data Vo output by the second processing unit 35 shown in FIG. As shown in FIG. 8, the case where the difference Δd = Δd2 is considered here as in the case shown in FIG.
When the video data Vid1-b of the (2n-1) th frame is supplied, the second processing unit 35 outputs this to the image projection unit 10. Next, the video data Vid1-b of the (2n + 1) th frame is supplied to the second processing unit 35. Here, based on the difference Δd, the second processing unit 35 stores the video data Vid1-b of the (2n + 1) th frame in the frame memory 36 without outputting it to the image projection unit 10 (see “Procedure of FIG. 8”). a "). Next, when the second n-th frame video data Vid2-b is supplied from the second scaler 33, the second processing unit 35 converts the video data Vid2-b into the (2n-1) -th frame video data Vid1-b. The data is output following b (“procedure b” in FIG. 8).

  When the video data Vid1-b of the second n frame is output, the second processing unit 35 reads the video data of the (2n + 1) frame from the frame memory 36 and outputs it to the image projection unit 10 (“Procedure c” in FIG. 8). "). Here, the second processing unit 35 outputs the video data of the (2n + 1) th frame from the output of the video data Vid2-b of the second n frame to the output of the video data of the next frame. 10 may be output.

Thereafter, the operation described above is repeated in the second processing unit 35.
For example, the second processing unit 35 outputs the video data Vid1-b of the (2n + 1) th frame to the image projecting unit 10, and then receives the video data Vid1-b of the (2n + 3) th frame. Without being output to the projection unit 10, it is stored in the frame memory 36 ("procedure d" in FIG. 8). The storage of the video data Vid1-b here may be performed by overwriting the video data of the (2n + 1) th frame that has already been read.

Next, when the video data Vid2-b of the (2n + 2) th frame is supplied from the second scaler 33, the second processing unit 35 uses the video data Vid2-b as the video data Vid1 of the (2n + 1) th frame. Subsequent to -b, the image is output to the image projection unit 10 ("procedure e" in FIG. 8). When the video data Vid1-b of the (2n + 2) th frame is output, the second processing unit 35 reads the video data of the (2n + 3) th frame from the frame memory 36 and outputs it to the image projection unit 10 (FIG. 8). "Procedure f"). Here, the second processing unit 35 outputs the video data of the (2n + 3) th frame from the output of the video data Vid2-b of the (2n + 2) th frame to the output of the video data of the next frame. Read from 36 and output.
By the output processing of the above procedure, the video processing circuit 30 can output the video data Vo without changing the frame order even when the difference Δd exceeds the processing delay amount for one frame. it can.

  As described above, in the projector 1, the input video data is supplied alternately to the two scalers sequentially in the frame order, and the video data after the upscaling processing is performed by each scaler is synthesized. ,Output. For example, in a scaler that upscales 1080p video data to 4K2K video data, the input / output frame frequency may be limited to 30 Hz. Even in this case, according to the projector 1, the 1080p input video data having a frame frequency of 60 Hz can be substantially upscaled to 4K2K video data having a frame frequency of 60 Hz to display the video. it can.

Further, in the projector 1, by using a scaler that can measure the processing delay amount of the own device, based on the difference in the processing delay amount actually measured by each scaler, the frame of the video data frame after the upscaling process is processed. The order can be defined.
Further, even if the processing delay amount in one scaler is larger than the processing delay amount in the other scaler, the projector 1 uses the frame memory to adjust the output timing of the video data of each frame ( In other words, it is possible to prevent the frame order of the video data after the upscaling process from being defined in a different frame order from the input video data.

In addition, the present invention can be implemented in a form different from the above-described embodiment. The following modifications may be combined as appropriate.
In the above-described embodiment, the video processing circuit 30 upscales 1080p video data to 4K2K video data, but the resolution (number of pixels) of the video data before and after the upscaling is not limited to this example.
For example, the video processing circuit 30 may upscale the resolution of input video data representing a 480i composite video signal or S terminal video to video data having a resolution such as 720p, 1080i, or 8K4K. In the present invention, it is possible to perform upscaling according to the function of the scaler and output the video data after the upscaling process. In the present invention, the specific algorithm of the upscaling process is not particularly limited.

  In the video processing circuit 30 of the above-described embodiment, the first scaler 32 and the second scaler 33 each have a function of measuring the processing delay amount in the own apparatus and supplying the measurement result to the CPU 34. On the other hand, the first scaler 32 and the second scaler 33 may not have a processing delay amount measurement function. For example, if the control is performed by the CPU 34 so that the difference Δd in the processing delay amount between the first scaler 32 and the second scaler 33 does not exceed the processing delay amount for one frame, the processing delay amount measurement function by the scaler is provided. Even if it is not used, it is possible to output the video data while maintaining the frame order.

  Even if it is assumed that the difference Δd in processing delay amount between the first scaler 32 and the second scaler 33 is equal to or greater than 2 frames, the projector 1 can store video data equal to or greater than 2 frames. By using the memory, the video data Vo can be output in the order of frames in the input video data Vid-in.

  Further, when the second processing unit 35 can perform the output process of the video data Vo based on the difference Δd without the control of the CPU 34, the CPU 34 only notifies the second processing unit 35 of the difference Δd. Good.

  In the information processing apparatus of the present invention, upscaling processing may be performed by operating three or more scalers in parallel. Even in this case, paying attention to the two scalers of the information processing apparatus according to the present invention, the first processing unit sequentially supplies the input video data to the two scalers sequentially according to the frame order. The second processing unit outputs the video data respectively supplied by the two scalers after the upscaling process in the same frame order as the input video data based on the processing delay amount in these two scalers.

Further, the detailed configuration of the video processing circuit 30 is not limited to that described with reference to FIGS. A part of the video processing circuit 30 described with reference to FIG. 2 may be omitted, or a processing unit not shown in FIG. 2 may be added.
Further, the functions realized by the information processing apparatus of the present invention can be realized by either hardware resources or software resources, or by their cooperation. For example, the present invention can be provided as a program executed by a computer.

  Further, the projector 1 is not limited to one having a plurality of light valves 13 corresponding to each color component. The projector 1 may have a single light valve 13. In this case, a color corresponding to each pixel is set using an optical filter or the like. The light valve 13 is not limited to the one using a transmissive liquid crystal panel. The projector 1 may use a reflective liquid crystal panel, an electro-optical element other than liquid crystal such as an organic EL (Electro-Luminescence) panel, or a digital mirror device. The light source 11 may be a solid light source such as an LED (Light Emitting Diode) or a laser.

  The display device of the present invention is not limited to a projector. The display device of the present invention may be a television, a car navigation device, a video phone, a digital still camera, a mobile phone, a smartphone, a tablet terminal, a personal computer, or the like.

DESCRIPTION OF SYMBOLS 1 ... Projector, 10 ... Image projection part, 20 ... Signal input part, 30 ... Image processing circuit, 31 ... 1st processing part, 32 ... 1st scaler, 33 ... 2nd scaler, 34 ... CPU, 35 ... 2nd process 36, frame memory.

Claims (8)

A first scaler and a second scaler for performing upscaling of the supplied video data;
A first processing unit that alternately supplies input video data of a plurality of frames continuous on a time axis to the first scaler and the second scaler sequentially according to the order of the frames;
When the upscaling processing of the video data supplied by the first processing unit is performed by the first scaler and the second scaler, the processed video data is processed in the first scaler and the second scaler. And a second processing unit that outputs the frames in the order of the frames based on the delay amount. Each of the first scaler and the second scaler measures the processing delay amount in its own machine,
The second processing unit includes:
The video data after the processing is output in the order of the frames based on a difference between the processing delay amount measured by the first scaler and the processing delay amount measured by the second scaler. The video processing apparatus according to 1. With frame memory,
When the difference in the processing delay amount between the first scaler and the second scaler exceeds a threshold,
The second processing unit includes:
The video data after the processing by one of the first scaler and the second scaler with the smaller processing delay amount is stored in the frame memory, and is read out and output at a timing according to the difference. 2. The video processing apparatus according to 2. The video processing apparatus according to any one of claims 1 to 3, wherein the input video data is 1080p video data having a frame frequency of 60 Hz. The video processing apparatus according to claim 4, wherein the processed video data is 4K2K video data. A first scaler and a second scaler for performing upscaling of the supplied video data;
A first processing unit that alternately supplies input video data of a plurality of frames continuous on a time axis to the first scaler and the second scaler sequentially according to the order of the frames;
When the upscaling processing of the video data supplied by the first processing unit is performed by the first scaler and the second scaler, the processed video data is processed in the first scaler and the second scaler. A second processing unit for outputting in the order of the frames based on a delay amount;
A display unit configured to display a video based on the video data output by the second processing unit. The first scaler and the second scaler that perform the upscaling processing of the supplied video data are sequentially supplied with a plurality of frames of input video data that are continuous on the time axis, according to the order of the frames, and the first scaler. When the upscale processing of the supplied video data is performed by the second scaler,
A semiconductor device that outputs the processed video data in the order of the frames based on processing delay amounts in the first scaler and the second scaler. A video processing method using a first scaler and a second scaler for performing upscaling processing of supplied video data,
Sequentially supplying input video data of a plurality of frames continuous on the time axis to the first scaler and the second scaler sequentially according to the order of the frames;
When the upscale processing of the supplied video data is performed by the first scaler and the second scaler, the processed video data is processed based on processing delay amounts in the first scaler and the second scaler. And a step of outputting in the order of the frames.

Images