JP2014135433A - Light-emitting element manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a light-emitting element having high luminous efficiency.SOLUTION: A light-emitting element manufacturing method comprises: forming a reflective layer 32 between a support substrate 100 and a semiconductor layer 20 so as to cover an entire surface of an n-type layer 21 including an n-side ohmic electrode 31. Even though the reflective layer 32 also serves as an electrode for the n-type layer 21, unlike the n-side ohmic electrode 31, the reflective layer 32 is composed of a material having high reflectance against light emitted from the semiconductor layer 20. As a result, the reflective layer 32 is inferior in a function (contact resistance and ohmic characteristics) as an electrode to the n-side ohmic electrode 31. The above-described structure is joined to the support substrate 100 via a support substrate side joining layer (joining layer) 101 and a semiconductor layer side joining layer (joining layer ) 33.

Description

  The present invention relates to a light emitting device using a group III nitride semiconductor formed by epitaxial growth and a method for manufacturing the same.

  Group III nitride semiconductors typified by GaN, AlGaN, and InAlGaN have wide band gaps, and therefore, materials for light emitting devices such as LEDs (light emitting diodes) such as blue and ultraviolet light and LDs (laser diodes) and power devices Is widely used. Since a group III nitride semiconductor substrate is expensive and not easily available, it is common to heteroepitaxially grow this compound semiconductor on a different substrate such as a sapphire substrate.

  The group III nitride semiconductor is usually formed by epitaxial growth in the order of an n-type layer, a light emitting layer, and a p-type layer after forming a buffer layer on the substrate. It is not impossible to form the layers sequentially from the p-type layer, but it is not general because a plurality of problems such as activation of the p-type layer and impurity diffusion occur. However, the sapphire that is the substrate in this configuration is insulative. In addition, since the p-type layer which is the uppermost layer has a lower mobility of charge carriers than the n-type layer, it is necessary to reduce the thickness and reduce the layer resistance. Due to these factors, when an LED or the like is manufactured in a state where this laminated structure is maintained, a great limitation is imposed on the layout. For example, it is necessary to provide both the p-side electrode and the n-side electrode on the surface opposite to the sapphire substrate. In this case, the location where these electrodes are provided does not contribute to light emission, so it is difficult to ensure an effective light emission area.

  For this reason, a laminated structure composed of an n-type layer, a light emitting layer, and a p-type layer is sequentially grown on the sapphire substrate, the p-type layer side is bonded to another substrate, and then the sapphire substrate is peeled and removed. A technique has been proposed in which a bonded substrate is used as a support substrate having a laminated structure. As a technique for peeling and removing the sapphire substrate, laser lift-off using laser light irradiation (for example, Patent Document 1), chemical lift-off for chemically removing the buffer layer (lift-off layer) between the sapphire substrate and the n-type layer ( For example, Patent Document 2) is known.

  If these technologies are used, the back surface of the n-type GaN layer (the surface on which the sapphire substrate is present) can be exposed, and a new support substrate should be either insulating or conductive. This increases the degree of freedom in layout. In particular, by forming an electrode on the entire surface of the p-type layer side, the electrode resistance on the p-type layer side is lowered, and by forming the electrode on a part of the surface of the n-type layer having a low resistivity, Lowered LEDs can be obtained. In this case, as described in Patent Document 3, if the support substrate is conductive, the support substrate can be used as the wiring on the p-type layer side. In this case, the light emitted from the LED is extracted from the surface of the n-type layer.

  In this way, by using laser lift-off or chemical lift-off, an LED having a substantial light emitting area can be obtained.

JP 2002-185039 A JP 2009-54888 A JP 2000-277804 A

  In the above configuration, the p-type layer side is bonded to the support substrate. In practice, however, the electrode formed on the surface of the p-type layer is connected to the support substrate side via a bonding layer such as solder or gold. This is done by joining. At this time, as the material of the p-side ohmic electrode, a layer of Ni and Au that makes ohmic contact with the p-type layer (Ni / Au), ITO or the like is used, and as the solder, for example, an Au—Sn alloy or the like is used. In the case of bonding between similar metals such as Au, these are bonded by hot pressing. In this case, the characteristics of the LED may be adversely affected due to heat applied at the time of bonding and heating necessary for subsequent ohmic contact.

  Although the mechanism for generating such adverse effects is not clear, for example, the heating necessary for bonding exceeds the optimum amount of heat for ohmic contact, or the metal such as Sn in the bonding layer is mixed with Ni / Au or ITO to make ohmic contact. It is conceivable that the bonding is inhibited or the activation rate of the acceptor in the p-type layer is changed by the movement of hydrogen. In this case, when the forward voltage Vf of the LED increases as a whole and the electrode resistance locally increases, a light emission abnormality such as partial light emission (light emission unevenness) occurs.

  As a result of diligent research by the inventors, the adverse effects such as the above-described abnormal light emission are caused by the fact that the electrode formed on the surface of the p-type layer is bonded to a support substrate or the like via a bonding layer of metal or the like, This phenomenon occurs remarkably when the p-type ohmic electrode is heated while being sandwiched between the substrate and the like, and the electrode formed on the surface of the p-type layer is not bonded to the support substrate or the like via a bonding layer such as metal. When the p-type ohmic electrode was heated in the state, it was found that it hardly occurred. Therefore, in a conventional vertical light emitting device structure in which a support substrate is bonded to the p-type layer side, it is actually difficult to stably supply an LED having a large substantial light emitting area and high luminous efficiency. there were.

  The present invention has been made in view of such problems, and an object thereof is to provide an invention that solves the above problems.

In order to solve the above problems, the present invention has the following configurations.
The light emitting device of the present invention has a laminated structure including an n-type group III nitride semiconductor layer, a light emitting layer, and a p-type group III nitride semiconductor layer, and the n-type group III nitride semiconductor layer is a bonding layer. And a reflection layer provided between the n-type group III nitride semiconductor layer and the bonding layer, and is configured to emit light from the main surface side of the p-type group III nitride semiconductor layer. It is characterized by emitting.
In the light emitting device of the present invention, the reflective layer is made of a metal or a dielectric multilayer film.
The light emitting device of the present invention further includes an n-side ohmic electrode locally formed in contact with the n-type group III nitride semiconductor layer between the n-type group III nitride semiconductor layer and the bonding layer. It is characterized by doing.
In the light emitting device of the present invention, the reflective layer and the n-type group III nitride semiconductor layer are in contact with the n-type group III nitride semiconductor layer and do not overlap with the n-side ohmic electrode. And a reflective underlayer that transmits the light.
In the light emitting device of the present invention, the reflective underlayer includes a single crystal AlN buffer layer used during the growth of the stacked structure and formed between the growth substrate and the n-type group III nitride semiconductor layer. It is characterized by that.
The light emitting device of the present invention is characterized in that a dielectric layer is provided at least on the reflective layer side in the reflective underlayer.
In the light-emitting element of the present invention, the reflective layer contains ruthenium (Ru), rhodium (Rh), molybdenum (Mo), or aluminum (Al).
In the light emitting device of the present invention, the reflective layer has a multilayer structure made of a dielectric, and the dielectric includes at least SiO ₂ , HfO ₂ , Sc ₂ O ₃ , TiO ₂ , Al ₂ O ₃ , and SiN. It is characterized by that.
The light emitting device of the present invention includes a p-side ohmic electrode formed on the p-type group III nitride semiconductor layer, partially transmitting light emitted from the semiconductor layer or having a mesh shape, and the p-side ohmic electrode. A p-side electrode locally covering and in contact with the p-side ohmic electrode.
The method for manufacturing a light-emitting device according to the present invention has a laminated structure including an n-type group III nitride semiconductor layer, a light-emitting layer, and a p-type group III nitride semiconductor layer, and the n-type group III nitride semiconductor layer Is a method of manufacturing a light emitting device having a structure in which a laminated structure is bonded to a support substrate via a bonding layer, the stacked structure being formed on the first substrate via a lift-off layer, and the n-type group III nitride semiconductor layer A growth step of forming the light emitting layer and the p-type group III nitride semiconductor layer in this order, and a main surface side of the p-type group III nitride semiconductor layer is joined to a second substrate via an intervening layer. 1 bonding step, a first peeling step of removing the lift-off layer and peeling the first substrate from the laminated structure, and a main surface side of the n-type group III nitride semiconductor layer in the laminated structure, n Forming the side ohmic electrode locally; A reflective layer forming step of forming a reflective layer that reflects light emitted from the optical layer, a second bonding step of bonding the support substrate to the reflective layer via a bonding layer, and removing the intervening layer And a second peeling step for peeling the second substrate from the semiconductor layer.
The method for manufacturing a light emitting device according to the present invention is characterized in that the thermal expansion coefficient of the second substrate at room temperature is in the range of 4 × 10 ^{−6 to} 7 × 10 ⁻⁶ / K.
The method for manufacturing a light emitting element according to the present invention is characterized in that the first substrate and the second substrate are made of the same material.
The method for manufacturing a light emitting element according to the present invention is characterized in that sapphire is the main body of the first substrate and the second substrate.
The method for manufacturing a light emitting device according to the present invention is characterized in that the intervening layer is made of a polyimide resin material.
The method for manufacturing a light emitting device of the present invention is characterized in that the thickness of the intervening layer is 0.3 μm or more and 5.0 μm or less.
In the method for manufacturing a light emitting device according to the present invention, the n-side ohmic electrode is locally formed on the exposed surface of the n-type group III nitride semiconductor layer between the first peeling step and the reflective layer forming step. A side ohmic electrode forming step, wherein in the reflecting layer forming step, the reflecting layer is formed at least on the surface of the n-type group III nitride semiconductor layer where the n-side ohmic electrode is not formed.
The method for manufacturing a light emitting device of the present invention is characterized in that, in the reflective layer forming step, the reflective layer is formed with a reflective base layer interposed between the n-type group III nitride semiconductor layer.
The method for manufacturing a light emitting device according to the present invention is characterized in that a p-side ohmic electrode is formed on a main surface side of the p-type group III nitride semiconductor layer between the growth step and the first bonding step.
In the method for manufacturing a light emitting device of the present invention, after the second peeling step, the stacked structure is locally etched from the main surface side of the p-type group III nitride semiconductor layer, so that the main surface side a semiconductor layer etching step for locally exposing any one of the n-type group III nitride semiconductor layer, the reflective layer, and the bonding layer; and the n-type group III nitride semiconductor locally exposed on the main surface side An n-side electrode forming step of forming an n-side electrode on the surface of any one of the layer, the reflective layer, and the bonding layer.

  With the above structure, a light-emitting element with high emission efficiency can be obtained.

It is sectional drawing which shows the structure of the light emitting element which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the 1st modification of the light emitting element which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the 2nd modification of the light emitting element which concerns on embodiment of this invention. It is process sectional drawing which shows the 1st example of the manufacturing method of the light emitting element which concerns on embodiment of this invention. It is process sectional drawing (continuation) which shows the 1st example of the manufacturing method of the light emitting element which concerns on embodiment of this invention. It is process sectional drawing which shows the 2nd example of the manufacturing method of the light emitting element which concerns on embodiment of this invention. It is process sectional drawing (continuation) which shows the 2nd example of the manufacturing method of the light emitting element which concerns on embodiment of this invention. It is process sectional drawing which shows the 3rd example of the manufacturing method of the light emitting element which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the other example of the 2nd board | substrate used in the manufacturing method of the light emitting element which concerns on embodiment of this invention.

  Hereinafter, an example of the light emitting element according to the embodiment of the present invention will be described. In this light emitting element, a semiconductor layer made of a group III nitride semiconductor is used. The semiconductor layer has a stacked structure including an n-type group III nitride semiconductor layer (n-type layer), a light emitting layer, and a p-type group III nitride semiconductor layer (p-type layer). A support substrate different from the growth substrate used for the growth of the semiconductor layer is bonded to the n-type layer side, and light emission is extracted from the p-type layer side. The growth substrate has a configuration in which it is replaced with another support substrate, and two bonding steps are required for this configuration. Note that a vertical light-emitting element that emits light when a current flows between the support substrate side and the upper portion of the semiconductor layer through a bonding layer will be described as an example. If a bonding layer of the same type as that of the vertical type is used, a horizontal light emitting element having two electrodes p and n on the same side without passing a current on the supporting substrate side may be used.

  FIG. 1 is a cross-sectional view showing the structure of the light emitting element 10. Here, in the light emitting element 10, the semiconductor layer 20 is formed on the support substrate 100.

  The semiconductor layer 20 includes an n-type AlGaN layer (n-type group III nitride semiconductor layer, hereinafter referred to as n-type layer) 21, a light emitting layer 22, and a p-type AlGaN layer (n-type group III nitride) in order from the lower side in FIG. A semiconductor layer (hereinafter referred to as a p-type layer) 23 is formed. This order is the same as that in the case of growing the laminated structure from the growth substrate. The thicknesses of the n-type layer 21 and the p-type layer 23 are, for example, about 2 to 6 μm and about 0.1 to 1 μm, respectively, and the p-type layer 23 is thinner than the n-type layer 21. The light emitting layer 22 is a layer having a single quantum well, a multiquantum well structure, or the like made of a heterostructure of a group III nitride semiconductor. Hereinafter, the case where the quantum well type AlGaN-based light emitting layer 22 emitting deep ultraviolet light having a wavelength of 340 nm is used will be described as an example. The configuration of the semiconductor layer 20 including the light emitting layer 22 is appropriately selected depending on the emission wavelength.

  Here, an n-side ohmic electrode 31 is formed on the surface of the n-type layer 21 on the lower surface (one main surface) of the semiconductor layer 20 in FIG. The n-side ohmic electrode 31 is made of a material that makes ohmic contact with the n-type layer 21, but locally covers the surface of the n-type layer 21, and the shape thereof is, for example, a mesh shape or a dot shape Can do. The reason why the shape is locally covered is that if the entire surface is formed, the effects of the reflective layer described below cannot be sufficiently exhibited.

  Further, a reflective layer 32 is formed between the support substrate 100 and the semiconductor layer 20 so as to cover the entire surface (the lower surface in FIG. 1) of the n-type layer 21 including the n-side ohmic electrode 31. Although the reflective layer 32 can also be an electrode for the n-type layer 21, unlike the n-side ohmic electrode 31, the reflective layer 32 is made of a material having a high reflectance of light emitted from the semiconductor layer 20. For this reason, the function (contact resistance and ohmic property) as the electrode is inferior to that of the n-side ohmic electrode 31. When the reflective layer 32 is in contact with the surface of the n-type layer 21, it may be in contact with at least a region where the n-side ohmic electrode 31 is not formed. Alternatively, the reflective layer 32 may be locally formed at a place other than where the n-side ohmic electrode 31 is formed, and the reflective layer 32 may not be provided between the n-side ohmic electrode 31 and the bonding layer. However, in the case of forming a reflective underlayer described later, the reflective underlayer contacts the surface of the n-type layer 21 in a region where the n-side ohmic electrode 31 is not formed.

  The above structure is bonded to the support substrate 100 via the support substrate side bonding layer (bonding layer) 101 and the semiconductor layer side bonding layer (bonding layer) 33. Here, the support substrate side bonding layer 101 is formed on the main surface of the support substrate 100 separated from the above structure, and the semiconductor layer side bonding layer 33 is formed to cover the entire surface of the reflective layer 32. The support substrate side bonding layer 101 and the semiconductor layer side bonding layer 33 are bonded via solder. As the support substrate 100, either a conductive material or an insulating material can be used. In the case of conductivity, electrical connection to the n-side ohmic electrode 31 (n-type layer 21) can be made through the support substrate 100. In the case of an insulating material, a metal wiring may be formed on the surface, or a part of the n-type layer 21 may be exposed by removing a part on the p-type layer 23 side.

  On the other hand, a p-side ohmic electrode 41 is formed on the entire upper surface (the other main surface) of the p-type layer 23 in FIG. The p-side ohmic electrode 41 is made of a material that is substantially transparent and conductive to light emitted from the semiconductor layer 20. A p-side electrode 42 is formed on part of the surface of the p-side ohmic electrode 41. Here, the p-side electrode 42 can be formed thick with a low resistivity material, and its electrical resistance is low. On the other hand, the p-side ohmic electrode 41 is required to have a high transmittance of light emitted from the semiconductor layer 20, and is formed thin so that the transmittance is sufficiently high. Alternatively, in order to substantially improve the transmittance, a configuration in which a large number of openings that transmit light are dispersed may be employed. By combining the p-side ohmic electrode 41 and the p-side electrode 42, they effectively function as electrodes for the p-type layer 23 and are covered with the p-side ohmic electrode 41 and not covered with the p-side electrode 42. The luminescence is taken out from. Electrical connection to the p-type layer 23 is made by performing wire bonding or the like on the p-side electrode 42.

  In this configuration, since the support substrate side bonding layer 101 and the semiconductor layer side bonding layer 33 are bonded via solder, for example, Sn contained in the solder may diffuse to the semiconductor layer 20 side. However, even if Sn is diffused, no adverse effect is observed with respect to ohmic properties and current spread between the n-side electrode and the n-type layer.

  Further, in this configuration, light is emitted mainly in the vertical direction in FIG. 1 over the entire surface of the semiconductor layer 20 (light emitting layer 22). Among these, the light emitted upward is transmitted upward through the p-side ohmic electrode 41 as described above. The structure that blocks this light is only the p-side electrode 42 having a small total area in FIG. On the other hand, since the light emitted downward is reflected by the reflection layer 32 with a high reflectance, it is emitted upward in the same manner as described above. At this time, the n-side ohmic electrode 31 having a low reflectance is meshed or dot-shaped to reduce the total area, and most of the n-side ohmic electrode 31 is covered with the reflective layer 32 having a high reflectance. can do. In this way, the formation of the reflective layer 32 on the n-type layer 21 side can be realized by performing substrate bonding and substrate peeling twice in a manufacturing method described later. In the conventional manufacturing method in which substrate bonding and substrate peeling are performed only once, it is difficult to improve the light emission efficiency (light extraction efficiency) by forming the reflective layer 32 on the n-type layer 21 side. Thus, it is difficult to take a configuration that improves the light extraction efficiency both above and below the semiconductor layer 20.

  For this reason, in this light emitting element 10, especially high luminous efficiency can be obtained. Similarly, a horizontal light emitting element in which a reflective layer is provided between a supporting substrate and a semiconductor layer can be obtained. This configuration will be described later.

In the configuration of FIG. 1, both the n-side ohmic electrode 31 and the reflective layer 32 are in direct contact with the n-type layer 21. Of these, the n-side ohmic electrode 31 needs to be in direct contact with the n-type layer 21 in order to function as an electrode, but the reflective layer 32 is not required to function as an electrode. There is no need for direct contact. For example, another layer (reflective base layer) may be interposed between the reflective layer 32 and the semiconductor layer 20. The reflective underlayer is required to have high light transmittance, but low electrical resistance is not required. Therefore, a transparent insulating layer such as SiO ₂ or SiN _x , a buffer layer used in a manufacturing method described later, and the like Can be used as a reflective underlayer. In this case, the n-type layer 21 can be locally exposed by providing an opening in the reflective underlayer, and the n-side ohmic electrode 31 and the n-type layer 21 can be brought into contact with each other in the opening. In this case, the combination of the reflective layer 32 and the reflective base layer can also be set as appropriate.

In this case, a structure as shown in FIG. In this structure, the n-side ohmic electrode 31 penetrates the reflective layer 32 a and contacts the semiconductor layer-side bonding layer (bonding layer) 33, so that the electricity between the n-type layer 21 and the support substrate-side bonding layer 101 is obtained. Joint can be obtained. For this reason, in this structure, an insulating layer between the upper surface and the lower surface can be used as the reflective layer 32a. For example, as a dielectric multilayer structure having a high reflectivity, SiO ₂ / Al / SiO ₂ , Al ₂ O ₃ / Al / Ai ₂ O ₃ , (HfO ₂ / SiO ₂ ) n / HfO ₂ / (Sc ₂ O ₃ / SiO ₂ ) n / Sc ₂ O ₃ (where n is the number of stacking cycles, for example, n = 5), or the like, a layer having a high reflectance can be used regardless of the electric resistance.

  Or it can also be set as the structure shown by FIG. 3 using the reflective base layer 32b. In this case, the reflective base layer 32b is locally removed, and the n-side ohmic electrode 31 is formed therein. Various materials having high light transmittance can be used for the reflective base layer 32b, but at least the dielectric layer similar to the above is provided on the reflective layer 32 side to increase the reflectance. It is preferable from the viewpoint. Further, a buffer layer (for example, AlN) described later can also be used as the reflective underlayer.

  The light emitting element 10 can be manufactured with a high yield by the manufacturing method described below. 4 and 5 are process cross-sectional views illustrating a method for manufacturing the light emitting element 10. In this manufacturing method, three types of substrates of the semiconductor layer 20 are used: a first substrate (growth substrate), a second substrate (transfer substrate), and a third substrate (support substrate). Here, the first substrate and the second substrate are used only during the manufacturing process and then removed. The third substrate is the support substrate 100, and is used as it is in the light-emitting element 10 after manufacture. Here, a case where two light emitting elements 10 are manufactured using a single support substrate 100 will be described.

  Here, first, as shown in FIG. 4A, an n-type layer 21, a light emitting layer 22, a p is formed on a first substrate (growth substrate) 50 via a lift-off layer 51 and a buffer layer 52. The mold layer 23 is sequentially grown (growth process).

  Here, as the first substrate (growth substrate) 50, the n-type layer 21 made of a highly crystalline group III nitride semiconductor (GaN or the like) can be epitaxially grown via the lift-off layer 51 and the buffer layer 52. For example, a sapphire substrate ((0001) substrate) can be used. The thickness is, for example, about 430 μm.

  As the lift-off layer 51, a material capable of crystal growth on the semiconductor layer 20 and capable of being chemically etched is used, and a material capable of peeling the semiconductor layer 20 from the growth substrate 50 by chemical lift-off later is used. As this material, for example, scandium (Sc) can be used, and can be formed on the growth substrate 50 by a sputtering method, a vacuum deposition method, or the like. Thereafter, the lift-off layer 51 is nitrided by performing heat treatment in an ammonia atmosphere to form a scandium nitride (ScN) layer. Instead of scandium nitride, crystallized hafnium, zirconium, or chromium nitride (CrN) may be used.

  Next, a buffer layer 52 serving as a base for forming a favorable crystalline semiconductor layer 20 is first formed on the lift-off layer 51. As the buffer layer 52, GaN, AlGaN, or AlN can be used depending on the application, but AlN is preferable. Thereafter, an n-type layer 21 (n-type GaN layer), a light emitting layer 22 (n-type AlGaN layer or the like), and a p-type layer 23 (p-type GaN layer or p-type AlGaN layer) are sequentially formed. Any of these can be formed by the MOCVD method or the like, and these can be continuously grown in the same reaction furnace by appropriately switching the reaction gas and temperature. The buffer layer 52, the n-type layer 21, and the p-type layer 23 have thicknesses of about 20 nm, 2500 nm, and 300 nm, respectively. The light-emitting layer 22 has a single quantum well structure, a multi-quantum well structure, or the like from which good light emission characteristics can be obtained, and the thickness is appropriately set according to the structure. Here, the p-type layer 23 is made thinner than the n-type layer 21. This configuration is also the same as the general configuration described in Patent Document 2 and the like.

Next, as illustrated in FIG. 4B, the SiO ₂ layer 53 is formed at a position to be the light emitting region (the semiconductor layer 20 in the light emitting element 10). For this purpose, the SiO ₂ layer 53 is first formed on the entire surface of the p-type layer 23 by the CVD method or the like, and then a photoresist pattern is formed at a position to be a light emitting region using photolithography. Thereafter, etching (wet etching, dry etching) is performed using this photoresist pattern as a mask, and the photoresist layer may be removed after removing the SiO ₂ layer 53 except for the portion to be the light emitting region.

Thereafter, as shown in FIG. 4C, dry etching from the p-type layer 23 to the lift-off layer 51 is performed using the SiO ₂ layer 53 as a mask (element isolation step). At this time, etching can be performed by appropriately switching the etching gas according to each layer to be etched. Note that the photoresist layer may remain at this point. For example, when sapphire is used as the growth substrate 50, since sapphire is a difficult-to-etch material, this etching stops at the surface of the growth substrate 50, and the p-type layer 23, the light emitting layer 22, the n-type layer 21, and the buffer. The side surfaces of the layer 52 and the lift-off layer 51 are exposed.

Next, as shown in FIG. 4D, a polyimide layer (intervening layer) 54 is formed on the SiO ₂ layer 53 by a method such as coating or printing. In FIG. 4D, the polyimide layer 54 is formed so as to cover the entire surface of the SiO ₂ layer 53. The thickness is preferably 0.3 μm to 5 μm, more preferably 1 μm to 5 μm, for example, about 2 μm. If the thickness is less than 0.3 μm, the amount required for bonding may be insufficient. If the thickness exceeds 5 μm, the polyimide layer has flexibility and high thermal expansion (about 25 × 10 ⁻⁶ / K). In addition, even when the first substrate and the second substrate have a small difference in thermal expansion coefficient or are made of the same material as described later, the gap between the first substrate 50 and the semiconductor layer 20 at the time of lift-off is set. Internal stress cannot be offset and cracks are likely to occur in the semiconductor layer during lift-off. The polyimide layer 54 is cured by, for example, a temperature of about 225 ° C. after being formed by coating or printing.

  As described above, the intervening layer is required to have an adhesive force and hardness to obtain an effect of canceling the internal stress due to the thermal expansion coefficient of the second substrate. The material for the intervening layer is most preferably a polyimide resin. Although a softer resin than polyimide and a resin having low heat resistance, such as silicon and resist, can be manufactured in the same manner, the semiconductor layer is likely to crack regardless of its thickness.

On the other hand, as shown in FIG. 4E, a second substrate (transfer substrate) 60 is prepared separately from the above structure. As the second substrate 60, a substrate in which a polyimide layer (intervening layer) 62 is formed on a second substrate main body 61 as a main body can be used. The second substrate main body 61 is a material that can mechanically support the semiconductor layer 20 and has a small difference in thermal expansion coefficient between the first substrate 50 and the group III nitride semiconductor layer 20. Any material (for example, 4 × 10 ^{−6 to} 7 × 10 ⁻⁶ / K material) can be used, but the same material as the growth substrate 50 (sapphire, etc.) is particularly preferably used.

  Next, as shown in FIG. 4F, the structure of FIG. 4D and the second substrate 60 are bonded by thermocompression bonding so that the polyimide layer 54 and the polyimide layer 62 are in contact (first). Joining process). The temperature at this time is higher than the cure temperature, but is 250 to 300 ° C., which is a range in which complete imidization is not performed. As a result, the polyimide layer 54 and the polyimide layer 62 are joined and solidified.

  In this state, as shown in FIG. 4G, the lift-off layer 51 is removed by wet etching using hydrochloric acid, nitric acid or the like, and the growth substrate 50 is peeled off (first peeling step). This process is the same as the chemical lift-off described in Patent Document 2. In FIG. 4G and subsequent figures, the vertical direction of the semiconductor layer 20 is shown reversed from that up to FIG.

  Next, as shown in FIG. 4H, the buffer layer 52 is removed by dry etching. As a result, the surface that was on the growth substrate 50 side in the n-type layer 21 in FIG. 4A is exposed. At this time, the n-type layer 21 directly under the buffer layer 52 in FIG. 4G is also etched, but the etching amount of the n-type layer 21 can be reduced by controlling the etching time. Further, when the etching surface is roughened by adjusting the dry etching conditions, the output can be increased. At this time, the exposed polyimide layer 62 may also be etched. In addition, when the buffer layer 52 is used as the reflective base layer 32b, it is not necessary to remove the buffer layer 52 over the entire surface, and only locally at the place where the n-side ohmic electrode 31 to be formed later is provided. Remove it.

  Thereafter, as shown in FIG. 4I, a mesh-like or dot-like n-side ohmic electrode 31 is formed on the exposed surface of the n-type layer 21 (n-side ohmic electrode forming step). The n-side ohmic electrode 31 is Ti / Al / Cr that makes ohmic contact with the n-type layer 21 and has a small contact resistance (a laminated structure including a Ti layer, an Al layer, and a Cr layer in this order from the n-type layer 21 side). Is used. The electrode having this configuration is effective in that it makes electrical contact with the n-type layer 21, but its reflectivity is not high in that it reflects light emitted from the semiconductor layer 20. Note that the pattern of the n-side ohmic electrode 31 does not have to be a mesh or a dot, as long as the contact resistance with the n-type layer 21 is low and the area covered by the n-type layer 21 can be reduced. The shape is arbitrary. The n-side ohmic electrode 31 can be formed by, for example, forming a resist pattern by photolithography, forming a film of the above material by a method such as vacuum deposition, and then removing the resist pattern.

Next, as shown in FIG. 4J, the reflective layer 32 and the semiconductor layer side bonding layer 33 are formed so as to cover the surface of the n-type layer 21 including the n-side ohmic electrode 31 (reflective layer forming step). . Unlike the n-side ohmic electrode 31, the material of the reflective layer 32 is ruthenium (Ru) as a conductive material that is inferior in electrode characteristics with respect to the n-type layer 21 but has a high reflectance with respect to light emitted from the semiconductor layer 20. Metal materials such as rhodium (Rh), Mo (molybdenum), W (tungsten), and Al (aluminum) can be used. Alternatively, when conductivity is not required like the reflective layer 32a in FIG. 2, a multilayer film including a dielectric layer made of SiO ₂ , HfO ₂ , Sc ₂ O ₃ , TiO ₂ , Al ₂ O ₃ , SiN, or the like. A structure can be used.

  Further, when the reflective layer 32 has a multilayer structure, a layer having a barrier property against diffusion of tin (Sn) or the like, which is a constituent element of solder, is inserted into the reflective layer 32 so that the solder becomes the semiconductor layer 20. It is possible to further reduce the adverse effect on the. As a material constituting the layer having a barrier property, for example, chromium (Cr) or the above-described dielectric material can be used.

  As the semiconductor layer side bonding layer 33, Au that can be easily and firmly bonded using solder is particularly preferably used.

  In FIG. 4J, the reflective layer 32 and the semiconductor layer side bonding layer 33 cover the entire surface of the n-type layer 21, but it is not necessary to cover the entire surface as long as a sufficient light emitting area can be secured. Further, in the case where sufficient bonding strength can be obtained without the semiconductor layer side bonding layer 33 after the second bonding step described later, the semiconductor layer side bonding layer 33 is not necessary.

  Next, as shown in FIG. 5 (k), a structure in which a support substrate side bonding layer 101 is formed on a support substrate (third substrate) 100 is created separately from the above structure. As the support substrate 100, a substrate made of a conductive material and having sufficient mechanical strength can be used. As the support substrate side bonding layer 101, Au can be used similarly to the semiconductor layer side bonding layer 33. However, in order to improve the adhesion between the support substrate side bonding layer 101 and the support substrate 100, a layer made of another metal material may be appropriately inserted between them.

  After that, as shown in FIG. 5 (l), the structure of FIG. 4 (j) and the structure of FIG. 5 (k) are joined by joining the semiconductor layer side joining layer 33 and the support substrate side joining layer 101. , Integrated (second joining step). For this bonding, for example, solder can be used. As a solder material, for example, a gold (Au) -tin (Sn) alloy can be used.

  Next, as shown in FIG. 5M, the polyimide layers (intervening layers) 54 and 62 are wet-etched using alkaline trimethylammonium hydride (TMAH), dilute sulfuric acid, sulfuric acid / hydrogen peroxide, or the like. Thus, the second substrate 60 (second substrate main body 61) can be peeled again from the semiconductor layer 20 or the like (second peeling step). In FIG. 5 (m) and thereafter, the vertical direction of the semiconductor layer 20 is again shown as the same direction as in FIGS. 4 (a) to 4 (d).

after that. As shown in FIG. 5N, the exposed SiO ₂ layer 53 is removed by wet etching. As a result, the surface of the p-type layer 23 is exposed.

  Thereafter, as shown in FIG. 5 (o), the p-side ohmic electrode 41 is formed on the exposed surface of the p-type layer 23 (p-side ohmic electrode forming step). As a material constituting the p-side ohmic electrode 41, a Ni / Au layer (a nickel (Ni) layer from the side close to the p-type layer 23) thin enough to have a sufficiently high light transmittance or having a plurality of fine openings. , A multilayer structure in which gold (Au) layers are sequentially formed) or ITO (Indium Tin Oxide), IMO (Indium Molybdenum Oxide), IZO (Indium Zinc Oxide), GZO (Galium Zinc Oxide), AZO (Aluminum Zinc Ox, etc.) An oxide conductive film can be used. For this reason, the light emitted from the semiconductor layer 20 can pass through the p-side ohmic electrode 41. On the other hand, it is difficult to perform wire bonding or the like on the p-side ohmic electrode 41. In FIG. 5 (o), the p-side ohmic electrode 41 covers the entire surface of the p-type layer 23. However, as in the case of the reflective layer 32 and the like, as long as sufficient light emission characteristics (current diffusibility) can be ensured. It is not necessary to cover the entire surface. Moreover, the material which comprises the p side ohmic electrode 41 can be suitably set according to light emission wavelength, for example, in the case of LED which light-emits visible light, oxide conductive films, such as ITO, are especially effective.

  Next, as shown in FIG. 5 (p), the p-side electrode 42 for external connection is locally formed on the p-side ohmic electrode 41 (p-side electrode forming step). As the p-side electrode 42, a Ti / Au layer having a small resistivity formed with a sufficiently thick layer can be used. The formation method is the same as that of the n-side ohmic electrode 31 described above. Since the light emitted from the semiconductor layer 20 cannot be transmitted through the p-side electrode 42, the light is shielded by this, but a sufficient light emitting area can be ensured by reducing this area. Further, by making the p-side electrode 42 sufficiently thick, wire bonding can be performed thereon.

  Thus, two light emitting elements 10 having the configuration shown in FIG. 1 are manufactured. If these separations are necessary, the support substrate 100 exposed between the two semiconductor layers 20 in FIG. 5 (p) may be cut. Even when three or more light-emitting elements 10 are manufactured, a single growth substrate (first substrate) 50, second substrate 60, and support substrate (third substrate) 100 are used in the same manner. can do.

  In this manufacturing method, a first peeling step (FIG. 4G) for peeling the growth substrate (first substrate) 50 and a second peeling step (FIG. 5) for peeling the second substrate (transfer substrate) 60 are performed. In step (m)), a step of peeling the substrate using wet etching is performed. Here, in particular, the first peeling process is the same process as the chemical lift-off described in Patent Document 2.

  In the laser lift-off described in Patent Document 1 and the chemical lift-off described in Patent Document 2, generally, a semiconductor layer is grown on a growth substrate, and the semiconductor layer is opposite to the growth substrate (the other main surface). The other substrate is firmly bonded to the side) using solder or the like, and then the growth substrate is peeled off to expose one main surface side of the semiconductor layer. In this case, as the growth substrate, sapphire is often used in the same manner as described above from the viewpoint that a semiconductor layer with good characteristics can be obtained. On the other hand, as another substrate, a conductive substrate is often used so that it can be used as a wiring to a p-type layer. For this reason, in general, the other substrate is often made of a material different from that of the growth substrate. In such a case, stress due to the difference between the thermal expansion coefficients of the two is generated, and cracks may occur in the semiconductor layer when performing laser lift-off or chemical lift-off.

  On the other hand, in the first peeling step of the manufacturing method described above, the growth substrate (first substrate) 50 and the main body (second substrate main body 61) of the second substrate 60 are made of the same material (sapphire). be able to. For this reason, even when laser lift-off or chemical lift-off is used in the same manner, there is no difference in thermal expansion coefficient between them. Furthermore, the semiconductor layer 20 and the second substrate main body 61 are bonded via polyimide layers (intervening layers) 54 and 62 having an appropriate thickness capable of maintaining the bonding. For this reason, cracks are unlikely to occur. In the second peeling step, the second substrate main body 61 and the support substrate (third substrate) 100 are made of different materials, but these are bonded via the polyimide layers (intervening layers) 54 and 62. The internal stress of the semiconductor layer 20 is smaller than that through the lift-off layer, and cracks are hardly generated.

  That is, in the above manufacturing method, cracks are unlikely to occur in the semiconductor layer 20 in both the first peeling step and the second peeling step. For this reason, the light emitting element 10 can be manufactured with a high yield.

  In the above example, chemical lift-off is used in the first peeling step, but laser lift-off described in Patent Document 1 or the like can be used instead. In any case, since the growth substrate 50 and the second substrate main body 61 can be reused after peeling, especially when expensive sapphire is used as these materials, the manufacturing cost is reduced by the above manufacturing method. be able to.

  Process sectional drawing of the manufacturing method used as the modification of said manufacturing method is shown in FIG. In this manufacturing method, the p-side ohmic electrode 41 is formed on the p-type layer 23 at an initial stage. As a result, the surface of the p-type layer 23 serving as a surface from which light is extracted is protected by the p-side ohmic electrode 41 during the manufacturing process.

  First, as shown in FIG. 6A, following the formation up to the p-type layer 23 (FIG. 4A), a p-side ohmic electrode 41 is also formed thereon, and heat treatment for forming an ohmic junction is performed. (P-side ohmic electrode forming step).

Thereafter, formation of the SiO ₂ layer 53 (FIG. 6B), element isolation step (FIG. 6C), formation of the polyimide layer 54 (FIG. 6D), preparation on the second substrate 60 side (FIG. 6 (e)), first bonding step (FIG. 6 (f)), first peeling step (FIG. 6 (g)), removal of buffer layer 52 (FIG. 6 (h)), n-side ohmic electrode forming step, Reflection layer forming step (FIG. 6 (i)), second bonding step (FIG. 6 (j)), second peeling step (FIG. 6 (k)), removal of SiO ₂ layer 53 (FIG. 7 (l)), Each of the p-side electrode forming step (FIG. 7 (m)) is performed in the same manner as described above. However, in the element isolation step (FIG. 6C), after the p-side ohmic electrode 41 is first etched, the p-type layer 23 and the like are etched. Since the materials of the p-side ohmic electrode 41 and the p-type layer 23 are greatly different, it is necessary to switch the gas when performing these dry etchings. Etching is particularly easy if the p-side ohmic electrode 41 is made thin.

  As described above, the light-emitting element 10 can also be manufactured by the manufacturing method illustrated in FIGS.

  In addition, a horizontal light-emitting element can be manufactured using the above manufacturing method. Here, unlike the light emitting element 10 described above, the horizontal light emitting element is a light emitting element in which both the p-side electrode for external connection and the n-side electrode for external connection are extracted from the same side of the semiconductor layer. It is. Here, the support substrate is bonded to one main surface side of the semiconductor layer, and both the p-side electrode for external connection and the n-side electrode for external connection are provided on the other main surface side. 8A to 8K are process sectional views showing the manufacturing method in this case. Here, the steps up to the first peeling step (corresponding to FIGS. 4A to 4G) are the same as those in the manufacturing method described above, and thus the description thereof is omitted. FIG. 8A shows a form immediately after the first peeling step.

  As shown in FIG. 8B, the reflective layer 32 and the semiconductor layer side bonding layer 33 are formed on the surface of the buffer layer 52 after the lift-off layer 51 is removed. Here, it is not necessary to establish electrical connection from the surface of the n-type layer 21 on the side where the growth substrate 50 is present to the n-type layer 21, and light emitted from the semiconductor layer 20 passes through the buffer layer 52. Layer 52 may or may not be removed. Further, if the exposed surface at this time is roughened, the output can be increased. However, also in this case, since it is necessary to reflect light on the side where the growth substrate 50 exists, the reflective layer 32 is formed in the same manner as in FIG. Further, in order to bond the side on which the reflective layer 32 is formed to the support substrate 100, the semiconductor layer side bonding layer 33 is formed in the same manner as in FIG. However, unlike FIG. 4J, the n-side ohmic electrode 31 is not formed here.

  Next, as illustrated in FIG. 7C, a structure is formed in which a support substrate side bonding layer 101 is formed on a support substrate (third substrate) 100. This step is the same as in FIG.

  Next, as shown in FIG. 8 (d), the structure of FIG. 8 (b) and the structure of FIG. 8 (c) are bonded to the semiconductor layer side bonding layer 33 and the support substrate side bonding layer 101. (2nd joining process). Thereafter, as shown in FIG. 8E, the polyimide layers 54 and 62 are removed to peel the second substrate 60 from the semiconductor layer 20 and the like again (second peeling step). These steps are the same as those in FIGS. 5 (l) and 5 (m).

Next, as shown in FIG. 8F, the SiO ₂ layer 53 is patterned again so as to have the shape of the light emitting region. This step can be performed in the same manner as the patterning in FIG.

Next, as shown in FIG. 8G, the p-type layer 23 and the light emitting layer 22 in the region where the SiO ₂ layer 53 has been removed are etched to expose the upper surface of the n-type layer 21 in the drawing (semiconductor). Layer etching step). This etching can be performed in the same manner as the etching in FIG. 4C, but this time, the n-type layer 21 remains.

Next, as shown in FIG. 8H, the SiO ₂ layer 53 is removed. This step can be performed in the same manner as in FIG.

  Next, as shown in FIG. 8 (i), after the p-side ohmic electrode 41 is formed on the exposed surface of the p-type layer 23 (p-side ohmic electrode forming step), it is shown in FIG. 8 (j). Thus, the p-side electrode 42 is formed (p-side electrode forming step). These steps are the same as those shown in FIGS.

  Next, as shown in FIG. 8K, the n-side ohmic electrode 31 is formed on the exposed surface of the n-type layer 21 (the upper surface in the drawing). In this light emitting element, unlike the above example, light emission is not extracted from the surface on which the n-type layer 21 is formed. For this reason, the n-side ohmic electrode 31 does not need to have a highly translucent mesh shape or dot shape, and can have, for example, a shape and size that allow wire bonding thereon.

  As described above, a horizontal light emitting device can be manufactured using the first bonding step, the first peeling step, the second bonding step, and the second peeling step in the same manner. Even in this case, the light-emitting element can be manufactured with a high yield because cracks are unlikely to occur in the semiconductor layer, particularly during the first peeling step (removal of the lift-off layer). In addition, since the reflective layer 32 having a high reflectance is formed on the lower side in FIG. 8K, which is the side from which light emission is not extracted, high luminous efficiency can be obtained. Note that the p-side ohmic electrode formation step can be performed after the growth step as in the case of the vertical light-emitting element.

  When the reflective layer 32 and the n-type layer 21 are in ohmic contact, the exposed n-type layer 21 and the buffer layer 52 are completely removed in the semiconductor layer etching step (FIG. 8G). The reflective layer 32 may be locally exposed on the main surface side (upper side in the drawing), and an n-side electrode may be formed here to form a horizontal light emitting element. Alternatively, the reflective layer 32 may be further removed to expose the semiconductor layer side bonding layer 33 on the main surface side, and an n-side electrode may be formed here to form a horizontal light emitting element. That is, in the case of a horizontal light emitting device, various methods can be used as a method for taking out the n-side electrode.

  In addition, various treatments can be applied to the surface of the p-type layer 23 in order to further increase the luminous efficiency. Examples of this treatment include forming fine irregularities and forming another film on the surface of the p-type layer 23. These processes are performed in each of the manufacturing methods described above, for example, immediately before FIG. 4B or immediately before FIG. 5O, immediately before FIG. 6A, and immediately before FIG. 8I. Is possible.

  Further, as described above, in the first peeling step, conventionally known chemical lift-off and laser lift-off can be used. For example, when sapphire is used as the growth substrate (first substrate) 50, this is peeled off. It is easy. On the other hand, it is preferable to use the same material as the first substrate 50 as the second substrate main body 61. However, the second substrate main body 61 is mainly made of the same material and provided with a structure for facilitating the second peeling step. It can also be used. In particular, unlike the first substrate, which is the growth substrate for the semiconductor layer, and the third substrate, which is the final support substrate in the light emitting element, the second substrate temporarily supports the semiconductor layer and the like during the manufacturing process. Since it is used only for the purpose, the degree of freedom for its structure is high. For this reason, a structure that facilitates the second peeling step can be appropriately selected and used.

  FIG. 9 is a cross-sectional view showing a configuration of the second substrate 160 as an example. In this case, the main body of the second substrate 160 is the sapphire substrate 161. Similar to the lift-off layer 51, a second lift-off layer 162 made of chromium (Cr) or scandium (Sc) is formed in a region other than the peripheral edge of the surface. Further, a polyimide layer 163 is formed covering the entire surface including the peripheral edge.

  In the second peeling step (FIG. 4E), as described above, the polyimide layers (intervening layers) 54 and 62 are wet using, for example, alkaline trimethylammonium hydride (TMAH), dilute sulfuric acid, sulfuric acid / hydrogen peroxide, or the like. Etching can be performed, whereby the second substrate main body 61 can be peeled off. However, since the etching rate of polyimide with these chemicals is not high, it takes a long time for the second substrate main body 61 to be peeled off. On the other hand, when the second substrate 160 shown in FIG. 7 is used, if only the end portion of the polyimide layer 163 is etched, the end portion of the second lift-off layer 162 inside is exposed. Thereafter, similarly to the first peeling step (FIG. 4G), the second lift-off layer 162 can be removed using hydrochloric acid, nitric acid or the like, and the second substrate main body 161 is peeled off. At this time, the etching rate of the second lift-off layer 162 is higher than the etching rate of the polyimide layer 162. For this reason, by using the second substrate 160, the processing speed of the second peeling step can be increased.

  In this case as well, the semiconductor layer 20 is joined to the second substrate main body 161 by the polyimide layers (intervening layers) 54 and 163 as in the above example. For this reason, it is the same that cracks are unlikely to occur in the semiconductor layer 20 in the first peeling step.

Example 1
Actually, vertical LEDs were manufactured by the manufacturing method of FIGS. 6 and 7, and the light emission characteristics were examined. Here, as the growth substrate (first substrate) 50, a substrate in which an AlN template layer having a thickness of 1.0 μm was formed on (0001) sapphire having a thickness of 430 μm was used. On top of that, an Sc layer having a thickness of 20 nm was formed as a lift-off layer 51, and nitriding was performed in an ammonia atmosphere. On this, a buffer layer 52 made of AlN single crystal having a thickness of 0.8 μm is grown at a high temperature, and an n-type layer (n-type AlGaN layer: thickness 0.8 μm) to be the semiconductor layer 20 is formed by MOCVD. The light emitting layer 22 (InAlGaN layer: thickness 340 nm) and the p-type layer (p-type AlGaN layer: thickness 30 nm) were sequentially formed. As the p-side ohmic electrode 41 on the p-type AlGaN layer, a Ni / Au layer having a total thickness of 50 nm and an aperture ratio of 20% was used.

  As the second substrate main body 61 in FIG. 6E, the same sapphire substrate as the growth substrate (first substrate) 50 was used. As the polyimide layers 54 and 62, those having a thickness of 2 μm were used, and the first bonding step (FIG. 6F) for bonding them was performed at 280 ° C. The first peeling step (FIG. 6G) was performed by wet etching the Sc layer (ScN layer), which is the lift-off layer 51, using hydrochloric acid. Thereafter, a Ti / Al / Cr layer (thickness 20 nm / thickness) of 10 μmφ and 100 μm pitch is formed as an n-side ohmic electrode 31 on the surface of the n-type AlGaN layer (n-type layer 21) exposed after etching the buffer layer 52 (AlN). 100 nm / 50 nm). A Ru / Cr / Au layer (thickness 50 nm / 50 nm / 300 nm) was formed thereon as the reflective layer 32 and the semiconductor layer side bonding layer 33 (FIG. 6 (i)).

  A Si substrate is used as the support substrate (third substrate) 100, and a Ti / Pt / Au / Sn / Au layer (thickness 20 nm / 200 nm / 100 nm / 200 nm / 700 nm) is used as the support substrate-side bonding layer 101. Was used. In the second bonding step (FIG. 6 (j)), the semiconductor layer side bonding layer 33 and the support substrate side bonding layer 101 were bonded at 280 ° C. using the solder composed of Au / Sn / Au.

In the second peeling step (FIG. 6 (k)), the polyimide layers (intervening layers) 54 and 62 were removed using TMAH. Thereafter, after removing the SiO ₂ layer 53 and performing a heat treatment at 400 ° C. for ohmic electrode formation, the exposed p-side ohmic electrode 41 is locally used as a p-side electrode 42 for external connection. A thick Ti / Au layer was formed. As a result, an LED having the structure shown in FIG. 1 was manufactured.

When the characteristics of this LED were measured, the light output P _O = 1.5 mW, the forward voltage Vf = 4.35 V, and the forward current If = 20 mA. Also, the light emission was uniform, and no abnormality was observed in 10 LEDs. That is, a vertical LED having good characteristics was obtained with a high yield.

(Comparative Example 1)
As the second substrate in Example 1 above, a Si substrate similar to the support substrate 100 is used, and this is bonded to the p-type layer side using solder instead of an intervening layer (polyimide layer), and then grown. The substrate is peeled in the same manner as in the first peeling step to expose the n-type layer, the Ti / Al / Cr layer as the n-side ohmic electrode, and the p-side as the n-side electrode for external connection on the n-side ohmic electrode A Ti / Au layer similar to the electrode was locally formed. Thereby, the substantial light emitting area was made the same as that in Example 1, and the light emitted from the semiconductor layer was extracted from the opposite side to Example 1.

  As a result, the same characteristics as in Example 1 were obtained for Po, Vf, and If. However, abnormal emission was observed on 2 of 10 chips. This cause is thought to be due to impurity diffusion from the solder.

(Comparative Example 2)
Instead of the n-side ohmic electrode 31 locally formed in Example 1, a thick Ti / Al / Cr layer was formed on the entire surface, and a structure in which no reflective layer was formed was created. As a result, Vf = 4.20 V, If = 20 mA, and the diode characteristics were good, but Po was a low value of 0.6 mW because there was no reflective layer on the n-layer side.

(Example 2)
The polyimide layers 54 and 62 in Example 1 were made as thick as 7 μm, and the others were the same as in Example 1. As a result, an LED having similar characteristics could be obtained. However, it was confirmed that a crack occurred in a part of the semiconductor layer.

(Example 3)
A horizontal LED was manufactured using the manufacturing method of FIG. 8 with the same growth substrate, lift-off layer, semiconductor layer and the like as in Example 1. The thickness of the SiO ₂ layer was 1 μm. Here, a Mo layer having a thickness of 50 nm was formed as the reflective layer 32 in FIG. 8B, and a Ti / Au layer similar to that in Example 1 was formed as the semiconductor layer side bonding layer 33. As for the support substrate 100 and the support substrate side bonding layer 101, the solder and the bonding temperature thereof were the same as in Example 1. However, a transfer substrate (second substrate) 60 and an aluminum nitride sintered substrate were used. Then, after forming the SiO ₂ layer 53 exposed after the second peeling step (FIG. 8E) (FIG. 8F), the n-type layer 21 was exposed by etching (FIG. 8D g)). Thereafter, after removing the SiO ₂ layer 53 (FIG. 8 (h)), the p-side ohmic electrode 41 and the p-side electrode 42 for external connection similar to those in Example 1 were formed on the exposed p-type layer 23. . Thereafter, an unpatterned Ti / Al / Cr layer similar to Example 1 was formed as the n-side ohmic electrode 31 on the exposed n-type layer 21. Thereby, a horizontal LED was manufactured.

As a result of measuring the characteristics of this LED, Po = 1.0 mW, Vf = 4.5 V, If = 20 mA. That is, it was confirmed that good characteristics can be obtained also in Example 3, which is a horizontal LED. Similar results were obtained even when the reflective layer 32 was a laminated structure of an Al layer having a thickness of 100 nm and an SiO ₂ layer having a thickness of 500 nm instead of the Mo layer.

DESCRIPTION OF SYMBOLS 10 Light emitting element 20 Semiconductor layer 21 n-type GaN layer (n-type group III nitride semiconductor layer: n-type layer)
22 Light emitting layer 23 p-type GaN layer (n-type group III nitride semiconductor layer: p-type layer)
31 n-side ohmic electrodes 32, 32a Reflective layer 32b Reflective underlayer 33 Semiconductor layer-side bonding layer (bonding layer)
41 p-side ohmic electrode 42 p-side electrode 50 Growth substrate (first substrate)
51 Lift-off layer 52 Buffer layer 53 SiO ₂ layer 54, 62, 163 Polyimide layer (intervening layer)
60, 160 Transfer substrate (second substrate)
61, 161 Second substrate main body 100 Support substrate (third substrate)
101 Support substrate side bonding layer (bonding layer)
162 Second lift-off layer

In order to solve the above problems, the present invention has the following configurations.
The method for manufacturing a light-emitting device according to the present invention has a laminated structure including an n-type group III nitride semiconductor layer, a light-emitting layer, and a p-type group III nitride semiconductor layer, and the n-type group III nitride semiconductor layer Is a method of manufacturing a light emitting device having a structure in which a laminated structure is bonded to a support substrate via a bonding layer, the stacked structure being formed on the first substrate via a lift-off layer, and the n-type group III nitride semiconductor layer A growth step of forming the light emitting layer and the p-type group III nitride semiconductor layer in this order, and a main surface side of the p-type group III nitride semiconductor layer through an intervening layer made of a polyimide-based resin material. A first bonding step of bonding to a second substrate made of the same material as the first substrate, and a first peeling step of removing the lift-off layer and peeling the first substrate from the laminated structure And the n-type group III nitride in the laminated structure The main surface side of the object semiconductor layer, locally forming an n-side ohmic electrode and having a reflective layer forming step of forming a reflective layer for reflecting light which the light emitting layer is emitted, bonded to the reflective layer A second bonding step of bonding the supporting substrate through a layer; and a second peeling step of removing the intervening layer and peeling the second substrate from the semiconductor layer.
Method of manufacturing a light emitting device of the present invention is characterized in that the thermal expansion coefficient at room temperature of the second substrate is in the range of ^{4 × 10 -6 ~7 × 10 -6} / K.
The method for manufacturing a light emitting element according to the present invention is characterized in that sapphire is the main body of the first substrate and the second substrate .
The method for manufacturing a light emitting device of the present invention is characterized in that the thickness of the intervening layer is 0.3 μm or more and 5.0 μm or less.
In the method for manufacturing a light emitting device according to the present invention, the n-side ohmic electrode is locally formed on the exposed surface of the n-type group III nitride semiconductor layer between the first peeling step and the reflective layer forming step. A side ohmic electrode forming step, wherein in the reflecting layer forming step, the reflecting layer is formed at least on the surface of the n-type group III nitride semiconductor layer where the n-side ohmic electrode is not formed.
The method for manufacturing a light emitting device of the present invention is characterized in that, in the reflective layer forming step, the reflective layer is formed with a reflective base layer interposed between the n-type group III nitride semiconductor layer.
In the method for manufacturing a light emitting device of the present invention, a single crystal AlN buffer layer is interposed between the lift-off layer and the stacked structure in the growth step, and the AlN buffer layer is locally formed in the reflective layer forming step. The n-side ohmic electrode is locally formed in the removed region.
The method for manufacturing a light emitting device according to the present invention is characterized in that a p-side ohmic electrode is formed on a main surface side of the p-type group III nitride semiconductor layer between the growth step and the first bonding step.
In the method for manufacturing a light emitting device of the present invention, after the second peeling step, the stacked structure is locally etched from the main surface side of the p-type group III nitride semiconductor layer, so that the main surface side a semiconductor layer etching step for locally exposing any one of the n-type group III nitride semiconductor layer, the reflective layer, and the bonding layer; and the n-type group III nitride semiconductor locally exposed on the main surface side And an n-side electrode forming step of forming an n-side electrode on the surface of any one of the layer, the reflective layer, and the bonding layer.

Claims (19)

  It has a laminated structure including an n-type group III nitride semiconductor layer, a light emitting layer, and a p-type group III nitride semiconductor layer, and the n-type group III nitride semiconductor layer is bonded to the support substrate through the bonding layer. And a reflection layer provided between the n-type group III nitride semiconductor layer and the bonding layer, and emitting light from a main surface side of the p-type group III nitride semiconductor layer. Light emitting element.   The light emitting device according to claim 1, wherein the reflective layer is made of a metal or a dielectric multilayer film. An n-side ohmic electrode locally formed between the n-type group III nitride semiconductor layer and the bonding layer and in contact with the n-type group III nitride semiconductor layer is further provided. Item 3. The light emitting device according to Item 1 or 2.   Between the reflective layer and the n-type group III nitride semiconductor layer, a reflection that transmits the light at a position that is in contact with the n-type group III nitride semiconductor layer and does not overlap with the n-side ohmic electrode. The light emitting device according to claim 3, further comprising an underlayer.   The reflective underlayer is used when the stacked structure is grown, and includes a single crystal AlN buffer layer formed between a growth substrate and the n-type group III nitride semiconductor layer. 5. The light emitting device according to 4.   The light emitting device according to claim 4, wherein a dielectric layer is provided at least on the reflective layer side of the reflective base layer.   The light emitting device according to any one of claims 1 to 6, wherein the reflective layer includes ruthenium (Ru), rhodium (Rh), molybdenum (Mo), or aluminum (Al). . The reflective layer has a multilayer structure made of a dielectric, and the dielectric contains at least SiO ₂ , HfO ₂ , Sc ₂ O ₃ , TiO ₂ , Al ₂ O ₃ , and SiN. The light emitting device according to any one of claims 1 to 7.   A p-side ohmic electrode formed on the p-type group III nitride semiconductor layer and partially transmitting light emitted from the semiconductor layer or having a mesh shape; and the p-side ohmic electrode locally covering the p-type ohmic electrode The light emitting device according to claim 1, further comprising a p-side electrode in contact with the side ohmic electrode. It has a laminated structure including an n-type group III nitride semiconductor layer, a light-emitting layer, and a p-type group III nitride semiconductor layer, and the n-type group III nitride semiconductor layer is bonded to the support substrate via the bonding layer. A method of manufacturing a light emitting device having the above-described configuration,
A growth step of forming the stacked structure on the first substrate through a lift-off layer in the order of the n-type group III nitride semiconductor layer, the light emitting layer, and the p-type group III nitride semiconductor layer;
A first bonding step of bonding a main surface side of the p-type group III nitride semiconductor layer to a second substrate via an intervening layer;
A first peeling step of removing the lift-off layer and peeling the first substrate from the laminated structure;
A step of locally forming an n-side ohmic electrode on the main surface side of the n-type group III nitride semiconductor layer in the stacked structure, and a reflective layer forming step of forming a reflective layer that reflects light emitted from the light emitting layer And
A second bonding step of bonding the support substrate to the reflective layer via a bonding layer;
A second peeling step of removing the intervening layer and peeling the second substrate from the semiconductor layer;
A method for manufacturing a light emitting element, comprising: The method for manufacturing a light-emitting element according to claim 10, wherein the second substrate has a coefficient of thermal expansion at room temperature of 4 × 10 ^{−6 to} 7 × 10 ⁻⁶ / K.   The method for manufacturing a light-emitting element according to claim 10 or 11, wherein the first substrate and the second substrate are made of the same material.   The method of manufacturing a light emitting element according to claim 12, wherein the main body of the first substrate and the second substrate is sapphire.   The method for manufacturing a light-emitting element according to any one of claims 10 to 13, wherein the intervening layer is made of a polyimide-based resin material.   The method of manufacturing a light emitting element according to claim 14, wherein the thickness of the intervening layer is 0.3 μm or more and 5.0 μm or less. An n-side ohmic electrode forming step for locally forming an n-side ohmic electrode on the exposed surface of the n-type group III nitride semiconductor layer between the first peeling step and the reflective layer forming step;
16. The reflection layer forming step, wherein the reflection layer is formed at least on the surface of the n-type group III nitride semiconductor layer where the n-side ohmic electrode is not formed. A method for producing a light-emitting element according to claim 1.   The method of manufacturing a light emitting element according to claim 16, wherein in the reflective layer forming step, the reflective layer is formed with a reflective base layer interposed between the n-type group III nitride semiconductor layer.   18. The light emitting device according to claim 10, wherein a p-side ohmic electrode is formed on a main surface side of the p-type group III nitride semiconductor layer between the growth step and the first bonding step. Device manufacturing method. After the second peeling step, the n-type group III nitride semiconductor layer on the main surface side by locally etching the stacked structure from the main surface side of the p-type group III nitride semiconductor layer, A semiconductor layer etching step for locally exposing either the reflective layer or the bonding layer;
An n-side electrode forming step of forming an n-side electrode on the surface of any one of the n-type group III nitride semiconductor layer, the reflective layer, and the bonding layer exposed locally on the main surface side;
The method for manufacturing a light-emitting element according to claim 10, comprising:

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