JP2014135314A - Failure analysis method for semiconductor devices - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an analysis success rate and to shorten an analysis time, in a failure analysis technology for semiconductor devices.SOLUTION: A luminous phenomenon generated immediately under a gate electrode of a transistor is acquired to estimate a suspected short-circuited wiring pair. A position and time of the luminous phenomenon based on the luminous phenomenon from the transistor is acquired, and the gate of the transistor included in the abnormal place is extracted. Specific wiring connected to the gate is extracted, and wiring adjacent to the wiring is extracted as adjacent wiring, and the adjacent wiring and the specific wiring are extracted as the wiring pair. Logical simulation of the specific wiring and the adjacent wiring is executed, and voltage waveforms of the wiring pair obtained from the execution result are compared with each other, and a different potential time zone where a voltage of the specific wiring configuring the wiring pair and a voltage of the adjacent wiring are different from each other is calculated. On the basis of the number of light emission belonging to the different potential time zone and the number of light emission belonging to a zone other than the potential time zone, index data that is an index of possibility of short circuit with the specific wiring is calculated.

Description

  The present invention relates to a semiconductor device failure analysis technique and a failure analysis program. The present invention also relates to a semiconductor device failure analysis technique and a technique effective when applied to a failure analysis program for estimating a wiring short-circuited with a specified wiring related to a short circuit failure.

  Japanese Laid-Open Patent Publication No. 2000-275306 (Patent Document 1) describes a method of identifying a faulty part of a semiconductor chip in which a part showing an abnormality of a power supply current (IDDQ) exists in a stationary state of a CMOS (Complementary Metal Oxide Semiconductor) circuit. Has been. Specifically, in this technique, a change mode of the abnormality IDDQ with respect to the operation test pattern of the semiconductor chip is defined, and a first information table indicating the correspondence between the change mode of the defined abnormality IDDQ and the physical abnormality is previously stored. You are going to create. Then, a second information table indicating the relationship between the light emission change with respect to the abnormal IDDQ pattern in the operation test pattern and the modeled physical abnormality is created in advance by the light emission analysis. Thereby, at the time of failure analysis, it is said that a location where a physical abnormality exists can be specified by comparing both tables, an abnormality IDDQ obtained from an actual semiconductor chip, and a change in light emission.

JP 2000-275306 A

  The stage where the developed LSI (Large Scale Integration) is completed and the function is evaluated, the stage where mass production of LSI begins and the improvement in yield is promoted, the stage where stress is applied to the LSI and the occurrence of defects is evaluated, LSI failures occur at various stages, such as a stage in which a customer accepts and tests the shipped LSI, a stage in which the customer incorporates and tests the LSI, and a stage in which the customer set is put on the market and operated.

  When such an LSI failure occurs, the cause of the failure can be ascertained quickly and fed back to the design, process, test, and customer in order to gain improved reliability as the product itself and as a semiconductor manufacturer. Indispensable.

  However, in recent years, LSIs have become larger, more functional, and faster, and due to a number of factors such as multilayer and miniaturization of wiring, the adoption of new materials, and changes in mounting methods, the difficulty of LSI failure analysis As a result, lowering of analysis success rate and longer analysis time have become problems.

  An object of the present invention is to provide a technique capable of improving the analysis success rate and shortening the analysis time in the semiconductor device failure analysis technique.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A semiconductor device failure analysis method according to an embodiment relates to a technique for estimating a wiring pair that is suspected of being short-circuited by acquiring an abnormal phenomenon based on an abnormal phenomenon. Specifically, the semiconductor device failure analysis method includes the following steps.

  This is a step of acquiring the position and time of the abnormal phenomenon based on the abnormal phenomenon from the semiconductor element. The gate of the transistor included in the position of the abnormal phenomenon is extracted. A wiring connected to the extracted gate is extracted as a specific wiring.

  Then, the wiring adjacent to the specific wiring is extracted as an adjacent wiring, and the extracted adjacent wiring and the specific wiring are extracted as a wiring pair. Subsequently, a logic simulation of the specific wiring and the adjacent wiring is executed, and a voltage waveform obtained from the result of the logic simulation is acquired.

  And the voltage waveform in the said wiring pair is compared, and the different electric potential time slot | zone in which the voltage of the said specific wiring and the voltage of the said adjacent wiring which comprise the said wiring pair differ is calculated. Subsequently, based on the number of times of light emission belonging to the different potential time zone and the number of times of light emission belonging to a time zone other than the different potential time zone, index data serving as an index of the possibility of short-circuiting with the specific wiring is calculated. .

  In the failure analysis technology for semiconductor devices, it is possible to improve the analysis success rate and shorten the analysis time.

It is explanatory drawing of electron beam testing. It is sectional drawing which shows an example of a multilayer wiring structure. It is explanatory drawing of the light emission detection technique. It is explanatory drawing of the mechanism by which the light emission phenomenon arises with the electron which flows through a channel area | region. It is a graph which shows the relationship between the gate voltage applied to a gate electrode, and emitted light intensity. It is explanatory drawing which shows an example of the signal transmission path | route between the cells which comprise a part of integrated circuit. It is explanatory drawing which shows an example of the voltage waveform which transmits the wiring which connects between cells. It is explanatory drawing which shows an example of the signal transmission path | route between the cells which comprise a part of integrated circuit. It is explanatory drawing which shows the other example of the voltage waveform which transmits the wiring which connects between cells. It is a figure which shows an example of the hardware constitutions of the defect analysis system in this Embodiment. It is a block diagram which shows an example of a structure of the analysis assistance control part provided in the analysis assistance apparatus of FIG. It is a flowchart which shows an example of the process outline | summary in the defect analysis process by the defect analysis system of FIG. It is explanatory drawing which showed an example of the function sharing of the failure analysis system which performs the failure analysis process of FIG. It is explanatory drawing which showed an example from the light emission detection by the failure analysis system of FIG. 11 to the setting of the light emission box. It is explanatory drawing which shows an example of the wiring extraction from the gate in a light emission box. It is explanatory drawing which shows the example of a display of the wiring extracted in FIG. 15, and an adjacent wiring. It is explanatory drawing which shows an example of the wiring pair which the wiring pair extraction part listed. It is explanatory drawing which shows an example of the logic waveform of each wiring which the waveform acquisition part provided in the analysis assistance control part of FIG. 11 acquired. It is explanatory drawing which shows the example of extraction of the different electric potential time slot | zone calculated by the different electric potential time slot | zone calculation part. It is explanatory drawing which shows an example of the counting of a different electric potential time slot | zone and a photon. In the score calculation of FIG. 20, it is explanatory drawing which shows an example at the time of increasing the number of detected photons. It is explanatory drawing of the mechanism of EBAC analysis technique. It is a flowchart which shows the flow of the defect analysis which this inventor examined.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

<background>
A technique called electron beam testing is used as a technique for observing an internal operation waveform (operation timing waveform) indicating the state of signal transmission in a semiconductor chip of an integrated circuit.

  This electron beam testing is an analysis technique that applies the fact that the detection yield of secondary electrons generated by irradiating an electron beam to the wiring that constitutes the integrated circuit changes depending on the potential applied to the wiring. Yes, up to the 130 nm process generation, it is still used as a general operation timing analysis method.

  According to this electron beam testing, the internal operation waveform transmitted through the wiring can be observed, so that a short circuit failure or an open failure of the wiring can be estimated from the abnormal waveform of the internal operation waveform.

  Specifically, this electron beam testing will be described.

  FIG. 1 is an explanatory diagram of electron beam testing. As shown in FIG. 1, for example, a field effect transistor constituting a part of an integrated circuit is formed on a semiconductor substrate 1S. This field effect transistor has a source region SR and a drain region DR which are semiconductor regions in a semiconductor substrate 1S, and a region between the source region SR and the drain region DR becomes a channel region.

  A gate electrode G is formed on the channel region via a gate insulating film GOX. A wiring is electrically connected to the field effect transistor configured as described above. For example, the source line SR is electrically connected to the source region SR, and the drain line DL is electrically connected to the drain region DR. In addition, a gate wiring GL is electrically connected to the gate electrode G. The gate wiring GL, the drain wiring DL, and the source wiring SL are composed of a plurality of wiring layers, and the wiring layers are formed in the interlayer insulating film IL.

  When the field effect transistor is an n-type MISFET (Metal-Insulator-Semiconductor Field Effect Transistor), the semiconductor substrate 1S is a p-type silicon substrate or a p-type well region, and the source region SR and the drain region DR are n-type. It becomes a semiconductor region.

  Here, for example, consider observing an operation waveform applied to the gate wiring GL connected to the gate electrode G. In this case, first, as shown in FIG. 1, a connection hole reaching the gate wiring GL is formed by FIB (Focused Ion Beam) processing, and then metal is formed in the connection hole by FIBCVD (Focused Ion Beam Chemical Vapor Deposition). Embed the membrane. Then, a pad FPD is formed on the connection hole in which the metal film is embedded. Thereby, the pad FPD electrically connected to the gate wiring GL can be formed on the surface of the interlayer insulating film.

  In this state, the electron beam irradiation / scanning unit EBU irradiates the pad FPD with the electron beam. At this time, the integrated circuit is in an operating state, and various operating voltages are applied to the gate wiring GL. That is, the operation waveform is transmitted to the gate line GL.

  Here, when the pad FPD is irradiated with an electron beam, secondary electrons are emitted from the pad FPD. However, since the surrounding potential changes depending on the voltage applied to the gate wiring GL, the secondary electrons of the secondary electrons. The number of supplements at the detector SED changes.

  Therefore, it is possible to analyze how the potential of the gate wiring GL to be analyzed changes with time by analyzing the number of secondary electrons captured by the secondary electron detector SED. It can be done. That is, the operation waveform of the gate wiring GL can be indirectly analyzed by measuring the number of secondary electrons captured in the secondary electron detector SED.

  As a result, according to the electron beam testing, it can be determined whether there is an abnormality in the operation waveform of the gate wiring GL to be analyzed. For example, when an abnormal waveform of the internal operation waveform exists, By analyzing this abnormal waveform, it is possible to estimate a short circuit failure or an open failure of the gate wiring GL.

  However, from the 130 nm process generation, multilayer wiring layers have been developed, and a design in which a wide range of power wiring and ground wiring is laid on the upper layer of the multilayer wiring layer has been adopted. For this reason, it is difficult to form a connection pad that is pulled up from the analysis target wiring to the surface of the multilayer wiring layer by the focused ion beam processing that has been performed so far.

  In other words, in electron beam testing, it is necessary to form a connection pad connected to the analysis target wiring on the surface of the multilayer wiring layer, but it is electrically connected to the analysis target wiring by miniaturization and densification of the wiring. Formation of connection pads has become difficult.

  Therefore, after the 130 nm process generation in which miniaturization and high density of wiring are progressing, it is becoming difficult to use electron beam testing for observing the operation waveform of the wiring to be analyzed from the surface side of the semiconductor chip.

  Specifically, FIG. 2 is a cross-sectional view showing an example of a multilayer wiring structure.

  As shown in FIG. 2, a multilayer wiring layer ML is formed on the semiconductor substrate 1S. In this case, when the wiring formed in the lower layer of the multilayer wiring layer ML is used as the analysis target wiring, the connection pad connected to the analysis target wiring formed in the lower layer is multilayered so as not to connect to other wiring. It can be seen that it is difficult to draw out to the surface of the wiring layer ML.

  That is, as shown in FIG. 2, since the number of layers of the multilayer wiring layer ML is increased and the wiring density is increasing, for example, when the analysis target wiring is formed in a relatively lower layer, this This makes it difficult to form connection pads that are electrically connected to the analysis target wiring. FIG. 2 shows an example in which the wiring L is formed by embedding a conductive film including a metal film in the wiring groove and the plug portion formed in the interlayer insulating film IL.

  From the above, with the miniaturization and high density of integrated circuits, a testing technique that replaces electron beam testing for observing the operation waveform of the wiring to be analyzed from the surface side of the semiconductor chip is required.

  Therefore, in recent years, several proposals have been made on the back surface timing analysis technique, which is a technique for observing the internal operation waveform of the integrated circuit from the back surface of the semiconductor chip, that is, from the silicon substrate side. For example, PICA (Pico-second Imaging for Circuit Analysis) is given as the first proposal of the back surface timing analysis technology.

  PICA is a method of observing operation timing by capturing light emission generated at a certain probability depending on voltage at the time of potential transition in a transistor constituting an integrated circuit to be operated, and integrating the light emission. That is, PICA is a technique for detecting light emission generated from a transistor at the timing of potential transition, and analyzing the internal operation waveform by specifying the timing at the time of potential transition from this light emission.

  A technique called TREM (Time Resolved Emission Microscopy) has been proposed as a modification method of this PICA, and a light emission location from a specific transistor is selected and taken in by a shutter. Has been put to practical use.

  Further, when a pn junction formed at the boundary between the active region of the transistor and the substrate region is irradiated with laser light, the intensity and phase of the reflected laser light reflected by the pn junction depends on the potential applied to the pn junction. There is an analysis method called LVP (Laser Voltage Probing) using a changing phenomenon (Franz-Keldysh effect / free carrier absorption). As a modification technique, an analysis method called LVI (Laser Voltage Imaging) using frequency analysis has been proposed, and both are put into practical use as defect analysis apparatuses.

  For failure analysis that is expected to become even more difficult in the future, we will introduce methods that can evaluate the characteristics of each analysis method and expand the scope of analysis, and use the introduced method as an analysis tool. It is necessary to expand the use as.

  In this embodiment, in particular, as a result of conducting an experiment to examine the application range of the above-described PICA technology, as an application development of the PICA technology, a technical technique that becomes an effective technique when put into practical use in future failure analysis I found an idea.

  Specifically, the PICA technology is a method of observing the internal operation waveform of the integrated circuit from the back surface of the semiconductor chip by using the light emission detection technology. This is a failure analysis technology that estimates open failures.

  In this regard, the present inventor applied the light emission detection technology used in the PICA technology to an analysis method for estimating a wiring on the other side that is short-circuited with a specific wiring specified to be related to a short circuit defect. I found out that I can do it.

  That is, this embodiment is a technical idea that expands the application range of the light emission detection technology used in the PICA technology. Hereinafter, before explaining the technical idea in the present embodiment, first, a light emission detection technique as a premise thereof will be described.

<Luminescence detection technology>
FIG. 3 is an explanatory diagram of the light emission detection technique. As shown in FIG. 3, for example, a field effect transistor constituting a part of the integrated circuit is formed on the semiconductor substrate 1S. This field effect transistor has a source region SR and a drain region DR which are semiconductor regions in a semiconductor substrate 1S, and a region between the source region SR and the drain region DR becomes a channel region. A gate electrode G is formed on the channel region via a gate insulating film GOX.

  A wiring is electrically connected to the field effect transistor configured as described above. For example, the source line SR is electrically connected to the source region SR, and the drain line DL is electrically connected to the drain region DR. In addition, a gate wiring GL is electrically connected to the gate electrode G. The gate wiring GL, the drain wiring DL, and the source wiring SL are composed of a plurality of wiring layers, and the wiring layers are formed in the interlayer insulating film IL.

  Here, when the field effect transistor is operated, electrons flow from the source region SR toward the drain region DR. A light emission phenomenon occurs when the electrons flow through the channel region. A technique for detecting this light emission phenomenon by the light detection unit LDU is a light emission detection technique.

  Hereinafter, a mechanism in which a light emission phenomenon occurs when electrons flow in the channel region will be described.

  FIG. 4 is an explanatory diagram of a mechanism in which a light emission phenomenon occurs due to electrons flowing in the channel region.

  In FIG. 4, a gate voltage VG is applied to the gate electrode G. The source region SR is fixed to the ground potential, and the drain voltage DR is applied to the drain region DR.

  For example, when the gate voltage VG applied to the gate electrode G is increased in a state where the positive drain voltage VD is applied to the drain region DR, electrons begin to flow on the surface of the semiconductor substrate 1S immediately below the gate electrode G.

  That is, when the gate voltage VG applied to the gate electrode G is gradually increased, electrons flow from the source region SR to the drain region DR through the region immediately below the gate electrode G. That is, electrons flow through the region immediately below the gate electrode G to the drain region DR while being accelerated by the potential difference applied between the source region SR and the drain region DR.

  At this time, some of the accelerated electrons collide with the silicon crystal existing in the region directly under the gate electrode G. However, when the energy of the accelerated electrons is high (hot electrons), Impact ionization occurs by colliding with the silicon crystal. That is, when the accelerated electrons collide with the silicon crystal, the electrons existing in the silicon crystal are blown off to generate hole / electron pairs. Then, the generated holes and electrons are recombined to cause a light emission phenomenon.

  Actually, since the generated holes and electrons travel in opposite directions, the probability that the simultaneously generated holes and electrons recombine is low. However, in FIG. Illustrated as electrons recombine.

  In practice, recombination occurs when electrons generated by impact ionization at one location collide with holes generated by impact ionization at another location, thereby causing a light emission phenomenon.

  Here, the important point is that the light emission intensity of the above-described light emission phenomenon depends on the magnitude of the gate voltage VG applied to the gate electrode G. This point will be described.

  FIG. 5 is a graph showing the relationship between the gate voltage VG applied to the gate electrode G and the light emission intensity. In FIG. 5, the horizontal axis indicates the gate voltage VG (V), and the vertical axis indicates the emission intensity (arbitrary unit).

  As shown in FIG. 5, when the gate voltage VG is in the vicinity of 0 V, the emission intensity is almost equal to zero, and thereafter, the emission intensity increases as the gate voltage VG increases. When the gate voltage VG becomes about half of the drain voltage VD, it can be seen that the emission intensity becomes the highest, and thereafter, the emission intensity decreases as the gate voltage VG increases.

  The reason why such a phenomenon occurs can be considered as follows. That is, when the gate voltage VG applied to the gate electrode G is in the vicinity of 0 V, the field effect transistor is off. For this reason, a channel region is not formed immediately below the gate electrode G, and no current flows even if there is a potential difference between the source region SR and the drain region DR.

  When the gate voltage VG is in the vicinity of 0 V as described above, since electrons hardly pass through the region immediately below the gate electrode G, hole / electron pairs are almost generated when the electrons collide with the silicon crystal. Absent. As a result, it is considered that the light emission phenomenon does not occur when the gate voltage VG is in the vicinity of 0V.

  Next, consider a case where the gate voltage VG rises to about half of the drain voltage VD. The gate voltage VG at this time is called an intermediate voltage. When the gate voltage VG is in the vicinity of the intermediate voltage, a channel region composed of a complete inversion layer is not formed immediately below the gate electrode G, but an initial stage (an incomplete channel is formed). The region is being formed).

  For this reason, current gradually starts to flow between the source region SR and the drain region DR. That is, when the gate voltage VG is an intermediate voltage, electrons begin to pass through the region immediately below the gate electrode G.

  As a result, electrons flowing in the region immediately below the gate electrode G are accelerated by a potential difference between the source region SR and the drain region DR. Here, when the gate voltage VG is an intermediate voltage, it is considered that the resistance is higher than that when a complete inversion layer is formed because the channel region is in an initial stage.

  High resistance means that the frequency with which the electrons collide with the silicon crystal increases, and this increases the possibility that the accelerated electrons collide with the silicon crystal and impact ionization occurs.

  As a result, when the gate voltage VG is an intermediate voltage, a large number of hole-electron pairs are generated by impact ionization, thereby increasing the probability of recombination of holes and electrons. From this, it is considered that light emission intensity increases because light emission due to recombination of holes and electrons increases.

  Next, consider a case where the gate voltage VG rises to about the drain voltage VD. In this case, a channel region made of a complete inversion layer is formed immediately below the gate electrode G. For this reason, a current flows between the source region SR and the drain region DR. As a result, electrons flowing in the region immediately below the gate electrode G are accelerated by a potential difference between the source region SR and the drain region DR.

  However, when the gate voltage VG rises to about the drain voltage VD, a channel region composed of a complete inversion layer is formed immediately below the gate electrode G, and the resistance of the channel region composed of this complete inversion layer is It is low.

  In other words, the lower resistance means that the frequency with which the electrons collide with the silicon crystal decreases, and this reduces the possibility that the accelerated electrons will collide with the silicon crystal and cause impact ionization. It becomes.

  As a result, when the gate voltage VG rises to about the drain voltage VD, the generation of hole / electron pairs due to impact ionization is reduced, thereby reducing the probability of recombination of holes and electrons. From this, it is considered that the light emission intensity decreases because light emission due to recombination of holes and electrons decreases.

  From the above, it can be seen that the light emission phenomenon that occurs in the region immediately below the gate electrode G tends to occur when the gate voltage VG applied to the gate electrode G is an intermediate voltage.

  Next, how the above-described light emission phenomenon is used for failure analysis of an integrated circuit will be described.

  FIG. 6 is an explanatory diagram showing an example of a signal transmission path between cells constituting a part of the integrated circuit. In FIG. 6, a cell CL1 and a cell CL2 are connected by wiring, and a cell CL2 and a cell CL3 are connected by wiring. Here, the cell is defined as a circuit having a certain function including a plurality of transistors.

  Here, it is assumed that the circuits constituting the cells CL1 to CL3 are constituted by, for example, logic circuits (digital circuits). In this logic circuit, the wiring connecting the cells is configured to be electrically connected to the gate electrode of the transistor.

  First, as shown in FIG. 6, attention is paid to a case where a signal is transmitted through the wiring between the cell CL1 and the cell CL2. Specifically, it is assumed that a signal in which a High signal (high voltage VH) and a Low signal (low voltage VL) are alternately changed is output from the cell CL1. In this case, a signal in which a High signal (high voltage VH) and a Low signal (low voltage VL) alternately change is transmitted through the wiring between the cell CL1 and the cell CL2 and input to the cell CL2.

  In this case, a voltage waveform as shown in FIG. 7 is observed in the wiring between the cell CL1 and the cell CL2. FIG. 7 is an explanatory diagram illustrating an example of a voltage waveform transmitted through a wiring connecting the cell CL1 and the cell CL2.

  As shown in FIG. 7, a signal that alternately changes the Low signal (low voltage VL) and the High signal (high voltage VH) is applied to the wiring connecting the cells CL1 and CL2. At this time, for example, a phenomenon of transition from a low signal (low voltage VL) to a high signal (high voltage VH) or a phenomenon of transition from a high signal (high voltage VH) to a low signal (low voltage VL) occurs. . In the process of this transition phenomenon, there is always a time for passing the intermediate voltage VM between the high voltage VH and the low voltage VL.

  As a result, the intermediate voltage VM is applied to the wiring that connects the cell CL1 and the cell CL2, and when the intermediate voltage VM is applied, the wiring is connected to the wiring that connects the cell CL1 and the cell CL2. There is a possibility that a light emission phenomenon may occur immediately below the gate electrode of the transistor.

  Actually, depending on the power supply voltage, the light emission phenomenon occurs about once every 100,000 to 1 million times. Since the occurrence probability of the light emission phenomenon is low, in practice, a pattern is looped by a tester and information for a certain time is added. In this way, the light emission phenomenon occurs in the process of the voltage transition phenomenon, and therefore, the voltage transition timing can be indirectly specified by observing this light emission phenomenon.

  That is, when a light emission phenomenon occurs, it can be seen that a voltage transition occurs at that timing, and therefore, by detecting and analyzing the light emission phenomenon, an operation waveform of a signal transmitted through the wiring can be obtained. .

  Then, by analyzing the acquired operation waveform (operation timing), an abnormality in the operation waveform can be detected. Such a technique is known as PICA or TREM.

  As described above, there is known a failure analysis technique for analyzing an operation waveform of a signal transmitted through a wiring by using a light emission phenomenon that occurs immediately below a gate electrode of a transistor. Has been found to be used for failure analysis technology different from operation timing. Hereinafter, this knowledge will be described.

  FIG. 8 is an explanatory diagram showing an example of a signal transmission path between cells constituting a part of the integrated circuit. In FIG. 8, a cell CL1 and a cell CL3 are connected by a wiring, and a cell CL2 and a cell CL4 are connected by a wiring. In FIG. 8, in order to simplify the description, a fixed high signal (high voltage VH) is output from the cell CL1 and a fixed low signal (low voltage) is output from the cell CL2 in the time period of interest. Assume that voltage VL) is output.

  In this state, it is assumed that a short-circuit portion ST exists between the wiring connecting cell CL1 and cell CL3 and the wiring connecting cell CL2 and cell CL4. In this case, since the High signal (high voltage VH) and the Low signal (low voltage VL) are in contact, the wiring connecting the cell CL1 and the cell CL3 and the wiring connecting the cell CL2 and the cell CL4 are as follows: The intermediate voltage VM is applied. That is, the intermediate voltage VM is input to the cells CL3 and CL4.

  In this case, for example, a voltage waveform as shown in FIG. 9 is observed in the wiring connecting the cell CL1 and the cell CL3. FIG. 9 is an explanatory diagram illustrating an example of a voltage waveform transmitted through the wiring connecting the cells CL1 and CL3.

  As shown in FIG. 9, the intermediate voltage VM is applied to the wiring connecting the cells CL1 and CL3. As a result, a light emission phenomenon may occur immediately below the gate electrode of the transistor connected to the wiring that connects the cell CL1 and the cell CL3.

  In particular, in the time zone of interest, a fixed High signal (high voltage VH) is output from the cell CL1, and a fixed Low signal (low voltage VL) is output from the cell CL2. For this reason, in this time zone, the intermediate voltage VM is always applied to the wiring connecting the cells CL1 and CL3, and the probability of occurrence of the light emission phenomenon is increased.

  That is, in the light emission phenomenon in the case where the short portion ST as shown in FIG. 8 exists, the light emission phenomenon having a higher intensity than the light emission phenomenon that occurs in the process of the voltage transition phenomenon as shown in FIG. 6 is detected. Is possible. Thus, for example, when there is a short-circuited portion ST between the wirings, in a state where a different voltage is applied between the wirings that are short-circuited, the intermediate voltage VM is applied to each wiring due to the short-circuiting. As a result, a light emission phenomenon occurs.

  Thus, the present inventor, for example, when there is a specific wiring identified as related to a short circuit failure, and when a plurality of wirings that may be short-circuited with the specific wiring are extracted, Based on this finding, we found the knowledge that the light emission phenomenon and its timing can be used for failure analysis technology that estimates which of the wirings is likely to be short-circuited with a specific wiring. The technical idea in the first embodiment is conceived. The technical idea in the first embodiment will be described below.

<Hardware configuration example of defect analysis device>
Below, the structure of the failure analysis apparatus which actualized the technical idea in this Embodiment 1 mentioned above is demonstrated. First, the hardware configuration of the failure analysis apparatus according to the first embodiment will be described.

  FIG. 10 is a diagram illustrating an example of a hardware configuration of the failure analysis system according to the present embodiment. The configuration illustrated in FIG. 10 is merely an example of the hardware configuration of the failure analysis system, and the hardware configuration of the failure analysis system is not limited to the configuration illustrated in FIG. There may be.

  In FIG. 10, the failure analysis system according to the first embodiment includes a logic simulator SML, a light emission detection device ELA, and an analysis support device BAS.

  The logic simulator SML is a tool for verifying the logic function and timing of the designed logic circuit. The design data of the target circuit is input, a simulation pattern, which is a verification pattern, is added to this, and the response is observed. A logic waveform which is a voltage waveform observed by the logic simulator SML is output to the analysis support apparatus BAS. Further, the logic simulator SML has, as software, for example, a waveform viewer (waveform viewer) for graphically viewing an input signal and a response signal.

  The light emission detection device ELA can detect weak light generated from a semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes, for example, an emission microscope that can detect weak light with high sensitivity. A light emission detector is included.

  Furthermore, the light emission detection device ELA includes a photoelectric conversion unit that generates light emission data that is an electrical signal from weak light detected by the light emission detection unit. In the light emission detection device ELA, for example, the weak light generated inside the semiconductor device is detected by the light emission detection unit, and the weak light detected by the light emission detection unit is converted into light emission data including an electrical signal by the photoelectric conversion unit. .

  Then, the light emission detection device ELA outputs the converted light emission data to the analysis support device BAS. Note that the light emission detection device ELA is configured to be able to acquire light emission data in a state where time division is not performed and light emission data in a state where time division is performed.

  The analysis support apparatus BAS includes a control unit CPU, a nonvolatile storage unit ROM, a volatile storage unit RAM, a display DSP, a keyboard KEY, a mouse MUS, a communication board CBD, a removable disk device RMD, a CD / DVD-ROM device CVD, and a hard disk device. An HDD, a printer PRT, a scanner SCN, and an analysis support control unit FAS are included.

  The control unit CPU includes, for example, a CPU (Central Processing Unit) and executes a program. This control unit CPU is connected to, for example, a non-volatile storage unit ROM, a volatile storage unit RAM, a hard disk device HDD, and an analysis support control unit FAS via the bus BUS, and controls these hardware devices. .

  The control unit CPU is also connected to an input device and an output device via a bus BUS. Examples of the input device include a keyboard KEY, a mouse MUS, a communication board CBD, and a scanner SCN. On the other hand, examples of the output device include a display DSP, a communication board CBD, and a printer PRT. Further, the control unit CPU may be connected to, for example, a removable disk device RMD or a CD / DVD-ROM device CVD.

  FIG. 10 shows a configuration in which the analysis support device BAS is directly connected to the logic simulator SML and the light emission detection device ELA. However, the analysis support device BAS is connected to the logic simulator SML and the light emission detection device ELA via a network. You may make it do.

  For example, when connecting via a network, the communication board CBD that constitutes a part of the analysis support apparatus BAS is connected to a LAN (local area network), a WAN (wide area network), or the Internet.

  The volatile storage unit RAM is an example of a volatile memory, and the recording media of the nonvolatile storage unit ROM, the removable disk device RMD, the CD / DVD-ROM device CVD, and the hard disk device HDD are examples of the nonvolatile memory. These volatile memory and non-volatile memory constitute a storage device of the analysis support apparatus BAS.

  For example, an operating system OS, a program group PRG, and a file group FLE are stored in the hard disk device HDD. The program included in the program group PRG is executed by the control unit CPU using the operating system OS.

  The volatile memory RAM temporarily stores at least a part of the operating system OS program and application programs to be executed by the control unit CPU, and stores various data necessary for processing by the control unit CPU. The The nonvolatile storage unit ROM stores a BIOS (Basic Input Output System) program, and the hard disk device HDD stores a boot program.

  When starting the analysis support device BAS, the BIOS program stored in the nonvolatile storage unit ROM and the boot program stored in the hard disk device HDD are executed, and the operating system OS is started by the BIOS program and the boot program. .

  The program group PRG stores a program that realizes the function of the analysis support apparatus BAS. This program is read by the control unit CPU and is executed by, for example, the analysis support control unit FAS.

  The file group FLE stores information, data, signal values, variable values, and parameters indicating the results of processing by the control unit CPU as items of the file. The file is stored in a recording medium such as a hard disk device HDD or a memory.

  Information, data, signal values, variable values, and parameters stored in a recording medium such as the hard disk device HDD or memory are read out to the main memory or cache memory by the control unit CPU, and extracted, searched, referenced, compared, calculated, It is used for the operation of the control unit CPU represented by processing, editing, output, printing, and display. For example, during the operation of the control unit CPU described above, information, data, signal values, variable values, and parameters are temporarily stored in a main memory, a register, a cache memory, a buffer memory, and the like.

  The functions of the analysis support apparatus BAS may be realized by firmware stored in the nonvolatile storage unit ROM, or only software, only hardware represented by elements, devices, boards, and wiring, software and hardware It may be realized in combination with hardware, or in combination with firmware.

  Firmware and software are stored as programs in a recording medium represented by a hard disk device HDD, a removable disk, a CD-ROM, a DVD-ROM, and the like. The program is read and executed by the control unit CPU. In other words, the program causes the computer to function as the analysis support apparatus BAS.

  As described above, the analysis support device BAS includes a control unit CPU as a processing device, a hard disk device HDD and memory as a storage device, a keyboard KEY, a mouse MUS as an input device, a communication board CBD, a scanner SCN, and a display as an output device. A computer including a DSP, a printer PRT, and a communication board CBD. Each function of the analysis support apparatus BAS is realized by using the above-described processing apparatus, storage apparatus, input apparatus, and output apparatus.

<Configuration example of analysis support control unit>
FIG. 11 is a block diagram showing an example of the configuration of the analysis support control unit FAS provided in the analysis support apparatus BAS of FIG.

  As shown in FIG. 11, the analysis support control unit FAS includes a light emission position acquisition unit LTD, a gate extraction unit GET, a wiring identification unit PSF, a wiring pair extraction unit PPE, a waveform acquisition unit WFA, a different potential time zone calculation unit DPT, an index. It has a data calculation unit IDC and an index data output unit IDO.

  The light emission position acquisition unit LTD acquires the abnormal phenomenon of the transistor detected by the light emission detection device ELA, that is, the position information of the light emission detected by the light emission detection device ELA from the light emission detection device ELA.

  Thus, the light emission position acquisition unit LTD can obtain information on which coordinates on the layout data in the integrated circuit correspond to the position information of the light emission detected by the light emission detection device ELA.

  The gate extraction unit GET picks up a gate present in a region on the light emission layout having a certain area. The wiring specifying unit PSF specifies the wiring connected to the gate extracted by the gate extraction unit GET as the specific wiring.

  The wiring pair extraction unit PPE extracts a wiring adjacent to the specific wiring specified by the wiring specification unit PSF as an adjacent wiring, and records the adjacent wiring as a wiring pair. In addition, the wiring pair extraction unit PPE transmits the names of all wirings to the logic simulator SML.

  The waveform acquisition unit WFA acquires a logic waveform of the target wiring from the logic simulator SML. The different potential time zone calculation unit DPT compares the logic waveforms of the wiring pairs recorded by the wiring pair extraction unit PPE and calculates a time zone in which the potentials of the pair wires are different.

  The indicator data calculation unit IDC receives the emission time information detected by the emission detection device ELA, and compares the emission time information with the different potential time zone calculated by the different potential time zone calculation unit DPT according to the number of detected photons. Calculate the index. The index data output unit IDO displays the calculated index on a display DSP or the like provided in the analysis support apparatus BAS and clearly indicates it to the analysis operator.

<Example of analysis processing by defect analysis system>
In describing the flow of processing in the following defect analysis, each function in the analysis support control unit FAS will be described.

  FIG. 12 is a flowchart showing an example of a processing outline in the failure analysis processing by the failure analysis system of FIG.

  The failure analysis processing by the failure analysis system estimates a pair that is highly likely to be short-circuited when the wiring to be analyzed is not known.

  First, the position and time of light emission in the semiconductor chip are detected (step S101). This is a function of the light emission detection device ELA, and the detected data is stored as numerical data of the light emission position and time in a storage device such as a hard disk device provided in the light emission detection device ELA. Here, one point of light emission is assumed. However, even with two or more points of light emission, analysis can be performed with the same processing flow.

  Light emission occurs at the gate portion as described in <Background> and the like. Therefore, the gate included in the light emission is subsequently extracted (step S102). The light emission normally detected has a spread of about several μm.

  On the other hand, miniaturization of recent integrated circuits has progressed, and a number of gates are included in a range of about several μm. Therefore, in order not to miss the defective pair, all the gates that may be included in the light emission are extracted.

  When the gate is extracted, the wiring connected to the extracted gate is listed as a specific wiring (step S103). This process uses, for example, an equipotential tracking function of the layout viewer.

  Here, the layout viewer is software installed in the analysis support apparatus BAS. This layout viewer is software that displays the layout of the semiconductor device as a graphic on the display DSP of the analysis support apparatus BAS based on the layout data.

  Subsequently, the wiring adjacent to each listed wiring is extracted as an adjacent wiring (step S104). Also in this process, for example, the equipotential tracking function of the layout viewer is used. Based on the processing in step S103 and the processing result in step S104, a list of wiring pairs that may be short-circuited is created (step S105).

  When the above processing is completed, logic simulation is executed for all the listed wirings (step S106), and the logic waveforms of all the wirings are obtained. When the logic waveform is obtained, the different potential time zone and the same potential time zone between the specific wiring whose gate is included in the light emitting region and its adjacent wiring can be obtained, and the different potential / same potential time zone for all pairs. Is extracted (step S107).

  The different potential time zone is obtained by exclusive OR (XOR) of the specific wiring whose gate is included in the light emitting region and its adjacent wiring, and the same potential time zone is the same as the specific wiring whose gate is included in the light emitting region. It is obtained by the reciprocal (XNOR) of the exclusive OR with the adjacent wiring.

  Subsequently, score calculation is performed between the timing of light emission and the different potential / same potential time zone (step S108) to calculate numerical data. The score calculation may be, for example, +1 if a photon enters a different potential time zone, -1 if a photon enters the same potential time zone, or a further weight. Here, for the sake of simplicity, a simple calculation method of + 1 / −1 is adopted.

  When the score which is the index data can be calculated, the wiring pairs are sorted and displayed in order from the high score according to the score (step S109). This display can be made user-friendly by improving visibility by displaying it with, for example, a histogram. Thereafter, the pair most likely to be short-circuited is highlighted (step S110).

<Principle of luminescence detection>
Here, the principle of the light emission detection of the light emission detection device ELA by the failure analysis process of FIG. 12 will be described.

  The luminescence detection device ELA has TRIEM, a so-called time-resolved image luminescence analysis function. This TRIEM is equivalent to the above-described PICA. TRIEM is an analysis technique that can detect in units of one photon and collects light emission information with a detector capable of time resolution of about 10 ps. Thereby, the information on the position and time of light emission is analyzed. What is captured here is that the silicon can be transmitted by light emission in the infrared region, and detection from the back surface of the semiconductor chip is possible.

  Until now, the waveform inside the integrated circuit has been observed by an electron beam tester, which has been an analysis from the surface of the semiconductor chip. However, in recent years, it has become difficult to perform analysis from the surface by laying multi-layer / surface power wiring, ground wiring, or flip chip mounting, and analysis using an electron beam tester has become impossible to apply.

  On the other hand, timing analysis from the back surface of a semiconductor chip is a practical and indispensable method in the future by using a technology capable of detecting the position and time of infrared light that passes through silicon.

  TRIEM has the function of cutting out the light emission timing of a specific area from the light emission image, and also has the function of cutting out the light emission position from the light emission timing, and this is the function of extracting the light emission image.

  That is, for example, when an elapsed time from the set trigger is designated as the light emission timing, an image that is emitting light at that time is displayed. Therefore, if all the time-resolved emission images are added, the emission image for the entire time is obtained.

<Function sharing example of defect analysis system>
FIG. 13 is an explanatory diagram showing an example of the function sharing of the failure analysis system that executes the failure analysis process of FIG.

  In FIG. 13, from the left to the right, the light emission detection device ELA, the analysis support device BAS, and the logic simulator SML are shown, and how the failure analysis processing of FIG. 12 is shared and processed.

  As shown in FIG. 13, the light emission detection device ELA executes the process of step S <b> 101 of FIG. 12. Further, the analysis support apparatus BAS executes the processes of steps S102 to S105 and the processes of steps S108 to S110 in FIG. The logic simulator SML executes the process of step S106 and the process of step S107 in FIG.

  The analysis result obtained in the process of step S101 is sent to the analysis support apparatus BAS, the process of step S102 is executed, and the analysis result obtained in the process of step S107 is sent to the analysis support apparatus BAS. Then, the process of step S108 is executed.

  Further, the list result of the specific wiring obtained by the process of step S105 is sent to the logic simulator SML, and the processes of steps S106 and S107 are executed based on the result. The extraction result of the different potential time zone of the wiring pair obtained by the process of step S107 is sent to the analysis support apparatus BAS, and the process of step S108 is executed.

  Thus, the first light emission detection is performed by time-resolved light emission analysis by the light emission detection device ELA. Here, the information to be used first is information on the light emission detection position.

  Then, the analysis support apparatus BAS extracts the specific wiring at the light emission location as the light emission position, and lists a pair of the specific wiring and the adjacent wiring involved in the light emission as a wiring pair. The logic simulation for all the wirings listed as the wiring pair is executed using the logic simulator SML.

  Then, the logic waveform is calculated by the logic simulator SML, the different potential of the wiring pair or the same potential time zone is extracted, and then the detection time data of the light emission is taken in by the analysis support device BAS, and the comparison and the comparison are executed. To do.

  The result of this comparison and control is calculated as a score value as described above, and is displayed on an appropriate display DSP from the higher score. This presents the analyst with the accuracy and suspicion as a wiring pair suspected of being short-circuited.

<Example of failure analysis system analysis>
Hereinafter, the operation of the failure analysis system of FIG. 11 will be described more specifically.

<Operation example of luminescence detection device>
FIG. 14 is an explanatory diagram showing an example from light emission detection to light emission box setting by the failure analysis system of FIG.

  First, in the process of step S101 in FIG. 12, the detection of light emission and the position of light emission are specified. Here, it is assumed that the light emission shown in FIG. 14A is detected by the light emission detection device ELA. FIG. 14A is an image diagram in which the emission point LHT is at the center and the emission image is superimposed on the microscope image.

  The coordinate system of the microscopic image shown in FIG. 14A at this time is the optical system stage coordinate system of the light emission detection device ELA, and therefore it is necessary to convert this coordinate system into a layout coordinate system. For this reason, two or three characteristic points in the image are selected by the analysis support apparatus BAS, and the respective light emission points are designated on the microscopic image and the layout image. Perform a coordinate system lock that corresponds to. If a characteristic light emitting point is not found in the image, the coordinate system lock may be performed using the pattern around the semiconductor chip.

  FIG. 14B shows a state where the coordinate system lock in which the stage coordinate system and the layout coordinate system of the light emission detection device ELA are made to correspond to each other and the light emission point LHT is displayed on the layout. The coordinate system lock process is executed by, for example, the gate extraction unit GET provided in the analysis support control unit FAS of FIG.

  As shown in FIG. 14B, by performing the coordinate system lock, the light emission coordinates in the microscope image described in the stage coordinate system can be described in the layout coordinate system. Therefore, a box can be drawn on the image displayed so as to surround the light emitting point.

  Then, the drawn box is transmitted to the layout viewer described in the layout coordinate system, and as shown in FIG. 14C, the light emitting box LBX that is a box surrounding the light emitting area is displayed in the layout image. Thereby, the setting of the light emission box LBX is completed. The light emitting box LBX describes the coordinates of each point of the light emitting box in the layout coordinate system.

<Operation example of gate extraction unit>
FIG. 15 is an explanatory diagram showing an example of wiring extraction from the gate in the light emitting box LBX.

  As one of the functions provided in the layout viewer, there is a function called a gate extraction function for extracting a gate in a light emitting box. This process corresponds to the process of step S102 of FIG. 12, and is executed by the gate extraction unit GET provided in the analysis support control unit FAS of FIG.

  The lower left of FIG. 15 shows an example of a gate extracted by the gate extraction function of the gate extraction unit GET. In this example, for example, four gates G1 to G4 are extracted. The lower right part of FIG. 15 shows an example of wiring traces extending from the gates G1 to G4. 15 shows an example of the entire view of the extracted gates G1 to G4 and the wirings Net1 to Net4 that are the specific wirings listed.

  This process corresponds to the process of step S103 of FIG. 12, and is executed by the wiring specifying unit PSF provided in the analysis support control unit FAS of FIG.

  The wiring specifying unit PSF lists up the wirings extending from the extracted gates G1 to G4 by the equipotential tracking function which is a function provided in the layout viewer. In this example, the lines Net1 to Net4 are listed as the lines extending from the extracted gates G1 to G4, respectively.

<Operation example of wiring pair extraction unit>
FIG. 16 is an explanatory diagram showing a display example of the wiring extracted in FIG. 15 and the adjacent wiring.

  The upper part of FIG. 16 shows a display example of the extracted wirings listed in FIG. 15, and the lower part of FIG. 16 shows a display example when listing adjacent wirings with respect to the extracted wirings listed. .

  These are displayed on a display DSP provided in the analysis support apparatus BAS. This processing is executed by the wiring pair extraction unit PPE provided in the analysis support control unit FAS, and corresponds to the processing in step S104 in FIG.

  As shown in the upper part of FIG. 16, the listed extracted wirings display, for example, wiring names, count numbers of light emitting boxes, and histograms of the count numbers. In the example of FIG. 16, since there is only one light emitting box, the count numbers are all “1”, and the histogram is also drawn with the same length.

  Here, when the uppermost wiring Net1 is selected and the “Extract” button B1 of “Adjacent Extract” below is pressed, the extraction of the adjacent wiring by the wiring pair extraction unit PPE is started. Extracted. This result can be browsed by, for example, pressing the “Result View” button B2, and for example, a list from which adjacent wirings are extracted is displayed as shown in the lower part of FIG.

  In the list from which the adjacent wiring is extracted, as shown in the lower part of FIG. 16, the adjacent distance of the wiring, the adjacent wiring layer, the parallel distance, the wiring name, and the wiring coordinates are displayed as information. In addition, these pieces of information can be sorted or highlighted for designated wiring. In highlight display, the original wiring and the adjacent wiring are displayed around the adjacent point.

  FIG. 17 is an explanatory diagram illustrating an example of the wiring pairs listed by the wiring pair extraction unit PPE.

  As shown in FIG. 15, wirings Net1 to Net4 are extracted as specific wirings connected to the gates G1 to G4, respectively. The wiring pair extraction unit PPE extracts all the adjacent wirings for the wirings Net1 to Net4 and displays them on the display DSP provided in the analysis support apparatus BAS as shown in FIG.

  At this time, when a power supply wiring for supplying the power supply voltage VDD and a ground wiring for supplying the reference potential VSS are adjacent to the wirings Net1 to Net4, the power supply wiring or the ground wiring is extracted as an adjacent wiring. . This process corresponds to the process in step S105 in FIG. 12, and is executed by the wiring pair extraction unit PPE provided in the analysis support control unit FAS in FIG.

  For example, in the case of the wiring pair shown in the upper left of FIG. 17, the wiring pair of the wiring Net1 and the adjacent wiring Net1-001 adjacent to the wiring Net1 is displayed, and in the lower right of FIG. A wiring pair with an adjacent wiring Net4-054 adjacent to the wiring Net4 is displayed.

  For example, there are 210, 249, 20, and 54 adjacent wirings in the wirings Net1 to Net4, respectively, and when there are 533 wiring pairs with the adjacent wirings in each of the wirings Net1 to Net4, they are displayed on the display DSP. 533 wiring pairs are displayed. In this way, all the wiring pairs adjacent to the wiring Net1 to the wiring Net4 are displayed on the display DSP.

<Operation example of waveform acquisition unit>
FIG. 18 is an explanatory diagram showing an example of the logical waveform of each wiring acquired by the waveform acquisition unit WFA provided in the analysis support control unit FAS of FIG.

  Next, a logic waveform, that is, a voltage waveform is obtained by logic simulation for the wirings listed by the wiring pair extraction unit PPE. This processing corresponds to the processing in step S106 in FIG. 12, and is executed by the waveform acquisition unit WFA provided in the analysis support control unit FAS in FIG.

  The wiring pair extraction unit PPE transmits a wiring name to the logic simulator SML to obtain a logic waveform. The logic simulator SML observes the logic waveforms of the wirings Net1 to Net4 extracted by the wiring specifying unit PSF and the wirings Net1 to Net4 listed by the wiring pair extraction unit PPE and the wirings that form the wiring pairs, respectively.

  Here, for example, when there are 533 adjacent wirings with respect to the four wirings Net1 to Net4, the logic simulator SML, as shown in FIG. 18, the four wirings Net1 to Net4 and the wirings Net1 to Net4 A total of 537 logic simulations with 533 wirings forming a wiring pair are performed, and the logic waveforms are observed. This observation result is stored in, for example, a storage unit included in the logic simulator SML.

  Subsequently, different potential time zones in the wirings Net1 to Net4 listed by the wiring pair extraction unit PPE are extracted. This process corresponds to the process in step S107 in FIG. 12, and is executed by the different potential time zone calculation unit DPT provided in the analysis support control unit FAS in FIG.

<Operation example of different potential time zone calculator>
FIG. 19 is an explanatory diagram illustrating an extraction example of the different potential time zone calculated by the different potential time zone calculation unit DPT.

  First, the waveform acquisition unit WFA acquires a logic waveform stored in a storage unit included in the logic simulator SML, and transmits all the acquired logic waveforms to the different potential time zone calculation unit DPT. The different potential time zone calculation unit DPT calculates a different potential time zone from the logical waveforms of the acquired wirings Net1 to Net4 and the adjacent wirings that are wiring pairs of the wirings Net1 to Net4.

  In FIG. 19, the left side shows the logic waveform acquired from the logic simulator SML, and the right side shows the different potential time zone calculated by the different potential time zone calculation unit DPT and the result of the same potential time zone.

  On the left side of FIG. 19, the uppermost line shows the logic waveform of the wiring Net1, and the lower part shows the logic waveform of the power supply wiring Power. Below the logic waveform of the power supply wiring, the logic waveform of the ground wiring Ground is shown. Here, the logic waveforms of the power supply wiring Power and the ground wiring Ground are in consideration of the possibility of a short circuit with the power supply wiring Power or the ground wiring Ground.

  Below the logic waveform of the ground wiring, the logic waveform of the adjacent wiring adjacent to the wiring Net1 is shown. Here, as shown in FIG. 17, when there are 210 adjacent wires in the wire Net1, 210 logic waveforms Net1-001 to Net1-210 are respectively calculated.

  Although not shown, the logic waveform of the wiring Net2 is shown below the logic waveform Net1-210, and the logic waveform of the power wiring Power and the logic waveform of the ground wiring Ground are respectively below the logic waveform of the wiring Net2. Indicated. Below the logic waveform of the ground wiring Ground, the logic waveforms of the adjacent wirings adjacent to the wiring Net2 are shown.

  Here, as shown in FIG. 17, when there are 249 adjacent wires in the wire Net2, 249 logic waveforms Net2-001 to Net2-249 are respectively calculated. In this way, the logic waveforms are also shown in the same configuration in the other wirings Net3 and Net4.

  The different potential time zone calculation unit DPT has the same potential time zone in which the logic waveform of the wiring Net1 and the logic waveform of the power wiring Power have the same potential, the logic waveform of the wiring Net1 and the logic waveform of the power wiring Power. The different potential time zones, which are the time zones in which are different from each other, are calculated, and the results are output.

  The uppermost stage on the right side of FIG. 19 shows the same potential time zone between the logic waveform of the wiring Net1 and the logic waveform of the power supply wiring Power calculated by the different potential time zone calculation unit DPT, and the logic waveform of the wiring Net1 and the logic waveform of the power supply wiring Power. The result Pair1-P of the different potential time zone is shown.

  As a result, in Pair1-P, the white part is a different potential time zone in which the logic waveform of the wiring Net1 and the logic waveform of the power supply power are different, and the hatched part is the logic waveform of the wiring Net1 and the power supply. The same potential time zone in which the logic waveform of the wiring Power is at the same potential is shown.

  Below the result Pair1-P, a result Pair1-G indicating the calculation result of the logic waveform of the wiring Net1 and the logic waveform of the ground wiring Ground is shown. Below the result Pair1-G, the wiring Net1 is displayed. A result Pair1-001 indicating the calculation result of the logical waveform and the logical waveform of the logical waveform Net1-001 is shown.

  Hereinafter, similarly, the results are shown for all the adjacent wirings including the wirings Net1 to Net4, the power supply wiring Power, and the ground wiring Ground. Here, as shown in FIG. 17, when there are 210 adjacent wirings in the wiring Net1, 210 results Pair1-001 to Pair1-210 are calculated in addition to the results Pair1-P and Pair1-G. Is done.

  Similarly, when there are 249 adjacent wirings in the wiring Net2, in addition to the results Pair2-P and Pair2-G, 249 results Pair2-001 to Pair2-249 are calculated.

  Similarly, when there are 20 adjacent wires in the wire Net3, 20 results Pair3-001 to Pair3-020 are calculated in addition to the results Pair3-P and Pair3-G, and 54 wires are calculated in the wire Net4. When there are adjacent wirings, in addition to the results Pair4-P and Pair4-G, 54 results Pair4-001 to Pair4-054 are calculated.

<Operation example of index data calculation unit>
Subsequently, the number of photons that enter the same potential time zone and the different potential time zone, which are the results calculated by the different potential time zone calculation unit DPT, is calculated. This processing corresponds to the processing in step S108 in FIG. 12, and is executed by the index data calculation unit IDC provided in the analysis support control unit FAS in FIG.

  First, the index data calculation unit IDC accesses the light emission detection device ELA of FIG. 11 and obtains data of the light emission time in the semiconductor chip stored in the storage device of the light emission detection device ELA. This data is data of the light emission time at the light emission position detected by the light emission detection device ELA in the process of step S101 of FIG.

  FIG. 20 is an explanatory diagram showing an example of counting of different potential time zones and photons.

  When the index data calculation unit IDC acquires the light emission time data, the index data calculation unit IDC compares the light emission time data with the different potential time zone as shown in FIG. Then, the number of photons entering the different potential time zone and the number of photons entering the same potential time zone are calculated. If a photon enters in the different potential time zone, +1 is set. If a photon enters in the same potential time zone, +1 is set.

  In FIG. 20A, for example, in the case of result Pair1-P, the total number of photons is 38. Of the 38 photons, the number of photons in the different potential time zone is 15, so the count is +15. Since the number of photons in the same potential time zone is 23, the count number is −23. Therefore, the score is 15-23 = −8.

  As described above, the index data calculation unit IDC performs all the results Pair1-P, Pair1-G, Pair1-001 to Pair1-210, Pair2-P, Pair2-G, Pair2-001 to Pair2-249, Pair3-P, Scores are calculated for Pair3-G, Pair3-001 to Pair3-020, Pair4-P, Pair4-G, Pair4-001 to Pair4-054. As shown in FIG. 20B, the index data calculation unit IDC displays the score along with the score, for example, as a histogram.

  In the example of FIG. 20, the result Pair1-002 has a score of +10, and since the number of photons in the different potential time zone is the largest, there is a possibility that a wiring short circuit has occurred in the wiring Net1 and the adjacent wiring Net1-002. Is estimated to be high. Here, although the total number of photons is 38, the accuracy of estimation can be further increased by increasing the number of detected photons.

  FIG. 21 is an explanatory diagram showing an example when the number of detected photons is increased in the score calculation of FIG.

  Here, a case where the number of detected photons is increased will be considered.

  First, in the capture of photons, there are photons that enter as signals and photons that enter as noise, and the average of each is 100 photons / time division and 10 photons / time division.

  Actually, there are peaks and valleys, but when considered as an average, it is considered that noise is 1/10 of the signal as a reasonable assumption in photon detection. When such photon detection is performed, the time-resolved image of the detected photon is a diagram shown in the upper part of FIG.

  When the scores are calculated for the different potential time zones and the same potential time zones by the method described with reference to FIG. 20, a histogram of the scores is displayed as in the window shown in FIG.

  In this case, the score of result Pair1-002 is the highest, and is nearly twice that of the second highest result Pair1-G. Even in numerical values, there is a clear difference between the score value of +1810 and +3090.

  As a result of this calculation, it is estimated that the wiring pair most likely to be short-circuited is the wiring pair of the result Pair1-002, that is, the wiring Net1 and the adjacent wiring Net1-002 with higher accuracy than in the case of FIG. can do.

  Here, since the simulated range of the logic waveform is not so wide, there are pairs with a large negative score in comparison with the light emission, but in contrast, if the simulation range is wide, it actually does not depend on the timing of light emission Since there are different potential time zones and equipotential time zones, it can be predicted that the score is concentrated around 0 for pairs not related to short circuit.

<Operation example of index data output unit>
Subsequently, based on the score calculation result shown in FIG. 21, the wiring pairs having a high possibility of short-circuiting are sorted, and for example, the most suspected wiring pair having the highest score value is highlighted. This processing corresponds to the processing in steps S109 and S110 in FIG. 12, and is executed by the index data output unit IDO provided in the analysis support control unit FAS in FIG.

  When the index data output unit IDO receives the score calculation result from the index data calculation unit IDC, the index data output unit IDO sorts the display order of the wiring pairs shown in FIG. 17 so that the score values are in descending order, and displays them on the display DSP. . At this time, the wiring pair with the highest score value is highlighted.

  As shown in FIG. 20 or FIG. 21, since the wiring pair with the highest score value is the wiring Net1 of the result Pair1-002 and the adjacent wiring Net1-002, the display DSP of the analysis support apparatus BAS includes the wiring Net1. And the wiring pair of the adjacent wiring Net1-002 are highlighted and displayed first.

  For example, when the wiring pair is listed by the wiring pair extraction unit PPE as shown in FIG. 17, the wiring pair of the wiring Net1 having the highest score value and the adjacent wiring Net1-002 is displayed in the upper left. .

  On the left side of the wiring pair of the wiring Net1 and the adjacent wiring Net1-002, the pair wiring of the wiring Net1 having the second highest score value and the ground wiring Ground is displayed. The observer then performs a hardware analysis based on the result displayed on the display DSP.

  In the hardware analysis, pads are formed on both wirings of the wiring pair having the highest score value, that is, the wiring Net1 suspected of being short-circuited and the adjacent wiring Net1-002 by FIB, and needles are applied to these pads. Then, an OBIRCH (Optical Beam Induces Resistance Change) analysis may be performed.

  In that case, even when the parallel running distance between adjacent wirings is long, the shorted portion can be narrowed down to about several μm.

  Also, FIB pads are formed by FIB for all wirings including a gate in the light emitting region, and EBAC analysis is performed. When short wirings can be observed by the EBAC analysis, pads are formed in the wirings and OBIRCH analysis is performed to short-circuit. You may make it identify a location.

  As described above, the failure analysis method according to the present embodiment can be realized. In the failure analysis method according to the first embodiment, a typical failure analysis method is described until a counterpart wiring that is short-circuited with a specific wiring is estimated.

  However, of course, the defect to be analyzed has a different aspect depending on the defect, and the specific wiring that is the analysis target wiring is specified by skipping any analysis process or using not only the light emission analysis but also the OBIRCH analysis. Or several types of failure diagnosis. In any case, it is desirable to select a method that can reduce the analysis time as much as possible while proceeding with the failure analysis while having the highest certainty.

  In the flowchart shown in FIG. 12, the process up to estimating a wiring pair that is likely to be short-circuited is described. However, if the failure analysis is further advanced, another analysis method such as EBAC analysis is performed. To identify the location of the defect that caused the failure by performing the OBIRCH analysis by pinpointing the specific wiring that is the analysis target wiring and the counterpart wiring, etc. Step on.

  Finally, defects are observed with SEM (Scanning Electron Microscope), TEM (Transmission Electron Microscope), etc., and elements are further observed with EDX (Energy Dispersion X-ray Spectroscopy), SIMS (Secondary Ion Mass Spectroscopy), etc. Advance the physical analysis process to identify Thereby, the identity of the defect can be clarified and linked to a countermeasure for removing the cause of the defect.

<Advantage of this embodiment>
In the following, the superiority of the technical idea in the present embodiment will be described in comparison with the technique studied by the present inventors. In the prior art before the technical idea in the present embodiment has been conceived, for example, EBAC analysis is used as a failure analysis technique for identifying a specific wiring that is an analysis target wiring and a short-circuited, so-called short-circuited wiring. Has been.

  First, the EBAC analysis technique will be described with reference to the drawings. FIG. 22 is an explanatory diagram of the mechanism of the EBAC analysis technique.

  In FIG. 22, for example, a field effect transistor that forms part of an integrated circuit is formed on a semiconductor substrate 1S. This field effect transistor has a source region SR and a drain region DR which are semiconductor regions in a semiconductor substrate 1S, and a region between the source region SR and the drain region DR becomes a channel region. A gate electrode G is formed on the channel region via a gate insulating film GOX.

  A wiring is electrically connected to the field effect transistor configured as described above. For example, the source line SR is electrically connected to the source region SR, and the drain line DL is electrically connected to the drain region DR.

  In addition, a gate wiring GL is electrically connected to the gate electrode G. The gate wiring GL, the drain wiring DL, and the source wiring SL are composed of a plurality of wiring layers, and the wiring layers are formed in the interlayer insulating film IL.

  Here, it is assumed that the gate wiring GL shown in FIG. 22 is the analysis target wiring. In this case, in the EBAC analysis, the pad FPD electrically connected to the gate wiring GL is formed by, for example, FIB processing.

  In the EBAC analysis, first, electrons irradiated to the integrated circuit from the electron beam irradiation / scanning unit EBU penetrate to a depth depending on the acceleration voltage. In this case, it is assumed that the acceleration voltage is adjusted so that the gate wiring GL is irradiated with electrons.

  Then, the electrons absorbed by the gate line GL pass through the gate line GL and are extracted from the probe PRB that is in contact with the pad FPD. A current made up of electrons drawn out to the probe PRB is amplified by an amplifier AMP and then input to a scanning electron microscope to form a two-dimensional image. Thereby, an image of the gate wiring GL can be observed.

  Here, when an open defect has occurred in the gate wiring GL, unlike the layout data, the wiring image is interrupted in the middle of the gate wiring GL. On the other hand, when a short circuit defect has occurred in the gate wiring GL, a wiring image of the counterpart wiring short-circuited with the gate wiring GL is observed. With such a mechanism, in the EBAC analysis, for example, a counterpart wiring that is short-circuited with a specific wiring can be specified.

  Hereinafter, the flow of failure analysis in the prior art from the analysis of the wiring to be analyzed to the physical analysis will be described.

  FIG. 23 is a flowchart showing the flow of failure analysis examined by the present inventors. As shown in FIG. 23, first, when a specific wiring related to a short-circuit defect is specified (S201), a first pad electrically connected to the specific wiring is formed by first FIB processing ( S202).

  Thereafter, an EBAC analysis is performed to identify the counterpart wiring that is short-circuited with the specific wiring (S203). At this time, when there are a plurality of locations close to each other between the specific wiring and the counterpart wiring, it is not possible to specify which location is a short-circuited location. For this reason, the 2nd pad electrically connected with the other party wiring is formed by the 2nd FIB processing (S204).

  Then, OBIRCH analysis is performed by performing needle contact on both the first pad electrically connected to the specific wiring and the second pad electrically connected to the counterpart wiring (S205). Since the short portion has a higher resistance than the current path by wiring, the short portion can obtain a stronger reaction in the current route when the laser is irradiated in the OBIRCH analysis. Therefore, the short portion is specified. be able to.

  In this way, after identifying the counterpart wiring that is short-circuited with the specific wiring and specifying the short-circuited portion, physical analysis is performed (S206).

  In the failure analysis in the above-described technique, the first FIB processing step for forming the first pad that is electrically connected to the specific wiring that is the analysis target wiring, and the second FIB processing for forming the second pad that is electrically connected to the counterpart wiring. The process exists in a separate process.

  Since this FIB processing step often takes time to form, if the first FIB processing step and the second FIB processing step exist separately, the failure analysis time becomes long.

  Note that the main application target in the present embodiment is an integrated circuit including a logic circuit such as a microcomputer or SOC (System On Chip), but is not limited to this, for example, a peripheral circuit of a built-in memory, There is a possibility that it can be widely applied to failure analysis inside memory and failure analysis of analog circuits.

  Based on the above, it is possible to estimate a wiring pair that is suspected of being short-circuited by acquiring data on the light emission position and the light emission time. Even when there are a large number of wiring pairs, a wiring pair suspected of being short-circuited can be efficiently estimated from these wiring pairs. As a result, the success rate of failure analysis can be improved and the analysis time can be shortened.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1S semiconductor substrate SR source region DR drain region GOX gate insulating film G gate electrode SL source wiring DL drain wiring GL gate wiring IL interlayer insulating film FPD pad EBU electron beam irradiation / scanning part SED secondary electron detector ML multilayer wiring layer L wiring LDU Photodetector CL1 Cell CL2 Cell CL3 Cell CL4 Cell ST Short location SML Logic simulator ELA Light emission detector BAS Analysis support device CPU Controller ROM Nonvolatile memory RAM Volatile memory DSP Display KEY Keyboard MUS Mouse CBD Communication board RMD Removal Disk device CVD CD / DVD-ROM device HDD Hard disk device PRT Printer SCN Scanner FAS Analysis support control unit BUS Bus PRG Program group FLE File group LTD Light emission position Acquisition unit GET Gate extraction unit PSF Wiring identification unit PPE Wiring pair extraction unit WFA Waveform acquisition unit DPT Different potential time zone calculation unit IDC Index data calculation unit IDO Index data output unit LHT Light emission point LBX Light emission box G1 Gate G2 Gate G3 Gate G4 Gate PRB probe AMP amplifier

Claims (8)

Obtaining the position and time of the abnormal phenomenon based on the abnormal phenomenon from the transistor;
Extracting a gate of a transistor included in the position of the abnormal phenomenon;
Extracting the wiring connected to the extracted gate as a specific wiring;
Extracting the wiring adjacent to the specific wiring as an adjacent wiring, extracting the adjacent wiring and the specific wiring as a wiring pair;
Executing a logic simulation of the specific wiring and the adjacent wiring, and obtaining a voltage waveform obtained from the result of the logic simulation;
Comparing voltage waveforms in the wiring pair, calculating a different potential time zone in which the voltage of the specific wiring and the voltage of the adjacent wiring constituting the wiring pair are different from each other;
Calculating index data serving as an index of the possibility of short-circuiting with the specific wiring based on the number of times of light emission belonging to the different potential time zone and the number of times of light emission belonging to a time zone other than the different potential time zone;
A method for analyzing a failure of a semiconductor device. The failure analysis method for a semiconductor device according to claim 1,
The transistor is a field effect transistor;
The defect analysis method for a semiconductor device, wherein the abnormal phenomenon is light emission based on a light emission phenomenon that occurs immediately below the gate electrode of the field effect transistor. The defect analysis method for a semiconductor device according to claim 2,
In the step of calculating the index data,
Based on the time of the light emission, the number of times of light emission belonging to the different potential time zone and the number of times of light emission belonging to other than the different potential time zone are respectively tabulated, and the number of times of light emission belonging to the different potential time zone and other than the different potential time zone. A failure analysis method for a semiconductor device, wherein the index data is calculated by taking a difference from the number of times of light emission belonging to. The failure analysis method for a semiconductor device according to claim 1,
The semiconductor device defect analysis method, wherein the specific wiring to be extracted includes a power supply wiring and a ground wiring. The failure analysis method for a semiconductor device according to claim 1,
The semiconductor device failure analysis method further comprises the step of associating the index data with the extracted wiring pair. The defect analysis method for a semiconductor device according to claim 5,
The semiconductor device failure analysis method further includes a step of sorting the wiring pairs associated with the index data in descending order of possibility of short-circuiting with the specific wiring based on the index data. The failure analysis method for a semiconductor device according to claim 1,
The indicator data is
Index points that are numerical data,
A failure analysis method for a semiconductor device, comprising: index graph data illustrating the index data. The defect analysis method for a semiconductor device according to claim 7,
The semiconductor device failure analysis method, wherein the index graph data is in a histogram format.

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