JP2014127886A - Image processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve acceleration of color conversion using hardware by a simple hardware configuration.SOLUTION: An image processing apparatus performs color conversion of a pixel outputted from a comparison processing part by a color conversion part, writes the color-converted pixel in an output buffer and copies and writes a pixel value of the pixel concerned in pixels with the same pixel value. The comparison processing part includes: a first comparator 32a; a first memory 34a for storing an address of a representative pixel of a second sub-block whose comparison result by the first comparator 32a is inconsistency; a second comparator 32b; a second memory 34b for storing addresses of representative pixels of respective second sub-blocks in a first sub-block whose comparison result by the second comparator 32b is inconsistency; and read control parts 36, 37 for reading out respective pixels other than the representative pixel of the first sub-block, the representative pixels whose addresses are stored in the second memory 34b and the representative pixel whose address is stored in the first memory 34a as pixels to be color-converted.

Description

  The present invention relates to an image processing apparatus.

In an image forming apparatus such as a printer or a copier, color conversion is performed on image data, and the color space of the input image data is matched with a color space that can be expressed by the image forming apparatus.
Since the color spaces are in a complicated relationship, the LUT (Look Up Table) in which the output value after color conversion is defined for the input value is not calculated one by one at the time of color conversion. (For example, refer to Patent Document 1). When an output value corresponding to all input values is determined in the LUT, a large capacity memory is required. Therefore, an ordinary LUT determines input values and output values only for representative colors, and outputs other values by interpolation. I am getting the value.

  Even if only the representative color holds the input value and the output value, the necessary memory capacity is not small. As the number of colors constituting the color space increases, the amount of data in the LUT increases and a large-capacity memory is required. It is known that a large burden is required for mounting such a color conversion circuit having a memory on hardware such as LSI (Large Scale Integration).

  In general, in order to speed up processing by hardware, it is effective to provide a plurality of processing circuits and perform processing in parallel. However, with respect to the color conversion circuit, since the large-capacity memory as described above is provided in parallel, mounting on hardware is more difficult. This is particularly difficult in an image forming apparatus that uses multiple colors such as C (cyan), M (magenta), Y (yellow), and K (black).

Therefore, conventionally, color conversion is often performed by software instead of hardware (see, for example, Patent Documents 1 and 2).
When color conversion is performed by software, the time required for color conversion of one pixel is longer than when color conversion is performed by hardware. However, the image areas of characters and figures are often the same color as long as they are within the image area of the same character and figure, and batch conversion is possible according to software. Therefore, if the image data has a large number of character and graphic image areas, the processing time can be shortened even with software color conversion.

  The above-mentioned patent document 1 makes use of such characteristics to obtain a continuous number of pixels having the same pixel value as the target pixel, and repeats the pixel value after color conversion of the target pixel by the continuous number, thereby performing color conversion processing. Time has been shortened. According to Patent Document 2, the same processing as Patent Document 1 is performed at the stage of generating image data by a printer driver.

JP 2008-205636 A JP 2004-54653 A

  On the other hand, image data often includes an image area of a photograph in addition to characters and figures. The image area of a photograph is not necessarily the same color, and it is difficult to predict pixel values of adjacent pixels. For this reason, there is no method other than color conversion for each pixel, which causes a reduction in processing speed. After all, color conversion by software has a longer processing time than color conversion by hardware, and speeding up of color conversion is desired.

  An object of the present invention is to realize high-speed color conversion by hardware with a simple hardware configuration.

According to the invention of claim 1,
A first input buffer for inputting image data in units of blocks and holding a plurality of blocks;
A comparison processing unit that inputs one block from the first input buffer, compares pixel values of each pixel in the one block, and outputs pixels for color conversion of the one block;
A color conversion unit that performs color conversion on the pixels output from the comparison processing unit;
An output buffer;
The pixel converted by the color conversion unit is written to the output buffer, and the pixel value of the pixel subjected to the color conversion is copied to a pixel whose pixel value matches the pixel subjected to the color conversion as a result of the comparison. And a buffer controller for writing
The comparison processing unit
A second input buffer;
A writing control unit for writing one block held in the first input buffer to the second input buffer;
The pixel value of each pixel in the second sub-block obtained by further dividing the first sub-block obtained by dividing the one block is compared, and the comparison indicating whether the pixel values match or do not match A first comparator for outputting a result;
A first memory for holding an address of a representative pixel of a second sub-block in which the comparison result by the first comparator does not match;
The pixel values of the representative pixels of the second sub-blocks in the first sub-block are compared, and if the pixel values match and the comparison result by the first comparator is coincident, the coincidence comparison result is output. A second comparator that outputs a non-matching comparison result when each pixel value does not match or the comparison result by the first comparator does not match,
A second memory for holding the address of the representative pixel of each second sub-block in the first sub-block in which the comparison result by the second comparator is inconsistent;
The pixels to be color-converted are pixels other than the representative pixel of the first sub-block, the representative pixel of the second sub-block whose address is held in the second memory, and the representative pixel whose address is held in the first memory. A read controller that reads out and outputs each pixel in the second sub-block from the second input buffer;
An image processing apparatus is provided.

According to invention of Claim 2,
The comparison processing unit includes a plurality of comparison modules including the second input buffer, the write control unit, the first comparator, the first memory, the second comparator, the second memory, and the read control unit. A plurality of blocks are input, each block is compared in parallel by each comparison module, and the pixels for color conversion of each block are sequentially output to the color conversion unit.
An image processing apparatus according to claim 1 is provided.

According to invention of Claim 3,
The write control unit uses a write address assigned in the order of each pixel other than the representative pixel in the first sub-block, the representative pixel in the second sub-block, and the representative pixel in the second sub-block in the second input buffer. Output and assign an address to one block written in the second input buffer;
An image processing apparatus according to claim 1 or 2 is provided.

According to invention of Claim 4,
The first comparator and the second comparator also compare the color space when comparing each pixel value, and if the pixel value and the color space match, each pixel value outputs a comparison result of matching, If the color space does not match, output a comparison result where each pixel value does not match.
An image processing apparatus according to any one of claims 1 to 3 is provided.

According to the invention of claim 5,
The first comparator and the second comparator also compare attributes when comparing each pixel value, and if the pixel value and the attribute match, each pixel value outputs a comparison result indicating that the pixel value or attribute matches. If they do not match, output a comparison result where each pixel value does not match.
An image processing apparatus according to any one of claims 1 to 3 is provided.

  According to the present invention, when the pixel values in the first sub-block match, color conversion can be performed collectively in units of the first sub-block. When the pixel values in the first sub-block do not match, color conversion can be performed in batch or color conversion can be performed for each pixel in units of the second sub-block smaller than the first sub-block. Therefore, the number of pixels for color conversion can be reduced and the color conversion processing time can be shortened. Even if there is only one color conversion unit, it is possible to increase the speed of color conversion, and it is possible to increase the speed of color conversion by hardware with a simple hardware configuration.

2 is a functional block diagram of the image forming apparatus. FIG. It is a block diagram of the component which performs color conversion of the image processing apparatus which concerns on 1st Embodiment. An example of inputting image data is shown. It is a block diagram of the comparison process part of FIG. The example of the address allocated to each pixel of 1 block is shown. The first comparator and the second comparator indicate the processing time required for comparison. (A) It is an example of the input order of the pixel to a color conversion part. (B) It is an example of the input order of the pixel to a color conversion part. (C) shows an example of the order of input of pixels to the color conversion unit when there is no second memory. An example of copying a color-converted pixel is shown. It is a block diagram in case a comparison process part is provided with the 3rd comparator. It is a block diagram of the component part which performs color conversion of the image processing apparatus which concerns on 2nd Embodiment. It is a block diagram of the comparison process part provided with the several comparison module. The comparison and color conversion processing times when a plurality of comparison modules are provided are shown. (A) When there is a non-matching pixel in one block, the processing time required for one comparison module and the processing time required for color conversion are shown. (B) When all the pixels in one block match, the processing time required for one comparison module and the processing time required for color conversion are shown. (C) When all the pixels in one block match, the processing time required for comparison and the processing time required for color conversion by a plurality of comparison modules are shown.

  Embodiments of an image processing apparatus according to the present invention will be described below with reference to the drawings.

[First Embodiment]
FIG. 1 is a functional block diagram of the image forming apparatus T. In the image forming apparatus T, the image processing apparatus G1 according to the first embodiment is mounted.
The image forming apparatus T forms an image on a sheet based on the image data. The image forming apparatus T can obtain image data by reading a document, or can obtain image data from PDL (Page Description Language) data received from a computer on a network.
As shown in FIG. 1, the image forming apparatus T includes a print controller 1, an image reading unit 2, an image memory 3, an image processing device G1, an image forming unit 4, a control unit 5, a storage unit 6, an operation unit 7, and a display unit. 8 and a communication unit 9.

  The print controller 1 includes a communication unit, receives PDL data from a computer on the network, rasterizes the PDL data, and generates bitmap format image data. The print controller 1 generates image data of four colors of C (cyan), M (magenta), Y (yellow), and K (black). The generated image data is output to the image memory 3 and held.

The print controller 1 generates attribute data indicating attributes for each pixel during the rasterization process. The attribute data is output together with the image data.
The attributes include text, graphics, and images. The print controller 1 sets the attribute of the pixel corresponding to each object of a character, a figure, and a photograph to the attribute of a character, a figure, and a photograph, respectively.

  The image reading unit 2 reads an original with a scanner or the like and generates image data of three colors of R (red), G (green), and B (blue). The generated image data is output to the image memory 3 and held.

  The image memory 3 is a memory that holds image data. As the image memory 3, a DRAM (Dynamic Random Access Memory) or the like can be used.

The image processing device G1 reads R, G, and B image data generated by the image reading unit 2 from the image memory 3, performs color conversion, and outputs C, M, Y, and K image data.
The image data generated by the print controller 1 is a color space of C, M, Y, and K, but the image processing device G1 converts the color of the image data and performs color correction on C, M, Y, and K. The image data can also be output.

The image processing device G1 performs various types of image processing on the color-converted image data.
For example, the image processing apparatus G1 compresses the color-converted image data, writes the image data in the image memory 3, reads out the image data from the image memory 3 in accordance with an instruction from the control unit 5, and decompresses the image data. The image processing apparatus G1 can also perform image processing such as enlargement or reduction, rotation, addition of a stamp and a page number on image data in accordance with an instruction from the control unit 5.
Further, the image processing apparatus G1 performs halftone processing on the image data and outputs the processed image data to the image forming unit 4. Examples of halftone processing include screen processing and error diffusion processing.

The image forming unit 4 forms an image on a sheet based on the image data.
Specifically, the image forming unit 4 includes four sets of an exposure unit, a development unit, and a photoreceptor for each of C, M, Y, and K colors. The exposure unit exposes the charged and rotating photoconductor by optical scanning based on the image data. The developing unit develops the electrostatic latent image formed on the photoreceptor by exposure with toner. The images of the respective colors formed on the four photoconductors in this way are transferred onto the paper in a superimposed manner via an intermediate transfer belt or the like, and fixed by a fixing device.

The control unit 5 includes a CPU (Central Processing Unit), a RAM (Random Access Memory), and the like. The control unit 5 reads a program stored in the storage unit 6 and controls each unit of the image forming apparatus T according to the program.
For example, the control unit 5 causes the image processing apparatus G1 to perform image processing on the image data and causes the image forming unit 4 to form an image.

  The storage unit 6 stores programs, files, and the like that can be read by the control unit 5. As the storage unit 6, for example, a storage medium such as a hard disk or a ROM (Read Only Memory) can be used.

The operation unit 7 includes an operation key and a touch panel configured integrally with the display unit 8, and outputs operation signals corresponding to these operations to the control unit 5.
The display unit 8 displays an operation screen and the like according to instructions from the control unit 5.
The communication unit 9 communicates with a server on the network according to an instruction from the control unit 5.

FIG. 2 shows components that perform color conversion of the image processing apparatus G1.
As shown in FIG. 2, the image processing apparatus G1 includes a buffer control unit g0, a first input buffer g1, a comparison processing unit g2A, a color conversion unit g3, an output buffer g4, and a buffer control unit g5.

The buffer control unit g0 writes and reads image data to and from the first input buffer g1.
The buffer control unit g0 outputs an enable signal and a write address to the first input buffer g1, and writes image data to the first input buffer g1 in units of blocks.
Further, the buffer control unit g0 outputs an enable signal and a read address to the first input buffer g1, and reads image data from the first input buffer g1 in units of blocks.

The first input buffer g1 is a memory that holds image data in units of blocks.
The first input buffer g1 inputs the image data held in the image memory 3 in units of blocks according to the enable signal and the write address from the buffer control unit g0, and holds a plurality of blocks. By holding a plurality of blocks, each block can be continuously output to the comparison processing unit g2A, which is preferable.
FIG. 3 shows an input example of image data.
As shown in FIG. 3, the first input buffer g1 holds, for example, 8 blocks of image data with 8 × 8 pixels as one block.

The comparison processing unit g2A receives one block from the first input buffer g1, compares the pixel value of each pixel in the one block, and outputs a pixel for color conversion of the one block.
At this time, the comparison processing unit g2A outputs the address ADRS of the pixel to be color-converted and the comparison result cmp to the buffer control unit g5.

The color conversion unit g3 performs color conversion on the pixel output from the comparison processing unit g2A.
The color conversion unit g3 includes a memory that holds a plurality of LUTs, and switches each LUT to use for color conversion. For example, when the color conversion of the image data generated by the image reading unit 2 is performed, the color conversion unit g3 outputs an LUT in which output values of C, M, Y, and K are determined for the input values of R, G, and B. Use. In addition, the color conversion unit g3 outputs the C, M, Y, and K corrected output values for the C, M, Y, and K input values at the time of color conversion of the image data generated by the print controller 1. A defined LUT is used.

In addition to the LUT, the color conversion unit g3 uses various color spaces such as L ^* a ^* b ^* , L ^* u ^* v ^* , sRGB and Adobe (registered trademark) RGB in C, M, Y, and K colors. It is preferable to provide an LUT corresponding to the space.
The color conversion unit g3 can widely correspond to the color space of the input image data by performing color conversion by switching the LUT according to the color space of the input image data.

Further, the color conversion unit g3 preferably includes an LUT for each attribute.
For example, since the required color characteristics differ between characters and photographs depending on the attributes, color characteristics suitable for each attribute can be reproduced by color conversion by using an LUT corresponding to the attributes.
The color conversion unit g3 includes, for example, three types of LUTs that reproduce color characteristics according to the attributes of characters, graphics, and photographs as LUTs that associate R, G, B, and C, M, Y, and K. The LUT may be switched depending on the attribute of the pixel to be color converted.
Since the image data is output together with the attribute data, the color conversion unit g3 can determine the attribute of each pixel based on this attribute data.

  In order to reduce the amount of data, the LUT can be an LUT in which input values and output values are composed of representative values of each color space. The color conversion unit g3 can interpolate a representative value close to the input value and obtain an output value.

Similar to the first input buffer g1, the output buffer g4 is a memory that holds image data in units of blocks.
The output buffer g4 holds each pixel after color conversion of a plurality of blocks output from the color conversion unit g3 according to the enable signal and the write address from the buffer control unit g5.
In addition, each held block is output in accordance with the enable signal and read address from the buffer control unit g5.

The buffer control unit g5 writes and reads image data to and from the output buffer g4.
The buffer control unit g5 outputs the enable signal and the write address to the output buffer g4 using the address ADRS output from the comparison processing unit g2A, and writes the pixel color-converted by the color conversion unit g3 to the output buffer g4. .
A pixel that has not undergone color conversion is a pixel whose pixel value matches that of the color-converted pixel. The buffer control unit g5 copies the pixel value of the color-converted pixel to the pixel whose pixel value matches the color-converted pixel according to the comparison result cmp output from the comparison processing unit g2A, and outputs an output buffer Write to g4.
Further, the buffer control unit g5 outputs an enable signal and a read address to the output buffer g4, and reads image data in units of blocks.

FIG. 4 is a configuration diagram of the comparison processing unit g2A.
As shown in FIG. 4, the comparison processing unit g2A includes a write control unit 30, a second input buffer 31, a first comparator 32a, a second comparator 32b, a memory control unit 33, a first memory 34a, and a second memory. 34b, a selector 35, read control units 36 and 37, and counters C1 to C3.

  The write control unit 30 outputs the enable signal WE and the write address WADRS to the second input buffer 31, and writes one block held in the first input buffer g1.

The second input buffer 31 is a memory that holds one block of image data.
The second input buffer 31 is preferably a memory that can hold a plurality of blocks in order to continuously output pixels to be color-converted between the plurality of blocks to the color conversion unit g3.

The second input buffer 31 receives one block from the first input buffer g1 in response to the enable signal WE from the write control unit 30, and holds the one block. At this time, the second input buffer 31 assigns and holds an address to each pixel of one block in accordance with the write address WADRS.
The write address WADRS is a representative pixel of the first sub-block obtained by dividing one block, a representative pixel of the second sub-block obtained by dividing the first sub-block, Addresses are assigned in the order of pixels other than the representative pixel. Such a write address WADRS makes it easy to read out the pixel for color conversion.

FIG. 5 shows an example of addresses assigned to one block. In FIG. 5, a circle represents a pixel, and 0 to 15 or a combination of 0 to 15 and a to c in the circle represents an address assigned to each pixel.
As shown in FIG. 5, when one block of 8 × 8 pixels is equally divided in the main scanning direction and the sub-scanning direction, four first sub-blocks of 4 × 4 pixels are obtained. Similarly, when the first sub-block is further equally divided, 16 second sub-blocks composed of 2 × 2 pixels are obtained.

The division method for one block is not limited to this. For example, 8 × 8 pixels are divided into four in the sub-scanning direction to obtain four first sub-blocks each consisting of 8 × 2 pixels, and the first sub-block is divided into two in the main scanning direction to obtain 4 × 2 pixels. Eight second sub-blocks can be obtained.
Considering the possibility of converting the image data to a low resolution, it is preferable that the second sub-block has the same number of pixels in the main scanning direction and the sub-scanning direction.

The first pixel of the first sub-block and the second sub-block, that is, the pixel located at the upper left in the first sub-block or the second sub-block is the representative pixel. When the first pixel is a representative pixel, the representative pixel of the first sub-block and the second sub-block may be the same pixel.
The representative pixel is not limited to the top pixel, and may be any one pixel in the first sub-block or the second sub-block. The first sub-block may have different settings, such as the first pixel and the second sub-block may be located in the upper right.

Each pixel in one block is input line by line starting from the top left pixel. Since the write address WADRS is output in the order of 0, 0a, 4, 4a, 1, 1a, 7, 7a, 0b, 0c,..., This address is assigned in order from the first pixel. As a result, as shown in FIG. 5, addresses 0 to 3 are assigned to the representative pixels of the first sub-blocks. Addresses 4 to 15 are assigned to the representative pixels of each second sub-block, except for representative pixels that have already been assigned addresses as representative pixels of the first sub-block.
Further, the three pixels other than the representative pixel in each second sub-block are assigned addresses in which a to c are combined with addresses 0 to 15 of the representative pixel according to the position in the second sub-block. For example, in the second sub-block whose representative pixel address is 0, the top left pixel is assigned 0, the top right pixel is 0a, the bottom left pixel is 0b, and the bottom right pixel is assigned the address 0c.

The second input buffer 31 outputs the pixel corresponding to the read address RADRS output from the selector 35 to the first comparator 32 a or the read control unit 37 in response to the enable signal output from the read control unit 36.
When the enable signal from the read control unit 36 is 0, read addresses RADRS of 0 to 15 are output from the selector 35. In this case, the second input buffer 31 sequentially outputs each second sub-block having addresses 0 to 15 as representative pixels to the first comparator 32a. For example, when an address of 0 is input, the second input buffer 31 outputs four pixels of addresses 0, 0a, 0b, and 0c to the first comparator 32a.

When the enable signal from the read control unit 36 is 1, the read address RADRS of 0 to 3 is output from the selector 35. In this case, the second input buffer 31 outputs the representative pixel of each first sub-block having addresses 0 to 3 to the read control unit 37.
When the enable signal from the read control unit 36 is 2, the representative address of each second sub-block in the first sub-block in the first sub-block in which the comparison result by the second comparator 32b did not coincide with the read address RADRS from the selector 35. The address is output. The second input buffer 31 outputs the representative pixel to the readout control unit 37.
When the enable signal from the read control unit 36 is 3, the selector 35 outputs the address of the representative pixel of the second sub-block where the comparison result by the first comparator 32a does not match as the read address RADRS. The second input buffer 31 outputs three pixels in the second sub-block other than the representative pixel to the read control unit 37.

The first comparator 32a compares the pixel values of the pixels every time each pixel of the second sub-block is output from the second input buffer 31, and the pixel values in the second sub-block match or do not match. A comparison result indicating this is output to the memory control unit 33. The first comparator 32a outputs to the first memory 34a the address of the representative pixel of the second sub-block whose comparison result does not match.
The first comparator 32a outputs the representative pixel of each second sub-block together with the comparison result to the second comparator 32b.

  The second comparator 32b compares the pixel value of each representative pixel every time the representative pixel of each second sub-block in the first sub-block is output from the first comparator 32a. The second comparator 32b matches the pixel values in the first sub-block when the pixel values of the representative pixels match and the comparison results by the first comparators 32a of the second sub-blocks match. A comparison result indicating that this is to be performed is output to the memory control unit 33. On the other hand, when the pixel values of the representative pixels do not match or the comparison result by the first comparator 32a of any second sub-block does not match, the pixel values in the first sub-block do not match. Is output to the memory control unit 33.

  The second comparator 32b outputs, to the second memory 34b, the address of the representative pixel of each second sub-block in the first sub-block whose comparison result does not match. When the representative pixel is the first pixel of the first sub-block and the second sub-block, there is a pixel having the same representative pixel of the first sub-block and the second sub-block. In this case, in order to avoid color conversion of the same pixel, the second comparator 32b excludes addresses 0 to 3 which are both the representative pixel of the second sub-block and the representative pixel of the first sub-block.

At the time of color conversion, when the LUT is switched according to the color space of the input image data, the first comparator 32a and the second comparator 32b compare the color space with each pixel value, and the pixel value and the color space are When the pixel values match, it is preferable to output a comparison result where the pixel values match, and when the pixel values or color spaces do not match, it is preferable to output a comparison result where the pixel values do not match.
As a result, the pixel value of the color-converted pixel can be copied to a pixel whose pixel value and color space match the color-converted pixel. In addition, pixels whose pixel values or color spaces do not match can be color-converted by an LUT corresponding to the color space. Even if pixels with different color spaces are mixed in the input image data, color conversion corresponding to each color space can be performed.

In addition, when the LUT is switched according to the attribute at the time of color conversion, the first comparator 32a and the second comparator 32b compare the attribute together with each pixel value, and when the pixel value and the attribute match, each pixel value is It is preferable to output a comparison result of matching, and output a comparison result of mismatching pixel values when the pixel values or attributes do not match.
Accordingly, the pixel value of the color-converted pixel can be copied to the pixel whose pixel value and attribute match the color-converted pixel. In addition, pixels whose pixel values or attributes do not match can be color-converted by an LUT corresponding to the attributes. Even if pixels having different attributes are mixed in the input image data, color conversion corresponding to each attribute can be performed.
Since the image data is output together with the attribute data, the first comparator 32a and the second comparator 32b can compare the attribute of each pixel based on the attribute data.

FIG. 6 is a diagram showing the processing time required for the comparison by the first comparator 32a and the second comparator 32b.
Each of the first comparator 32a and the second comparator 32b takes three clocks from the start of one comparison, that is, the input of four pixels to the end of the comparison and the output of the comparison result. Therefore, as shown in FIG. 6, the processing time required until the comparison of all the second sub-blocks whose representative pixel addresses are 0 to 15 is 18 (18 = 16−1 + 3) clocks.
When the comparison of the second sub-blocks whose representative pixel addresses are 6, 9, 12, and 15 is completed, the first sub-blocks can be compared, and the comparison of the second comparator 32b is started. Therefore, the processing time required until the comparison of all the first sub-blocks and the second sub-blocks is 21 (21 = 19−1 + 3) clocks. When all the comparisons are completed, pixel input to the color conversion unit g3 is started.

  The memory control unit 33 outputs the enable signal WE and the write address WADRS to the first memory 34a if the comparison result output from the first comparator 32a does not match when the comparison by the first comparator 32a is completed. To do. Thereby, the memory control unit 33 can write the address output from the first comparator 32a in the first memory 34a every time the comparison of the 16 second sub-blocks is completed.

The memory control unit 33 outputs the enable signal WE and the write address WADRS to the second memory 34b if the comparison result output from the second comparator 32b does not match when the comparison by the second comparator 32b is completed. To do. Accordingly, the memory control unit 33 can write the address output from the second comparator 32b to the second memory 34b every time the comparison of the four first sub-blocks is completed.
Note that the write address WADRS and the read address RADRS output by the memory control unit 33 are addresses for reading the addresses written in the first memory 34a and the second memory 34b in the order of writing.

The memory control unit 33 can determine the timing when each of the first comparators 32a and the second comparators 32b ends the comparison from the count value of the counter C1.
As shown in FIG. 6, the comparison of each first sub-block ends after 12, 15, 18 and 21 clocks from the start of pixel input to the first comparator 32a. The comparison of each second sub-block is completed every clock from 3 clocks to 18 clocks after the pixel input to the first comparator 32a is started. The counter C1 starts counting simultaneously with the start of pixel input to the first comparator 32a. Therefore, when the count values are 12, 15, 18, and 21, the memory control unit 33 compares the second comparator 32b. When the count value is 3-18, it is determined that the comparison of the first comparator 32a is completed.

When all the comparisons by the first comparator 32a and the second comparator 32b are completed and the representative pixels of the respective first sub-blocks have been input to the color conversion unit g3, the memory control unit 33 reads the second memory 34b. The address RADRS is output, and the address held in the second memory 34b is read. At this time, the memory control unit 33 outputs a processing end signal DOF_1.
The memory control unit 33 outputs the read address RADRS to the first memory 34a when the input of the representative pixel of the second sub-block whose address is held in the second memory 34b to the color conversion unit g3 is completed. The address held by 34a is read. At this time, the memory control unit 33 outputs a processing end signal DOF_2.

The memory control unit 33 outputs the processing end signal DOF_all when the pixels in the second sub-block other than the representative pixels whose addresses are stored in the first memory 34a have been input to the color conversion unit g3.
When the addresses are not held in the first memory 34a and the second memory 34b, the memory control unit 33 outputs the processing end signal DOF_all when the input of each representative pixel of the first sub-block to the color conversion unit g3 is completed. To do.

Note that the memory control unit 33 can determine the timing at which each pixel has been input to the color conversion unit g3 based on the count value of the counter C1.
For example, when two addresses are written in the first memory and three addresses are written in the second memory 34b, 3 pixels and 6 pixels are input after the four representative pixels of the first sub-block. The memory control unit 33 may determine the timing at which each pixel has been input to the color conversion unit g3 from the end of the comparison, based on the count value of the counter C1.

  The memory control unit 33 uses the comparison result output from each of the first comparator 32a and the second comparator 32b as a comparison result cmp of each pixel value in the first sub-block and the second sub-block. Output to g5.

The first memory 34a holds the address output from the first comparator 32a in response to the enable signal WE and the write address WADRS from the memory control unit 33.
The second memory 34b holds the address output from the second comparator 32b in response to the enable signal WE and the write address WADRS from the memory control unit 33.
The first memory 34 a and the second memory 34 b output the held addresses to the selector 35 in accordance with the read address RADRS from the memory control unit 33.

  The first memory 34a and the second memory 34b are preferably FIFO (First In First Out) memories capable of reading data in the order of writing.

The selector 35 sequentially outputs the count value 0 to 15 of the counter C3 when the enable signal input from the read control unit 36 is 0 as the address ADRS, and when the enable signal is 1, the selector 35 outputs the count value 0 to 0 of the counter C2. 3 is output sequentially.
The selector 35 outputs the address output from the second memory 34b as the address ADRS when the enable signal input from the read controller 36 is 2, and from the first memory 34a when the enable signal is 3. Output the specified address.
The address ADRS from the selector 35 is output to the second input buffer 31 as the read address RADRS, and is also output to the buffer control unit g5 as the address ADRS of the pixel for color conversion.

The read control units 36 and 37 control the enable signal output to the second input buffer 31 and the read address RADRS to read out pixels from the second input buffer 31 in units of second sub-blocks and read out pixels to be color-converted. .
Specifically, when one new block is held in the second input buffer 31, the read control unit 36 outputs an enable signal of 0 to the selector 35 and the second input buffer 31.

Further, the read control unit 36 outputs one enable signal to the selector 35 and the second input buffer 31 when the comparison of the first comparator 32 a and the second comparator 32 b is completed.
As shown in FIG. 6, the timing at which the comparisons by the first comparators 32 a and the second comparators 32 b are completed is after the pixel input to the first comparator 32 a is started by the output of the 0 enable signal. 21 clocks later. Therefore, the read control unit 36 outputs a 1 enable signal 21 clocks after the 0 enable signal is output.

The read control unit 36 outputs two enable signals to the selector 35 and the second input buffer 31 when the processing end signal DOF_1 is output from the memory control unit 33.
In addition, when the processing end signal DOF_2 is output from the memory control unit 33, the read control unit 36 outputs the three enable signals and the second input buffer 31 to the selector 35.

When the enable signal output to the selector 35 is 0, the read control unit 37 stops the pixel output from the second input buffer 31 to the color conversion unit g3.
When the enable signal output to the selector 35 is 1, each representative pixel of the first sub-block having addresses 0 to 3 is output from the second input buffer 31. The read control unit 37 sequentially outputs the representative pixels to the color conversion unit g3.

When the enable signal output to the selector 35 is 2, the representative pixel of each second sub-block in the first sub-block that does not match is output from the second input buffer 31. The read control unit 37 sequentially outputs the representative pixels to the color conversion unit g3.
When the enable signal output to the selector 35 is 3, each pixel other than the representative pixel in the mismatched second sub-block is output from the second input buffer 31. The read control unit 37 sequentially outputs the pixels to the color conversion unit g3.

When one block is input to the second input buffer 31, the counter C1 resets the count value and newly starts counting, and outputs a count value of 0 to 63.
When the processing end signal DOF_all of the previous block is output from the memory control unit 33, the counter C2 resets the count value and newly starts counting, and outputs a count value of 0 to 3.
When one block is input to the second input buffer 31, the counter C3 resets the count value, newly starts counting, and outputs a count value of 0 to 15.

Next, a processing procedure at the time of color conversion by the image processing apparatus G1 will be described.
First, the buffer control unit g0 writes the image data held in the image memory 3 to the first input buffer g1 in units of blocks, and the first input buffer g1 holds a plurality of blocks. The buffer control unit g0 reads one block out of the plurality of blocks from the first input buffer g1, and outputs it to the comparison processing unit g2A.

In the comparison processing unit g2A, the write control unit 30 writes one input block into the second input buffer 31, and assigns an address as shown in FIG.
At the first block, when one block is written in the second input buffer 31, the counters C1 to C3 start counting. Further, the read control unit 36 outputs a 0 enable signal to the selector 35 and the second input buffer 31.

The selector 35 sequentially outputs the count values 0 to 15 of the counter C3 to the second input buffer 31 as the read address RADRS in response to the 0 enable signal.
The second input buffer 31 outputs the pixels of the second sub-block to the first comparator 32a in the order of the representative pixel addresses from 0 to 15 in response to the enable signal of 0 and the read address RADRS.

The first comparator 32 a compares the pixel values of the pixels of the second sub-block and outputs the comparison result to the memory control unit 33. If the comparison result does not match, the first comparator 32a outputs the address of the representative pixel of the mismatched second sub-block to the first memory 34a.
When a mismatch result is input from the first comparator 32a, the memory control unit 33 outputs the enable signal WE and the write address WADRS to the first memory 34a and the address output from the first comparator 32a. Write to the first memory 34a.

The first comparator 32a outputs the representative pixel of the second sub-block together with the comparison result to the second comparator 32b.
The second comparator 32b compares the pixel values of the representative pixels when the representative pixels of the second sub blocks in the first sub block are input. From the comparison result and the comparison result of the first comparator 32a, the second comparator 32b outputs the comparison result of each pixel value in the first sub-block to the memory control unit 33. The second comparator 32b outputs to the second memory 34b the address of the representative pixel of each second sub-block in the first sub-block where the comparison result does not match.
When the mismatched comparison result is input from the second comparator 32b, the memory control unit 33 outputs the enable signal WE and the write address WADRS to the second memory 34b, and the address output from the second comparator 32b. Write to the second memory 34b.

  When the comparison between the first comparator 32a and the second comparator 32b is completed, the read control unit 36 outputs an enable signal of 1 to the selector 35. The selector 35 sequentially outputs the count values 0 to 3 from the counter C2 as the read address RADRS in response to one enable signal. The second input buffer 31 sequentially outputs the representative pixels of each first sub-block to the read control unit 37 in accordance with the read addresses RADRS from 0 to 3.

The memory control unit 33 outputs the processing end signal DOF_1 when the comparison by the first comparator 32a and the second comparator 32b is completed and the representative pixel of each first sub-block has been input to the color conversion unit g3. .
Further, the memory control unit 33 outputs the read address RADRS to the second memory 34b. The second memory 34b outputs the held address.

  The read control unit 36 outputs two enable signals to the selector 35 in response to the processing end signal DOF_1. The selector 35 outputs the address output from the second memory 34b as the read address RADRS in response to the two enable signals. The second input buffer 31 outputs the representative pixel of each second sub-block in the first sub-block that does not match according to the read address RADRS.

The memory control unit 33 outputs the processing end signal DOF_2 when the input of the representative pixel of each second sub-block whose address is held in the second memory 34b to the color conversion unit g3.
In addition, the memory control unit 33 outputs the read address RADRS to the first memory 34a. The first memory 34a outputs the held address.

The read control unit 36 outputs three enable signals to the selector 35 in response to the processing end signal DOF_2. The selector 35 outputs the address output from the first memory 34a as the read address RADRS in response to the three enable signals. The second input buffer 31 outputs each pixel other than the representative pixel in the mismatched second sub-block according to the read address RADRS.
When the enable signal input to the selector 35 is 1 to 3, the read control unit 37 sequentially outputs the pixels output from the second input buffer 31 to the color conversion unit g3.

The memory control unit 33 outputs the processing end signal DOF_all when the pixels in the second sub-block other than the representative pixel whose address is held in the first memory 34a has been input to the color conversion unit g3.
In response to the processing end signal DOF_all, the next block is written into the second input buffer 31, and the counter C2 resets the count value and newly starts counting.
Thereafter, the pixel for color conversion of each block is output from the comparison processing unit g2A in the same manner as the processing procedure described above.

FIG. 7A shows an example of the input order of pixels to the color conversion unit g3.
In the first block, when the comparison results of the second sub-blocks whose representative pixel addresses are 0 and 4 do not match, the comparison results of the first sub-block whose representative pixel address is 0 also do not match. In this case, addresses 0 and 4 are held in the first memory 34a, and addresses 4, 5, and 6 are held in the second memory 34b. As a result, as shown in FIG. 7A, the representative pixel (address 0 to 3) of each first sub-block, the representative pixel (address 4, 5, 6) Pixels for color conversion are input to the color conversion unit g3 in the order of pixels (addresses 0a, 0b, 0c, 4a, 4b, 4c) other than the representative pixels in the mismatched second sub-block. In the second to fourth blocks, since the comparison results of both the first subblock and the second subblock match, only the representative pixels (addresses 0 to 3) of each first subblock are input to the color conversion unit g3. .

FIG. 7B shows an example of the input order in the case where the comparison result of the second sub-block whose address of the representative pixel is 9 does not match in the first block.
In this case, the comparison result of the first sub-block whose representative pixel address is 1 also does not match. Addresses 0, 4 and 9 are held in the first memory 34a, and addresses 4, 5, 6, 7, 8 and 9 are held in the second memory 34b. As a result, as shown in FIG. 7B, the representative pixels (addresses 0 to 3) of the first sub-blocks and the representative pixels (addresses 4 to 9) of the second sub-blocks in the mismatched first sub-blocks. Pixels for color conversion are input to the color conversion unit g3 in the order of pixels (addresses 0a, 0b, 0c, 4a, 4b, 4c, 9a, 9b, and 9c) other than the representative pixels of the mismatched second sub-block. .

In the example shown in FIG. 7A, when the comparison processing unit g2A has no second memory 34b and only the first memory 34a, in the first block where there is a mismatched pixel, FIG. As shown, it is necessary to input the representative pixels (addresses 0 to 15) of all the second sub-blocks to the color conversion unit g3. Thereafter, each pixel (address 0a, 0b, 0c, 0d, 4a, 4b, 4c) other than the representative pixel of the mismatched second sub-block whose address is held in the first memory 34a is input to the color conversion unit g3. .
As can be seen by comparing FIG. 7A and FIG. 7C, the comparison processing unit g2A includes the second memory 34b, thereby reducing the number of pixels input to the color conversion unit g3. Color conversion processing time can be shortened.
When all the pixels of one block match as in the second to fourth blocks, only the representative pixel (address 0 to 3) of the first sub-block is input to the color conversion unit g3.
When such address control is performed, the counter C2 counts 0 to 15. If all the pixels match, the memory control unit 33 outputs the processing end signal DOF_all when the representative pixel of the first sub-block is input to the color conversion unit g3.

The color conversion unit g3 performs color conversion on the pixel output from the comparison processing unit g2A, and outputs the pixel after color conversion to the output buffer g4.
The buffer control unit g5 outputs the address ADRS output from the selector 35 of the comparison processing unit g2A to the output buffer g4 as the write address WADRS. Thereby, the buffer control unit g5 can write the color-converted pixel in the output buffer g4.
In addition, the buffer control unit g5 applies, to each pixel in the first subblock with the same comparison result cmp output from the memory control unit 33 of the comparison processing unit g2A, after color conversion of the representative pixel of the first subblock. Copy and write pixel values. Similarly, the buffer control unit g5 copies and writes the pixel value after color conversion of the representative pixel of the second sub-block to each pixel in the second sub-block with the same comparison result cmp.

FIG. 8 shows a copy example.
When the comparison results of the second sub-blocks whose representative pixel addresses are 0 and 4 do not match, the pixels subjected to color conversion by the color conversion unit g3 have addresses 0, 1, 2, 3, 4, 5, 6, These are pixels 0a, 0b, 0c, 4a, 4b and 4c. Since the address is output as the write address WADRS from the buffer control unit g5, the pixel value after color conversion is written in the output buffer g4 as shown in FIG.

  Pixels that have not undergone color conversion are pixels whose pixel values match the representative pixels of the first sub-block or the second sub-block. Therefore, the buffer control unit g5 copies and writes the pixel value of each representative pixel in the first sub-block unit or the second sub-block unit in which the pixel values match with respect to the pixel that has not undergone color conversion. For example, the comparison result cmp of the second sub-block whose representative pixel address is 5 is the same. As shown in FIG. 8, the buffer control unit g5 copies the pixel value after color conversion of the representative pixel having the address 5 to each pixel having the address 5a to 5c.

When the writing of one block is completed, the buffer control unit g5 outputs the read address RADRS to the output buffer g4 and reads the image data of one block from the output buffer g4. Since this read address RADRS is output in the order of 0, 0a, 4, 4a, 1, 1a, 7, 7a, 0b, 0c, 4b, 4c,..., Each pixel is read in the original order.
The output buffer g4 outputs one block of image data according to the read address RADRS from the buffer control unit g5.

As described above, according to the first embodiment, the image processing apparatus G1 inputs the image data in units of blocks and holds the first input buffer g1 that holds a plurality of blocks, and the first input buffers g1 to 1 A block is input, the pixel value of each pixel in the one block is compared, the comparison processing unit g2A that outputs the pixel for color conversion of the one block, and the pixel output from the comparison processing unit g2A are color-converted The color conversion unit g3, the output buffer g4, and the pixel color-converted by the color conversion unit g3 are written to the output buffer g4. As a result of the comparison, the pixel whose pixel value matches the color-converted pixel A buffer control unit g5 for copying and writing the pixel value of the converted pixel.
The comparison processing unit g2A includes the second input buffer 31, the write control unit 30 that writes the one block held in the first input buffer g1 to the second input buffer 31, and the first block obtained by dividing one block. A first comparator 32a that compares pixel values of each pixel in the second sub-block obtained by further dividing one sub-block, and outputs a comparison result indicating whether each pixel value matches or does not match; The pixel value of the representative pixel of each second sub-block in the first sub-block is compared with the first memory 34a holding the address of the representative pixel of the second sub-block whose comparison result by the first comparator 32a does not match If the pixel values match and the comparison result by the first comparator 32a matches, the comparison result of the match is output, and the pixel values do not match or the comparison result by the first comparator 32a does not match. The second comparator 32b that outputs a mismatched comparison result, and the second comparator 32b that holds the address of the representative pixel of each second subblock in the first subblock where the comparison result by the second comparator 32b does not match. 2 memory 34b, as a pixel for color conversion, the representative pixel of the first sub-block, the representative pixel of the second sub-block whose address is held in the second memory 34b, and the representative whose address is held in the first memory 34a Read control units 36 and 37 that read out and output each pixel in the second sub-block other than the pixels from the second input buffer 31 are provided.

As a result, when the pixel values in the first sub-block match, color conversion can be performed collectively in units of the first sub-block. When the pixel values in the first sub-block do not match, color conversion can be performed in batch or color conversion can be performed for each pixel in units of the second sub-block smaller than the first sub-block. By reducing the number of pixels to be color-converted, the color conversion processing time can be shortened, and the color conversion speed can be increased.
As described above, by providing the second memory 34b, the number of pixels for color conversion can be further reduced, and the speed can be further increased.

  Although it is possible to speed up color conversion by providing a plurality of color conversion units g3 and performing color conversion of each block in parallel, a memory for holding an LUT must be provided for each color conversion unit g3. For example, when the data amount of one LUT is 10 Mbit, if four color conversion units g3 are provided, a memory of 40 Mbit is required. Since the circuit scale for color conversion becomes very large and it is difficult to mount on an LSI or the like, it is difficult to realize color conversion by hardware.

  On the other hand, in the comparison processing unit g2A, when one pixel has a data amount of 8 bits and one block has 8 × 8 pixels, the capacity of the first input buffer g1 is 2048 bits (8 × 8 pixels × 4 colors × 8 bits). It ’s enough. The capacity of the second input buffer 31 is 2048 bits (2048 = 8 × 8 pixels × 4 colors × 8 bits), the capacity of the first memory 34a is 256 bits, and the capacity of the second memory 34b is 32 bits. The capacity of the memory for comparison is 4384 (2336 = 2048 + 2048 + 256 + 32) bits, and the capacity of the memory for color conversion is 10 Mbits. Therefore, a memory having a capacity of about 10.00 Mbits as a whole is sufficient. The circuit scale is much smaller than when a plurality of color conversion units g3 are provided, and mounting on an LSI or the like is easy. Even if there is only one color conversion unit g3, it is possible to speed up the color conversion as described above. Therefore, the speed of the color conversion by hardware can be realized with a simple hardware configuration.

[Modification]
As shown in FIG. 9, the comparison processing unit g2A described above further includes a third comparator 32c that compares the representative pixels of the first sub-blocks, and outputs a comparison result by the comparator 32c to the buffer control unit g5. Can do. When the counter C2 counts 0, the memory control unit 33 outputs the processing end flag DOF_all, so that only the representative pixel with the address 0 is input to the color conversion unit g3. When the comparison result cmp by the comparator 34c matches, the buffer control unit g5 may copy the pixel value of the representative pixel at the address 0 subjected to color conversion to each pixel of one block and write it in the output buffer g4.
As a result, when all the pixel values of one block match, the color conversion processing time can be further shortened.

[Second Embodiment]
The image processing apparatus according to the second embodiment includes a plurality of comparison modules using each component of the above-described comparison processing unit g2A as one comparison module, and compares a plurality of blocks in parallel by the plurality of comparison modules. Do.

FIG. 10 is a configuration diagram of components that perform color conversion in the image processing device G2 according to the second embodiment. The image processing apparatus G2 is mounted on the image forming apparatus T (see FIG. 1) in the same manner as the image processing apparatus G1 according to the first embodiment.
The image processing device G2 has the same configuration as the image processing device G1 except that it includes a comparison processing unit g2B shown in FIG. 10 instead of the comparison processing unit g2A. That is, the image processing apparatus G2 includes a buffer control unit g0, a first input buffer g1, a comparison processing unit g2B, a color conversion unit g3, an output buffer g4, and a buffer control unit g5 as shown in FIG. The same components as those of the image processing device G1 are denoted by the same reference numerals and detailed description thereof is omitted, and the comparison processing unit g2B having a different configuration will be described below.

FIG. 11 is a configuration diagram of the comparison processing unit g2B.
As illustrated in FIG. 11, the comparison processing unit g2B includes a block control unit 11, four comparison modules M1 to M4, and a selector 12.
In FIG. 11, the processing end signals DOF_all output when the memory control unit 33 of each of the comparison modules M1 to M4 finishes inputting all the pixels for color conversion of one block to the color conversion unit g3 are represented as DOF_all1 to DOF_all4, respectively. ing.
10 and 11, the comparison results cmp output from the memory control unit 33 of each of the comparison modules M1 to M4 are represented as cmp1 to cmp4, respectively.

The block control unit 11 receives four blocks from the first input buffer g1, distributes and outputs the blocks one by one in the order of the comparison modules M1, M2, M3, and M4.
After the first four blocks are output, each time the comparison modules M1 to M4 complete the input of the pixels to be color-converted into the color conversion unit g3, the processing end signals DOF_all1 to DOF_all4 are output from the comparison modules M1 to M4. The block control unit 11 inputs the next one block from the first input buffer g1 in response to the processing end signals DOF_all1 to DOF_all4, and outputs them to the comparison modules M1 to M4, respectively.

Each of the comparison modules M1 to M4 compares the input pixels in one block, and outputs the pixels for color conversion in one block to the color conversion unit g3.
As shown in FIG. 11, the comparison module M1 includes a write controller 30, a second input buffer 31, a first comparator 32a, a second comparator 32b, a memory controller 33, a first memory 34a, and a second memory 34b. , A selector 35, read control units 36 and 37, and counters C1 to C3. Since each component of the comparison module M1 is the same as the comparison processor g2A of the first embodiment, the same components are denoted by the same reference numerals and detailed description thereof is omitted.
The other comparison modules M2 to M4 have the same configuration as the comparison module M1. Although not shown in FIG. 11, the other comparison modules M2 to M4 output the comparison results cmp2 to cmp4 and the address ADRS of the pixel to be color-converted to the color converter g3, respectively.

  The counter C2 of each comparison module M1 to M4 starts counting in response to the processing end signals DOF_all1 to DOF_all4 from the comparison modules M1 to M4 comparing the previous blocks. For example, the counter C2 of the comparison module M1 starts counting when the processing end signal DOF_all4 is output from the comparison module M4 that compares the previous blocks.

The selector 12 switches the outputs from the four comparison modules M1 to M4 and outputs the pixels to be color-converted to the color conversion unit g3 in block order.
Specifically, the selector 12 switches the outputs from the four comparison modules M1 to M4 according to the inputs of the process end signals DOF_all1 to DOF_all4.
The selector 12 switches to the output of the comparison module M2 when the processing end signal DOF_all1 is input, and switches to the output of the comparison module M3 when the processing end signal DOF_all2 is input. The selector 12 switches to the output of the comparison module M4 when the processing end signal DOF_all3 is input, and switches to the output of the comparison module M1 when the processing end signal DOF_all4 is input.

Next, a processing procedure at the time of color conversion of the image processing apparatus G2 according to the second embodiment will be described.
First, the buffer control unit g0 writes the image data held in the image memory 3 to the first input buffer g1 in units of blocks, and the first input buffer g1 holds a plurality of blocks. In order to continuously output each block to the comparison processing unit g2B, it is preferable that the first input buffer g1 can hold five or more blocks larger than the number of comparison modules M1 to M4. The buffer control unit g0 reads four blocks out of the plurality of blocks from the first input buffer g1, and outputs them to the comparison processing unit g2B.

In the comparison processing unit g2B, the block control unit 11 sequentially outputs the input four blocks to the comparison modules M1 to M4.
In each of the comparison modules M1 to M4, the write control unit 30 writes one input block into the second input buffer 31, and assigns an address as shown in FIG.
Thereafter, the comparison module M1 to M4 compares the pixel value of each pixel of one block and outputs a pixel for color conversion, which is the same as the image processing device G1 of the first embodiment. Description is omitted.

  In the first block, when the comparison module M1 outputs a pixel for color conversion in the first block, the selector 12 outputs the pixel to the color conversion unit g3. The comparison module M1 outputs a processing end signal DOF_all1 when all the pixels to be color-converted are input to the color conversion unit g3. In response to the processing end signal DOF_all1, the block control unit 11 inputs the next block (fifth block) and outputs it to the comparison module M1.

  In response to the processing end signal DOF_all1 from the comparison module M1, the comparison module M2 starts outputting pixels for color conversion in the second block. Further, the selector 12 switches the output of the comparison module M1 to the output of the comparison module M2 in response to the processing end signal DOF_all1, and outputs the pixel output from the comparison module M2 to the color conversion unit g3. The comparison module M2 outputs the processing end signal DOF_all2 when all the pixels to be color-converted are input to the color conversion unit g3. In response to the processing end signal DOF_all2, the block control unit 11 inputs the next block (sixth block) and outputs it to the comparison module M2.

  In response to the processing end signal DOF_all2 from the comparison module M2, the comparison module M3 starts outputting pixels for color conversion in the third block. Further, the selector 12 switches the output of the comparison module M2 to the output of the comparison module M3 in response to the processing end signal DOF_all2, and outputs the pixel output from the comparison module M3 to the color conversion unit g3. The comparison module M3 outputs the processing end signal DOF_all3 when all the pixels to be color-converted are input to the color conversion unit g3. In response to the processing end signal DOF_all3, the block control unit 11 inputs the next block (seventh block) and outputs it to the comparison module M3.

In response to the processing end signal DOF_all3 from the comparison module M3, the comparison module M4 starts outputting the pixels for color conversion in the fourth block. Further, the selector 12 switches the output of the comparison module M3 to the output of the comparison module M4 according to the processing end signal DOF_all3, and outputs the pixel output from the comparison module M4 to the color conversion unit g3. The comparison module M4 outputs a processing end signal DOF_all4 when all the pixels to be color-converted are input to the color conversion unit g3. In response to the processing end signal DOF_all4, the block control unit 11 inputs the next block (eighth block) and outputs it to the comparison module M4.
Further, in response to the processing end signal DOF_all4, the comparison module M1 starts outputting a pixel for color conversion of the fifth block. In response to the processing end signal DOF_all4, the selector 12 switches the output of the comparison module M4 to the output of the comparison module M1, and outputs the pixels from the comparison module M1.

In this way, the pixels for color conversion of each block are sequentially output to the color conversion unit g3 by the comparison modules M1 to M4.
Subsequent processing procedures of the color conversion unit g3, the output buffer g4, and the buffer control unit g5 are the same as those of the image processing apparatus G1 of the first embodiment, and thus description thereof is omitted.

  Similarly to the comparison processing unit g2A according to the first embodiment, each of the comparison modules M1 to M4 includes the second memory 34b, so that the number of pixels input to the color conversion unit g3 can be reduced, and color conversion is performed. Processing time can be shortened.

FIG. 12 shows the processing time required for comparison and color conversion of each of the comparison modules M1 to M4.
In FIG. 12, comparison 1 input to comparison 4 input indicate the time from the start of input of pixels to the first comparator 32a and the second comparator 32b of each of the comparison modules M1 to M4 until the input ends. Yes. The comparison 1 output to the comparison 4 output indicate the time from the start of the output of the comparison results of the first comparator 32a and the second comparator 32b of each of the comparison modules M1 to M4 to the end of the output. The comparison 1 input to comparison 4 input and the comparison 1 output to comparison 4 output each require (19-1) clocks.
Since three clocks are required for one comparison, the start timing of each comparison 1 output to comparison 4 output is delayed by 3 clocks from the start timing of each comparison 1 input to comparison 4 input.

The color conversion 1 input in FIG. 12 indicates the time from the start of pixel input to the color conversion unit g3 from the comparison processing unit g2B to the end of input.
According to the comparison processing unit g2B, input of pixels of each block to the color conversion unit g3 is started when the comparison 1 output to the comparison 4 output are completed. When the comparison results of the second sub-blocks at the addresses 0 and 4 in the first block are not coincident and the comparison results in the second to fourth blocks are all coincident, as shown by the color conversion 1 input, the input of the first block Requires 13 clocks and 4 clocks are required for input of the second to fourth blocks.

On the other hand, the color conversion 2 input in FIG. 12 starts the pixel input to the color conversion unit g3 when each of the comparison modules M1 to M4 has no second memory 34b and only the first memory 34a. It shows the time from input to end of input.
In the configuration of only the first memory 34a, if there is a mismatched pixel, it is necessary to color-convert all the representative pixels of the second sub-block as described above. Therefore, as shown by the color conversion 2 input, 22 clocks are required for the input of the first block including the non-matching pixels, and 4 clocks are required for the inputs of the second to third blocks where all the pixels match.
As can be seen by comparing the color conversion 1 input and the color conversion 2 input, the configuration having the second memory 34b has a shorter color conversion processing time than the configuration having only the first memory 34a.

  Also, rather than one comparison module comparing each block as in the comparison processing unit g2A, a plurality of comparison modules M1 to M4 compare each block in parallel as in the comparison processing unit g2B. However, color conversion may be efficient. It is particularly efficient when all pixel values in one block match.

FIGS. 13A to 13C show the processing time required for comparing each block and the processing time required for color conversion.
In FIG. 13A to FIG. 13C, the comparison 1 input to comparison 4 input are input after the pixel input to the first comparator 32a and the second comparator 32b is started when each block is compared. Shows the time until completion. The comparison 1 output to the comparison 4 output indicate the time from the start of the output of the comparison result of the first comparator 32a and the second comparator 32b to the end of the output when comparing each block. The comparison 1 input to comparison 4 input and the comparison 1 output to comparison 4 output each require (19-1) clocks.
The color conversion input indicates the time from the start of pixel input to the color conversion unit g3 to the end of input.

FIGS. 13A and 13B show the processing time of comparison and color conversion when one comparison module compares each block.
In the case of one comparison module, when the comparison 2 input is started at the end of the comparison 1 input, the input of the pixels of the previous block is completed to the first comparator 32a and the second comparator 32b. Thus, the pixel of the next block can be input. Further, at the end of each comparison 1 output to each comparison 4 output, that is, when the output of the comparison result of each block is completed, the input of the pixel of each block to the color conversion unit g3 can be started.
If there is a mismatched pixel in one block and 22 clocks are required to input one block of pixels to the color converter g3 as shown in FIG. 13A, the input to the color converter g3 of the previous block is input. By the end, output of the comparison result of the next block has been completed. In this case, the pixels for color conversion of each block can be continuously input to the color conversion unit g3.

On the other hand, if all the pixels in one block match, only the four pixels at addresses 0 to 3 in each block need be color-converted, and the input to the color converter g3 is completed in four clocks.
Therefore, in the case of one comparison module, as shown in FIG. 13B, the input of the pixel for color conversion of the previous block is completed earlier than the output of the comparison result of the next block is completed. Therefore, there is a waiting time until the input of the pixel for color conversion of the next block, and the pixel cannot be continuously input to the color conversion unit g3.

FIG. 13C shows the processing time for comparison and color conversion when a plurality of comparison modules M1 to M4 compare each block in parallel.
In the case of the plurality of comparison modules M1 to M4, the comparison 1 input to the comparison 4 input are started before the end point of the comparison 1 output to the comparison 4 output, and the next comparison is not performed without waiting for the comparison of the pixels in the previous block. The block comparison starts.
Even when all the pixels in one block match, as shown in FIG. 13C, when the input of the pixel to the color conversion unit g3 of the previous block is completed, the comparison result of the next block The output of is also finished. Therefore, pixels for color conversion of each block can be continuously input to the color conversion unit g3, and color conversion is efficient.
In FIG. 13C, the processing time of the fifth to eighth blocks is represented by a white arrow.
When the input of the color conversion for the fourth block is completed, the output of the comparison result for the fifth block has not been completed yet, so there is a slight waiting time. However, the overall waiting time is short, and the color conversion processing time is much shorter than that shown in FIG.

As described above, according to the second embodiment, the image processing apparatus G2 inputs image data in units of blocks, and holds the first input buffer g1 that holds a plurality of blocks, and the first input buffers g1 to 1 A block is input, the pixel value of each pixel in the block is compared, and the comparison processing unit g2B that outputs the pixel for color conversion of the block and the pixel output from the comparison processing unit g2B are color-converted The color conversion unit g3, the output buffer g4, and the pixel color-converted by the color conversion unit g3 are written in the output buffer g4. As a result of comparison, for the pixel whose pixel value matches the color-converted pixel, A buffer control unit g5 for copying and writing the pixel value of the color-converted pixel.
The comparison processing unit g2B includes a second input buffer 31, a write control unit 30, a first comparator 32a, a first memory 34a, a second comparator 32b, a second memory 34b, and read control units 36 and 37. The comparison modules M1 to M4 are provided, and a plurality of blocks are input and distributed to the comparison modules M1 to M4. The comparison modules M1 to M4 perform the comparison in parallel, and the pixels for color conversion of each block are sequentially color-converted. To the part g3.

As a result, when the pixel values in the first sub-block match, color conversion can be performed collectively in units of the first sub-block. When the pixel values in the first sub-block do not match, color conversion can be performed in batch or color conversion can be performed for each pixel in units of the second sub-block smaller than the first sub-block. It is possible to reduce the color conversion processing time by reducing the number of pixels for color conversion, and to increase the speed of color conversion.
Further, by providing the second memory 34b, it is possible to further reduce the number of pixels for color conversion and further increase the speed.

  Furthermore, the pixel values in the first sub-block and the second sub-block can be compared in parallel, and the pixels for color conversion in each block can be continuously color-converted. Color conversion can be further accelerated.

  Although it is possible to reduce the color conversion processing time by providing a plurality of color conversion units g3 and performing color conversion of each block in parallel, it is necessary to provide a memory for holding the LUT for each color conversion unit g3. . For example, when the data amount of one LUT is 10 Mbit, if four color conversion units g3 are provided, a memory of 40 Mbit is required. Since the circuit scale for color conversion becomes very large and it is difficult to mount on an LSI or the like, it is difficult to realize color conversion by hardware.

  On the other hand, the comparison processing unit g2B includes a plurality of comparison modules M1 to M4, thereby realizing high-speed color conversion. When one pixel has a data amount of 8 bits and one block is 8 × 8 pixels, the capacity of the first input buffer g1 is 8192 bits (8 × 8 pixels × 4 colors × 8 bits × 4 blocks). The capacity of the second input buffer 31 in each comparison module M1 to M4 is 2048 bits (2048 = 8 × 8 pixels × 4 colors × 8 bits), the capacity of the first memory 34a is 256 bits, and the capacity of the second memory 34b is 32 bits. Is enough. Even if four comparison modules M1 to M4 are provided, the capacity of the memory for comparison is 17536 bits (17536 = 8192 + (2048 + 256 + 32) × 4) bits, and the capacity of the memory for color conversion is 10 Mbits. A memory with a capacity of 10.02 Mbit is used. Compared with the case where a plurality of color conversion units g3 are provided, color conversion can be speeded up with a simple hardware configuration.

The above embodiment is a preferred example of the present invention, and the present invention is not limited to this. Modifications can be made as appropriate without departing from the spirit of the present invention.
For example, in the second embodiment, as in the first embodiment, each comparison module M1 to M4 may include a third comparator 32c as shown in FIG.

T Image forming apparatus 3 Image memory G1 Image processing apparatus (first embodiment)
g0, g5 Buffer control unit g1 First input buffer g2A Comparison processing unit 30 Write control unit 31 Second input buffer 32a First comparator 32b Second comparator 32c Third comparator 33 Memory control unit 34a First memory 34b First 2 Memory 36, 37 Read control unit C1-C3 Counter G2 Image processing apparatus (second embodiment)
g2B Comparison processing unit 11 Block control units M1 to M4 Comparison module 12 Selector g3 Color conversion unit g4 Output buffer

Claims (5)

A first input buffer for inputting image data in units of blocks and holding a plurality of blocks;
A comparison processing unit that inputs one block from the first input buffer, compares pixel values of each pixel in the one block, and outputs pixels for color conversion of the one block;
A color conversion unit that performs color conversion on the pixels output from the comparison processing unit;
An output buffer;
The pixel converted by the color conversion unit is written to the output buffer, and the pixel value of the pixel subjected to the color conversion is copied to a pixel whose pixel value matches the pixel subjected to the color conversion as a result of the comparison. And a buffer controller for writing
The comparison processing unit
A second input buffer;
A writing control unit for writing one block held in the first input buffer to the second input buffer;
The pixel value of each pixel in the second sub-block obtained by further dividing the first sub-block obtained by dividing the one block is compared, and the comparison indicating whether the pixel values match or do not match A first comparator for outputting a result;
A first memory for holding an address of a representative pixel of a second sub-block in which the comparison result by the first comparator does not match;
The pixel values of the representative pixels of the second sub-blocks in the first sub-block are compared, and if the pixel values match and the comparison result by the first comparator is coincident, the coincidence comparison result is output. A second comparator that outputs a non-matching comparison result when each pixel value does not match or the comparison result by the first comparator does not match,
A second memory for holding the address of the representative pixel of each second sub-block in the first sub-block in which the comparison result by the second comparator is inconsistent;
The pixels to be color-converted are pixels other than the representative pixel of the first sub-block, the representative pixel of the second sub-block whose address is held in the second memory, and the representative pixel whose address is held in the first memory. A read controller that reads out and outputs each pixel in the second sub-block from the second input buffer;
An image processing apparatus comprising: The comparison processing unit includes a plurality of comparison modules including the second input buffer, the write control unit, the first comparator, the first memory, the second comparator, the second memory, and the read control unit. A plurality of blocks are input, each block is compared in parallel by each comparison module, and the pixels for color conversion of each block are sequentially output to the color conversion unit.
The image processing apparatus according to claim 1. The write control unit uses a write address assigned in the order of each pixel other than the representative pixel in the first sub-block, the representative pixel in the second sub-block, and the representative pixel in the second sub-block in the second input buffer. Output and assign an address to one block written in the second input buffer;
The image processing apparatus according to claim 1. The first comparator and the second comparator also compare the color space when comparing each pixel value, and if the pixel value and the color space match, each pixel value outputs a comparison result of matching, If the color space does not match, output a comparison result where each pixel value does not match.
The image processing apparatus according to claim 1. The first comparator and the second comparator also compare attributes when comparing each pixel value, and if the pixel value and the attribute match, each pixel value outputs a comparison result indicating that the pixel value or attribute matches. If they do not match, output a comparison result where each pixel value does not match.
The image processing apparatus according to claim 1.

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