JP2014127581A - Multilayer ceramic electronic component - Google Patents

Multilayer ceramic electronic component Download PDF

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JP2014127581A
JP2014127581A JP2012283150A JP2012283150A JP2014127581A JP 2014127581 A JP2014127581 A JP 2014127581A JP 2012283150 A JP2012283150 A JP 2012283150A JP 2012283150 A JP2012283150 A JP 2012283150A JP 2014127581 A JP2014127581 A JP 2014127581A
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strip
width
multilayer ceramic
band
component
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Takanori Kamatani
孝則 鎌谷
Koji Taketomi
幸治 武冨
Katsuyuki Horie
克之 堀江
Kenichiro Nogi
謙一郎 野木
拓哉 ▲柳▼町
Takuya Yanagimachi
Daizo Yokoyama
大造 横山
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a multilayer ceramic electronic component in which desired component characteristics can be maintained well, even if a component-specific conductor part incorporated in the component body is formed by using a thin film formation method, and a plurality of strip connections are formed at the end of the conductor part.SOLUTION: A multilayer ceramic capacitor 10 has a plurality of strip connections 12a at the end of an internal electrode 12, formed by using a thin film formation method, substantially in parallel and integrally via a strip gap 12b. End of each strip connection 12a is connected with an external electrode 14. The strip connection 12a has a width in the range of 3-80 μm, the width of the strip connection 12a and the width of strip gap 12b satisfy a condition; the width W12a of the strip connection 12a≥the width W12b of the strip gap 12b.

Description

本発明は、積層型セラミックコンデンサや積層型セラミックインダクタ等を含む積層型セラミック電子部品、特に部品本体に内蔵された部品特有の導体部が薄膜形成手法を利用して形成されている積層型セラミック電子部品に関する。   The present invention relates to a multilayer ceramic electronic component including a multilayer ceramic capacitor, a multilayer ceramic inductor, and the like, in particular, a multilayer ceramic electronic in which a component-specific conductor portion incorporated in a component body is formed by using a thin film forming method. Regarding parts.

薄膜形成手法(例えばスパッタリング法や蒸着法)を利用して形成された部品特有の導体部(例えば積層型セラミックコンデンサの複数の内部電極や積層型セラミックインダクタのコイル)が部品本体に内蔵され、該部品本体に設けられた外部電極が前記導体部の端に接続された構造を備えている積層型セラミック電子部品(例えば積層型セラミックコンデンサや積層型セラミックインダクタ)は、一般に、(1)多数の導体パターン(分断されて導体部となる)が所定配列で設けられたグリーンシートを含む複数の積層用グリーンシートを作製する工程、(2)積層用グリーンシートを適宜積み重ねて熱圧着して多数の導体パターンを含む積層シートを作製する工程、(3)導体パターンが分断されるように前記積層シートを切断して導体部を含む積層チップを作製する工程、(4)積層チップを焼成して焼成チップを作製する工程、(5)導体部の端に接続するように焼成チップに外部電極を作製する工程、を経て製造されている(下記特許文献1及び2を参照)。   A component-specific conductor portion (for example, a plurality of internal electrodes of a multilayer ceramic capacitor or a coil of a multilayer ceramic inductor) formed by using a thin film formation method (for example, a sputtering method or a vapor deposition method) is built in the component body. In general, a multilayer ceramic electronic component (for example, a multilayer ceramic capacitor or a multilayer ceramic inductor) having a structure in which an external electrode provided on a component body is connected to an end of the conductor is generally (1) a large number of conductors. A step of producing a plurality of laminated green sheets including a green sheet in which patterns (divided into conductor portions) are provided in a predetermined arrangement; (2) a plurality of conductors by appropriately stacking and laminating the laminated green sheets. A step of producing a laminated sheet including a pattern; (3) a conductor obtained by cutting the laminated sheet so that the conductor pattern is divided; Manufactured through a step of manufacturing a multilayer chip including (4) a step of baking the multilayer chip to manufacture a fired chip, and (5) a step of manufacturing an external electrode on the fired chip so as to be connected to the end of the conductor portion. (See Patent Documents 1 and 2 below).

ところで、前記工程(2)で作製された積層シートに含まれる導体パターンは既に硬質であるため、前記工程(3)における切断負荷は、前記導体部を厚膜形成手法(ペーストを印刷し乾燥したものを前記工程(4)に対応する工程で一括で焼成する手法)を利用して形成する場合に比べて格段高い。前記切断負荷を低減するには、下記特許文献2の図2に示されるように、前記工程(1)で形成される導体パターンの被切断部分の形状を複数の帯状部分が略平行に並んだ形状として該複数の帯状部分の幅を狭くすれば良いが、帯状部分の幅を狭くすると(換言すれば帯状部分間の隙間を広くすると)と、製造後の積層型セラミック電子部品の部品特性、特に周波数特性が変動することが実験によって確認されている。   By the way, since the conductor pattern included in the laminated sheet prepared in the step (2) is already hard, the cutting load in the step (3) is a thick film forming technique (paste is printed and dried). Compared with the case of forming the object by using a method in which the product is baked in a step corresponding to the step (4)). In order to reduce the cutting load, as shown in FIG. 2 of the following Patent Document 2, the shape of the cut portion of the conductor pattern formed in the step (1) has a plurality of strip-like portions arranged substantially in parallel. The width of the plurality of strip-shaped portions may be narrowed as a shape, but when the width of the strip-shaped portions is narrowed (in other words, the gap between the strip-shaped portions is widened), the component characteristics of the laminated ceramic electronic component after manufacture, In particular, it has been confirmed by experiments that the frequency characteristics fluctuate.

特開平01−042809号公報Japanese Patent Application Laid-Open No. 01-042809 特開平09−312232号公報JP 09-31232 A

本発明の目的は、部品本体に内蔵された部品特有の導体部が薄膜形成手法を利用して形成され、且つ、該導体部の端部に複数の帯状接続部が形成されている場合でも所期の部品特性を良好に維持できる積層型セラミック電子部品を提供することにある。   An object of the present invention is to provide a component-specific conductor portion built in the component main body by using a thin film forming method, and a plurality of strip-shaped connection portions are formed at the end portions of the conductor portion. It is an object of the present invention to provide a multilayer ceramic electronic component that can maintain good component characteristics at the initial stage.

前記目的を達成するため、本発明は、薄膜形成手法を利用して形成された部品特有の導体部が部品本体に内蔵され、該部品本体に設けられた外部電極が前記導体部の端に接続された構造を備える積層型セラミック電子部品において、前記導体部はその端部に複数の帯状接続部を帯状間隙を介して略平行に、且つ、一体に有していて各帯状接続部の端を前記外部電極に接続されており、前記帯状接続部の幅は3〜80μmの範囲内にあり、前記帯状接続部の幅と前記帯状間隙の幅とは帯状接続部の幅≧帯状間隙の幅の条件を満足している。   In order to achieve the above-mentioned object, the present invention has a component-specific conductor formed by using a thin film forming method built in the component body, and an external electrode provided on the component body is connected to the end of the conductor portion. In the multilayer ceramic electronic component having the above-described structure, the conductor portion has a plurality of strip-like connection portions at the end portions thereof substantially in parallel with the strip-like gap and integrally, and the end of each strip-like connection portion is provided. It is connected to the external electrode, and the width of the band-shaped connecting portion is in the range of 3 to 80 μm, and the width of the band-shaped connecting portion and the width of the band-shaped gap are the width of the band-shaped connecting portion ≧ the width of the band-shaped gap. The condition is satisfied.

本発明によれば、部品本体に内蔵された部品特有の導体部が薄膜形成手法を利用して形成され、且つ、該導体部の端部に複数の帯状接続部が形成されている場合でも所期の部品特性を良好に維持できる積層型セラミック電子部品を提供することができる。   According to the present invention, even when a conductor portion unique to a component built in the component body is formed by using a thin film forming method and a plurality of strip-like connection portions are formed at the end portion of the conductor portion. It is possible to provide a monolithic ceramic electronic component capable of maintaining good component characteristics at the initial stage.

本発明の前記目的とそれ以外の目的と、構成特徴と、作用効果は、以下の説明と添付図面によって明らかとなる。   The above object and other objects, structural features, and operational effects of the present invention will become apparent from the following description and the accompanying drawings.

図1(A)は本発明を適用した積層型セラミックコンデンサの側面図、図1(B)は図1(A)のB−B線に沿う横断面図、図1(C)は図1(B)のC−C線に沿う縦断面図である。1A is a side view of a multilayer ceramic capacitor to which the present invention is applied, FIG. 1B is a cross-sectional view taken along line BB in FIG. 1A, and FIG. It is a longitudinal cross-sectional view which follows the CC line of B). 図2(A)〜図2(I)は図1に示した積層型セラミックコンデンサの製法説明図である。2 (A) to 2 (I) are diagrams illustrating a method of manufacturing the multilayer ceramic capacitor shown in FIG. 図3はサンプル1〜20の帯状接続部及び帯状間隙の仕様と各々の評価結果を示す図である。FIG. 3 is a diagram showing the specifications of the strip-shaped connecting portions and the strip-shaped gaps of Samples 1 to 20 and the evaluation results thereof. 図1に示した積層型セラミックコンデンサの構造変形例を示す図1(B)対応図である。FIG. 2B is a view corresponding to FIG. 1B showing a structural modification of the multilayer ceramic capacitor shown in FIG. 1.

図1(A)〜図1(C)は本発明を適用した積層型セラミックコンデンサ(以下、単にコンデンサと言う)を示す。   1A to 1C show a multilayer ceramic capacitor (hereinafter simply referred to as a capacitor) to which the present invention is applied.

このコンデンサ10は長さ>幅=高さ或いは長さ>幅>高さの基準寸法関係を有する略直方体状を成しており、略直方体状の部品本体11の長さ方向両端部に1対の外部電極14を有している。因みに、コンデンサ10の長さは図1(A)及び図1(C)における左右方向の寸法を指し、幅は図1(B)における上下方向の寸法を指し、高さは図1(A)及び図1(C)における上下方向の寸法を指す。   This capacitor 10 has a substantially rectangular parallelepiped shape having a reference dimension relationship of length> width = height or length> width> height, and a pair is provided at both ends in the longitudinal direction of the substantially rectangular parallelepiped component body 11. The external electrode 14 is provided. Incidentally, the length of the capacitor 10 refers to the horizontal dimension in FIGS. 1A and 1C, the width refers to the vertical dimension in FIG. 1B, and the height refers to FIG. And the dimension of the up-down direction in FIG.1 (C) is pointed out.

部品本体11は、部品特有の導体部である複数(図中は20)の内部電極12を高さ方向で略平行に向き合うように内蔵している。また、各内部電極12はその周囲(外部電極14に接続された後記各帯状接続部12aの端を除く)を誘電体部13によって覆われており、高さ方向で略平行に向き合う内部電極12の間それぞれには該誘電体部13が層状に存在している。各内部電極12はスパッタリング法や蒸着法等の薄膜形成手法を利用して形成されたものであり、その材料は金属、例えばニッケル又は銀である。誘電体部13は厚膜形成手法(スラリーを塗工し乾燥して得たシートを積み重ねてこれを焼成する手法)を利用して形成されたものであり、その材料はセラミックス、例えばチタン酸バリウム、チタン酸ストロンチウム、チタン酸カルシウム、チタン酸マグネシウム、ジルコン酸カルシウム、チタン酸ジルコン酸カルシウム、ジルコン酸バリウム又は酸化チタンである。   The component main body 11 incorporates a plurality (20 in the figure) of internal electrodes 12 which are conductor portions peculiar to the components so as to face each other substantially in parallel in the height direction. In addition, each internal electrode 12 is covered with a dielectric portion 13 at the periphery (except for the end of each band-like connection portion 12a, which will be described later connected to the external electrode 14), and the internal electrodes 12 face each other substantially in parallel in the height direction. The dielectric portions 13 are present in layers between each of the gaps. Each internal electrode 12 is formed by using a thin film forming method such as a sputtering method or a vapor deposition method, and the material thereof is a metal such as nickel or silver. The dielectric portion 13 is formed by using a thick film forming method (a method of stacking sheets obtained by applying slurry and drying and firing the stacked sheets), and the material thereof is ceramic, for example, barium titanate. Strontium titanate, calcium titanate, magnesium titanate, calcium zirconate, calcium zirconate titanate, barium zirconate or titanium oxide.

図1(B)及び図1(C)から分かるように、上から奇数番目の内部電極12は各々の左側端部に所定幅W12aの複数(図中は6)の帯状接続部12aを所定幅W12bの帯状間隙12bを介して略平行に、且つ、一体に有していて、該各帯状接続部12aの端を左側の外部電極14に接続されている。また、上から偶数番目の内部電極12も各々の右側端部に所定幅W12aの複数(図中は6)の帯状接続部12aを所定幅W12bの帯状間隙12bを介して略平行に、且つ、一体に有していて、該各帯状接続部12aの端を右側の外部電極14に接続されている。   As can be seen from FIG. 1 (B) and FIG. 1 (C), odd-numbered internal electrodes 12 from the top are provided with a plurality of (six in the drawing) strip-like connection portions 12a having a predetermined width W12a at the left end portions. They are provided in parallel and integrally with each other via a belt-like gap 12b of W12b, and the end of each belt-like connecting portion 12a is connected to the left external electrode 14. The even-numbered internal electrodes 12 from the top also have a plurality (six in the figure) of strip-shaped connecting portions 12a having a predetermined width W12a at the right end portions thereof in parallel with the strip-shaped gaps 12b having a predetermined width W12b, and They are integrally formed, and the ends of the respective strip-like connecting portions 12a are connected to the right external electrode.

後の説明から明らかなように、各内部電極12の各帯状接続部12aの幅W12aは、各内部電極12の幅W12に拘わらず、3〜80μmの範囲内にあることが好ましい。また、各内部電極12の各帯状接続部12aの幅W12aと各帯状間隙の幅W12bとの関係は、帯状接続部12aの幅W12a≧帯状間隙の幅W12bの条件を満足していることが好ましい。   As will be apparent from the following description, the width W12a of each strip-like connecting portion 12a of each internal electrode 12 is preferably in the range of 3 to 80 μm regardless of the width W12 of each internal electrode 12. In addition, the relationship between the width W12a of each strip-like connection portion 12a of each internal electrode 12 and the width W12b of each strip-like gap preferably satisfies the condition of the width W12a of the strip-like connection portion 12a ≧ the width W12b of the strip-like gap. .

各外部電極14は、部品本体11の長さ方向両端部に密着した下地層(符号無し)と該下地層の表面に形成された表面層との2層構造、或いは、下地層と表面層との間に1以上の中間層を有する多層構造を有している。下地層は例えばニッケル又は銀から成り、表面層は例えばスズ、パラジウム、金又は亜鉛から成り、中間層は例えば白金、パラジウム、金、銅又はニッケルから成る。   Each external electrode 14 has a two-layer structure of a base layer (no reference) closely attached to both ends in the length direction of the component body 11 and a surface layer formed on the surface of the base layer, or a base layer and a surface layer. It has a multilayer structure having one or more intermediate layers between them. The underlayer is made of, for example, nickel or silver, the surface layer is made of, for example, tin, palladium, gold, or zinc, and the intermediate layer is made of, for example, platinum, palladium, gold, copper, or nickel.

図2(A)〜図2(I)は図1に示したコンデンサ10の製法を示す。   2A to 2I show a method of manufacturing the capacitor 10 shown in FIG.

図1に示したコンデンサ10を製造するに際しては、先ず、スパッタリング法、蒸着法、電解メッキ法又は無電解メッキ法の薄膜形成手法を用いて、ポリエチレンテレフタレート等のプラスチック又はステンレス等の金属から成るベースシート(符号無し)の一面に、内部電極12を構成する金属材料から成る所定厚さで多数の導体パターンCPを所定配列(例えばマトリクス配列や千鳥配列)で形成して転写シートTSを作製する(図2(A)を参照)。図2(A)から分かるように、転写シートTSに形成された各導体パターンCPは、図1(B)に示した内部電極12(帯状接続部12aを含む)が2つの帯状接続部12aを介して連なった様な形状を有している。   When the capacitor 10 shown in FIG. 1 is manufactured, first, a base made of a plastic such as polyethylene terephthalate or a metal such as stainless steel is formed by using a thin film forming method such as sputtering, vapor deposition, electrolytic plating, or electroless plating. A transfer sheet TS is produced by forming a large number of conductor patterns CP in a predetermined arrangement (for example, a matrix arrangement or a staggered arrangement) with a predetermined thickness made of a metal material constituting the internal electrode 12 on one surface of a sheet (no reference). (See FIG. 2A). As can be seen from FIG. 2A, each conductor pattern CP formed on the transfer sheet TS has two strip-shaped connection portions 12a formed by the internal electrodes 12 (including the strip-shaped connection portions 12a) shown in FIG. It has a shape that is connected through.

また、誘電体部13を構成するセラミック材料の粉末を含むスラリーを用意し、ダイコータ等を用いて、ポリエチレンテレフタレート等のプラスチックから成るベースシート(図示省略)の一面に、該スラリーを所定厚さ及び幅で塗工し乾燥処理を施して第1グリーンシートS1を作製する(図2(B)を参照)。   Further, a slurry containing ceramic material powder constituting the dielectric portion 13 is prepared, and the slurry is applied to one surface of a base sheet (not shown) made of plastic such as polyethylene terephthalate using a die coater or the like. The first green sheet S1 is manufactured by coating with a width and drying (see FIG. 2B).

次に、転写シートTSの各導体パターンCPが形成された面を第1グリーンシートS1の一面に重ねて熱圧着し、その後に転写シートTSのベースシートを剥離して、複数の導体パターンCPが転写された第2グリーンシートS2を作製すると共に、該第2グリーンシートS2と各導体パターンCPの転写位置が左右方向にずれた第3グリーンシートS3を作製する(図2(C)及び図2(D)を参照)。   Next, the surface on which the respective conductor patterns CP of the transfer sheet TS are formed is superposed on one surface of the first green sheet S1 and thermocompression bonded, and then the base sheet of the transfer sheet TS is peeled off to form a plurality of conductor patterns CP. The transferred second green sheet S2 is manufactured, and a third green sheet S3 in which the transfer positions of the second green sheet S2 and each conductor pattern CP are shifted in the left-right direction is manufactured (FIGS. 2C and 2). (See (D)).

次に、打ち抜き刃及びヒータを有する吸着ヘッド等を用いて、積層台(図示省略)の上面に第1グリーンシートS1から打ち抜いた部分(ベースシートは含まない)を所定数に達するまで積み重ねて熱圧着し、その上面に第2グリーンシートS2から打ち抜いた部分(ベースシートは含まない)と第3グリーンシートS3から打ち抜いた部分(ベースシートは含まない)を交互に、且つ、各々が所定数に達するまで積み重ねて熱圧着し、その上面に第1グリーンシートS1から打ち抜いた部分(ベースシートは含まない)を所定数に達するまで積み重ねて熱圧着し、これを熱間静水圧プレス機等を用いて最終的に熱圧着して積層シートLSを作製する(図2(E)及び図2(F)を参照)。   Next, using a suction head having a punching blade and a heater or the like, the portion punched from the first green sheet S1 (not including the base sheet) is stacked on the upper surface of the stacking table (not shown) until a predetermined number is reached and heat is applied. The parts punched from the second green sheet S2 (not including the base sheet) and the parts punched from the third green sheet S3 (not including the base sheet) are alternately formed on the upper surface thereof, and each has a predetermined number. They are stacked and thermocompression bonded until they reach, and the top punched parts (not including the base sheet) are stacked and thermocompression bonded until reaching a predetermined number, and this is used with a hot isostatic press or the like. Finally, the laminated sheet LS is manufactured by thermocompression bonding (see FIGS. 2E and 2F).

次に、ダイシング機や押し切り機等を用いて、積層シートLSを格子状(図中の太線を参照)に切断して積層チップLCを作製する(図2(G)を参照)。図2(G)から分かるように、積層シートLS内の各導体パターンCPは、2つの帯状接続部12aが連なった部分の略中央を切断されて分断される。   Next, using a dicing machine, a press cutting machine, or the like, the laminated sheet LS is cut into a lattice shape (see the thick line in the figure) to produce a laminated chip LC (see FIG. 2G). As can be seen from FIG. 2 (G), each conductor pattern CP in the laminated sheet LS is divided by cutting substantially the center of the portion where the two strip-like connecting portions 12a are connected.

次に、多数の積層チップLCを焼成炉に投入し、前記第1グリーンシートS1に含まれるセラミック材料に応じた雰囲気下及び温度プロファイルで焼成(脱バインダ処理と焼成処理を含む)を行って、焼成チップ(部品本体11に相当)BCを作製する(図2(H)を参照)。   Next, a large number of laminated chips LC are put into a firing furnace, and firing (including binder removal processing and firing processing) is performed in an atmosphere and a temperature profile according to the ceramic material included in the first green sheet S1. A fired chip (corresponding to the component main body 11) BC is manufactured (see FIG. 2H).

次に、ローラ塗布機等を用いて、焼成チップBCの長さ方向両端部に外部電極ペースト(下地層を構成する材料の粉末を含む)を塗布し、該外部電極ペーストに含まれる金属材料に応じた雰囲気下及び温度プロファイルで焼付けを行って下地層を形成し、続いて該下地層の表面に表面層、或いは、1以上の中間層と表面層を順に電解メッキ法等で形成して、1対の外部電極14を作製する(図2(I)を参照)。   Next, using a roller applicator or the like, the external electrode paste (including the powder of the material constituting the base layer) is applied to both ends in the longitudinal direction of the fired chip BC, and the metal material contained in the external electrode paste is applied. Baking is performed in an appropriate atmosphere and temperature profile to form a base layer, and subsequently forming a surface layer on the surface of the base layer, or one or more intermediate layers and a surface layer in order by an electrolytic plating method, A pair of external electrodes 14 is manufactured (see FIG. 2I).

ここで、図1に示したコンデンサ10で得られる効果を検証するために用意したサンプル1〜20の帯状導体部12a及び帯状間隙12bの仕様と各々の評価方法及び評価結果を、図3を引用して説明する。   Here, the specifications of the strip conductor portions 12a and the strip gaps 12b of the samples 1 to 20 prepared for verifying the effect obtained by the capacitor 10 shown in FIG. 1, the evaluation methods and the evaluation results thereof are cited with reference to FIG. To explain.

各サンプル1〜20は図1に示したコンデンサ10と同様の構造を有する1005サイズのコンデンサであって、内部電極12はニッケルから成り、その総数は200で、各々の幅W12は略370μm、長さ(帯状接続部12aを含む)は略800μm、厚さ(帯状接続部12aを含む)は略1μmで、各帯状接続部12aの長さL12aは略140μmである。誘電体部13はチタン酸バリウムから成り、内部電極12の間それぞれに存在する誘電体部13の層状部分の厚さは略1.2μmである。各外部電極14は、銀製の下地層とスズ製の表面層とから成る2層構造を有しており、部品本体11の左右面及び上下面に回り込んだ部分の長さは略200μmである。   Each sample 1-20 is a 1005 size capacitor having the same structure as the capacitor 10 shown in FIG. 1. The internal electrodes 12 are made of nickel, the total number is 200, and each width W12 is approximately 370 μm, long. The thickness (including the strip-shaped connection portion 12a) is approximately 800 μm, the thickness (including the strip-shaped connection portion 12a) is approximately 1 μm, and the length L12a of each strip-shaped connection portion 12a is approximately 140 μm. The dielectric portion 13 is made of barium titanate, and the thickness of the layered portion of the dielectric portion 13 existing between the internal electrodes 12 is approximately 1.2 μm. Each external electrode 14 has a two-layer structure composed of a silver base layer and a tin surface layer, and the length of the portion of the component main body 11 that wraps around the left and right surfaces and the top and bottom surfaces is approximately 200 μm. .

各サンプル1〜20は前記製法(図2(A)〜図2(I)を参照)に準じて製造されたものであって、各々の内部電極12はスパッタリング法によって形成されている。各サンプル1〜20における「帯状接続部12aの幅W12a(μm)」と「帯状間隙12bの幅W12b(μm)」と「帯状接続部12aの数」は図3に示した通りである。   Each sample 1-20 is manufactured according to the said manufacturing method (refer FIG. 2 (A)-FIG. 2 (I)), Comprising: Each internal electrode 12 is formed by sputtering method. The “width W12a (μm) of the strip-shaped connecting portion 12a”, “width W12b (μm) of the strip-shaped gap 12b”, and “number of strip-shaped connecting portions 12a” in the samples 1 to 20 are as shown in FIG.

図3に示したサンプル4、7、10、13、16及び19の「帯状接続部12aの数」は、「帯状接続部12aの幅W12a(μm)」及び「帯状間隙12bの幅W12b(μm)」に記した数値に準じて、幅W12が略370μmの内部電極12の端部に収まる最大数としてある。加えて、サンプル1〜3の「帯状接続部12aの数」は比較のためにサンプル4と同じにし、サンプル5及び6の「帯状接続部12aの数」は比較のためにサンプル7と同じにし、サンプル8及び9の「帯状接続部12aの数」は比較のためにサンプル10と同じにし、サンプル11及び12の「帯状接続部12aの数」は比較のためにサンプル13と同じにし、サンプル14及び15の「帯状接続部12aの数」は比較のためにサンプル16と同じにし、サンプル17、18及び20の「帯状接続部12aの数」は比較のためにサンプル19と同じにしてある。   The “number of strip-shaped connecting portions 12a” of Samples 4, 7, 10, 13, 16, and 19 shown in FIG. 3 are “width W12a (μm) of strip-shaped connecting portion 12a” and “width W12b of strip-shaped gap 12b (μm)”. According to the numerical value described in “)”, the width W12 is the maximum number that can be accommodated at the end of the internal electrode 12 having a width of about 370 μm. In addition, the “number of strip connections 12a” of Samples 1 to 3 is the same as Sample 4 for comparison, and the “number of strip connections 12a” of Samples 5 and 6 is the same as Sample 7 for comparison. Samples 8 and 9 have the same “number of strip connections 12a” as sample 10 for comparison, and samples 11 and 12 have the same “number of strip connections 12a” as sample 13 for comparison. 14 and 15 have the same “number of strip connections 12a” as sample 16 for comparison, and samples 17, 18 and 20 have the same “number of strip connections 12a” as sample 19 for comparison. .

図3の「共振周波数の変動率(%)」は、各サンプル1〜20の設計段階で求めた共振周波数と各々30個のサンプル1〜20の実際の共振周波数の平均値との偏差を百分率で表したものである。因みに、各サンプル1〜20の実際の共振周波数は、各々の自己共振点であり、インピーダンスアナライザ(アジレントテクノロジー製 4294A)で測定した。   The “resonance frequency fluctuation rate (%)” in FIG. 3 is a percentage of the deviation between the resonance frequency obtained in the design stage of each sample 1 to 20 and the average value of the actual resonance frequency of each of 30 samples 1 to 20. It is represented by. Incidentally, the actual resonant frequency of each sample 1-20 is each self-resonant point, and was measured with an impedance analyzer (4294A manufactured by Agilent Technologies).

また、図3の「帯状接続部12aの端の形態異常率(%)」は、各サンプル1〜20を前記製法(図2(A)〜図2(I)を参照)に準じて製造する途中で、積層チップ作製工程(図2(G)を参照)で作製された積層チップLCを各々100個取り出し、帯状接続部12aの端(切断面及びその近傍部分を指す)に亀裂や欠けやバリ発生等の形態異常が有るか否かを光学顕微鏡で観察し、形態異常有りと確認された数nを百分率(n/100)で表したものである。   In addition, the “morphological abnormality rate (%) at the end of the belt-like connecting portion 12a” in FIG. 3 is obtained by manufacturing each sample 1 to 20 in accordance with the above manufacturing method (see FIGS. 2A to 2I). In the middle, 100 laminated chips LC produced in the laminated chip producing process (see FIG. 2G) are each taken out, and cracks or chips are formed at the end of the strip-like connecting portion 12a (pointing to the cut surface and its vicinity). Whether or not there is a morphological abnormality such as the occurrence of burrs is observed with an optical microscope, and the number n confirmed as having a morphological abnormality is expressed as a percentage (n / 100).

図3から分かるように、サンプル2〜19のうち、サンプル4、7、10、16及び19において−1%といった共振周波数の変動が確認され、且つ、サンプル17、18及び19において1%といった帯状接続部12aの端の形態異常が確認されたが、周波数変動率は極めて僅かであるため、帯状接続部12aの幅W12aが3〜80μmの範囲内にあれば、帯状間隙12bの幅W12bに拘わらず、所期の周波数特性を良好に維持できると言える。   As can be seen from FIG. 3, among samples 2 to 19, a change in resonance frequency of −1% is confirmed in samples 4, 7, 10, 16 and 19, and a band shape of 1% in samples 17, 18 and 19 is observed. Although an abnormality in the shape of the end of the connecting portion 12a was confirmed, the frequency variation rate is very small. Therefore, if the width W12a of the strip-shaped connecting portion 12a is in the range of 3 to 80 μm, the width W12b of the strip-shaped gap 12b is concerned. Therefore, it can be said that the desired frequency characteristics can be maintained satisfactorily.

また、図3から分かるように、サンプル2〜19のうち、僅かな共振周波数の変動が確認されサンプル4、7、10、16及び19を除いて考えれば、帯状接続部12aの幅W12aが3〜80μmの範囲内であっても、帯状接続部12aの幅W12a≧帯状間隙の幅W12bの条件を満足している方が、所期の周波数特性をより一層良好に維持できると言える。   Further, as can be seen from FIG. 3, if the slight resonance frequency fluctuation is confirmed among the samples 2 to 19, and the samples 4, 7, 10, 16, and 19 are excluded, the width W12a of the strip-like connecting portion 12a is 3 Even within the range of ˜80 μm, it can be said that the desired frequency characteristics can be maintained better if the condition of the width W12a of the band-shaped connecting portion 12a ≧ the width W12b of the band-shaped gap is satisfied.

尚、、図3に示したサンプル2〜19は何れも内部電極12(帯状接続部12aを含む)の厚さが略1μmであるが、該内部電極12の厚さが1μmよりも薄い場合や1μmよりも厚い場合でも、加えて、内部電極12がニッケル以外の金属から成る場合でも、帯状接続部12aの幅W12aが3〜80μmの範囲内にあり、帯状接続部12aの幅W12a≧各帯状間隙の幅W12bの条件を満足していれば、前記同様の効果が得られる。   In each of Samples 2 to 19 shown in FIG. 3, the thickness of the internal electrode 12 (including the strip-shaped connecting portion 12a) is approximately 1 μm. However, when the thickness of the internal electrode 12 is less than 1 μm, Even when the internal electrode 12 is made of a metal other than nickel, even if it is thicker than 1 μm, the width W12a of the band-shaped connecting portion 12a is in the range of 3 to 80 μm, and the width W12a of the band-shaped connecting portion 12a ≧ each band-shaped The same effect as described above can be obtained if the condition of the gap width W12b is satisfied.

図4は、図1に示したコンデンサ10の構造変形例を示す。   FIG. 4 shows a structural modification of the capacitor 10 shown in FIG.

このコンデンサ10’が図1に示したコンデンサ10と異なるところは、内部電極12と複数の帯状接続部12bとの間に該内部電極12の幅W12よりも幅が狭く、且つ、複数の帯状接続部12bの全体幅以上の幅を有する引出部12cを介在させた点にある。このコンデンサ10’にあっては、引出部12cを設けたことによって帯状接続部12bの長さL12aが短くなるものの、帯状接続部12aの幅W12aが3〜80μmの範囲内にあり、帯状接続部12aの幅W12a≧各帯状間隙の幅W12bの条件を満足していれば、内部電極12の厚さが1μmよりも薄い場合や1μmよりも厚い場合でも、加えて、内部電極12がニッケル以外の金属から成る場合でも、前記同様の効果が得られる。   This capacitor 10 ′ is different from the capacitor 10 shown in FIG. 1 in that the width between the internal electrode 12 and the plurality of strip-shaped connection portions 12b is narrower than the width W12 of the internal electrode 12, and the plurality of strip-shaped connections. The leading portion 12c has a width greater than the entire width of the portion 12b. In this capacitor 10 ', although the length L12a of the strip-shaped connecting portion 12b is shortened by providing the lead-out portion 12c, the width W12a of the strip-shaped connecting portion 12a is in the range of 3 to 80 μm, and the strip-shaped connecting portion If the condition of width W12a of 12a ≧ width W12b of each band gap is satisfied, even if the thickness of the internal electrode 12 is thinner than 1 μm or thicker than 1 μm, in addition, the internal electrode 12 is other than nickel Even when made of metal, the same effect as described above can be obtained.

以上、本発明を積層型セラミックコンデンサに適用した実施形態を説明したが、積層型セラミックコンデンサ以外の積層型セラミック電子部品、例えば部品特有の導体部としてコイルを内蔵した積層型セラミックインダクタに本発明を適用した場合、詳しくはコイルの端部に複数の帯状接続部を帯状間隙を介して略平行に、且つ、一体に設けた場合でも、帯状接続部の幅が3〜80μmの範囲内にあり、帯状接続部の幅≧帯状間隙の幅の条件を満足していれば、前記同様の効果が得られる。   As described above, the embodiment in which the present invention is applied to the multilayer ceramic capacitor has been described. However, the present invention is applied to multilayer ceramic electronic components other than the multilayer ceramic capacitor, for example, a multilayer ceramic inductor having a built-in coil as a conductor portion unique to the component. When applied, in detail, even when a plurality of strip-shaped connection portions are provided substantially in parallel and integrally with the end portions of the coil via the strip-shaped gap, the width of the strip-shaped connection portions is in the range of 3 to 80 μm, As long as the condition of the width of the band-shaped connecting portion ≧ the width of the band-shaped gap is satisfied, the same effect as described above can be obtained.

10,10’…積層型セラミックコンデンサ、11…部品本体、12…内部電極、12a…帯状接続部、12b…帯状間隙、13…誘電体部、14…外部電極。   DESCRIPTION OF SYMBOLS 10, 10 '... Multilayer ceramic capacitor, 11 ... Component main body, 12 ... Internal electrode, 12a ... Band-shaped connection part, 12b ... Band-shaped gap | interval, 13 ... Dielectric part, 14 ... External electrode.

Claims (2)

薄膜形成手法を利用して形成された部品特有の導体部が部品本体に内蔵され、該部品本体に設けられた外部電極が前記導体部の端に接続された構造を備える積層型セラミック電子部品において、
前記導体部はその端部に複数の帯状接続部を帯状間隙を介して略平行に、且つ、一体に有していて各帯状接続部の端を前記外部電極に接続されており、
前記帯状接続部の幅は3〜80μmの範囲内にあり、前記帯状接続部の幅と前記帯状間隙の幅とは帯状接続部の幅≧帯状間隙の幅の条件を満足している、
ことを特徴とする積層型セラミック電子部品。
In a multilayer ceramic electronic component having a structure in which a component-specific conductor formed using a thin film forming method is built in a component main body, and an external electrode provided on the component main body is connected to an end of the conductor portion ,
The conductor portion has a plurality of strip-like connection portions at its end portions substantially in parallel with the strip-like gap, and integrally, and the end of each strip-like connection portion is connected to the external electrode,
The width of the band-shaped connecting portion is in the range of 3 to 80 μm, and the width of the band-shaped connecting portion and the width of the band-shaped gap satisfy the condition of the width of the band-shaped connecting portion ≧ the width of the band-shaped gap.
A multilayer ceramic electronic component characterized by that.
前記導体部は、スパッタリング法、蒸着法、電解メッキ法又は無電解メッキ法を利用して形成されたものである、
ことを特徴とする請求項1に記載の積層型セラミック電子部品。
The conductor portion is formed using a sputtering method, a vapor deposition method, an electrolytic plating method or an electroless plating method.
The multilayer ceramic electronic component according to claim 1, wherein:
JP2012283150A 2012-12-26 2012-12-26 Multilayer ceramic electronic component Pending JP2014127581A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110246690A (en) * 2015-11-27 2019-09-17 三星电机株式会社 Multilayer ceramic electronic component
US20200066457A1 (en) * 2018-08-24 2020-02-27 Apple Inc. Self-fused capacitor
US20200118759A1 (en) * 2018-10-10 2020-04-16 Samsung Electro-Mechanics Co., Ltd. Multi-layered ceramic electronic component

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110246690A (en) * 2015-11-27 2019-09-17 三星电机株式会社 Multilayer ceramic electronic component
US10943736B2 (en) 2015-11-27 2021-03-09 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing a multilayer ceramic electronic component with improved withstand voltage characteristics
CN110246690B (en) * 2015-11-27 2021-09-21 三星电机株式会社 Multilayer ceramic electronic component
US20200066457A1 (en) * 2018-08-24 2020-02-27 Apple Inc. Self-fused capacitor
US20200118759A1 (en) * 2018-10-10 2020-04-16 Samsung Electro-Mechanics Co., Ltd. Multi-layered ceramic electronic component
US11164702B2 (en) * 2018-10-10 2021-11-02 Samsung Electro-Mechanics Co., Ltd. Multi-layered ceramic electronic component having step absorption layer

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