JP2014123792A - Image data transfer system - Google Patents

Abstract

In transferring image data, error correction is accurately performed while maintaining line synchronization.
A transmission device reads one line written in a line buffer 11 in synchronization with an input synchronization signal in a packet unit by a read control unit 13, adds error detection data to each packet, and outputs it together with an output synchronization signal Transmit to the receiving device. The receiving device detects the error of each received packet using the error detection data, and writes each packet to the line buffer in synchronization with the output synchronization signal. The receiving device concatenates and reads each packet and outputs image data in units of one line. When an error is detected, the receiving apparatus transmits a retransmission request signal to the transmitting apparatus, writes the retransmitted packet in the line buffer, and corrects the error. In response to the retransmission request signal, the reading control unit 13 of the transmitting apparatus reads the packet in which the error is detected from the line buffer 11 and retransmits the packet.
[Selection] Figure 2

Description

  The present invention relates to an image data transfer system.

  An interface used for transferring image data is susceptible to noise including static electricity. In high-speed serial communication performed between the print controller and the print engine, a scramble circuit and a descramble circuit are generally mounted as countermeasures against unnecessary radiation (EMI; Electro Magnetic Interference). Once an error occurs due to noise, the receiving descrambling circuit continues to output erroneous data until the transmitting scrambling circuit is reset.

  Conventionally, image data is transmitted in units of main scanning lines, and a checksum is added to the image data of each line to detect errors caused by noise or the like (see, for example, Patent Document 1). In addition, an unused bit is provided in the data of each line, and a parity bit is added to the unused bit to detect an error (see, for example, Patent Document 2).

JP 2006-191188 A JP 2010-288014 A

  As described in Patent Document 2, there is a method of correcting an error by correcting a pixel in which an error has occurred based on peripheral pixel data, but the original image data cannot always be reproduced. In order to correct the error accurately, it is necessary to retransmit the image data.

When transferring image data line by line, the scramble circuit can be reset for each line and error correction can be performed. However, even for an error of several pixels, the image data must be retransmitted in units of lines, and the transfer rate of the image data is reduced for error correction.
Assuming that errors occur continuously on multiple lines, to maintain the line synchronization and continue transfer without waiting for error correction on each line, the memory for multiple lines must be stored on the transmission side and the reception side. It is necessary to provide each. A handshake between the sender and receiver is also required.

  Further, the print engine is usually optimized to form an image based on line-synchronized image data. However, since the order of lines is changed by retransmission, it is necessary to correct the order of the original lines.

  An object of the present invention is to perform error correction accurately while maintaining line synchronization in the transfer of image data.

According to the invention of claim 1,
A transmission device that transmits image data, and a reception device that receives the image data;
The transmitter is
A line buffer;
A write controller that outputs a write address to the line buffer in synchronization with an input synchronization signal and writes image data to the line buffer in units of one line;
A read control unit that outputs a read address to the line buffer, reads the written image data in units of packets smaller than one line, and generates an output synchronization signal;
A detection data adding unit for adding error detection data to each read packet, and transmitting each packet together with an output synchronization signal;
The receiving device is:
An error detection unit that detects an error of each packet received from the transmission device using error detection data attached to each packet;
A line buffer;
A write control unit that outputs a write address to the line buffer in synchronization with the output synchronization signal received from the transmitter, and writes each received packet to the line buffer;
A read control unit that outputs a read address to the line buffer in synchronization with the received output synchronization signal, concatenates and reads the written packets, and outputs image data in units of one line;
When a packet error is detected by the error detector, the write controller of the receiver transmits a retransmission request signal to the transmitter, returns the write address, and is retransmitted from the transmitter To the line buffer, error correction,
In response to the retransmission request signal, the reading control unit of the transmitting device returns the reading address and reads the packet in which the error is detected from the line buffer and retransmits the packet.
An image data transfer system is provided.

According to invention of Claim 2,
When retransmitting a packet, the reading control unit of the transmitting apparatus uses an assertion period of one line indicated by the input synchronization signal and a negation period until the next line for reading one line including the packet to be retransmitted. ,
An image data transfer system according to claim 1 is provided.

According to invention of Claim 3,
When the end timing of one line including the packet to be retransmitted exceeds the start timing of the next line indicated by the input synchronization signal, the reading control unit of the transmission device may receive the next of the output synchronization signal after the end timing. Delay the start of the line,
An image data transfer system according to claim 1 or 2 is provided.

According to invention of Claim 4,
When the read control unit of the transmission device delays the start timing of the next line of the output synchronization signal, each line indicated by the input synchronization signal until the start timing of each subsequent line coincides with the input synchronization signal. Shorten the negation period between them, and advance the timing to read each line,
An image data transfer system according to claim 3 is provided.

According to the invention of claim 5,
The reading control unit of the transmitting apparatus performs the reading of the packet in parallel with the detection of the error of the previous packet, and when an error is detected in the previous packet and a retransmission request signal is received, Next to the packet, read the previous packet in which an error was detected,
The write control unit of the receiving device performs packet writing in parallel with detection of an error of the previous packet, and transmits the retransmission request signal when an error is detected in the previous packet, Next to the packet being written, the previous packet retransmitted from the transmitter is written.
An image data transfer system according to any one of claims 1 to 4 is provided.

According to the invention of claim 6,
The read address and the write address are a bit string obtained by combining the address of the packet in the upper bits and the address of the pixels in the packet in the lower bits,
The reading control unit of the transmitting device returns the address of the packet to the previous one, reads the previous packet in which the error was detected,
The write control unit of the receiving device writes the retransmitted previous packet by returning the address of the packet to the previous one,
An image data transfer system according to claim 5 is provided.

According to the invention of claim 7,
The reading control unit of the transmitting device and the writing control unit of the receiving device include two counters that alternately count each time a packet is transmitted, and use the count value by the two counters as the address of the packet,
The two counters are
If no error is detected, each counter counts against the count value of the other counter,
If an error is detected once or an odd number of times consecutively, the counter that counts immediately after detection stops counting and maintains the count value, and the next counter that counts counts against its own count value,
If an error is detected a number of times consecutively, the counter that counts immediately after detection stops counting and maintains the count value, and the next counter that counts counts against the count value of the other counter.
An image data transfer system according to claim 6 is provided.

According to the invention described in claim 8,
The transmission device includes a serial conversion unit that converts the packet into serial data, scrambles and transmits the data,
The receiving device includes a parallel conversion unit that descrambles the received packet and converts the packet into parallel data.
An image data transfer system according to any one of claims 1 to 7 is provided.

According to the invention of claim 9,
The reading control unit of the transmitting device makes the interval between the packets to be read longer than the time required for resetting the scramble process,
An image data transfer system according to claim 8 is provided.

According to the invention of claim 10,
The image data is compressed image data.
An image data transfer system according to any one of claims 1 to 9 is provided.

  According to the present invention, even if an error occurs, it can be retransmitted in units of packets smaller than one line and error correction can be performed, and the error correction can be accurately performed while suppressing a decrease in the transfer rate of image data. Also, even when a packet is retransmitted, line synchronization can be performed with an output synchronization signal, and the order of packets on one line can be maintained by address control. Therefore, in the transfer of image data, it is possible to correct errors accurately while maintaining line synchronization.

1 shows a configuration example of an image data transfer system according to the present embodiment. It is a block diagram of the transmission process part of FIG. It is a timing chart which shows an input synchronizing signal. It is a figure explaining count operation of two counters. It is a timing chart which shows an error flag signal and a flag count signal when an error is detected once. It is a timing chart which shows an error flag signal and a flag count signal when an error is detected a number of times continuously. It is a timing chart which shows an error flag signal and a flag count signal when an error is detected odd number of times continuously. It is a timing chart explaining count operation of two counters when an error is detected once. It is a timing chart explaining the count operation | movement of two counters when an error is detected continuously several times. It is a timing chart explaining the count operation of two counters when an error is detected continuously odd times. It is a timing chart which shows an input synchronizing signal and the output synchronizing signal which a transmitter and a receiver generate. It is a timing chart which shows an input synchronizing signal and the output synchronizing signal which a transmitter and a receiver each generate | occur | produce when a packet is resent. It is a timing chart which shows an input synchronizing signal and the output synchronizing signal which a transmission device and a receiving device each generate | occur | produce when the end timing of one line exceeds the start timing of the next line by packet retransmission. It is a block diagram of the reception process part of FIG.

  Hereinafter, an embodiment of an image data transfer system of the present invention will be described with reference to the drawings.

FIG. 1 shows an image data transfer system G according to the present embodiment.
As shown in FIG. 1, the image data transfer system G includes a transmission device g1 and a reception device g2, and transfers 8-bit image data D from the transmission device g1 to the reception device g2.
The transmission device g1 can be, for example, a print controller that generates image data. The receiving device g2 can be a print engine that forms an image based on image data transmitted from the print controller.
The transmitter g1 and the receiver g2 are connected by a dedicated line.

  The transmission device g1 includes an image data generation unit 101, a transmission processing unit 102, and a serial conversion unit 103. The transmission device g1 may include an image data input unit that inputs image data to be transferred.

The image data generation unit 101 generates image data D in a bitmap format. For example, the image data generation unit 101 rasterizes PDL (Page Description Language) data transmitted from a computer terminal on the network, and performs C (cyan), M (magenta), Y (yellow), and K (black). Four-color image data D is generated.
Further, the image data generation unit 101 generates attribute data indicating the attribute of each pixel of the image data D, and outputs it together with the image data D. The attribute is, for example, a character (Text), a graphic (Graphics), or a photograph (Image).

The transmission processing unit 102 divides the image data D output from the image data generation unit 101 in units of packets, adds error detection data to each packet, and outputs the packet.
The error detection method is not particularly limited, and examples include CRC (Cyclic Redundancy Check), parity check, checksum, and Hamming code. CRC is preferable because of its simple circuit configuration, and an example using CRC will be described here.

The serial conversion unit 103 has a scramble circuit.
The serial conversion unit 103 converts each packet output from the transmission processing unit 102 into serial data, further scrambles it with a scramble circuit, and transmits it to the receiving device g2. By scramble processing, unnecessary radiation associated with the transfer of image data can be prevented. The serial conversion unit 103 resets the scramble process every time a packet is transmitted.

  The receiving device g2 includes a parallel conversion unit 201 and a reception processing unit 202 as shown in FIG.

The parallel conversion unit 201 has a descrambling circuit.
The parallel conversion unit 201 converts each packet received from the transmission device g1 into parallel data, further descrambles it by a descrambling circuit, and outputs it to the reception processing unit 202. The parallel conversion unit 201 resets the descrambling process every time a packet is received.

The reception processing unit 202 concatenates the packets output from the parallel conversion unit 201 and outputs image data in units of one line. At this time, the reception processing unit 202 detects an error of each packet, and transmits a retransmission request signal RETRY signal to the transmission device g1.
The reception processing unit 202 performs error correction using the packet retransmitted from the transmission device g1, and connects the packets after error correction to output image data in units of one line.

Next, details of the transmission processing unit 102 and the reception processing unit 202 will be described.
FIG. 2 is a configuration diagram of the transmission processing unit 102.
As shown in FIG. 2, the transmission processing unit 102 includes a line buffer 11, a writing control unit 12, a reading control unit 13, and a detection data adding unit 14.
Image data D is input to the transmission processing unit 102 together with input synchronization signals HV (Horizontal Valid), VV (Vertical Valid), and IND (INDex).

FIG. 3 shows the input synchronization signals HV, VV and IND.
As shown in FIG. 3, the input synchronization signal HV indicates the effective area of the image in the main scanning direction, that is, the effective area of each line.
Further, as shown in FIG. 3, the input synchronization signal VV indicates the effective area of the image in the sub-scanning direction, that is, the effective area of each page, as shown in FIG.
The input synchronization signal IND indicates the start timing of each line. As shown in FIG. 3, only the start timing of each line is asserted.

The line buffer 11 is a memory that can hold one line of image data.
When the enable signal WE and the write address WADRS are input from the write control unit 12, the line buffer 11 receives one line of the image data D and holds it in association with the write address WADRS.
Further, when the enable signal RE and the read address RADRS are input from the read control unit 13, the line buffer 11 outputs the image data D corresponding to the read address RADRS to the detection data adding unit 14.

The writing control unit 12 writes the image data D into the line buffer 11 in units of one line in synchronization with the input synchronization signals HV and VV.
Specifically, when both the input synchronization signals HV and VV are in the assert period, the write control unit 12 outputs the enable signal WE to the line buffer 11 and permits writing to the line buffer 11.
Further, the write control unit 12 outputs the write address WADRS for one line to the line buffer 11 using a counter. When one line is composed of 8000 pixels, when the input synchronization signals HV and VV are switched to the assertion period, the write control unit 12 counts up from 0 by 1 by the counter and outputs each count value as the write address WADRS. . Thereby, the write addresses WADRS of 0 to 7999 are assigned in order from the first pixel of one line. The write controller 12 resets the counter to 0 each time the input synchronization signal HV switches to the negate period.

  The write control unit 12 outputs the input synchronization signals HV, VV, and IND to the read control unit 13.

The read control unit 13 reads one line of image data written in the line buffer 11 in units of packets smaller than one line. One packet is preferably composed of powers of 2 pixels.
At the time of reading, the read control unit 13 outputs the read address RADRS to the line buffer 11 and reads image data in units of packets.

The read address RADRS is a bit string obtained by combining the address of the packet in the upper bits and the address of the pixels in the packet in the lower bits.
When one packet is 128 pixels, one line of 8000 pixels is divided into 63 packets. In this case, when the addresses 0 to 62 of each packet are arranged in the upper 6 bits and the addresses 0 to 127 of 128 pixels in the packet are arranged in the lower 7 bits and combined, the read addresses RADRS of 0 to 7999 which are the same as the write address WADRS. Can be configured.
For example, the write address WADRS is 299 for the 300th pixel from the beginning of one line. When one line is divided into packets, the 300th pixel is positioned 43rd from the beginning in the third packet. The address of the packet is 2, and the address of the pixel in the packet is 43. A bit string in which 2 is arranged in the upper 6 bits and 43 is arranged in the lower 7 bits is 0000100101011 and indicates the same 299 as the write address WADRS.

The read control unit 13 includes counters Ev, Od, and C, and outputs a read address RADRS using these count values.
The two counters Ev and Od alternately count each time a packet is transmitted, and count from 0 to 62.
The counter C repeatedly counts 0 to 130.
The readout control unit 13 uses the count values 0 to 62 obtained by the two counters Ev and Od as the addresses of the packets, and uses the count values 0 to 127 obtained by the counter C as the addresses of the pixels in the packet. A read address RADRS is configured.

With reference to FIG. 4, the basic counting operation of the two counters Ev and Od will be described.
DE (Data Enable) shown in FIG. 4 is an output synchronization signal indicating an effective area of a packet. HSYNC is an output synchronization signal indicating the start timing of each line.
The read control unit 13 outputs a select signal EO for switching between the assertion period and the negation period each time the counter C counts 129 in order to cause the counter Ev and the counter Od to count alternately.

The counter Od counts when the select signal EO switches to the assert period as shown in FIG. The counter Od outputs a count value CNT_O of 0 at the first count, and outputs a count value CNT_O obtained by counting +1 with respect to the count value CNT_E of the other counter Ev at the next count.
The counter Ev counts when the select signal EO switches to the negate period as shown in FIG. The counter Ev outputs a count value CNT_E of 1 at the first count, and outputs a count value CNT_E obtained by counting +1 with respect to the count value CNT_O of the other counter Od at the next count.
Each of the counters Ev and Od resets the count value when the output synchronization signal HSYNC is asserted.

  As shown in FIG. 4, the read control unit 13 selects the count value CNT_O when the select signal EO is in the assert period, and selects the count value CNT_E when the select signal EO is in the negate period. As a result, every time a packet is read and transmitted, a count value CNT_SEL in ascending order of 0, 1, 2, 3,... 62 is obtained. The read control unit 13 uses the count value CNT_SEL as a packet address.

  The read control unit 13 reads a packet in parallel with the reception device g2 detecting an error in the previous packet. When an error is detected in the previous packet, the read control unit 13 receives the retransmission request signal RETRY during reading of the packet. Therefore, next to the packet being read, the read control unit 13 receives the retransmission request signal RETRY. Read the packet again.

At this time, the read control unit 13 returns the address of the packet at the time of reading to the previous one, and reads the previous packet in which an error is detected. Since the same address control is performed when a packet received by the receiving device g2 is written, the receiving device g2 can write the packets in the correct order even if the order of transferring the packets by retransmission is changed.
Specifically, the read control unit 13 outputs an error flag signal EF and a flag count signal EFCnt, controls the counting operation of the two counters Ev and Od, and obtains the address of the previous packet.

The read controller 13 uses a counter (not shown) and outputs an error flag signal EF and a flag count signal EFCnt in response to the retransmission request signal RETRY.
Since the packet error is detected by the CRC code added to the end of the packet, as shown in FIG. 5a, when the error of the previous packet is detected, the retransmission request signal RETRY from the receiving device g2 is , Input during reading of the next packet.

The counter for the error flag signal EF counts by +1 when the retransmission request signal RETRY is input, and resets to 0 when the counter C counts 129.
As shown in FIG. 5a, the read control unit 13 outputs an error flag signal EF having an assert period when the count value is 1 and a negate period when the count value is 0.

The counter for the flag count signal EFCnt counts how many times the error flag signal EF is asserted continuously. Specifically, when the counter C counts 128, the counter counts +1 if the error flag signal EF is asserted, and resets it to 0 if it is not asserted.
As shown in FIG. 5a, the read control unit 13 outputs a flag count signal EFCnt having an assert period when the count value is 1 and a negate period when the count value is 0.

The counter for the flag count signal EFCnt is a counter that outputs the lower 1 bit.
As shown in FIG. 5b, when the error flag signal EF is continuously asserted twice, a count value of + 1 + 1 = 10 is obtained, but 0 of the lower 1 bit is output as the count value. As a result, as shown in FIG. 5b, the flag count signal EFCnt is asserted in response to the first assertion of the error flag signal EF and negated in response to the next assertion of the error flag signal EF.
When the error flag signal EF is continuously asserted three times, the flag count signal EFCnt repeats assertion and negation every time the error flag signal EF is asserted, as shown in FIG. 5c.
As described above, the flag count signal EFCnt repeats the assertion period and the negation period each time a packet is transmitted when an error occurs continuously a plurality of times.

The counters Ev and Od check the error flag signal EF and the flag count signal EFCnt at the time of counting, and perform a counting operation as follows according to each error flag signal EF and flag count signal EFCnt.
When an error is detected once or an odd number of times, the error flag signal EF is asserted immediately after detection. The counter Ev or Od that counts immediately after detection stops counting and maintains the count value CNT_E or CNT_O immediately before each. At the next count, the error flag signal EF is negated and the flag count signal EFCnt is asserted. The counter Ev or Od at this time counts +1 with respect to the count value CNT_E or CNT_O of each counter Ev or Od itself.

  When an error is detected consecutively several times, the error flag signal EF is asserted immediately after detection. The counter Ev or Od that counts immediately after detection stops counting and maintains the respective count value CNT_E or CNT_O. At the next count, both the error flag signal EF and the flag count signal EFCnt are negated. The counter Ev or Od at the time of counting is incremented by one with respect to the count value CNT_O or CNT_E of the other counter Od or Ev.

FIG. 6 is a timing chart showing the counting operation of each counter Ev and Od when an error is detected once.
In accordance with the select signal EO, the counter Od first counts zero. Next, the counter Ev counts 1. Next, the counter Od counts, but since no error is detected, the counter Od counts +1 with respect to the count value CNT_E = 1. In FIG. 6, partner + 1 indicates that the two counters Ev and Od count with respect to the count value of the other counter Od or Ev.
At the next count, immediately after the error is detected, the error flag signal EF is asserted. The counter Ev stops the count operation and maintains the previous count value CNT_E = 1. Keep in FIG. 6 indicates that the count value is maintained.
At the next count, the error flag signal EF is negated, but the flag count signal EFCnt is asserted. Therefore, the counter Od counts +1 with respect to the count value CNT_O = 2 immediately before the counter Od itself. Self + 1 in FIG. 6 indicates that counting is performed with respect to the count value of the counter Ev or Od itself.

Further, since no error is detected at the next count, the error flag signal EF and the flag count signal EFCnt are negated. The counter Ev counts +1 with respect to the count value CNT_O = 3.
As a result, the count value CNT_E is output in the order of 1, 1, 4 from the counter Ev, and the count value CNT_O is output in the order of 0, 2, 3 from the counter Od.
The count value CNT_SEL selected from the count values CNT_E and CNT_O is output in the order of 0, 1, 2, 1, 3, and 4. In this manner, when an error is detected, the read control unit 13 can return the address of the next packet to be output to the address of the packet that was output immediately before and output the packet.

FIG. 7 is a timing chart showing the counting operations of the counters Ev and Od when an error is detected a number of times consecutively.
If an error is detected twice consecutively from the first packet, as shown in FIG. 7, both the error flag signal EF and the flag count signal EFCnt are negated at the time of the next count immediately after the error detection. ing. The counter Od that counts at this time counts +1 with respect to the count value CNT_E of the other counter Ev.

  By such a counting operation, the count value CNT_SEL is in the order of 0, 1, 0, 1, 2, and 3, and the addresses 0 and 1 of the packet in which the error is detected are output again.

FIG. 8 is a timing chart showing the counting operations of the counters Ev and Od when errors occur continuously for an odd number of times.
When an error is detected three times continuously from the first packet, as shown in FIG. 8, the error flag signal EF is negated at the next count after the third error detection, but the flag count The signal EFCnt is asserted. At this time, the counter Ev that performs counting counts +1 with respect to its own count value CNT_E.

  By such a counting operation, the count value CNT_SEL is in the order of 0, 1, 0, 1, 0, 2, 3, and the addresses 0, 1, 0 of the packet in which the error is detected are output again.

  The read control unit 13 outputs an enable signal of 0 to the selector 142 while the count value of the counter C is 0 to 127, and permits the packet output. Further, when the count value is 128, the read control unit 13 outputs an enable signal of 1 and permits the output of the CRC code.

It is preferable that the read control unit 13 sets the interval between read packets to be longer than the time required for reset so that the scramble process can be reset for each packet.
In this embodiment, two clocks are required for resetting. Therefore, the read control unit 13 counts up to 128 by the counter C as described above, and further counts 129 and 130 and sets an interval of 2 clocks, and then resets the count value and reads the next packet. .

When reading each packet, the read control unit 13 generates an output synchronization signal DE in which the counter C count value is between 0 and 128 as an assertion period, and the count value is between 129 and 130 as a negation period, Output. That is, the output synchronization signal DE indicates the effective area of each packet.
Further, the read control unit 13 generates and outputs output synchronization signals HSYNC and VSYNC in response to reading of each packet. The output synchronization signal HSYNC indicates the start timing of each line, and the output synchronization signal VSYNC indicates the start timing of each page.

FIG. 9 shows the input synchronization signal HV when no error occurs, the output synchronization signals DE and HSYNC generated by the transmission device g1, and the output synchronization signals HV and IND generated by the reception device g2.
As shown in FIG. 9, the output synchronization signal DE is delayed by one line from the input synchronization signal HV. When the input synchronization signal HV is in the assertion period of the mth line, the output synchronization signal DE is in the assertion period of each packet of the (m-1) th line. The start timing of each line indicated by the output synchronization signal HSYNC is synchronized with the input synchronization signal HV as shown in FIG. 9 if no error occurs.
The output synchronization signals HV and IND on the reception side are generated according to the output synchronization signal HSYNC on the transmission side, and the start timing of each line is synchronized between the reception side and the transmission side as shown in FIG. Can do.

When the packet is retransmitted, the reading control unit 13 reads not only one line including the packet to be retransmitted but also the next line as well as the assertion period of the line indicated by the input synchronization signal HV as shown in FIG. The negation period t1 is also used.
As shown in FIG. 10, if the reading of one line including the packet to be retransmitted can be completed by the start timing of the next line indicated by the input synchronization signal HV, the original line cycle is not shifted, and the receiving side and the transmitting side Thus, error correction can be performed while maintaining line synchronization.

When there are many packets to be retransmitted and reading of one line including the packet to be retransmitted cannot be completed by the start timing of the next line, as shown in FIG. 11, the end timing of one line is determined by the input synchronization signal HV. The start timing of the next line shown is exceeded. In this case, as shown in FIG. 11, the read control unit 13 delays the start timing of the next line of the output synchronization signal HSYNC after the end timing of one line, for example, after a predetermined period t2.
On the receiving side, as shown in FIG. 11, the output synchronizing signal HV is generated in accordance with the start timing indicated by the output synchronizing signal HSYNC. Therefore, even if a deviation occurs in the original line period due to retransmission of the packet, the receiving side Synchronization can be maintained.

When delaying the start timing of the next line of the output synchronization signal HSYNC, the read control unit 13 determines that the input synchronization signal HV is not changed until the start timing of each subsequent line coincides with the input synchronization signal HV as shown in FIG. The negation period t1 between the lines shown is shortened, and the start timing of reading each line is advanced.
As a result, the line period shifted due to the retransmission of the packet can be matched with the original line period indicated by the input synchronization signal HV.

  The read control unit 13 outputs the output synchronization signal DE to the CRC generation unit 141 of the detection data adding unit 14.

The detection data adding unit 14 includes four sets of CRC generation units 141 and selectors 142 for each color of C, M, Y, and K. Each color packet output from the line buffer 11 is input to the CRC generation unit 141 for each color.
The CRC generation unit 141 outputs the packet output from the line buffer 11 to the selector 142 in synchronization with the synchronization signal DE. In addition, the CRC generation unit 141 generates a CRC code from the packet and outputs the CRC code to the selector 142. The CRC code is error detection data and is the remainder when the bit string of the packet is divided by a predetermined generator polynomial.

  The selector 142 outputs the packet output from the detection data adding unit 14 while the 0 enable signal is input from the read control unit 13. The selector 142 outputs a CRC code when the enable signal from the read control unit 13 is switched from 0 to 1. As a result, the CRC code is added to the image data of 128 pixels, and a packet of apparently 129 pixels is output.

FIG. 12 is a configuration diagram of the reception processing unit 202.
As shown in FIG. 12, the reception processing unit 202 includes an error detection unit 21, a line buffer 22, a write control unit 23, and a read control unit 24.

  The error detection unit 21 includes a counter 211, a CRC generation unit 212, a comparator 213, and an OR circuit 214. Four sets of CRC generators 212 and comparators 213 are provided for each color of C, M, Y, and K. Each color packet received from the transmission device g1 is input to the CRC generation unit 212 corresponding to each color.

  The counter 211 starts counting from 0 when the output synchronization signal DE is asserted, and resets the count value to 0 when the output synchronization signal DE is negated. As a result, count values of 0 to 130 are sequentially output to the comparator 213.

When the output synchronization signal DE is in the assert period, the CRC generation unit 212 outputs the packet received from the transmission device g1 to the comparator 213.
The CRC generation unit 212 generates a CRC code from the image data of 128 pixels from the beginning of the received packet, and outputs the CRC code to the comparator 213.

When the count value of the counter 211 is from 0 to 127, image data of 128 pixels from the beginning of the received packet is input from the CRC generation unit 212 to the comparator 213. The comparator 213 outputs the image data to the line buffer 22.
When the count value of the counter 211 is 128, the CRC code added to the 128-pixel image data is input from the CRC generation unit 212 to the comparator 213. The comparator 213 compares the CRC code with the CRC code generated and input by the CRC generation unit 212, and outputs a comparison result indicating match or mismatch to the OR circuit 214.
When an unmatched comparison result is input from any of the four comparators 213, the OR circuit 214 outputs a comparison result indicating mismatch to the write control unit 23.

The line buffer 22 is a memory that can hold one line of image data.
When the enable signal WE and the write address WADRS are input from the write control unit 23, the line buffer 22 is sequentially input in units of 128 pixel packets from the error detection unit 21 in association with the write address WADRS. Holds image data.
When the enable signal RE and the read address RADRS are input from the read control unit 24, the line buffer 11 outputs one line of image data corresponding to the read address RADRS.

  When an error is detected, image data having the same write address WADRS as the previously held image data is input by retransmission of the packet, but the line buffer 22 is input later with the same write address WADRS. Overwrite and save the image data.

When the output synchronization signal DE received from the transmission device g1 is in the assert period, the write control unit 23 outputs the enable signal WE to the line buffer 22 and permits writing to the line buffer 22.
Further, the write control unit 23 outputs the write address WADRS to the line buffer 22 and writes the received image data in units of packets in the line buffer 22.

This write address WADRS is combined with the address of the packet in the upper bits and the address of the pixels in the packet in the lower bits, similar to the read address RADRS used by the read controller 13 of the transmitter g1 when reading the packet. Bit string.
Thus, it is possible to configure the write address WADRS that matches the read address RADRS of 0 to 7999 used by the read control unit 24 at the time of reading.
The write control unit 23 includes the same counters Ev, Od, and C as the read control unit 13, and uses the count values of the two counters Ev and Od as packet addresses and the count value of the counter C as pixel addresses in the packet. . Since the counting operations of the counters Ev, Od, and C are as described above, description thereof is omitted here.

  The write control unit 23 writes a packet in parallel with detection of an error in the previous packet. Since an error is detected by a CRC code added to the end of the packet, if an error has occurred, a mismatch comparison result is input from the error detection unit 21 during writing of the packet. When the write control unit 23 transmits a retransmission request signal RETRY to the transmission device g1, the previous packet in which an error is detected is retransmitted from the transmission device g1. The write controller 23 writes the retransmitted previous packet to the line buffer 22 after the packet being written.

At this time, the write control unit 23 returns the address of the packet at the time of writing to the previous one and writes the retransmitted one previous packet. Although the order in which packets are transferred by resending varies, the writing control unit 23 can write the packets in the correct order by performing the same address control as the reading control unit 13 of the transmission device g1.
Specifically, the writing control unit 23 outputs an error flag signal EF and a flag count signal EFCnt in response to the transmission of the retransmission request signal RETRY, and controls the counting operation of the two counters Ev and Od to provide one. Get the address of the previous packet. The control method of the count operation is the same as that of the above-described read control unit 13 and is as described above, and thus detailed description thereof is omitted here.

  The read control unit 24 reads and connects the packets written in the line buffer 22 in synchronization with the received output synchronization signals HSYNC and VSYNC, and outputs image data in units of one line. Specifically, when either the output synchronization signal HSYNC or VSYNC is asserted, the read control unit 24 sequentially outputs the count values 0 to 7999 of the counter that repeatedly counts 0 to 7999 as the read address RADRS.

The read control unit 24 generates output synchronization signals HV, VV, and IND from the received output synchronization signals HSYNC and VSYNC.
Specifically, the read control unit 24 sets an assertion period from when the output synchronization signal HSYNC is asserted to when the counter counts 0 to 7999, and after the count ends, until the output synchronization signal HSYNC is asserted next time. An input synchronization signal HV is generated with a negation period as.
Further, the reading control unit 24 starts the reading of the first line of one page and continues to the assertion period until the reading of all the lines of one page is completed, and until the reading of the first line of the next page is started. Is generated as a negation period.
Further, the read control unit 24 outputs the output synchronization signal HSYNC as the output synchronization signal IND.

  In the image data transfer system G, a processing procedure when image data is transferred from the transmission device g1 to the reception device g2 will be described.

The transmission device g1 packetizes the image data D to be transferred line by line by the transmission processing unit 102, and adds error detection data to each packet.
First, the writing control unit 12 inputs one line of image data in synchronization with the input synchronization signals HV, VV, and IND, and writes the image data in the line buffer 11.
The read control unit 13 reads one line of image data from the line buffer 11 in units of packets. Further, the read control unit 13 generates and outputs output synchronization signals DE, HSYNC, and VSYNC in response to reading of each packet.
The detection data adding unit 14 adds error detection data to the image data read from the line buffer 11 in units of packets and outputs the data.

The transmission device g1 converts each packet to which the error detection data is added into serial data by the serial conversion unit 103, and scrambles and transmits the serial data.
The reception device g2 converts each packet transmitted from the transmission device g1 into parallel data by the parallel conversion unit 201, and then performs a descrambling process.

The reception device g2 connects the packets descrambled by the reception processing unit 202 and outputs one line of image data.
First, the error detection unit 21 detects an error of each packet that has been descrambled.
Further, the write control unit 23 writes each packet in the line buffer 22 in synchronization with the output synchronization signals DE, HSYNC, and VSYNC.
When no error is detected and there is no error correction, the read control unit 24 reads and connects the packets written in the line buffer 22 in synchronization with the output synchronization signal HSYNC and outputs one line of image data.

If an error is detected and there is error correction, an error in the previous packet is detected while the write control unit 23 is writing the packet, so the write control unit 23 transmits a retransmission request signal RETRY. Send to g1.
Assuming that the address of the packet being written by the write control unit 23 is n, in the transmission device g1, the read control unit 13 receives the retransmission request signal RETRY while reading the packet at the address n, and the previous packet Are read from the line buffer 11. As a result, the previous packet (packet address n−1) in which an error was detected is retransmitted to the receiving device g2.

  In the receiving device g2, the write control unit 23 overwrites the line buffer 11 with the packet (address n-1 of the previous packet) retransmitted next to the packet being written (address n of the packet). Correct the error. The read controller 24 reads out the packets written in the line buffer 22 and outputs one line of image data.

  As described above, according to the present embodiment, the image data transfer system G includes the transmission device g1 that transmits image data and the reception device g2 that receives the image data. The transmission device g1 synchronizes with the line buffer 11, the input synchronization signals HV, VV, and IND, the write control unit 12 that writes image data to the line buffer 11 in units of one line, and the image that is written to the line buffer 11. The data is read in units of packets smaller than one line, and the output control signals DE, HSYNC, and VSYNC are generated and transmitted to the receiving device g2, and error detection data is sent to each read packet. In addition, a detection data adding unit 14 for transmitting to the receiving device g2 is provided. The receiving device g2 detects an error of each packet received from the transmitting device g1, using the error detection data added to each packet, a line buffer 22, and each received packet. The write controller 23 that writes to the line buffer 22 in synchronization with the received output synchronization signal DE, and each packet written to the line buffer 22 in synchronization with the output synchronization signals HSYNC and VSYNC received from the transmitter g1. And a readout control unit 24 that outputs the image data in units of one line. When the error detection unit 21 detects a packet error, the write control unit 23 of the reception device g2 transmits a retransmission request signal to the transmission device g1, and writes the retransmitted packet from the transmission device g1 to the line buffer 22. Correct the error. In response to the retransmission request signal, the read control unit 13 of the transmission device g1 reads the packet in which the error is detected from the line buffer 11, and the detection data adding unit 14 adds the error detection data to the read packet. And retransmits to the receiving device g2.

  Thus, even if an error occurs, it can be retransmitted in units of packets smaller than one line and error correction can be performed, and the error correction can be accurately performed while suppressing a decrease in the transfer rate of image data. Also, even when a packet is retransmitted, line synchronization can be performed with an output synchronization signal, and the order of packets on one line can be maintained by address control. Therefore, error correction can be performed while maintaining line synchronization in the transfer of image data.

The above embodiment is a preferred example of the present invention, and the present invention is not limited to this. Modifications can be made as appropriate without departing from the spirit of the present invention.
For example, in the above-described embodiment, the example of the counters Ev, Od, and C that counts up in order to output the ascending write addresses WADRS and RADRS has been described. , RADRS can also be output.

Further, the line buffers 11 and 22 may be memories that can hold image data of a plurality of lines instead of one line.
When one line is divided into N packets, if there is a memory for one line, errors can be corrected up to N errors that occur during the assertion period of one line. Therefore, if the memory can hold k lines of image data, k × N error corrections are possible.

  Further, the image data to be transferred can be compressed image data. The compressed image data may not be restored due to an error, and the influence of the error is large. It is preferable to transfer the image data compressed by the image data transfer system G because the compressed image data can be accurately error-corrected.

  Further, the read control unit 13 and the write control unit 23 perform address control to return to the address of the previous packet so that the packet is retransmitted immediately after an error is detected. There is no particular limitation on how many addresses the address is returned to. For example, the read control unit 13 and the write control unit 23 may perform address control so as to return to the address of the previous packet.

  In addition, once an error occurs, errors may occur continuously, and the transfer rate may decrease due to multiple retransmissions of packets. Therefore, after an error occurs, the read control unit 13 may further divide one packet and read it in units smaller than one packet. As a result, the data size to be retransmitted can be reduced, and a decrease in transfer rate can be suppressed.

G image data transfer system g1 transmission device 102 transmission processing unit 11 line buffer 12 write control unit 13 read control unit Ev counter Od counter C counter 14 detection data addition unit 103 serial conversion unit g2 reception device 201 parallel conversion unit 202 reception processing Unit 21 Error detection unit 22 Line buffer 23 Write control unit Ev Counter Od Counter C Counter 24 Read control unit

Claims (10)

A transmission device that transmits image data, and a reception device that receives the image data;
The transmitter is
A line buffer;
A write controller that outputs a write address to the line buffer in synchronization with an input synchronization signal and writes image data to the line buffer in units of one line;
A read control unit that outputs a read address to the line buffer, reads the written image data in units of packets smaller than one line, and generates an output synchronization signal;
A detection data adding unit for adding error detection data to each read packet, and transmitting each packet together with an output synchronization signal;
The receiving device is:
An error detection unit that detects an error of each packet received from the transmission device using error detection data attached to each packet;
A line buffer;
A write control unit that outputs a write address to the line buffer in synchronization with the output synchronization signal received from the transmitter, and writes each received packet to the line buffer;
A read control unit that outputs a read address to the line buffer in synchronization with the received output synchronization signal, concatenates and reads the written packets, and outputs image data in units of one line;
When a packet error is detected by the error detector, the write controller of the receiver transmits a retransmission request signal to the transmitter, returns the write address, and is retransmitted from the transmitter To the line buffer, error correction,
In response to the retransmission request signal, the reading control unit of the transmitting device returns the reading address and reads the packet in which the error is detected from the line buffer and retransmits the packet.
Image data transfer system. When retransmitting a packet, the reading control unit of the transmitting apparatus uses an assertion period of one line indicated by the input synchronization signal and a negation period until the next line for reading one line including the packet to be retransmitted. ,
The image data transfer system according to claim 1. When the end timing of one line including the packet to be retransmitted exceeds the start timing of the next line indicated by the input synchronization signal, the reading control unit of the transmission device may receive the next of the output synchronization signal after the end timing. Delay the start of the line,
The image data transfer system according to claim 1 or 2. When the read control unit of the transmission device delays the start timing of the next line of the output synchronization signal, each line indicated by the input synchronization signal until the start timing of each subsequent line coincides with the input synchronization signal. Shorten the negation period between them, and advance the timing to read each line,
The image data transfer system according to claim 3. The reading control unit of the transmitting apparatus performs the reading of the packet in parallel with the detection of the error of the previous packet, and when an error is detected in the previous packet and a retransmission request signal is received, Next to the packet, read the previous packet in which an error was detected,
The write control unit of the receiving device performs packet writing in parallel with detection of an error of the previous packet, and transmits the retransmission request signal when an error is detected in the previous packet, Next to the packet being written, the previous packet retransmitted from the transmitter is written.
The image data transfer system according to any one of claims 1 to 4. The read address and the write address are a bit string obtained by combining the address of the packet in the upper bits and the address of the pixels in the packet in the lower bits,
The reading control unit of the transmitting device returns the address of the packet to the previous one, reads the previous packet in which the error was detected,
The write control unit of the receiving device writes the retransmitted previous packet by returning the address of the packet to the previous one,
The image data transfer system according to claim 5. The reading control unit of the transmitting device and the writing control unit of the receiving device include two counters that alternately count each time a packet is transmitted, and use the count value by the two counters as the address of the packet,
The two counters are
If no error is detected, each counter counts against the count value of the other counter,
If an error is detected once or an odd number of times consecutively, the counter that counts immediately after detection stops counting and maintains the count value, and the next counter that counts counts against its own count value,
If an error is detected a number of times consecutively, the counter that counts immediately after detection stops counting and maintains the count value, and the next counter that counts counts against the count value of the other counter.
The image data transfer system according to claim 6. The transmission device includes a serial conversion unit that converts the packet into serial data, scrambles and transmits the data,
The receiving device includes a parallel conversion unit that descrambles the received packet and converts the packet into parallel data.
The image data transfer system according to claim 1. The reading control unit of the transmitting device makes the interval between the packets to be read longer than the time required for resetting the scramble process,
The image data transfer system according to claim 8. The image data is compressed image data.
The image data transfer system according to claim 1.

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