JP2014123622A - Semiconductor package and semiconductor package manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package which can easily route wiring in a plane direction.SOLUTION: A semiconductor package 1 comprises: a plurality of wiring patterns 20 formed on the same plane; an insulation layer 30 for insulating the wiring patterns 20 from each other and making the wiring patterns 20 adhere to each other; and semiconductor elements 50 mounted on a lower surface side of the wiring patterns 20. The semiconductor package 1 further comprises: semiconductor elements 70 mounted on an upper surface side of the wiring patterns 20; and an insulation layer 60 which is formed on an undersurface of the insulation layer 30 and covers a whole of the semiconductor elements 50. The semiconductor element 50 and the semiconductor element 70 are linearly connected with each other at a position where at least a part of the semiconductor element 50 and at least a part of the semiconductor element 70 overlap each other in planar view via the common wiring pattern 20.

Description

  The present invention relates to a semiconductor package and a method for manufacturing the semiconductor package.

  In recent years, along with demands for downsizing and higher functionality of electronic devices, semiconductor elements (chips) such as ICs and LSIs used therein have been highly integrated and increased in capacity. Further, a package for mounting a semiconductor element is also required to be downsized (thinned), multi-pin, and high in density. Therefore, in order to meet such a demand, a system in package (SiP) in which a plurality of semiconductor elements are mounted on one substrate has been put into practical use. In particular, SiP using a three-dimensional mounting technique in which a plurality of semiconductor elements are three-dimensionally stacked, so-called chip stacked package, can be highly integrated and can reduce the wiring length. Therefore, it is widely used because it has the advantage that the circuit operation speed can be increased and the floating capacitance of the wiring can be reduced.

  As a three-dimensional mounting technique for manufacturing this type of chip stacked package, a plurality of semiconductor elements on which through electrodes are formed are stacked on a substrate, and the through electrodes and the micro bumps formed on the through electrodes are stacked. Thus, a technique for electrically connecting semiconductor elements has been proposed (see, for example, Patent Document 1).

  Further, Patent Documents 2 and 3 are known as prior arts related to the above prior art.

JP 2006-179562 A JP 2011-129717 A JP 2007-173570 A

  By the way, in the chip stacked package, it is necessary to secure a power supply path and an external connection I / O path. However, when the semiconductor elements are directly connected to each other by the through electrodes and the micro bumps, it is difficult to draw the wiring connected to the semiconductor elements to the outside from the stacked position of the semiconductor elements. It is difficult.

  According to one aspect of the present invention, a plurality of wiring patterns formed on the same plane, a first insulating layer that insulates the wiring patterns and adheres the wiring patterns, and a lower surface side of the wiring pattern A mounted first electronic component; a second electronic component mounted on the upper surface side of the wiring pattern; and a second insulating layer formed on the lower surface of the first insulating layer and covering the entire first electronic component; , And at least a part of the first electronic component and the second electronic component are linearly connected at a position overlapping in plan view via the common wiring pattern.

  According to one aspect of the present invention, there is an effect that the wiring can be easily routed in the plane direction.

(A) is a schematic sectional drawing which shows the semiconductor package of 1st Embodiment, (b) is an expanded sectional view which expanded a part of semiconductor package shown in (a). The schematic perspective view of a board | substrate. 1 is a schematic plan view showing a semiconductor package of a first embodiment. (A)-(d) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 1st Embodiment. (A)-(d) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 1st Embodiment. (A)-(c) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 1st Embodiment. (A)-(c) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 1st Embodiment. (A) is a schematic sectional drawing which shows the semiconductor package of a modification, (b) is a schematic plan view which shows the semiconductor package of a modification. (A) is a schematic sectional drawing which shows the semiconductor package of 2nd Embodiment, (b) is an expanded sectional view which expanded a part of semiconductor package shown to (a). (A)-(e) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 2nd Embodiment. (A)-(c) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 2nd Embodiment. (A)-(d) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 3rd Embodiment. (A)-(c) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 3rd Embodiment. (A) is a schematic sectional drawing which shows the semiconductor package of 4th Embodiment, (b) is an expanded sectional view which expanded a part of semiconductor package shown in (a). (A), (c), (d) is schematic sectional drawing which shows the manufacturing method of the semiconductor package of 4th Embodiment, (b) is the enlarged plan view which expanded a part of semiconductor package shown to (a). . (A) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 4th Embodiment, (b), (c) is the enlarged plan view which expanded a part of semiconductor package shown to (a). Note that (b) is a plan view of the semiconductor package shown in (a) as viewed from below, and (c) is a plan view of the semiconductor package as shown in (a) from above. (A), (c) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 4th Embodiment, (b) is the enlarged plan view which expanded a part of semiconductor package shown to (a). (A)-(c) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 4th Embodiment. (A) is a schematic sectional drawing which shows the semiconductor package of 5th Embodiment, (b) is an expanded sectional view which expanded a part of semiconductor package shown in (a). (A)-(e) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 5th Embodiment. (A)-(c) is a schematic sectional drawing which shows the manufacturing method of the semiconductor package of 5th Embodiment. The schematic sectional drawing which shows the semiconductor package of a modification.

  Hereinafter, each embodiment will be described with reference to the accompanying drawings. In the accompanying drawings, in order to make the features easy to understand, the portions that become the features may be shown in an enlarged manner for the sake of convenience, and the dimensional ratios and the like of the respective components are not always the same as the actual ones. In the cross-sectional view, hatching of some members is omitted in order to make the cross-sectional structure of each member easy to understand.

(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS.
As shown in FIG. 1A, the semiconductor package 1 includes a wiring board 10, a semiconductor element 70, and an underfill resin 75. The wiring substrate 10 includes a wiring pattern 20, an insulating layer 30, a substrate 40, a semiconductor element 50, conductor wires 55, 56, 57, an insulating layer 60, and a solder resist layer 65. The wiring substrate 10 is a substrate in which a semiconductor element 50 is built in a housing portion A1 formed by the wiring pattern 20, the insulating layer 30, and the substrate 40.

  Many wiring patterns 20 are formed on the same plane. In a part of the pattern of the wiring pattern 20, a protruding portion 25 that protrudes from the lower surface of the wiring pattern 20 to the insulating layer 60 side (here, the lower side) is formed. For example, the protruding portion 25 is formed on the wiring pattern 20 at a portion to which the connection terminal 51 of the semiconductor element 50 is connected. The protrusion 25 is formed on the wiring pattern 20 where the conductor wires 55, 56, 57 are connected. Further, the wiring pattern 20 has a wiring pattern 21 formed in a frame shape on the peripheral edge of the semiconductor package 1. A frame-like protrusion 25 </ b> A is formed on the lower surface of the wiring pattern 21. Each protrusion 25 and protrusion 25A are formed, for example, in a substantially rectangular shape in cross section.

  The insulating layer 30 is formed so as to cover the side surface of the wiring pattern 20 and the side surfaces of the protrusions 25 and 25A. The insulating layer 30 has a function of electrically insulating the wiring patterns 20 and a function of bonding the wiring patterns 20 together. That is, many wiring patterns 20 are supported by the insulating layer 30. The insulating layer 30 of this example is formed so that the lower surface thereof is flush with the lower surfaces of the protrusions 25 and 25A. Note that the protrusions 25 and 25 </ b> A may be formed such that the lower surface protrudes downward from the lower surface of the insulating layer 30. As a material of the insulating layer 30, for example, an organic resin such as an epoxy resin or a polyimide resin can be used.

  Further, a part of the pattern of the wiring pattern 20 has a protruding portion 26 that protrudes from the upper surface of the insulating layer 30 to the side opposite to the insulating layer 60 (here, the upper side). For example, the wiring pattern 20 at a portion to which the connection terminal 71 of the semiconductor element 70 is connected has the protruding portion 26. Each projecting portion 26 is formed in, for example, a substantially semicircular shape in a sectional view or a trapezoidal shape in a sectional view.

  Here, as an example of the wiring pattern 20 and the protruding portion 26, a metal layer in which a copper (Cu) layer / nickel (Ni) layer / gold (Au) layer is sequentially laminated from the lower surface side of the wiring pattern 20 can be exemplified. . Further, as an example of the wiring pattern 20 and the protruding portion 26, a metal layer in which Cu layer / Ni layer / palladium (Pd) layer / Au layer is laminated in order from the lower surface side of the wiring pattern 20, Cu layer / Ni layer / Pd Examples thereof include a metal layer in which layers / silver (Ag) layers are sequentially laminated, and a metal layer in which Cu layers / Ni layers / Pd layers / Ag layers / Au layers are sequentially laminated. Here, the Cu layer is a metal layer made of Cu or Cu alloy, the Ni layer is a metal layer made of Ni or Ni alloy, the Au layer is a metal layer made of Au or Au alloy, and the Pd layer is Pd or Pd alloy. The above-mentioned Ag layer is a metal layer made of Ag or an Ag alloy. Thus, as the wiring pattern 20 and the protruding portion 26, a metal layer in which the Au layer or the Ag layer is exposed from the insulating layer 30 can be used. Moreover, as a material of the projection part 25, copper and a copper alloy can be used, for example.

  As shown in FIG. 1B, the substrate 40 is bonded to the lower surface of the frame-shaped protrusion 25 </ b> A formed in the outer peripheral region of the semiconductor package 1. For example, the substrate 40 is bonded to the lower surface of the protrusion 25A with an adhesive (not shown). The substrate 40 is a multilayer wiring substrate in which a plurality of wiring layers and a plurality of interlayer insulating layers are alternately stacked. In the substrate 40 of this example, three wiring layers 41, 42, 43 and three interlayer insulating layers 44, 45, 46 are alternately stacked, and vias provided in the interlayer insulating layers 44, 45, 46, respectively. The wiring layers 41, 42, 43 and the protrusion 25A are electrically connected by 47, 48, 49. In addition, as a material of the wiring layers 41, 42, 43 and the vias 47, 48, 49, for example, copper or a copper alloy can be used. As a material of the interlayer insulating layers 44, 45, 46, for example, an organic resin such as an epoxy resin or a polyimide resin can be used. Further, as a material for the interlayer insulating layers 44, 45, 46, an epoxy or polyimide thermosetting resin is impregnated into a reinforcing material such as glass, aramid, LCP (Liquid Crystal Polymer) fiber woven fabric or nonwoven fabric. An insulating resin containing a reinforcing material can also be used.

  As shown in FIG. 2, the substrate 40 has a hollow portion B formed in the center thereof, and is formed in a frame shape. Specifically, a hollow portion B having a plurality of steps on the side surface is formed in the central portion of the substrate 40.

  More specifically, as shown in FIG. 1B, an interlayer insulating layer 44 having an opening B1 is formed on the lower surface of the protrusion 25A. The upper surface of the interlayer insulating layer 44 is formed smaller than the lower surface of the protrusion 25A. The entire upper surface of the interlayer insulating layer 44 is covered with the frame-shaped protrusion 25A. Note that the lower surface of the protrusion 25 </ b> A formed inside the interlayer insulating layer 44 is exposed in a frame shape from the opening B <b> 1 of the interlayer insulating layer 44.

  On the lower surface of the interlayer insulating layer 44, a wiring layer 41 in which a connection pad P1 is disposed in the vicinity of the opening B1 is formed. The protrusion 25A and the wiring layer 41 are electrically connected by a via 47 penetrating the interlayer insulating layer 44 in the thickness direction.

  An interlayer insulating layer 45 is formed on the lower surface of the wiring layer 41. The interlayer insulating layer 45 is formed with an opening B2 having a larger opening diameter than the opening B1 so that the connection pad P1 protrudes inward. Therefore, the lower surface of the interlayer insulating layer 44 formed in the vicinity of the opening B1 is exposed in a frame shape from the opening B2 of the lower interlayer insulating layer 45. The connection pad P1 is disposed on the lower surface of the interlayer insulating layer 44 exposed in the frame shape.

  Further, on the lower surface of the interlayer insulating layer 45, a wiring layer 42 in which a connection pad P2 is disposed in the vicinity of the opening B2 is formed. The wiring layer 41 and the wiring layer 42 are electrically connected by a via 48 that penetrates the interlayer insulating layer 45 in the thickness direction.

  An interlayer insulating layer 46 is formed on the lower surface of the wiring layer 42. The interlayer insulating layer 46 is formed with an opening B3 having a larger opening diameter than the opening B2 so that the connection pad P2 protrudes inward. Therefore, the lower surface of the interlayer insulating layer 45 formed in the vicinity of the opening B2 is exposed in a frame shape from the opening B3 of the lower interlayer insulating layer 46. The connection pad P2 is disposed on the lower surface of the interlayer insulating layer 45 exposed in the frame shape.

  An outermost layer (here, the lowermost layer) wiring layer 43 is formed on the lower surface of the interlayer insulating layer 46 as the outermost layer (here, the lowermost layer). The wiring layer 42 and the wiring layer 43 are electrically connected by a via 49 that penetrates the interlayer insulating layer 46 in the thickness direction.

  Thus, the cavity B having a stepped step on the side surface is formed at the center of the substrate 40. Specifically, the inner surface of the cavity B includes the inner surface of the interlayer insulating layer 44 (wiring layer 41), the lower surface of the interlayer insulating layer 44 (wiring layer 41), and the inner surface of the interlayer insulating layer 45 (wiring layer 42). A side surface, a lower surface of the interlayer insulating layer 45 (wiring layer 42), an inner surface of the interlayer insulating layer 46, and a lower surface of the interlayer insulating layer 46 are formed in a step shape.

The open end of the cavity B on the upper surface side (opening B1 side) of the interlayer insulating layer 44 is closed by the protrusion 25 and the insulating layer 30.
The required number (here, two) of the accommodating portions A1 surrounded by the cavity B of the substrate 40 (specifically, the inner surface of the cavity B of the substrate 40), the protrusions 25 and 25A, and the insulating layer. The semiconductor element is accommodated. Specifically, the semiconductor element 50 is accommodated in the accommodating portion A1 with the connection terminal 51 disposed on the circuit formation surface (here, the upper surface) facing upward (projecting portion 25 side). . Each semiconductor element 50 is connected to the protrusion 25. For example, each semiconductor element 50 is flip-chip mounted on the wiring pattern 20. That is, the semiconductor element 50 is bonded face-down to the wiring pattern 20 by bonding the connection terminals 51 of the semiconductor element 50 to the protrusions 25 formed on the lower surface of the wiring pattern 20. The semiconductor element 50 is electrically connected to the wiring pattern 20 via the connection terminal 51 and the protrusion 25. Here, a part of the wiring pattern 20 connected to the connection terminal 51 through the protrusion 25 is routed in a plane direction orthogonal to the thickness direction of the wiring substrate 10 in a cross-sectional view, and the routed destination Are connected to the connection pads P1 and P2 of the substrate 40 through the protrusions 25 and the conductor wires 57, for example.

  As the semiconductor element 50, for example, a memory chip such as a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, or a flash memory chip can be used. For example, solder bumps or Au bumps can be used as the connection terminals 51. As a material for the solder bump, for example, an alloy containing lead (Pb), an alloy of tin (Sn) and Au, an alloy of Sn and Cu, an alloy of Sn and Ag, or an alloy of Sn, Ag, and Cu can be used.

  In the cavity B of the substrate 40, a conductor wire 55 that connects the predetermined protrusions 25 to each other is provided. The predetermined wiring patterns 20 are electrically connected to each other by the conductor wire 55. In other words, the predetermined wiring patterns 20 are electrically connected three-dimensionally (three-dimensionally) by the conductor wires 55. The hollow portion B is provided with a conductor wire 56 that connects the predetermined protruding portion 25 and the protruding portion 25A. The predetermined wiring pattern 20 and the wiring pattern 21 are electrically connected by the conductor wire 56. Further, the hollow portion B is provided with a conductor wire 57 that connects the predetermined protruding portion 25 and the connection pads P1, P2 of the substrate 40. With this conductor wire 57, the predetermined wiring pattern 20 and the wiring layers 41 and 42 of the substrate 40 are electrically connected. As the material of the conductor wires 55, 56, and 57, a material that can be bent three-dimensionally can be used. For example, as the conductor wires 55, 56, and 57, a Cu wire, an Au wire, or an aluminum (Al) wire can be used.

  The insulating layer 60 is formed so as to fill the cavity B (specifically, the openings B1, B2, B3). The insulating layer 60 covers the inner surface of the substrate 40 (the side surface of the cavity B), the protrusion 25 exposed from the substrate 40 and the lower surface of the insulating layer 30, the entire semiconductor element 50, and the conductor wires 55, 56, and 57. Is formed. The insulating layer 60 is an insulating layer having a lower elastic modulus than the insulating layer 30. That is, the insulating layer 60 is made of a low elastic material having a lower elastic modulus than the organic resin that forms the insulating layer 30. As this low elastic material, for example, a material having a Young's modulus in the vicinity of room temperature (20 to 30 ° C.) of 1 MPa to 10 MPa is preferable. As such a low elastic material, for example, a silicone-based, fluorine-based, polyolefin-based or urethane-based elastomer can be used.

  The solder resist layer 65 is formed so as to cover a part of the upper surface of the wiring pattern 20 and a part of the upper surface of the insulating layer 30. In the solder resist layer 65, an opening 65X is formed at a position corresponding to a chip mounting region where a required number (here, two) of semiconductor elements 70 are mounted. In the solder resist layer 65 of this example, as shown in FIG. 3, an opening 65X having a substantially rectangular shape in plan view is formed at the center.

  As shown in FIG. 1A, a required number (here, two) of semiconductor elements 70 are mounted on the wiring board 10 having the above-described structure. Specifically, the semiconductor element 70 is flip-chip mounted on the chip mounting region of the wiring board 10. That is, by connecting the connection terminal 71 disposed on the circuit formation surface (here, the lower surface) of the semiconductor element 70 to the protruding portion 26 formed on the wiring pattern 20, the semiconductor element 70 is attached to the wiring substrate 10. Joined face down. The semiconductor element 70 is electrically connected to the wiring pattern 20 via the connection terminals 71 and the protrusions 26.

  Here, as shown in FIG. 1B, a required number (two in FIG. 1) of connection terminals 71A among the connection terminals 71 are built in the wiring board 10 (arranged in the insulating layer 60). ) The connection terminal 51 of the semiconductor element 50 and the wiring pattern 20 are shared. Specifically, the connection terminal 71 </ b> A is conductively connected in a uniaxial manner with the connection terminal 51 disposed so as to face the wiring pattern 20. “Conductively connected uniaxially” means a conductor formed in the thickness direction of the wiring board 10 (here, without routing the wiring pattern 20 or the like in a plane direction orthogonal to the thickness direction in a cross-sectional view) The connection is made by the wiring pattern 20 and the protrusions 25 and 26). That is, the connection terminal 71 </ b> A is linearly connected at the same plane coordinates (positions overlapping in plan view) as the predetermined connection terminal 51. Thereby, the connection terminals 51 and 71A of the semiconductor elements 50 and 70 can be connected with the shortest distance. Although not shown in detail, the wiring pattern 20 connected to the required number of connection terminals 71B among the connection terminals 71 via the protrusions 26 is routed in the planar direction, and the routed end is connected to the wiring pattern 20. The part is connected to the connection terminal 51 of the semiconductor element 50 or connected to the connection pads P <b> 1 and P <b> 2 of the substrate 40.

  Further, the two semiconductor elements 70 are electrically connected to each other by a conductor wire 55 provided in the insulating layer 60. More specifically, the required number (here, two) of connection terminals 71C among the connection terminals 71 are electrically connected to the protrusions 25 via the protrusions 26 and the wiring patterns 20. The protrusion 25 is connected to the conductor wire 55, and is electrically connected to the protrusion 25 that is electrically connected to the connection terminal 71 </ b> C of the other semiconductor element 70 via the conductor wire 55. . That is, the connection terminal 71 </ b> C of one semiconductor element 70 is electrically connected to the protrusion 25 via the protrusion 26, the wiring pattern 20 (first wiring pattern), the protrusion 25, and the conductor wire 55. Is connected to the connection terminal 71 </ b> C of the other semiconductor element 70 through the wiring pattern 20 (second wiring pattern) and the protrusion 26. As described above, the two semiconductor elements 70 are electrically connected three-dimensionally (three-dimensionally) by the conductor wires 55 provided in the insulating layer 60. Note that the wiring pattern 20 connected to the connection terminal 71C of one semiconductor element 70 via the protrusion 26 is routed in the plane direction, and the end portion of the wiring pattern 20 is connected to the other semiconductor element 70 via the protrusion 26. You may make it connect to the connection terminal 71C.

  As shown in FIG. 3, each semiconductor element 50 and each semiconductor element 70 are formed in a substantially rectangular shape in plan view. The two semiconductor elements 70 are arranged side by side along the left-right direction in the drawing. Each semiconductor element 50 built in the wiring board 10 is arranged so that a part thereof overlaps a part of the corresponding semiconductor element 70 in plan view. That is, each semiconductor element 50 and each semiconductor element 70 are arranged so that only a part thereof overlaps in plan view. At this time, the two semiconductor elements 50 are arranged such that the distance between one semiconductor element 50 and the other semiconductor element 50 is longer than the distance between one semiconductor element 70 and the other semiconductor element 70. These are arranged side by side along the horizontal direction in the figure.

  As the semiconductor element 70, for example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used. Further, as the connection terminal 71, for example, a solder bump or an Au bump can be used in the same manner as the connection terminal 51.

  As shown in FIG. 1A, the underfill resin 75 is provided so as to fill a gap between the upper surface of the wiring substrate 10 and the lower surface of the semiconductor element 70. The underfill resin 75 improves the connection strength of the connection portion between the connection terminal 71 and the protrusion 26, suppresses the corrosion of the wiring pattern 20 and the occurrence of electromigration, and prevents the reliability of the wiring pattern 20 from being lowered. It is resin for. In addition, as a material of the underfill resin 75, for example, an insulating resin such as an epoxy resin can be used.

Next, the operation of the semiconductor package 1 will be described.
In the semiconductor package 1, the wiring pattern 20 is interposed between the semiconductor element 50 and the semiconductor element 70, and the semiconductor elements 50 and 70 are electrically connected to each other by the wiring pattern 20. According to this, the power supply path and the external connection I / O path can be easily secured by routing the wiring pattern 20 electrically connected to the semiconductor elements 50 and 70 in the plane direction. Further, since the semiconductor elements 50 and 70 can be electrically connected by drawing the wiring pattern 20 in the plane direction, the semiconductor element 50 and the semiconductor element 70 are arranged at positions shifted in plan view as in this example. You can also. That is, the degree of freedom of arrangement of the semiconductor elements 50 and 70 can be improved.

  Further, a part of the connection terminal 71 of the semiconductor element 70 is linearly connected to the connection terminal 51 of the semiconductor element 50 at a position overlapping in plan view via the common wiring pattern 20 and the protrusions 25 and 26. did. Thereby, the connection terminals 51 and 71 of the semiconductor elements 50 and 70 can be connected at a short distance. Therefore, it is possible to increase the circuit operation speed and reduce the stray capacitance of the wiring.

  Further, the two semiconductor elements 70 are electrically connected to each other by a conductor wire 55 provided in the insulating layer 60. That is, the conductor wire 55 that can be bent in three dimensions is used for the wiring pattern 20 connected to the connection terminal 71 of one semiconductor element 70 and the wiring pattern 20 connected to the connection terminal 71 of the other semiconductor element 70. And connected electrically. Thereby, for example, even when the connection terminals 71 are extremely dense, the wiring patterns 20 electrically connected to the connection terminals 71 can be easily connected.

Next, a method for manufacturing the semiconductor package 1 will be described.
In the step shown in FIG. 4A, first, a support substrate 80 is prepared. The support substrate 80 is, for example, a flat plate having a rectangular shape in plan view. As the support substrate 80, for example, a metal plate or a metal foil can be used. In the present embodiment, for example, a copper plate is used. The thickness of the support substrate 80 is, for example, about 70 to 200 μm. As the support substrate 80, a large substrate on which a large number of semiconductor packages 1 can be taken can be used. 4 to 7, for convenience of explanation, a part of a region that becomes one semiconductor package 1 is shown in an enlarged manner.

  Next, in the step shown in FIG. 4B, a resist layer 81 having an opening 81 </ b> X corresponding to the shape of the protrusion 26 is formed on the lower surface of the support substrate 80. As a material of the resist layer 81, a material having an etching resistance against the etching process in the next step can be used. Specifically, as the material of the resist layer 81, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist or a liquid resist such as a novolac resin or an acrylic resin) can be used. For example, when using a photosensitive dry film resist, the dry film is laminated on the lower surface of the support substrate 80 by thermocompression bonding, and the dry film is patterned by exposure and development to form the resist layer 81. In the case where a liquid photoresist is used, the resist layer 81 can be formed through the same process.

  Subsequently, using the resist layer 81 as an etching mask, the support substrate 80 is etched (half-etched) from the lower surface side to form a recess 80 </ b> X on the lower surface of the support substrate 80. Specifically, the support substrate 80 exposed from the opening 81 </ b> X of the resist layer 81 is thinned by etching from the lower surface side, and the recess 80 </ b> X is formed on the exposed lower surface of the support substrate 80. The etching process in this step can be performed by, for example, wet etching (isotropic etching). When the support substrate 80 is thinned by such wet etching, an etching solution used in the wet etching can be appropriately selected according to the material of the support substrate 80. For example, when copper is used as the material of the support substrate 80, an aqueous solution of ferric chloride, an aqueous solution of cupric chloride or an aqueous solution of ammonium persulfate can be used as an etchant, and spray etching is performed from the lower surface side of the support substrate 80. The support substrate 80 can be thinned. When the support substrate 80 is thus patterned by wet etching, the cross-sectional shape of the recess 80X is semicircular or trapezoidal (in the illustrated example, semi-circular) due to the side etch phenomenon in which etching proceeds in the in-plane direction of the support substrate 80. It is formed in a circular shape.

Next, in the step shown in FIG. 4C, the resist layer 81 shown in FIG. 4B is removed by, for example, an alkaline stripping solution.
Next, in the step shown in FIG. 4D, an insulating layer 30A having an opening 30X at a predetermined location is formed on the lower surface of the support substrate 80, and the entire upper surface of the support substrate 80 is covered. A resist layer 83 is formed. The opening 30 </ b> X is formed so as to expose the lower surface of the support substrate 80 at a portion corresponding to the formation region of the wiring pattern 20. As the material of the insulating layer 30A and the resist layer 83, a material having a plating resistance against the plating process in the next step can be used. As the material of the resist layer 83, a photosensitive dry film resist or a liquid photoresist (for example, a dry film resist such as an epoxy resin, a novolac resin, an acrylic resin, or a liquid resist) can be used. The resist layer 83 can be formed by the same method as the resist layer 81. Further, the insulating layer 30A is formed by laminating a resin film made of an epoxy resin or the like on the lower surface of the support substrate 80, for example, and then heat-treating and curing the resin film at a temperature of about 190 ° C. while pressing the resin film. It can be formed by forming the opening 30X. The opening 30X can be formed by a photolithography method, for example, when the insulating layer 30A is formed using a photosensitive resin. The opening 30X can also be formed by a laser processing method using, for example, a CO ₂ laser or a YAG laser.

  Subsequently, using the insulating layer 30A and the resist layer 83 as a plating mask, the lower surface of the support substrate 80 is subjected to electrolytic plating using the support substrate 80 as a plating power feeding layer. Specifically, by performing electrolytic plating on the lower surface of the support substrate 80 and the inner surface of the recess 80X exposed from the opening 30X of the insulating layer 30A, the metal layer 84 is formed on the lower surface of the support substrate 80 and the inner surface of the recess 80X. Form. Here, when the wiring pattern 20 and the protrusion 25 shown in FIG. 1 are Au layer / Ni layer / Cu layer, the lower surface of the support substrate 80 and the recess 80X exposed from the opening 30X by electrolytic plating. The metal layer 84 is formed by sequentially stacking an Au layer and a Ni layer on the inner surface.

  Next, in the step shown in FIG. 5A, an electrolytic plating method (for example, electrolytic copper plating) using the insulating substrate 30A and the resist layer 83 as a plating mask and using the support substrate 80 as a plating power feeding layer on the lower surface of the metal layer 84. Act). As a result, in the recess 80X, the metal layer 84 formed on the inner surface of the recess 80X is plated inward to fill the recess 80X with the conductive layer 85 such as copper, and in the opening 30X, the opening Plating is applied from the lower surface of the support substrate 80 exposed from 30X or the lower surface of the conductive layer 85, and the conductive layer 86 such as copper is filled in the opening 30X. Through this step, the protrusion 26 constituted by the metal layer 84 and the conductive layer 85 is formed, and the wiring pattern 20 constituted by the metal layer 84 and the conductive layer 86 is formed. In addition, the wiring pattern 20 composed of the conductive layer 86 is formed on the lower surface of the protruding portion 26 by this step. That is, the wiring pattern 20 having the protrusions 26 is formed. Subsequently, the resist layer 83 is removed by, for example, an alkaline stripping solution.

  Next, in the step shown in FIG. 5B, an insulating layer 30B having openings 30Y at predetermined positions is formed on the lower surfaces of the insulating layer 30A and the wiring pattern 20. The opening 30 </ b> Y is formed so as to expose a portion of the wiring pattern 20 corresponding to the formation region of the protrusion 25. The insulating layer 30B can be formed by the same method as the insulating layer 30A. By this step, the insulating layer 30 including the insulating layer 30A and the insulating layer 30B is formed on the lower surface of the support substrate 80.

  Subsequently, in the process shown in FIG. 5C, an electrolytic plating method (for example, an electrolytic copper plating method) using the insulating substrate 30 as a plating mask and using the support substrate 80 as a plating power feeding layer on the lower surface of the wiring pattern 20 is performed. Apply. Thus, plating is applied from the lower surface of the wiring pattern 20 exposed from the opening 30Y, and the protrusion 25 made of copper or the like is formed in the opening 30Y. Also, plating is applied from the lower surface of the wiring pattern 21 formed in a frame shape, and a protrusion 25A made of copper or the like is formed in the opening 30Y. In this step, the lower surfaces of the protrusions 25 and 25A are formed so as to be flush with the lower surface of the insulating layer 30 (insulating layer 30B).

  Next, in the step shown in FIG. 5D, the frame-shaped substrate 40 is formed on the lower surface of the frame-shaped protrusion 25A formed in the peripheral portion of the region to be the semiconductor package 1 in the support substrate 80. For example, a substrate 40 in which interlayer insulating layers 44, 45, 46 and wiring layers 41, 42, 43 are alternately laminated is prepared, and the substrate 40 is bonded to the lower surface of the protrusion 25A with an adhesive (not shown). . Further, the interlayer insulating layers 44, 45, and 46 and the wiring layers 41, 42, and 43 may be sequentially stacked on the lower surface of the protruding portion 25A by a build-up method. By this step, the accommodating portion A1 surrounded by the inner side surface of the substrate 40, the protruding portions 25 and 25A, and the insulating layer 30 is formed.

  Next, in the step shown in FIG. 6A, the connection terminals 51 of the semiconductor element 50 are flip-chip bonded to the protrusions 25 formed on the lower surface of the predetermined wiring pattern 20 in the housing portion A1. That is, the semiconductor element 50 is flip-chip mounted on the wiring pattern 20 in the housing portion A1.

Subsequently, in the step shown in FIG. 6B, in the housing portion A1, predetermined protrusions 25 are electrically connected to each other by wire bonding using the conductor wires 55, 56, and 57.
For example, among the two semiconductor elements 70 shown in FIG. 1B, the projection terminal 25 to be connected to the connection terminal 71 </ b> C of one semiconductor element 70 via the projection 26 and the wiring pattern 20, and the other semiconductor The connection terminal 71 </ b> C of the element 70 is connected to the protruding portion 25 to be connected via the protruding portion 26 and the wiring pattern 20 by the conductor wire 55.

  For example, the wiring pattern 20 having a first end connected to the connection terminal 51 via the protrusion 25 and a second end that is a previous end routed from the first end in the planar direction. The projecting portion 25 formed at the second end of the projecting portion and the projecting portion 25 </ b> A are connected by a conductor wire 56. Alternatively, the first end portion to be connected to the connection terminal 71 (see FIG. 1) of the semiconductor element 70 via the protrusion portion 26 and the end portion that is routed in the planar direction from the first end portion. The protruding portion 25 formed at the second end portion of the wiring pattern 20 having a certain second end portion and the protruding portion 25 </ b> A are connected by the conductor wire 56.

  In the step shown in FIG. 6B, in the housing portion A1, the predetermined protrusion 25 and the connection pads P1, P2 of the substrate 40 are electrically connected by wire bonding using the conductor wire 57.

  For example, the wiring pattern 20 having a first end connected to the connection terminal 51 via the protrusion 25 and a second end that is a previous end routed from the first end in the planar direction. The projecting portion 25 formed at the second end portion of the first and second connection pads P1 and P2 are connected by a conductor wire 57. Alternatively, the first end portion to be connected to the connection terminal 71 (see FIG. 1) of the semiconductor element 70 via the protrusion portion 26 and the end portion that is routed in the planar direction from the first end portion. The protrusion 25 formed at the second end of the wiring pattern 20 having a certain second end is connected to the connection pads P1, P2 by the conductor wire 57.

  Next, in the step shown in FIG. 6C, in the housing portion A1, the protrusions 25 and 25A and the lower surfaces of the insulating layer 30, the side surfaces of the wiring layers 41 and 42 and the interlayer insulating layers 44, 45 and 46, and the semiconductor element 50 An insulating layer 60 is formed so as to cover the whole and the entire conductor wires 55 to 57. Specifically, the insulating layer 60 completely closes the cavity B, and the lower surfaces of the protrusions 25 and 25A and the insulating layer 30, the side surfaces of the wiring layers 41 and 42 and the interlayer insulating layers 44, 45 and 46, and the semiconductor element 50. In addition, the cavity B is formed in an amount sufficient to cover the conductor wires 55 to 57 as a whole. The insulating layer 60 is formed so that the lower surface thereof is substantially flush with the lower surface of the interlayer insulating layer 46 of the substrate 40. For example, the insulating layer 60 is formed by applying a liquid insulating resin into the accommodating portion A1 (cavity portion B) by potting and curing the insulating resin while maintaining a temperature of, for example, about 50 to 100 ° C. Can do.

  Subsequently, in the step shown in FIG. 7A, the support substrate 80 shown in FIG. 6C is removed. For example, when a copper plate is used as the support substrate 80, the support substrate 80 can be removed by wet etching using a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, a metal layer 84 (for example, an Au layer) and an insulating layer 30 are formed on the surface in contact with the support substrate 80 shown in FIG. 6C, and the metal layer 84 and the insulating layer 30 serve as an etching stopper layer. Therefore, only the support substrate 80 that is a copper plate can be selectively etched.

  Next, in the step shown in FIG. 7B, a solder resist layer 65 having openings 65X at predetermined positions is formed on the upper surfaces of the wiring pattern 20 and the insulating layer 30. The opening 65X is formed so as to expose the protrusion 26, the wiring pattern 20, and the insulating layer 30 corresponding to the chip mounting region. The solder resist layer 65 can be formed, for example, by laminating a photosensitive solder resist film or applying a liquid solder resist and patterning the resist into a required shape.

The wiring board 10 shown in FIG. 1 can be manufactured by the above manufacturing process.
Subsequently, in the process illustrated in FIG. 7C, the semiconductor element 70 is mounted on the upper surface of the wiring substrate 10. Specifically, the connection terminal 71 of the semiconductor element 70 is flip-chip bonded onto the protrusion 26 exposed from the opening 65X of the solder resist layer 65. Next, an underfill resin 75 is filled between the wiring board 10 and the semiconductor element 70 flip-chip mounted on the wiring board 10, and the underfill resin 75 is cured. In addition, when the underfill resin 75 is filled, the solder resist layer 65 functions as a dam member for blocking the underfill resin 75 so that the underfill resin 75 does not flow out more than necessary. The semiconductor package 1 shown in FIG. 1 can be manufactured by the above manufacturing process.

According to this embodiment described above, the following effects can be obtained.
(1) In the semiconductor package 1, the wiring pattern 20 is interposed between the semiconductor element 50 and the semiconductor element 70, and the semiconductor elements 50 and 70 are electrically connected to each other by the wiring pattern 20. According to this, the power supply path and the external connection I / O path can be easily secured by routing the wiring pattern 20 electrically connected to the semiconductor elements 50 and 70 in the plane direction.

  Further, since the semiconductor elements 50 and 70 can be electrically connected by routing the wiring pattern 20 in the plane direction, the semiconductor element 50 and the semiconductor element 70 are partially overlapped in plan view as in this example. It can also be arranged. That is, the degree of freedom of arrangement of the semiconductor elements 50 and 70 can be improved.

  Further, since the semiconductor elements 50 and 70 are electrically connected by the wiring pattern 20, it is not necessary to form through electrodes in the semiconductor elements 50 and 70. Thereby, the semiconductor elements 50 and 70 can be manufactured at low cost. Moreover, since it is not necessary to ensure the area | region for forming a penetration electrode, it can suppress that the semiconductor elements 50 and 70 enlarge.

  Furthermore, since the upper surface (surface opposite to the circuit formation surface) of the semiconductor element 70 can be exposed, a heat dissipation path (for example, a heat dissipation plate) can be easily formed on the upper surface of the semiconductor element 70. .

  (2) A part of the connection terminal 71 of the semiconductor element 70 and a connection terminal 51 of the semiconductor element 50 are linearly connected at a position overlapping in plan view via the common wiring pattern 20 and the protrusions 25 and 26. I tried to do it. Thereby, the connection terminals 51 and 71 of the semiconductor elements 50 and 70 can be connected at a short distance. Therefore, it is possible to increase the circuit operation speed and reduce the stray capacitance of the wiring.

  (3) By the way, as a method of electrically connecting the two semiconductor elements 70 to each other, the two semiconductor elements 70 are electrically connected using a silicon interposer or the like in which fine wiring is formed instead of the wiring pattern 20 or the like. A connection method is also known. However, when the connection terminals 71 of the semiconductor element 70 have a very high density, the wiring formed in the silicon interposer becomes extremely fine, which causes a problem that the manufacturing cost increases. Furthermore, there arises a problem that the conductor loss increases due to an increase in resistance accompanying a reduction in the cross-sectional area of the wiring, and a problem that crosstalk is likely to occur as the wiring pitch is narrowed.

  On the other hand, in this embodiment, the two semiconductor elements 70 are electrically connected to each other by the conductor wire 55 provided in the insulating layer 60. That is, the conductor wire 55 that can be bent in three dimensions is used for the wiring pattern 20 connected to the connection terminal 71 of one semiconductor element 70 and the wiring pattern 20 connected to the connection terminal 71 of the other semiconductor element 70. And connected electrically. Thereby, for example, even when the connection terminals 71 have a very high density, the wiring patterns 20 electrically connected to the connection terminals 71 are connected to each other without using the planar fine wiring described above. The wire 55 can be easily connected. Further, since the cross-sectional area of the conductor wire 55 can be easily increased as compared with the fine wiring, an increase in conductor loss can be suppressed. Furthermore, since predetermined wiring patterns are three-dimensionally connected by the conductor wire 55, a wide wiring pitch can be secured and crosstalk can be reduced.

  (4) On the upper surface of the wiring pattern 20, a protrusion 26 protruding upward from the upper surface of the insulating layer 30 is formed. By connecting the connection terminal 71 of the semiconductor element 70 to such a protrusion 26, the connection terminal 71 of the semiconductor element 70 and the protrusion 26 (wiring pattern 20) can be compared with the case where the protrusion 26 is not formed. The contact property can be improved.

  (5) Protrusions 25 projecting downward from the lower surface of the wiring pattern 20 are formed on the lower surface, and an insulating layer 30 covering the side surfaces of the projecting portions 25 is formed. Thereby, compared with the case where the projection part 25 is not formed, the connection reliability of the connection terminal 51 of the semiconductor element 50 and the projection part 25 (wiring pattern 20) can be improved. For example, even when a low melting point alloy is used as the material of the connection terminal 51, it is possible to suppress the connection terminal 51 (low melting point alloy) from spreading in the plane direction by the insulating layer 30 covering the side surface of the connection terminal 51. it can. Therefore, the connection terminal 51 can be suitably connected only to a desired position (that is, the protruding portion 25) of the wiring pattern 20.

  (6) By forming the insulating layer 60 with a low elastic material, it is possible to relieve stress generated due to mismatch of thermal expansion coefficients between the semiconductor elements 50 and 70 and the wiring pattern 20 and the protrusions 25 and 26. .

  (7) A frame-shaped substrate 40 is formed on the lower surface side of the wiring pattern 20, and the connection pads P <b> 1 and P <b> 2 formed on the substrate 40 and the wiring pattern 20 (protrusion 25) are electrically connected by the conductor wire 57. I tried to do it. As a result, even when a large number of wiring patterns 20 drawn outside from the stacked position of the semiconductor elements 50 and 70 are required, the wiring patterns 20 and the connection pads P1 and P2 are connected by the conductor wires 57. Thus, a large number of wiring patterns 20 can be easily pulled out.

In addition, the said 1st Embodiment can also be implemented in the following aspects which changed this suitably.
In the first embodiment, each semiconductor element 70 mounted on the upper surface of the wiring board 10 and each semiconductor element 50 mounted on the opposite side of the semiconductor element 70 across the wiring pattern 20 are mutually viewed in plan view. It was arranged so that only a part overlapped. For example, as shown in FIGS. 8A and 8B, the entire semiconductor element 50 mounted in the accommodating portion A1 is arranged so as to overlap the semiconductor element 70 in plan view. May be. In this case, as shown in FIG. 8A, most of the connection terminals 71 of the semiconductor element 70 can be conductively connected to the connection terminals 51 of the semiconductor element 50 in a uniaxial manner. Even in such a case, the protrusions 25 and 26 are formed on the lower surface side and the upper surface side of the wiring pattern 20, respectively, and a wide space in the thickness direction is secured. It can be easily routed in the plane direction. For this reason, as shown in FIG. 8A, even if the semiconductor element 70 and the semiconductor element 50 are arranged at positions separated in the plane direction, the semiconductor element 50 is drawn by drawing the wiring pattern 20 in the plane direction. , 70 can be easily connected.

(Second Embodiment)
The second embodiment will be described below with reference to FIGS. This embodiment is different from the first embodiment in that the protrusions 25 and 26 are omitted. Hereinafter, the difference from the first embodiment will be mainly described. The same members as those shown in FIGS. 1 to 8 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 9A, the insulating layer 30 is formed so as to cover the side surface of the wiring pattern 20. The upper surface of the insulating layer 30 is formed to be substantially flush with the upper surface of the wiring pattern 20, and the lower surface of the insulating layer 30 is formed to be substantially flush with the lower surface of the wiring pattern 20.

  The substrate 40 is bonded to the lower surface of the frame-like wiring pattern 21 formed on the peripheral edge of the semiconductor package 1. As shown in FIG. 9B, in the substrate 40 of this example, three wiring layers 41, 42, 43 and three interlayer insulating layers 44, 45, 46 are alternately stacked. The wiring layer 41 is electrically connected to the wiring pattern 21 by a via 47 that penetrates the interlayer insulating layer 44 in the thickness direction.

  In the cavity B formed in the central portion of the substrate 40, the opening end on the upper surface side (opening B 1 side) of the interlayer insulating layer 44 is closed by the wiring pattern 20 and the insulating layer 30. The entire upper surface of the interlayer insulating layer 44 is covered with the wiring pattern 21.

  A required number (two in this case) of semiconductor elements 50 are contained in the accommodating portion A1 surrounded by the cavity B of the substrate 40 (specifically, the inner surface of the cavity B), the wiring pattern 20, and the insulating layer 30. Is housed. Specifically, the semiconductor element 50 is accommodated in the accommodating portion A1 with the connection terminal 51 disposed on the circuit formation surface (here, the upper surface) facing upward (wiring pattern 20 side). . For example, each semiconductor element 50 is flip-chip mounted on the wiring pattern 20. That is, by joining the connection terminal 51 of the semiconductor element 50 to the lower surface of the wiring pattern 20, the semiconductor element 50 is joined to the wiring pattern 20 face down. The semiconductor element 50 is electrically connected to the wiring pattern 20 via the connection terminal 51. Here, for example, a part of the pattern of the wiring pattern 20 is routed in the planar direction from the end connected to the connection terminal 51, and the routed end is connected to the wiring pattern 21 via the conductor wire 56. Connected to. Further, for example, a part of the wiring pattern 20 is routed in the planar direction from the end connected to the connection terminal 51, and the routed end is connected to the substrate 40 via the conductor wire 57. Connected to pads P1 and P2.

  Conductor wires 55 and 56 that connect predetermined wiring patterns 20 to each other are provided in the cavity B of the substrate 40. The hollow portion B is provided with a conductor wire 57 that connects the predetermined wiring pattern 20 and the connection pads P1 and P2.

  The insulating layer 60 is formed so as to fill the cavity B (specifically, the openings B1, B2, B3). The insulating layer 60 covers the inner side surface of the substrate 40 (side surface of the cavity B), the lower surface of the wiring pattern 20 and the insulating layer 30 exposed from the substrate 40, the entire semiconductor element 50, and the entire conductor wires 55 to 57. Is formed.

On the upper surfaces of the wiring pattern 20 and the insulating layer 30, a solder resist layer 65 having an opening 65X formed at a position corresponding to the chip mounting region is formed.
The wiring substrate 10A having the wiring pattern 20, the insulating layer 30, the substrate 40, the semiconductor element 50, the conductor wires 55 to 57, the insulating layer 60, and the solder resist layer 65 described above includes a required number ( Here, two semiconductor elements 70 are mounted. Specifically, the semiconductor element 70 is flip-chip mounted on the wiring pattern 20 exposed from the opening 65X of the solder resist layer 65. That is, by bonding the connection terminal 71 of the semiconductor element 70 to the upper surface of the wiring pattern 20, the semiconductor element 70 is bonded face-down to the wiring board 10 </ b> A. The semiconductor element 70 is electrically connected to the wiring pattern 20 via the connection terminal 71.

  Here, the required number (here, two) of connection terminals 71A among the connection terminals 71 share the wiring pattern 20 with the connection terminals 51 of the semiconductor element 50 built in the wiring board 10A. Specifically, the connection terminal 71 </ b> A is conductively connected in a uniaxial manner with the connection terminal 51 disposed so as to face the wiring pattern 20. In the present embodiment, “uniaxially conductively connected” refers to a conductor (here, the wiring pattern 20) formed in the thickness direction of the wiring substrate 10A without routing the wiring pattern 20 or the like in the plane direction. It means connecting. Although not shown in detail, the wiring pattern 20 connected to the required number of connection terminals 71B among the connection terminals 71 is routed in the plane direction, and the end portion that is routed is the semiconductor element 50. Are connected to the connection terminals 51 of the substrate 40 or to the connection pads P1 and P2 of the substrate 40.

  Further, the two semiconductor elements 70 are electrically connected to each other by a conductor wire 55 provided in the insulating layer 60. That is, the connection terminal 71 </ b> C of one semiconductor element 70 is electrically connected to the conductor wire 55 via the wiring pattern 20, and the wiring pattern 20 connected to the conductor wire 55 is connected to the connection terminal 71 of the other semiconductor element 70. It is connected.

Next, a method for manufacturing the semiconductor package 1A will be described.
In the step shown in FIG. 10A, first, a support substrate 90 is prepared. The support substrate 90 is, for example, a flat plate having a rectangular shape in plan view. As the support substrate 90, for example, a metal plate or a metal foil can be used. In the present embodiment, for example, a copper foil is used. The thickness of the support substrate 90 is, for example, about 35 to 100 μm. As the support substrate 90, a large-sized substrate from which a large number of semiconductor packages 1A can be taken can be used. 10 to 11, for convenience of explanation, a part of a region that becomes one semiconductor package 1 </ b> A is enlarged.

  Next, in the step shown in FIG. 10B, the insulating layer 30 having the opening 30 </ b> X at a predetermined location is formed on the lower surface of the support substrate 90. The opening 30 </ b> X is formed so as to expose a portion of the support substrate 90 corresponding to the formation region of the wiring pattern 20. As a material of the insulating layer 30, a material having plating resistance with respect to the plating process in the next step can be used.

  Subsequently, in the step shown in FIG. 10C, electrolytic plating using the insulating substrate 30 as a plating mask and using the supporting substrate 90 as a plating power supply layer is performed on the lower surface of the supporting substrate 90. Specifically, the metal layer 91 is formed on the lower surface of the support substrate 90 by performing electrolytic plating on the lower surface of the support substrate 90 exposed from the opening 30 </ b> X of the insulating layer 30. Here, when the wiring pattern 20 is an Au layer / Ni layer / Cu layer, an Au layer and a Ni layer are sequentially laminated on the lower surface of the support substrate 90 exposed from the opening 30X by an electrolytic plating method. A metal layer 91 is formed.

  Next, using the insulating layer 30 as a plating mask, an electrolytic plating method (for example, an electrolytic copper plating method) using the support substrate 90 as a plating power feeding layer is performed on the lower surface of the metal layer 91. Thus, plating is applied from the lower surface of the metal layer 91, and the conductive layer 92 such as copper is filled in the opening 30X. By this step, the wiring pattern 20 composed of the metal layer 91 and the conductive layer 92 is formed.

  Next, in the step shown in FIG. 10D, the frame-shaped substrate 40 is formed on the lower surface of the frame-shaped wiring pattern 21 formed in the peripheral portion of the region to be the semiconductor package 1A of the support substrate 90. . Subsequently, the connection terminal 51 of the semiconductor element 50 is flip-chip bonded to the predetermined wiring pattern 20 in the housing portion A1.

  Next, in the step illustrated in FIG. 10E, the predetermined wiring patterns 20 are electrically connected to each other by wire bonding using the conductor wire 55 in the housing portion A <b> 1. Further, the predetermined wiring pattern 20 and the wiring pattern 21 are electrically connected by wire bonding using a conductor wire 56. Further, the predetermined wiring pattern 20 and the connection pads P1 and P2 of the substrate 40 are electrically connected by wire bonding using the conductor wire 57. Subsequently, the cavity B is filled, and an insulating layer 60 is formed to cover the lower surface of the wiring pattern 20 and the insulating layer 30, the inner surface of the substrate 40, the entire semiconductor element 50, and the entire conductor wires 55 to 57.

  Next, in the step shown in FIG. 11A, the support substrate 90 shown in FIG. 10E is removed. For example, when a copper foil is used as the support substrate 90, the support substrate 90 can be removed by wet etching using a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, a metal layer 91 (for example, an Au layer) and an insulating layer 30 are formed on the surface in contact with the support substrate 90 shown in FIG. 10E, and the metal layer 91 and the insulating layer 30 are formed as an etching stopper layer. Therefore, only the support substrate 90 that is a copper foil can be selectively etched.

  Next, in the step shown in FIG. 11B, a solder having an opening 65X for exposing the wiring pattern 20 and the insulating layer 30 corresponding to the chip mounting area on the upper surface of the wiring pattern 20 and the insulating layer 30. A resist layer 65 is formed. The wiring substrate 10A shown in FIG. 9 can be manufactured by the above manufacturing process.

  Subsequently, in the step shown in FIG. 11C, the connection terminal 71 of the semiconductor element 70 is flip-chip bonded onto the wiring pattern 20 exposed from the opening 65X of the solder resist layer 65. Next, an underfill resin 75 is filled between the wiring board 10 </ b> A and the semiconductor element 70, and the underfill resin 75 is cured. Through the above manufacturing process, the semiconductor package 1A shown in FIG. 9 can be manufactured.

According to this embodiment described above, the same effects as (1) to (3), (6), and (7) of the first embodiment are obtained.
(Third embodiment)
The third embodiment will be described below with reference to FIGS. This embodiment is different from the second embodiment in the structure of the frame-shaped substrate. Hereinafter, the difference from the second embodiment will be mainly described. The same members as those shown in FIGS. 1 to 11 are denoted by the same reference numerals, and detailed description of these elements is omitted.

A method for manufacturing the semiconductor package 1B shown in FIG.
In the step shown in FIG. 12A, the insulating layer 30 and the wiring pattern 20 are formed on the lower surface of the support substrate 90 by the same manufacturing steps as those shown in FIGS. 10A to 10C. The wiring pattern 20 includes a metal layer 91 formed on the lower surface of the support substrate 90 and a conductive layer 92 formed on the lower surface of the metal layer 91.

Next, in the step shown in FIG. 12B, a frame-shaped insulating layer 93 having a cavity C at the center is formed on the lower surface of the wiring pattern 21 formed in a frame shape in the wiring pattern 20. For example, a resin film made of an insulating resin such as an epoxy resin or a polyimide resin is laminated on the lower surfaces of the wiring pattern 20 and the insulating layer 30 and cured by heat treatment at a temperature of about 190 ° C. while pressing the resin film. Later, the insulating layer 93 can be formed by forming the cavity C at a required location (here, the central portion). The cavity C can be formed by photolithography when the insulating layer 93 is formed using a photosensitive resin, for example. The cavity C can also be formed by a laser processing method using, for example, a CO ₂ laser or a YAG laser. By this step, the housing portion A1 surrounded by the inner surface of the insulating layer 93 and the wiring pattern 20 and the insulating layer 30 is formed.

Subsequently, in the step shown in FIG. 12C, a through hole 93 </ b> X for exposing a part of the lower surface of the wiring pattern 21 is formed at a required portion of the insulating layer 93. The through hole 93X can be formed by a laser processing method using, for example, a CO ₂ laser or a YAG laser. For example, when the insulating layer 93 is formed using a photosensitive resin, the required through hole 93X may be formed simultaneously with the formation of the cavity C by photolithography.

  Next, in the step shown in FIG. 12D, the connection terminal 51 of the semiconductor element 50 is flip-chip bonded to the predetermined wiring pattern 20 in the housing portion A1. Subsequently, in the accommodating portion A1, predetermined wiring patterns 20 are electrically connected to each other by wire bonding using a conductor wire 55. Next, the cavity C is filled with an insulating resin to form an insulating layer 60 that covers the lower surfaces of the wiring pattern 20 and the insulating layer 30, the inner surface of the insulating layer 93, the entire semiconductor element 50, and the entire conductor wire 55.

  Next, in the step shown in FIG. 13A, an electrolytic plating method (for example, electrolytic copper plating) using the support substrate 90 as a plating power feeding layer on the lower surface of the wiring pattern 21 exposed from the through hole 93X of the insulating layer 93. Act). Thereby, plating is performed from the lower surface of the wiring pattern 20 exposed from the through hole 93X, and the columnar metal post 94 made of copper or the like is formed in the through hole 93X. The metal post 94 is formed so as to penetrate the insulating layer 93 in the thickness direction, and the upper surface thereof is connected to the wiring pattern 21. Subsequently, an electrolytic plating method using the support substrate 90 as a plating power feeding layer is performed on the lower surface of the metal post 94 to form a metal layer 94A. As an example of the metal layer 94A, a metal layer in which a Ni layer / Au layer is sequentially laminated from the lower surface of the metal post 94 can be cited. As described above, when the metal layer 94A is a Ni layer / Au layer, the metal layer 94A is formed by sequentially laminating the Ni layer and the Au layer on the lower surface of the metal post 94 by electrolytic plating. In addition, as another example of the metal layer 94A, from the lower surface of the metal post 94, a metal layer in which Ni layer / Pd layer / Au layer is sequentially laminated, a metal layer in which Ni layer / Pd layer / Ag layer is sequentially laminated, Ni A metal layer in which layer / Pd layer / Ag layer / Au layer is laminated in this order can be exemplified.

  Next, in the step shown in FIG. 13B, the support substrate 90 shown in FIG. 13A is removed. For example, when a copper foil is used as the support substrate 90, the support substrate 90 can be removed by wet etching using a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, a metal layer 91 (for example, an Au layer) and an insulating layer 30 are formed on the surface in contact with the support substrate 90 shown in FIG. 13A, and on the lower surface side of the structure shown in FIG. Since the metal layer 94A (for example, Au layer) and the insulating layers 60 and 93 are exposed, only the support substrate 90 that is a copper foil can be selectively etched.

  Next, in the step shown in FIG. 13C, a solder resist layer 65 having an opening 65 </ b> X is formed on the upper surfaces of the wiring pattern 20 and the insulating layer 30. The wiring board 10B of this embodiment can be manufactured by the above manufacturing process.

  Subsequently, the connection terminal 71 of the semiconductor element 70 is flip-chip bonded onto the wiring pattern 20 exposed from the opening 65 </ b> X of the solder resist layer 65. Next, an underfill resin 75 is filled between the wiring board 10B and the semiconductor element 70, and the underfill resin 75 is cured. The semiconductor package 1B of this embodiment can be manufactured by the above manufacturing process.

According to this embodiment described above, the same effects as (1) to (3) and (6) of the first embodiment are obtained.
(Fourth embodiment)
Hereinafter, a fourth embodiment will be described with reference to FIGS. This embodiment is different from the second embodiment in the structure of a frame-like substrate. Hereinafter, the difference from the second embodiment will be mainly described. The same members as those shown in FIGS. 1 to 13 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 14A, the semiconductor package 1C includes a wiring board 10C, two semiconductor elements 70, and an underfill resin 76. The wiring substrate 10 </ b> C includes a wiring pattern 20, an insulating layer 30, a substrate 95, a lead portion 96, a semiconductor element 50, conductor wires 55 and 58, and an insulating layer 60.

  The substrate 95 has a hollow portion D formed in the center thereof, and is formed in a frame shape. The substrate 95 is formed so that its upper surface protrudes upward from the upper surface of the wiring pattern 20, and its lower surface protrudes downward from the lower surface of the wiring pattern 20. As shown in FIG. 14B, a part of the lead portion 96 is formed in the substrate 95. That is, the substrate 95 is formed so as to include a part of the lead portion 96. In addition, as a material of the board | substrate 95, organic resins, such as an epoxy resin and a polyimide resin, can be used, for example.

  The insulating layer 60 is formed so as to fill the accommodating portion A <b> 1 formed by the inner surface of the substrate 95 formed below the wiring pattern 20 and the lower surfaces of the wiring pattern 20 and the insulating layer 30. The insulating layer 60 is formed so as to cover the inner surface of the substrate 95 formed below the wiring pattern 20, the lower surface of the wiring pattern 20 and the insulating layer 30, the entire semiconductor element 50, and the entire conductor wires 55 and 58. Yes. The lower surface of the insulating layer 60 is formed so as to be substantially flush with the lower surface of the substrate 95.

  The lead part 96 is formed so as to protrude outward from the outer surface of the substrate 95. The lead portion 96 is bent downward from the end portion on the substrate 95 side, and is formed in a substantially L shape in sectional view. For example, the lead part 96 is formed in a peripheral shape along the outer peripheral edge (outer shape) of the wiring board 10C.

  The lead part 96 has a metal layer 97 and a metal layer 98 laminated on the metal layer 97. One end of the metal layer 97 (the end on the wiring pattern 20 side) is formed on the same plane as the wiring pattern 20. The metal layer 97 is formed so that the end portion on the wiring pattern 20 side penetrates the substrate 95 in the planar direction (width direction), and further, the end portion protrudes inward from the inner side surface of the substrate 95. ing. The metal layer 97 formed in the substrate 95 has its side surface and lower surface covered with the substrate 95 and its upper surface covered with the metal layer 98. The metal layer 97 is electrically connected to a predetermined wiring pattern 20 by a conductor wire 58 provided in the insulating layer 60. For example, the wiring pattern 20 electrically connected to the metal layer 97 is routed in the planar direction from the end portion to which the conductor wire 58 is connected, and the routed end portion is the connection terminal of the semiconductor element 50. 51 (or the connection terminal 71 of the semiconductor element 70) is electrically connected. Thereby, the semiconductor element 50 (or the semiconductor element 70) is electrically connected to the lead portion 96 through the connection terminal 51 (or connection terminal 71), the wiring pattern 20, and the conductor wire 58. Note that the lower surface of the metal layer 97 protruding inward from the inner surface of the substrate 95 is covered with the insulating layer 60.

  As an example of the metal layer 97, similarly to the wiring pattern 20, a metal layer in which a Cu layer / Ni layer / Au layer is sequentially laminated from the lower surface side (the upper surface of the insulating layer 60) of the metal layer 97 can be exemplified. Further, as an example of the metal layer 97, from the lower surface side of the metal layer 97, a metal layer in which Cu layer / Ni layer / Pd layer / Au layer is sequentially laminated, and Cu layer / Ni layer / Pd layer / Ag layer are sequentially laminated. And a metal layer in which a Cu layer / Ni layer / Pd layer / Ag layer / Au layer are sequentially laminated.

  The metal layer 98 is formed so that the end portion on the wiring pattern 20 side penetrates the substrate 95 in the planar direction, and the end portion is formed to be substantially flush with the inner side surface of the substrate 95. The metal layer 98 formed in the substrate 95 has its side surface and upper surface covered with the substrate 95 and its lower surface covered with the metal layer 97. In addition, as a material of the metal layer 98, copper and a copper alloy can be used, for example.

  As shown in FIG. 14A, a required number (two in this case) of semiconductor elements 70 are mounted on the wiring board 10C having the above-described structure. Specifically, the semiconductor element 70 is formed on the wiring substrate 10 </ b> C in the housing portion A <b> 2 formed by the inner side surface of the substrate 95 formed above the wiring pattern 20 and the upper surfaces of the wiring pattern 20 and the insulating layer 30. Flip chip mounting. That is, by bonding the connection terminal 71 of the semiconductor element 70 to the upper surface of the wiring pattern 20, the semiconductor element 70 is bonded face-down to the wiring board 10C.

  The underfill resin 76 is formed in the housing portion A2, and is formed so as to fill a gap between the upper surface of the wiring board 10C and the lower surface of the semiconductor element 70. The underfill resin 76 includes a part of the inner surface of the substrate 95 formed above the wiring pattern 20, the end surface of the metal layer 98 exposed from the substrate 95, the wiring pattern 20 exposed from the substrate 95, The upper surface of the metal layer 97 and the insulating layer 30 and a part of the semiconductor element 70 are covered.

Next, a method for manufacturing the semiconductor package 1C will be described.
In the step shown in FIG. 15A, first, the support substrate 100 is prepared. The support substrate 100 is, for example, a flat plate having a rectangular shape in plan view. The support substrate 100 is a member whose part finally becomes the metal layer 98. As the support substrate 100, for example, a metal plate or a metal foil can be used. In the present embodiment, for example, a copper plate is used. The thickness of the support substrate 100 is, for example, about 70 to 200 μm. 15 to 17, for convenience of explanation, a part of the region that will eventually become the semiconductor package 1C is shown enlarged.

  15A and 15B, the shape of the opening 101X corresponding to the shape of the wiring pattern 20 (see FIG. 15A) and the shape of the metal layer 97 is formed on the lower surface of the support substrate 100. A resist layer 101 having an opening 101Y corresponding to (see FIG. 15B) is formed. As a material of the resist layer 101, a material having resistance to plating for the plating process in the next step can be used. The resist layer 101 is a member that partially becomes the insulating layer 30 in the end. Note that FIG. 15B is an enlarged plan view of a part of the structure shown in FIG. 15A (see the alternate long and short dash line), and is viewed from the lower surface side of the structure shown in FIG. FIG.

  Next, in the steps shown in FIG. 15C and FIG. 15D, electrolytic plating using the support substrate 100 as a plating power feeding layer is performed on the lower surface of the support substrate 100 using the resist layer 101 as a plating mask. . Specifically, the metal layer 102 is formed on the lower surface of the support substrate 100 by performing electrolytic plating on the lower surface of the support substrate 100 exposed from the openings 101X and 101Y of the resist layer 101. Here, when the wiring pattern 20 and the metal layer 97 shown in FIG. 14 are Au layer / Ni layer / Cu layer, the bottom surface of the support substrate 100 exposed from the openings 101X and 101Y is formed by electrolytic plating. The metal layer 97 is formed by sequentially stacking an Au layer and a Ni layer. In FIG. 15C, the opening 101Y is not shown because the cross-sectional structure at the position of the line 15a-15a shown in FIG. 15B is shown. FIG. 15D shows a cross-sectional structure taken along the line 15d-15d shown in FIG.

  Next, using the resist layer 101 as a plating mask, the lower surface of the metal layer 102 is subjected to an electrolytic plating method (for example, an electrolytic copper plating method) using the support substrate 100 as a plating power feeding layer. Thus, plating is applied from the lower surface of the metal layer 102, and the conductive layer 103 such as copper is filled in the opening 101X, and the conductive layer 104 such as copper is filled in the opening 101Y. By this step, the wiring pattern 20 composed of the metal layer 102 and the conductive layer 103 is formed in the opening 101X, and the metal layer 97 composed of the metal layer 102 and the conductive layer 104 is formed in the opening 101Y. .

  Next, in the steps shown in FIGS. 16A to 16C, a part of the support substrate 100 and the resist layer 101 is removed by pressing or etching. Specifically, the resist layer 101 formed in the outer peripheral region (see the broken line frame) of the structure shown in FIG. 15C by pressing or etching, and the support substrate 100 formed on the resist layer 101. Is removed to form an opening 100X. As a result, the resist layer 101 becomes the insulating layer 30, and a protruding portion 100 </ b> A that protrudes outward from the side surface of the insulating layer 30 is formed on the support substrate 100. A large number of protrusions 100A are formed in a peripheral shape along the outer peripheral edge (outer shape) of the insulating layer 30. The protrusions 100A are separated from each other by the opening 100X formed in this step.

  Next, in the steps shown in FIGS. 17A and 17B, a frame-shaped substrate 95 is formed so as to surround a part of the metal layer 97 and the protruding portion 100A. At this time, the substrate 95 is such that one end of the metal layer 97 and the protruding portion 100A (the end on the wiring pattern 20 side) protrudes from the inner surface of the substrate 95, and the other of the metal layer 97 and the protruding portion 100A. Are formed so as to protrude from the outer surface of the substrate 95. Further, the substrate 95 is formed so that the upper surface thereof protrudes above the upper surface of the protruding portion 100 </ b> A and the lower surface protrudes below the lower surface of the metal layer 97. The substrate 95 can be formed by, for example, a resin mold forming method.

  Next, in the step shown in FIG. 17C, the inner surface of the substrate 95 formed below the wiring pattern 20, the lower surface of the wiring pattern 20, the lower surface of the metal layer 97, and the lower surface of the insulating layer 30 are formed. In the accommodating portion A1, the connection terminal 51 of the semiconductor element 50 is flip-chip bonded to the predetermined wiring pattern 20. Subsequently, in the accommodating portion A1, predetermined wiring patterns 20 are electrically connected to each other by wire bonding using a conductor wire 55. In addition, the predetermined wiring pattern 20 and the metal layer 97 protruding from the inner surface of the substrate 95 are electrically connected by wire bonding using the conductor wire 58. Next, the housing portion A1 is filled, the inner surface of the substrate 95 exposed in the housing portion A1, the lower surface of the wiring pattern 20, the metal layer 97 and the insulating layer 30 exposed in the housing portion A1, and the semiconductor element 50. An insulating layer 60 that covers the entirety and the entire conductor wires 55 and 58 is formed.

  Next, in the step shown in FIG. 18A, a part of the support substrate 100 shown in FIG. 17C is removed by etching or the like. Specifically, in the accommodating portion A2 formed by the inner surface of the substrate 95 formed above the wiring pattern 20, the upper surface of the wiring pattern 20, the upper surface of the metal layer 97, and the upper surface of the insulating layer 30. The support substrate 100 exposed to is removed. Thereby, a portion of the protruding portion 100A protruding from the inner surface of the substrate 95 into the accommodating portion A2 is removed, and a metal layer 98 stacked on the metal layer 97 is formed. And the lead part 96 comprised by these metal layers 97 and 98 is formed. The wiring substrate 10C shown in FIG. 14 can be manufactured by the above manufacturing process.

  Next, in the step shown in FIG. 18B, the connection terminal 71 of the semiconductor element 70 is flip-chip bonded to the predetermined wiring pattern 20 in the housing portion A2. Subsequently, the underfill resin 76 is filled into the housing portion A2, and the underfill resin 76 is cured.

  Next, in the step shown in FIG. 18C, the lead portion 96 is formed in a substantially L shape in sectional view by bending the middle portion of the lead portion 96 protruding outward from the outer surface of the substrate 95 downward. . The semiconductor package 1C shown in FIG. 14 can be manufactured by the above manufacturing process.

According to this embodiment described above, the same effects as (1) to (3) and (6) of the first embodiment are obtained.
(Fifth embodiment)
Hereinafter, a fifth embodiment will be described with reference to FIGS. This embodiment is different from the second embodiment in the structure of the insulating layer. Hereinafter, the difference from the second embodiment will be mainly described. The same members as those shown in FIGS. 1 to 18 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 19A, the semiconductor package 1D includes a wiring board 10D, two semiconductor elements 70, and an underfill resin 75. The wiring substrate 10 </ b> D includes a wiring pattern 20, a substrate 40, a semiconductor element 50, conductor wires 55, 56, 57, an insulating layer 61, and a solder resist layer 65.

  As shown in FIG. 19B, the insulating layer 61 is formed so as to fill the opening 20X that defines the wiring pattern 20 and the cavity B. The insulating layer 61 is formed so as to cover the side surface and the lower surface of the wiring pattern 20, the inner surface of the substrate 40, the entire semiconductor element 50, and the conductor wires 55, 56, and 57. The insulating layer 61 has a function of electrically insulating the wiring patterns 20 and a function of bonding the wiring patterns 20 together. That is, many wiring patterns 20 are supported by the insulating layer 61. The insulating layer 61 of this example is formed so that its lower surface is flush with the lower surface of the interlayer insulating layer 46 of the substrate 40. The insulating layer 61 is an insulating layer made of a low elastic material having a low elastic modulus. The low elastic material is preferably a material having a Young's modulus in the vicinity of room temperature of 1 MPa or more and 10 MPa or less, for example. As such a low elastic material, for example, a silicone-based, fluorine-based, polyolefin-based or urethane-based elastomer can be used.

  Thus, the wiring substrate 10D is formed on the first insulating layer that insulates the wiring patterns 20 and adheres the wiring patterns 20 and the lower surface of the first insulating layer, and covers the entire semiconductor element 50. The insulating layer 61 is formed integrally with the two insulating layers.

Next, a method for manufacturing the semiconductor package 1D will be described.
In the step shown in FIG. 20A, first, a support substrate 90 is prepared. The support substrate 90 is, for example, a flat plate having a rectangular shape in plan view. As the support substrate 90, for example, a metal plate or a metal foil can be used. In the present embodiment, for example, a copper foil is used. Next, in a step shown in FIG. 20B, a resist layer 105 having an opening 105X at a predetermined location is formed on the lower surface of the support substrate 90. The opening 105 </ b> X is formed so as to expose a portion of the support substrate 90 corresponding to the formation region of the wiring pattern 20. As a material of the insulating layer 105, a material having plating resistance with respect to the plating process in the next step can be used. As a material of the insulating layer 105, for example, a material similar to that of the resist layer 83 can be used.

  Subsequently, in the step shown in FIG. 20C, as in the step shown in FIG. 10C, the lower surface of the support substrate 90 exposed from the opening 105X of the resist layer 105 is subjected to electrolytic plating. The metal layer 91 and the conductive layer 92 are sequentially laminated on the lower surface of the support substrate 90. Thereby, the wiring pattern 20 including the metal layer 91 and the conductive layer 92 is formed.

  Next, the resist layer 105 is removed with, for example, an alkaline stripping solution. Thereby, an opening 20 </ b> X that defines the wiring patterns 20 is formed between the wiring patterns 20. Subsequently, in the step shown in FIG. 20D, a frame-shaped substrate 40 is formed on the lower surface of the frame-shaped wiring pattern 21. Next, in the housing portion A1, the connection terminals 51 of the semiconductor element 50 are flip-chip bonded to the predetermined wiring pattern 20.

  Next, in the step illustrated in FIG. 20E, the predetermined wiring patterns 20 are electrically connected to each other by wire bonding using the conductor wire 55 in the housing portion A <b> 1. Further, the predetermined wiring pattern 20 and the wiring pattern 21 are electrically connected by wire bonding using a conductor wire 56. Further, the predetermined wiring pattern 20 and the connection pads P1 and P2 of the substrate 40 are electrically connected by wire bonding using the conductor wire 57.

  Subsequently, the insulating layer 61 is formed so as to cover the side surface and the lower surface of the wiring pattern 20, the inner side surface of the substrate 40, the entire semiconductor element 50, and the entire conductor wires 55 to 57 in the housing portion A <b> 1. Specifically, the insulating layer 61 completely covers the opening 20X and the cavity B, and entirely covers the side surface and the bottom surface of the wiring pattern 20, the inner surface of the substrate 40, the semiconductor element 50, and the conductor wires 55 to 57. The opening 20X and the cavity B are formed so as to be filled in a sufficient amount. For example, the insulating layer 61 is formed by applying a liquid insulating resin into the opening 20X and the accommodating portion A1 (cavity portion B) by potting, and curing the insulating resin while maintaining a temperature of about 50 to 100 ° C., for example. Can be formed. The wiring patterns 20 are bonded to each other by the insulating layer 61 thus cured.

  Next, in the step shown in FIG. 21A, the support substrate 90 shown in FIG. For example, when a copper foil is used as the support substrate 90, the support substrate 90 can be removed by wet etching using a ferric chloride aqueous solution, a cupric chloride aqueous solution, an ammonium persulfate aqueous solution, or the like. At this time, a metal layer 91 (for example, an Au layer) and an insulating layer 61 are formed on the surface in contact with the support substrate 90 shown in FIG. 20E, and the metal layer 91 and the insulating layer 61 are formed as an etching stopper layer. Therefore, only the support substrate 90 that is a copper foil can be selectively etched.

  Next, in a step shown in FIG. 21B, a solder resist layer 65 having an opening 65X is formed on the upper surfaces of the wiring pattern 20 and the insulating layer 61. The wiring board 10D of this embodiment can be manufactured by the above manufacturing process.

  Subsequently, the connection terminal 71 of the semiconductor element 70 is flip-chip bonded onto the wiring pattern 20 exposed from the opening 65 </ b> X of the solder resist layer 65. Next, an underfill resin 75 is filled between the wiring board 10 </ b> D and the semiconductor element 70, and the underfill resin 75 is cured. The semiconductor package 1D of this embodiment can be manufactured by the above manufacturing process.

According to this embodiment described above, the same effects as (1) to (3), (6), and (7) of the first embodiment are obtained.
(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.

  In each of the above embodiments, the two semiconductor elements 70 are electrically connected by the conductor wire 55 provided in the insulating layers 60 and 61. Alternatively, the two semiconductor elements 70 are electrically connected to each other by the wiring pattern 20 extending in the planar direction. For example, as shown in FIG. 22, the two semiconductor elements 70 are electrically connected to each other by a wiring board (interposer) 110 formed in the insulating layer 60 (or the insulating layer 61). May be. Here, the interposer 110 has a large number of connection terminals 111 connected to fine wiring (not shown) formed in large numbers on one surface (here, the upper surface). As a material for the base material of the interposer 110, for example, an inorganic material such as silicon, glass, or ceramic can be used. Then, by connecting the connection terminal 111 and the predetermined protrusion 25 (or the predetermined wiring pattern 20), the two semiconductor elements 70 are connected to the wiring pattern 20, the connection terminal 111, the fine wiring in the interposer 110, and the like. Electrically connected to each other. Specifically, the connection terminal 71 of one semiconductor element 70 is connected to the connection terminal 111 via the protruding portion 26, the wiring pattern 20, and the protruding portion 25, and the connecting terminal 111 is different from the fine wiring. The protrusion 25 is connected to the connection terminal 71 of the other semiconductor element 70 via the wiring pattern 20 and the protrusion 26.

-You may make it form the projection parts 25 and 26 with respect to the wiring pattern 20 in the said 3rd-5th embodiment.
In the first embodiment, the protrusion 25 is formed on the lower surface of the wiring pattern 20 where the conductor wires 55 to 57 are connected. However, the protrusion 25 may be omitted. That is, the conductor wires 55 to 57 may be directly connected to the lower surface of the wiring pattern 20.

  In each of the above embodiments, when the wiring pattern 20 is interposed between the semiconductor element 50 and the semiconductor element 70 and the semiconductor elements 50 and 70 are connected to each other by the wiring pattern 20, the conductor wire 55 is It may be omitted.

In each of the above embodiments, when the conductor wire 55 is formed in the insulating layers 60 and 61, the semiconductor element 50 may be omitted.
The conductor wire 56 in the first, second, and fifth embodiments may be omitted.

-You may abbreviate | omit the board | substrate 40 in the said 1st-3rd and 5th embodiment.
In the third embodiment, the insulating layer 93, the metal post 94, and the metal layer 94A may be omitted.

  The insulating layers 30 and 60 in the first, third, and fourth embodiments may be changed to the insulating layer 61 in the fifth embodiment. That is, you may make it form the insulating layers 30 and 60 in 1st, 3rd and 4th embodiment integrally.

The solder resist layer 65 in each of the above embodiments may be omitted.
-Underfill resin 75 and 76 in each above-mentioned embodiment may be omitted.
In each of the above embodiments, for example, as shown in FIG. 22, a chip component 112 electrically connected to the wiring pattern 20 (protrusion 25) is provided in the insulating layer 60 (or insulating layer 61). Also good. For example, a chip capacitor, a chip resistor, or a chip inductor can be used as the chip component 112.

  In each of the above embodiments, the semiconductor device 50 is embodied in the wiring boards 10, 10 </ b> A, 10 </ b> B, 10 </ b> C, and 10 </ b> D that incorporate the semiconductor element 50. For example, instead of the semiconductor element 50, for example, the semiconductor device 50 may be embodied as a wiring board incorporating electronic components such as the chip component 112 and a crystal resonator.

  In each of the above embodiments, the semiconductor element 70 is mounted on the wiring boards 10, 10 </ b> A, 10 </ b> B, 10 </ b> C, 10 </ b> D, but instead of the semiconductor element 70, for example, an electronic component such as the above-described chip component or crystal resonator May be mounted on the wiring boards 10, 10A, 10B, 10C, 10D.

In the above embodiments, the number of electronic components mounted on the wiring boards 10, 10A, 10B, 10C, and 10D is not particularly limited.
In the above embodiments, the number of electronic components built in the wiring boards 10, 10A, 10B, 10C, and 10D is not particularly limited.

1, 1A, 1B, 1C, 1D Semiconductor package 10, 10A, 10B, 10C, 10D Wiring board 20 Wiring pattern 25 Protrusion (first protrusion)
26 Protrusion (second protrusion)
30 Insulating layer (first insulating layer)
30A Insulating layer (third insulating layer)
30B Insulating layer (4th insulating layer)
30X opening (first opening, third opening)
30Y opening (fourth opening)
40,95 Substrate 41-43 Wiring layer (metal layer)
50 Semiconductor element (first electronic component)
55 Conductor wire (first conductor wire)
56, 58 Conductor wire 57 Conductor wire (second conductor wire)
51 Connection terminal 60 Insulating layer (second insulating layer)
61 Insulating layer (first insulating layer and second insulating layer)
70 Semiconductor element (second electronic component)
71, 71A to 71C Connection terminals 80, 90, 100 Support substrate 80X Recess 81 Resist layer 81X Opening (second opening)
93 Insulating layer (substrate)
94 Metal post (metal layer)
A1 housing part (space)
BD cavity part

Claims (11)

Many wiring patterns formed on the same plane;
A first insulating layer that insulates the wiring patterns and adheres the wiring patterns;
A first electronic component mounted on the lower surface side of the wiring pattern;
A second electronic component mounted on the upper surface side of the wiring pattern;
A second insulating layer formed on a lower surface of the first insulating layer and covering the entire first electronic component;
A semiconductor package characterized in that at least a part of the first electronic component and the second electronic component are linearly connected at a position overlapping in plan view via the common wiring pattern. A first protrusion formed on the lower surface of the wiring pattern;
A second protrusion formed on the upper surface of the wiring pattern,
The first insulating layer covers a side surface of the wiring pattern and a side surface of the first protrusion,
2. The semiconductor package according to claim 1, wherein the first electronic component is flip-chip bonded to the first protrusion, and the second electronic component is flip-chip bonded to the second protrusion. A plurality of the second electronic components are mounted on the upper surface side of the wiring pattern,
A first conductor wire is formed in the second insulating layer to connect the wiring patterns electrically connected to the second electronic component and to electrically connect the two second electronic components to each other. The semiconductor package according to claim 1, wherein the semiconductor package is provided. Many wiring patterns formed on the same plane;
A first insulating layer that insulates the wiring patterns and adheres the wiring patterns;
A plurality of second electronic components mounted on the upper surface side of the wiring pattern;
A first conductor wire connecting the wiring patterns electrically connected to the second electronic component on the lower surface side of the wiring pattern, and electrically connecting the two second electronic components to each other;
A second insulating layer formed on the lower surface of the first insulating layer and covering the entire first conductor wire;
A semiconductor package comprising: It has a frame-like substrate formed on the lower surface side of the wiring pattern,
The said 2nd insulating layer is formed so that the space formed by the said board | substrate, the said wiring pattern, and the said 1st insulating layer may be filled. The semiconductor package described.   The semiconductor package according to claim 5, further comprising a second conductor wire formed in the second insulating layer and electrically connecting the metal layer formed on the substrate and the wiring pattern.   The semiconductor package according to claim 1, wherein the first insulating layer and the second insulating layer are integrally formed. Preparing a support substrate;
Forming a first insulating layer having a plurality of first openings on the lower surface of the support substrate;
Forming a wiring pattern on the lower surface of the support substrate in the first opening;
Mounting a first electronic component on the lower surface side of the wiring pattern;
Forming a second insulating layer covering the entire first electronic component on the lower surface side of the wiring pattern;
Removing the support substrate;
Mounting a second electronic component on the upper surface side of the wiring pattern,
A method of manufacturing a semiconductor package, wherein at least a part of the second electronic component and the first electronic component are linearly connected at a position overlapping in plan view via a common wiring pattern. The step of forming the first insulating layer and the wiring pattern includes:
Forming a resist layer having a second opening on the lower surface of the support substrate;
Forming a recess in the lower surface of the support substrate exposed from the second opening;
Removing the resist layer;
Forming on the lower surface of the support substrate a third insulating layer having a third opening exposing a portion of the lower surface of the support substrate and the recess;
Forming a second protrusion in the recess and forming the wiring pattern in the third opening;
A fourth insulating layer having a fourth opening exposing a part of the lower surface of the wiring pattern is formed on the lower surface of the third insulating layer and the lower surface of the wiring pattern, and the third insulating layer and the fourth insulation are formed. Forming the first insulating layer including a layer;
Forming a first protrusion in the fourth opening,
The first electronic component is flip-chip bonded to the first protrusion,
9. The method of manufacturing a semiconductor package according to claim 8, wherein the second electronic component is flip-chip bonded to the second protrusion. Before the step of forming the second insulating layer,
Forming a first conductor wire electrically connecting the first wiring pattern and the second wiring pattern among the wiring patterns on the lower surface side of the wiring pattern;
The second insulating layer is formed to cover the entire first conductor wire;
A plurality of the second electronic components are mounted on the upper surface side of the wiring pattern, and the two second electronic components are electrically connected to each other by the first wiring pattern, the second wiring pattern, and the first conductor wire. 10. The method of manufacturing a semiconductor package according to claim 8, wherein the semiconductor package is connected. Preparing a support substrate;
Forming a first insulating layer having a plurality of first openings on the lower surface of the support substrate;
Forming a wiring pattern on the lower surface of the support substrate in the first opening;
Forming a first conductor wire electrically connecting the first wiring pattern and the second wiring pattern among the wiring patterns on the lower surface side of the wiring pattern;
Forming a second insulating layer covering the entire first conductor wire on the lower surface side of the wiring pattern;
Removing the support substrate;
Mounting a plurality of electronic components on the upper surface side of the wiring pattern,
The two electronic components are electrically connected to each other by the first wiring pattern, the second wiring pattern, and the first conductor wire.