JP2014120761A - Crystal silicon solar cell preventing generation of dark area due to breaking of electrode gate lines - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a crystal silicon solar cell that can ameliorate loss of electric performance due to gate break, allows finer gate lines to be designed, has a simple structure and is easily materialized.SOLUTION: An embodiment comprises a silicon chip body 1. On a surface of the silicon chip body 1, a plurality of main gate lines 2 are formed in the longitudinal direction; a plurality of fine gate lines 3 are formed in the transverse direction to electrically connect to the main gate lines 2; and a plurality of second gate lines 4 are provided to electrically connect the fine gate lines 3.

Description

  The present invention relates to a battery, and more particularly to a crystalline silicon solar battery that prevents the occurrence of dark areas due to disconnection of electrode gate lines.

  From the viewpoint of the conventional solar cell industry, electrode gate lines play an important role in crystalline silicon solar cells. This has an effect on the collection of photogenerated carriers. However, the conventional solar cell electrode design is difficult to collect the current from the part of the area that has been separated from the main gate due to the gate break when the gate line printing is not continuous due to the broken part . For this reason, the gate line transmission resistance also increases, and a dark area occurs in the EL test image. Therefore, when the electrode design of a conventional solar cell develops in a fine and dense direction, the thinner the gate line design, the greater the probability of gate break during printing. And the dead zone of the produced crystalline silicon solar cell also becomes large, which is disadvantageous for its use and promotion.

JP 2008-135655 A

In order to solve the above-described problems existing in the prior art, the present invention provides a crystalline silicon solar cell that prevents the generation of dark areas due to disconnection of electrode gate lines.
The object of the present invention is realized by the following technical solution.
Dark area due to disconnection of electrode gate line, including silicon chip, main gate lines are vertically distributed in the silicon chip body, fine gate lines are laterally distributed, and second gate lines are arranged between the fine gate lines. Crystalline silicon solar cell that prevents the generation of water.

Further, in the crystalline silicon solar cell in which the generation of dark areas due to the disconnection of the electrode gate lines is prevented, the main gate lines are distributed at equal distances.
Furthermore, in the crystalline silicon solar cell in which the generation of dark areas due to the disconnection of the electrode gate lines is prevented, the fine gate lines are distributed at equal distances.
Furthermore, in the crystalline silicon solar cell in which the generation of dark areas due to the disconnection of the electrode gate lines is prevented, the second gate lines are distributed between the fine gate lines in the linear vertical direction.

  An object of the present invention is to provide a crystalline silicon solar cell that can improve the loss of electrical performance due to a gate break and can be designed to have a finer gate line with a thinner structure, which is simple in structure and easy to realize.

  Main gate lines are distributed in the vertical direction on the silicon chip body, and fine gate lines are distributed in the horizontal direction. Then, the second gate line is provided between the fine gate lines, and a crystalline silicon solar cell in which generation of a dark area due to disconnection of the electrode gate line is prevented is obtained.

  The effect of the technical solution of the present invention can improve the electrical performance loss caused by the gate break. At the same time, the occurrence of gate break dark areas can be effectively avoided during manufacturing and use. Since the second gate line is present, the fine gate line can be designed to be thinner, the printing power consumption can be reduced, and the electrical performance can be improved. Since the present invention has features such as a simple structure and easy implementation, it is worth spreading in this field.

It is a top view (Example 1) showing the whole structure of the crystalline silicon solar cell which prevented generation | occurrence | production of the dark area by the disconnection of an electrode gate line. It is a top view (Example 2) showing the whole structure of the crystalline silicon solar cell which prevented generation | occurrence | production of the dark area by the disconnection of an electrode gate line. It is a top view (Example 3) showing the whole structure of the crystalline silicon solar cell which prevented generation | occurrence | production of the dark area by the disconnection of an electrode gate line.

  The crystalline silicon solar cell shown in FIG. 1 that prevents generation of dark areas due to disconnection of electrode gate lines includes a silicon chip body 1 and includes a main gate line 2 in the vertical direction of the silicon chip body 1. . At the same time, considering the work demand for solar cells, the fine gate lines 3 are installed in the lateral direction of the silicon chip body 1. Further, the second gate line 4 is provided between the fine gate lines 3 in order to prevent a phenomenon in which a failure occurs in the current supply due to the gate break.

In a preferred embodiment of the present invention, the main gate lines 2 are installed in parallel and the fine gate lines 3 are installed at equal intervals in order to stabilize the working efficiency of the entire battery.
Furthermore, considering the consistency of the entire installation, the second gate line 4 is arranged in a vertical shape with an interval in the vertical direction as a whole, for the convenience of processing and manufacturing. The fine gate lines 3 are arranged between the fine gate lines 3 in a vertical arrangement and distributed between the fine gate lines.

  In the actual use situation of the present invention, since the second gate line 4 exists, the second gate line 4 in one stage can be connected to the two fine gate lines 3. It is also possible to design to connect with three or more fine gate lines 3. In this way, the connection between the adjacent fine gate lines 3 can be increased. Even if the electrode gate line is cut off improperly during the manufacturing and use period, the connection can be effectively performed through the second gate line 4, and the current flows through the adjacent second gate line 4 in a short path. Can be transferred to the line.

  Further, even in a special application, it is possible to increase the number of second gate lines 4 extending over one row or multiple rows, and the fine gate lines 3 can be connected to improve the dead zone in the maximum range. At the same time, it is possible to avoid an unnecessary increase in the second gate line 4 to a certain degree, and to reduce material consumption.

  Although the number of main gate lines shown in FIG. 1 is two, the number of main gate lines is arbitrarily determined according to the actual demand and the size of the battery module, and three shown in FIG. 2 and four shown in FIG. Or it can be expanded in a four-way continuous form.

  According to the above embodiment, the present invention can improve the loss of electrical performance due to the gate break. At the same time, during the manufacturing and use period, it is possible to effectively avoid the gate break and eliminate the dark area to the maximum extent. Further, since the second gate line is provided, the fine gate line can be designed to be thinner, and the printing power consumption can be reduced and the electrical performance can be improved. Also, the structure of the present invention is simple and easy to implement, so it is worth spreading in this field.

  The embodiment described above is a typical example to which the technology of the present invention is applied, and all technical methods formed without changing the technical idea of the present invention are within the scope of the present invention. Further, the description of the embodiment does not limit the contents of the present invention.

1. Silicon chip body 2. Main gate line 3. Fine gate line 4. Second gate line

Claims (4)

  A main gate line is distributed in the vertical direction in the silicon chip main body, a plurality of fine gate lines are connected to the main gate line in the horizontal direction, and the second gate line is fine. A crystalline silicon solar cell which prevents generation of a dark area due to disconnection of an electrode gate line, wherein a fine gate line is connected between the gate lines.   2. The crystalline silicon solar cell according to claim 1, wherein the fine gate lines are distributed at equal intervals between the main gate lines, and a dark area is prevented from being generated due to disconnection of the electrode gate lines.   2. The crystalline silicon solar cell according to claim 1, wherein the second gate lines are distributed at equal intervals between the fine gate lines, and the generation of dark areas due to disconnection of the electrode gate lines is prevented.   The second gate lines are arranged vertically in the vertical direction as a whole, and are arranged in a linear shape and distributed between the fine gate lines in the vertical direction. The crystalline silicon solar cell according to claim 1, wherein generation of dark areas due to disconnection of the electrode gate lines is prevented.

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