JP2014120652A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem in the case of forming in an embedded gate transistor, an asymmetric structure in which a bit-con diffusion layer is formed deep that when ions are implanted through a bit contact hole, the ions are implanted to the diffusion layer side which is necessary to be formed shallow and intended transistor characteristics cannot be achieved.SOLUTION: A semiconductor device manufacturing method comprises: forming a space part 9-Sp in a first mask film 9 on a semiconductor substrate; forming a sidewall film 10 and performing ion implantation on a part of the semiconductor substrate 1 corresponding to just under a space 10r in the space part to form a bit-con diffusion layer 11; subsequently, filling the space 10r with a second mask film; selectively removing the sidewall film 10 by using the first mask film 9 and the second mask film 12 as masks to form a first groove corresponding to a gate trench formed on the substrate 1. By the method, the bit-con diffusion layer 11 can be formed in a self-alignment manner with the gate trench.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Currently, a DRAM (Dynamic Random Access Memory) employs a buried gate electrode as disclosed in Patent Document 1. The reason is as follows: (1) By embedding the gate electrode in the substrate, a three-dimensional channel structure can be formed, and a reduction in effective channel length accompanying miniaturization can be compensated. 2) By embedding the gate electrode in the substrate, the arrangement of contact plugs, bit lines, and capacitors installed on the substrate can be relatively easily advanced.

JP 2012-99793 A

  In Patent Document 1, as a select transistor of a DRAM memory cell, an impurity diffusion layer (referred to as a bit capacitor diffusion layer) to which a bit line is connected is formed deeply to the vicinity of the bottom of the buried gate electrode, and a capacitor element such as a capacitor and a capacitor contact An asymmetric structure is formed in which an impurity diffusion layer (referred to as a capacitor diffusion layer) connected via a shallow junction is formed. The bit-con diffusion layer is formed by forming a buried gate electrode, forming a bit-con interlayer insulating film thereon, forming a bit contact hole in the bit-con interlayer insulating film, and then using the bit-con interlayer insulating film as a mask on the substrate surface. Ion implantation is performed (see FIGS. 17 and 18 of Patent Document 1). At this time, it is influenced by the overlap between the bit contact hole pattern and the buried gate electrode pattern and the fact that the bit contact hole diameter is larger than the width of the bit capacitor diffusion layer, and through the buried gate electrode to the capacitor contact side substrate. As a result, ions may be implanted to deepen the capacitor diffusion layer that should be formed shallow, which may cause deterioration of characteristics such as STH characteristics (refresh characteristics).

Patent Document 1 also shows a mode in which a bit-con diffusion layer is formed by forming a mask for ion implantation before forming a gate trench (FIG. 24). In this case, ion implantation into the substrate on the capacitor contact side can be suppressed, but if a photolithography process for forming an ion implantation mask is added and misalignment with the gate trench occurs, the gate trenches on both sides are formed. The formed transistor characteristics may be different.
Thus, there is room for further improvement in the conventional bitcon diffusion layer forming method.

  In the present invention, the bit-con diffusion layer is formed by self-alignment when forming the trench for forming the buried gate electrode.

That is, according to one embodiment of the present invention,
Forming a first mask film on the semiconductor substrate;
Forming a space portion penetrating a part of the first mask film;
Forming a sidewall film so as to cover an upper surface of the first mask film and a side surface of the first mask film in the space portion;
Ion implantation into a portion of the semiconductor substrate corresponding to the space portion and directly under the space excluding the sidewall film covering the side surface of the first mask film;
Filling the space with a second mask film;
The sidewall film is selectively removed using the first mask film and the second mask film as a mask, and transferred to the semiconductor substrate between the first mask film and the second mask film. Forming a groove of 1;
A method for manufacturing a semiconductor device, comprising:

Also, according to another embodiment of the present invention,
Forming a plurality of active regions on a semiconductor substrate having the same shape by an element isolation layer, extending in a first direction, and aligned in a second direction intersecting the first direction; ,
Forming a plurality of line patterns extending in the second direction with a first mask film on the semiconductor substrate;
Forming a sidewall film so as to cover an upper surface and a side surface of the line pattern;
A step of ion-implanting into a part of the plurality of active regions corresponding to a space portion between the line patterns and directly under a space portion excluding a sidewall film covering a side surface of the first mask film;
There is provided a method of manufacturing a semiconductor device, wherein each of the space portions straddles an individual center point within the same space portion with respect to a plurality of active regions arranged in the second direction. .

  According to an embodiment of the present invention, an impurity diffusion layer can be formed by implanting impurities into a substrate portion corresponding to a bit contact connection portion in the course of forming a trench for a buried gate electrode by double patterning. It becomes like this. As a result, the impurity is not injected into the capacitor contact side substrate through the buried gate electrode, and there is no fear of deteriorating characteristics such as STH.

It is a figure explaining an example of the layout of the semiconductor device concerning one example of an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention, and is a cross-sectional view taken along line A-A ′ of FIG. 1. FIG. 2 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention, and is a cross-sectional view taken along line B-B ′ of FIG. 1. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention, and is a cross-sectional view of a peripheral circuit region. It is a figure explaining the other layout example of the memory cell part of the semiconductor device which concerns on one Example of this invention. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. 5A and 5B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where FIG. 5A is a cross-sectional view taken along the line AA ′ in FIG. 4, and FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIGS. 7A and 7B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where FIG. 6A is a cross-sectional view taken along line AA ′ in FIG. 6 and FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. FIGS. 7A and 7B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where FIG. 6A is a cross-sectional view taken along line AA ′ in FIG. 6 and FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. FIGS. 7A and 7B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where FIG. 6A is a cross-sectional view taken along line AA ′ in FIG. 6 and FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIGS. 11A and 11B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where FIG. 10A is a cross-sectional view taken along line AA ′ in FIG. 10 and FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIGS. 13A and 13B are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where FIG. 12A is a cross-sectional view taken along line AA ′ in FIG. 12 and FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIG. 15 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along the line AA ′ of FIG. 14, and (b) is BB ′ of FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIG. 17 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ of FIG. 16, and (b) is BB ′ of FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIG. 19 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along the line AA ′ in FIG. 18, and (b) is BB ′ in FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIG. 21 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 20, and (b) is BB ′ in FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIG. 23 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along the line AA ′ in FIG. 22, and (b) is BB ′ in FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIG. 25 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 24, and (b) is BB ′ in FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. FIG. 25 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 24, and (b) is BB ′ in FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. FIG. 25 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 24, and (b) is BB ′ in FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. FIG. 25 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 24, and (b) is BB ′ in FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIG. 30 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along the line AA ′ of FIG. 29, and (b) is BB ′ of FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. FIG. 30 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along the line AA ′ of FIG. 29, and (b) is BB ′ of FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. FIG. 30 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along the line AA ′ of FIG. 29, and (b) is BB ′ of FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. FIG. 30 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along the line AA ′ of FIG. 29, and (b) is BB ′ of FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIG. 35 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 34 and (b) is BB ′ in FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. FIG. 35 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 34 and (b) is BB ′ in FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. FIG. 35 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 34 and (b) is BB ′ in FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. 39 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 38, and (b) is BB ′ in FIG. 38; FIG. 6C is a cross-sectional view of the peripheral circuit region. 39 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 38, and (b) is BB ′ in FIG. 38; This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. 39 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 38, and (b) is BB ′ in FIG. 38; This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. 39 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 38, and (b) is BB ′ in FIG. 38; This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. 39 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 38, and (b) is BB ′ in FIG. 38; This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. 39 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 38, and (b) is BB ′ in FIG. 38; This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. 46 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 45, and (b) is BB ′ in FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. 46 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 45, and (b) is BB ′ in FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIG. 49 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 48, and (b) is BB ′ in FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. FIG. 49 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 48, and (b) is BB ′ in FIG. This corresponds to a cross-sectional view taken along a line, and (c) is a cross-sectional view of the peripheral circuit region. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, and shows the top view of a memory cell part. FIG. 52 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, where (a) is a cross-sectional view taken along line AA ′ in FIG. 51, and (b) is BB ′ in FIG. FIG. 6C is a cross-sectional view of the peripheral circuit region. FIG. 15 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to a modification of the embodiment of the present invention, where (a) is a cross-sectional view taken along the line AA ′ in FIG. 14, and (b) is B in FIG. This corresponds to a cross-sectional view taken along the line -B ', and (c) is a cross-sectional view of the peripheral circuit region.

  Hereinafter, specific embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to these embodiments. Of these figures, the aspect ratio in the sectional views is different from the actual structure.

Embodiment 1
FIG. 1 is a diagram showing a planar layout of a main part of a memory cell part and a part of a peripheral circuit part including a circuit for driving the memory cell of a semiconductor device according to an embodiment of the present invention. In the memory cell portion, the active region K forming the control transistor of the memory cell has substantially the same shape and extends in the α direction or the α ′ direction (both are referred to as the first direction), and in the Y direction (the first direction). 2 direction) in parallel with equal intervals. The diffusion layer at the center of each active region K is connected to a bit line BL extending in the X direction (third direction) via a bit contact 25P formed in the bit contact hole 24, and the sense amplifier 100 in the peripheral circuit portion. It is connected to the. On the other hand, a word line mWL serving as a gate electrode embedded in the semiconductor substrate extends in the Y direction and is connected to a word driver 200 of a peripheral circuit. In each active region K arranged in the Y direction, two word lines mWL extend over each other, and a bit-con diffusion layer in which a bit contact 25P is connected between the word lines mWL and on both outer sides of the word lines mWL. A capacitor diffusion layer connected to the capacitor contact 35 is disposed. The capacitor contact 35 is connected to the lower electrode 39 of the capacitor via the pad electrode 37. In this example, the lower electrode 39 of the capacitor is arranged in four directions at a pitch of 3F in the X direction and 2F in the Y direction. However, the present invention is not limited to this. Here, F represents a minimum processing dimension or a minimum process dimension, for example, 1F = 35 nm.

  2A is a cross-sectional view taken along line AA ′ of FIG. 1, FIG. 2B is a cross-sectional view taken along line BB ′ (word line mWL) of FIG. 1, and FIG. 2C is a cross-sectional view of a peripheral circuit portion. .

  As shown in FIG. 2A, in the memory cell portion, an element isolation layer 5 that defines an active region K is formed in a semiconductor substrate (hereinafter referred to as substrate 1) by the STI method. A conductor 19 composed of a barrier film 19a and a metal film 19b, which is insulated from the substrate 1 via a film 18, is buried to form a buried gate electrode (word line mWL). A bit capacitor diffusion layer 11 connected to the bit contact 25P is formed between the two word lines mWL, and the capacitor capacitor diffusion layer 6 connected to the capacitor contact 35 on both outer sides of the two word lines mWL. Is formed. That is, two memory cells having an asymmetric structure in which the bit capacitor diffusion layer 11 is formed deeper than the capacitor capacitor diffusion layer 6 are formed in each active region K. In this example, the trench diffusion layer 17 as shown in Patent Document 1 is formed below the word line mWL, but the trench diffusion layer 17 is not essential. In this configuration, that is, the substrate region between adjacent word lines mWL is not used as a channel region, but is replaced with a bitcon diffusion layer 11 made of a high concentration impurity, and a trench diffusion layer 17 is formed at the bottom of the gate trench. Therefore, the channel region of each transistor is formed only on the side wall of each gate trench on the side far from the bit contact 25P. As a result, one memory cell (capacitor) of the memory cells corresponding to each of the two word lines mWL (buried gate electrode 19) located in the same active region stores “1” information. Thus, when the embedded gate electrode constituting the other memory cell is repeatedly turned on and off, a disturb failure that changes the storage state of one memory cell in the “1” state to “0” can be avoided. It has become.

  On the substrate 1, there are formed a pad oxide film 2, a silicon oxide film 7a which also serves as a hard mask and a bit-con interlayer film at the time of forming a word line trench, and a buried insulating film 20 on the word line mWL which also serves as a bit-con interlayer film. On the buried insulating film 20, a bit line BL composed of a metal layer 26 and a cap layer 27, a bit line side wall 29BS on the side surface of the bit line BL, and a cover film 33 covering them are formed. A first interlayer insulating film 34 and an etching stopper film 38 are stacked on the cover film 33. The capacitor contact 35 penetrates the first interlayer insulating film 34 and reaches the capacitor diffusion layer 6 on the substrate 1. On the pad electrode 37 covered with the etching stopper film 38 on the capacitor contact 35, and on the pad electrode 37. An upper electrode 40 of the capacitor is formed through a capacitor insulating film (not shown) so as to cover the lower electrode 39 and the lower electrode 39 of the capacitor. The upper electrode 40 is connected to the upper layer wiring 43 through a contact plug 42 formed in the second interlayer insulating film 41.

  2B, the word line mWL is formed so that the bottom surface on the element isolation layer 5 is deeper than the bottom surface on the substrate 1 (active region K), and the trench diffusion layer 17 in the active region K is formed. Is formed in a saddle fin structure.

  On the other hand, in the peripheral circuit portion, as shown in FIG. 2C, an NMOS region in which an nMOS transistor is formed and a PMOS region in which a pMOS transistor is formed are provided on the substrate 1 by an element isolation layer 5. Since the substrate 1 is p-type, an n-well is formed in the PMOS region. The pMOS transistor has substantially the same configuration as that of the nMOS transistor, and a configuration having a different conductivity type is indicated by “′”. Here, an example is shown in which the drains are connected to form a CMOS. These transistors have a diffusion layer having an LDD structure composed of an LDD region 30 (30 ′) and a high concentration diffusion region 32 (32 ′), and the element isolation layer 5 is formed wider than the memory cell portion. Therefore, the first element isolation insulating film 5a and the second element isolation insulating film 5b, which are the same as the memory cell portion, are formed. The gate electrodes (PG) of both transistors have a metal layer 26 formed in the same layer as the metal layer 26 of the bit line, and gate polysilicon 22 (formed on the substrate 1 via the gate insulating film 21 ( 22 ') to form a polymetal structure.

  Next, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to FIGS. The plan view of the memory cell portion is shown as appropriate, and each will be described with reference to cross-sectional views corresponding to FIGS. 2A to 2C (NMOS regions).

  First, as shown in FIGS. 4 and 5, a pad oxide film 2 and a mask 3 are formed on a substrate 1 (p-type silicon substrate), and for element isolation having a depth of 250 to 300 nm by photolithography and dry etching. The groove 4 is formed. Here, it is set to 300 nm. 4 is a plan view of the memory cell portion, FIG. 5 is a sectional view taken along line AA ′ in FIG. 4, a sectional view taken along line BB ′, and FIG. 2C (NMOS region). Sectional drawing (c) of the peripheral circuit part corresponding to is shown. The same applies to the sectional views following the plan view.

  The memory cell portion has a strip-like active region pattern extending in a snake shape in the X direction, and the peripheral circuit portion has a mask pattern having an active region pattern in which a transistor is formed on the surface of the substrate 1. Form. As the mask 3, a single layer film or a laminated film such as a silicon nitride film, an amorphous carbon film, or an amorphous silicon film can be used. In addition, a double patterning technique can be used for forming a fine pattern of the memory cell portion as in the formation of a gate trench described later, but the details are omitted.

  Next, as shown in FIGS. 6 and 7, an insulating film is embedded in the element isolation trench 4 to form an element isolation layer 5. In the memory cell portion, the first element isolation insulating film 5a is formed by the SOD method, the flowable-CVD method, or the like so that the insulating film can be sufficiently filled in the narrow groove 4 and the wide groove 4 in the peripheral circuit portion. The second element isolation insulating film 5b is formed on the first element isolation insulating film 5a by a plasma CVD method or the like.

  The mask 3 is removed, and channel ion implantation necessary for each active region is performed. At this time, the oxide film is etched so that the active region and the outermost surface of the element isolation layer 5 are flush with each other. In the peripheral circuit portion, ion implantation for forming a n-well or a double well for forming a p-well in the n-well may be performed as desired.

  Further, as shown in FIG. 8, the peripheral circuit portion is masked with a photoresist PR1, and n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the active region K of the memory cell portion to diffuse the diffusion layer 6. Form.

  Next, as shown in FIG. 9, a hard mask layer for forming a gate trench is formed on the substrate 1. As the hard mask layer, a silicon oxide film 7a that finally becomes a part of the bit-con interlayer insulating film is formed to a thickness of 300 nm, and then an amorphous carbon film 7b having a thickness of 200 nm and a silicon nitride film 7c having a thickness of 60 nm are formed thereon. A silicon oxide film 8 having a thickness of 40 nm is formed. The silicon oxide film 7 a to the silicon nitride film 7 c are collectively referred to as a second hard mask layer 7, and the silicon oxide film 8 is referred to as a first hard mask layer 8.

  Further, as shown in FIGS. 10 and 11, a first mask film 9 is formed on the first hard mask layer 8. As the first mask film 9, an organic coating film having an antireflection function is preferably used. Here, as the first mask film 9, a bottom anti-reflection coating (BARC) film 9a not containing 200 nm of silicon and a silicon-containing BARC (Si-BARC) film 9b having a thickness of 30 nm are stacked. A photoresist PR2 is formed thereon. The photoresist PR2 is formed with openings having positions and widths extending in the Y direction and serving as both outer surfaces of the two word trenches to be formed on each active region K. That is, the opening is formed so as to pass over the center points of the active regions arranged in the Y direction.

Next, as shown in FIGS. 12 and 13, the first mask film 9 is etched using the photoresist PR2 as a mask. Etching is performed by RIE dry etching of CF ₄ / O ₂ -based gas. The photoresist PR2 disappears during the etching of the BARC film 9a, and then the etching proceeds using the Si-BARC film 9b as a mask. As a result, a space portion 9-Sp transferred from the opening of the photoresist PR2 is formed so as to penetrate the first mask film 9.

  Next, as shown in FIGS. 14 and 15, a first sidewall film 10 made of silicon oxide is formed by plasma CVD. At this time, the film is formed at a low temperature of 400 ° C. or less, for example, in a range in which the shape of the space portion 9-Sp formed in the first mask film 9 is not impaired. In the space portion 9-Sp, the first sidewall film 10 forms a space (concave portion) 10r, and the side wall surface of the concave portion 10r corresponds to the opposing inner side surfaces of the two gate trenches formed in the subsequent process. In addition, the film thickness of the first sidewall film 10 is adjusted. In this embodiment, the first sidewall film 10 is formed to a thickness of 35 nm.

  Subsequently, in the present invention, after the first sidewall film 10 is formed, ion implantation for forming the bit-con diffusion layer 11 is performed. A difference occurs in the ion irradiation range by the film thickness of the first mask film 9, and ions are preferentially implanted into the portion of the substrate 1 corresponding to the recess 10r. The film thickness and implantation conditions of the first mask film 9 are as follows. As a result, the bit-con diffusion layer 11 is formed by ion-implanting n-type impurities such as phosphorus (P) and arsenic (As) to a region deeper than the diffusion layer 6. If the ion permeability of the first and second hard mask layers is better than that of the first mask film 9, the thickness of the first mask film 9 can be reduced.

Next, as shown in FIGS. 16 and 17, the second mask film 12 is formed on the entire surface and etched back to embed the second mask film 12 in the recess 10r. As the second mask film, the same material as that of the BARC 9a used for the first mask film 9 can be used, and the etch back can be performed by RIE dry etching of CF ₄ / O ₂ gas. The upper surface of the second mask film 12 is almost the same height as the uppermost surface of the first sidewall film 10.

Next, as shown in FIGS. 18 and 19, the first sidewall film 10 is removed by dry etching. Dry etching is performed by RIE dry etching with CH ₂ F ₂ / CHF ₃ / O ₂ gas. By this dry etching, the first sidewall film 10 on the first mask film 9 and the side wall portion where the second mask film 12 is not formed is selectively removed, and a first trench corresponding to a gate trench described later is formed. A groove 13 is formed. The first hard mask layer 8 is also removed together with the first sidewall 10.

  Next, as shown in FIGS. 20 and 21, the second mask film 12 and the first mask film 9 are removed by oxygen plasma ashing. Note that the process may proceed to the next step without removing the second mask film 12 and the first mask film 9. In the first hard mask layer 8, a second groove 14 is formed by transferring the first groove 13.

Subsequently, as shown in FIGS. 22 and 23, the exposed second hard mask layer 7 is etched using the exposed first hard mask layer 8 and the first sidewall film 10 as a mask to form the second groove. A third groove 15 to which 14 is transferred is formed. The silicon nitride film 7c is RIE dry etching with CF ₄ / CHF ₃ gas, the amorphous carbon film 7b is RIE dry etching with O ₂ / Ar gas, and the silicon oxide film 7a is RIE with CHF ₃ / O ₂ gas. Perform dry etching. The pad oxide film 2 on the surface of the substrate 1 is also removed at the same time, and the surface of the substrate 1 is exposed. In the etching of the silicon oxide film 7a, the amorphous carbon film 7b mainly functions as a mask. At this stage, all the film on the amorphous carbon film 7b has been removed. Even when dry etching of the second hard mask layer 8 is performed without removing the second mask film 12 and the first mask film 9, the second mask film 12 is processed in the RIE dry etching process of the amorphous carbon film 7b. The first mask film 9 is completely eliminated. In FIG. 23B, the upper surface position 7a-s of the silicon oxide film 7a and the upper surface position 7b-s of the amorphous carbon film 7b are indicated by broken lines.

Subsequently, as shown in FIG. 24 and FIG. 25, the substrate 1 and the element isolation layer 5 are etched using the remaining second hard mask layer 7 as a mask to transfer the third groove 15 (fourth groove ( Gate trench) 16 is formed. Etching is performed by RIE dry etching with HBr / SF ₆ -based gas, and the amorphous carbon film 7b disappears during the etching. The element isolation layer 5 is etched deeper than the silicon portion of the active region, and as shown in FIG. 26B, the bottom of the gate trench 16 is formed in a saddle fin shape with the silicon portion protruding in a convex shape. . The gate trench 16 can have a depth of 150 to 200 nm from the surface of the substrate 1, and here, the element isolation layer 5 is formed to have a depth of 200 nm. In addition, this invention is not limited to such a shape, The element isolation layer 5 and the board | substrate 1 may be etched by the substantially equivalent depth. In FIG. 25B, the upper surface position 1-s of the semiconductor substrate 1 and the upper surface position 7a-s of the silicon oxide film 7a are indicated by broken lines. The same applies to FIG. 26B, FIG. 27B, and FIG. 30B described later.

  The above RIE etching process can be continuously performed while changing the etchant in the same apparatus.

  Next, as shown in FIG. 26, after the peripheral circuit portion is masked with a photoresist PR3, an n-type impurity is implanted into the memory cell region to form a trench diffusion layer 17 at the bottom of the gate trench 16 in the active region K. . Note that this step is not essential and can be omitted.

  Subsequently, as shown in FIG. 27, the substrate 1 exposed in the gate trench 16 is oxidized to form a gate insulating film 18.

  Next, as shown in FIG. 28, a conductor film 19 composed of a laminate of a TiN barrier film 19a and a W film 19b is formed.

Next, as shown in FIGS. 29 and 30, the buried gate electrode 19 is etched back so that the surface of the conductor film 19 is deeper than the surface of the substrate 1 and preferably deeper from the substrate surface than the bottom of the diffusion layer 6. (Word line mWL) is formed. Etch back can be performed by RIE dry etching of CF ₄ / Cl ₂ gas. At this time, the remaining silicon oxide film 7a of the second hard mask layer 7 is also etched back to a thickness of 20 nm.

  Next, as shown in FIG. 31, an insulating film (silicon nitride film) 20 to be a part of the bit-con interlayer film is formed on the entire surface to a thickness of 50 nm. Thus, the buried insulating film 20 is buried on the word line mWL.

  Next, as shown in FIG. 32, the buried insulating film 20, silicon oxide film 7a, and pad oxide film 2 in the peripheral circuit portion are removed, and a gate insulating film 21 is formed on the substrate 1 in the peripheral circuit portion by thermal oxidation. . At this time, the surface of the buried insulating film 20 is also oxidized (reference numeral 21 '). Further, a gate polysilicon film 22 having a thickness of 50 nm and a silicon oxide film 23 having a thickness of 50 nm are formed.

  Subsequently, as shown in FIG. 33, after the peripheral circuit portion is masked with the photoresist PR3, the silicon oxide film 23 and the gate polysilicon film 22 in the memory cell portion are removed. At this time, the surface of the buried insulating film 20 is also etched to a thickness of 40 nm.

  Next, as shown in FIGS. 34 and 35, a bit contact hole 24 is opened in the memory cell portion with a groove pattern extending in the Y direction between two word lines mWL. In the prior art, after the bit contact hole 24 is opened, ions are implanted into the exposed substrate 1 to form a bit capacitor diffusion layer. Therefore, due to misalignment of the bit contact hole 24, ions are also formed on the capacitor diffusion layer side. In the present invention, since the bit capacitor diffusion layer 11 is formed in a self-aligning manner using a mask for forming the gate trench, impurity ions are implanted into the capacitor diffusion layer side. It is not gone. Here, the bit contact hole 24 is formed as a groove pattern extending in the Y direction across each active region K. However, the present invention is not limited to this, and the bit contact diffusion layer 11 is exposed. It may be formed individually.

  Next, as shown in FIG. 36, a polysilicon film 25 for bit contact is formed. Subsequently, as shown in FIG. 37, the polysilicon film 25 is etched back to expose the buried insulating film 20. At this time, the buried insulating film 20 is also etched back, and the film thickness on the silicon oxide film 7a is reduced to 15 nm. In the peripheral circuit portion, the silicon oxide film 23 is removed after the etch back. When the bit contact holes 24 are individually formed, bit contacts are formed by the polysilicon film 25 at this stage.

  Next, as shown in FIGS. 38 and 39, a metal film 26 made of a laminate of a TiN barrier film and a W film to be a bit line, a cap insulating film 27 made of a silicon nitride film, and an oxide film hard mask 28 are formed. Then, a mask pattern of photoresist PR4 is formed on the bit line pattern in the memory cell portion and on the gate electrode pattern in the peripheral circuit portion.

  Next, as shown in FIG. 40, the oxide film hard mask 28 is etched using the photoresist PR4 as a mask, and the cap insulating film 27 is further etched using the oxide film hard mask 28 as a mask. Subsequently, as shown in FIG. 41, the metal film 26 and the gate polysilicon film 22 are etched using the remaining oxide film hard mask 28 and the cap insulating film 27 as a mask. When the bit contact hole 24 of the memory cell portion is formed in a line pattern, the bit polysilicon film 25 is also etched simultaneously with the gate polysilicon film 22 to be separated as the bit contact 25P.

  Subsequently, after forming a second sidewall film 29 made of silicon nitride on the entire surface as shown in FIG. 42, the memory cell portion is masked with a photoresist PR5 as shown in FIG. The second sidewall film 29 is etched back to form the first LDD sidewall 29S. Further, the LDD region 30 is formed by ion implantation into the peripheral circuit portion. The LDD region 30 is implanted with ions of different conductivity types for PMOS and NMOS.

  Next, as shown in FIG. 44, a third sidewall film 31 made of silicon oxide for forming the LDD structure of the peripheral circuit portion is formed. In the memory cell portion, the bit line BL is filled with the third sidewall film 31.

  Next, as shown in FIGS. 45 and 46, the peripheral circuit portion is masked with a photoresist PR6, the third sidewall film 31 in the memory cell portion is selectively removed, and then the second sidewall film 31 is etched. The bit line side wall 29BS is formed by backing.

  Next, as shown in FIG. 47, the memory cell portion is masked with a photoresist PR7, and the third sidewall film 31 is etched back to form the second LDD sidewall 31S. Further, ions are implanted into the peripheral circuit portion to form the high concentration diffusion layer region 32. The heavily doped diffusion region 32 is also implanted with ions of different conductivity types for PMOS and NMOS.

  As shown in FIGS. 48 and 49, a cover nitride film 33 is formed on the entire surface. Subsequently, as shown in FIG. 50, a first interlayer insulating film 34 made of silicon oxide is formed on the entire surface by the SOD method. Thereafter, as shown in FIGS. 51 and 52, in the memory cell portion, a capacitor contact hole connected to the capacitor capacitor diffusion layer 6 is formed, and a capacitor contact 35 is formed. In the peripheral circuit portion, contact holes connected to the high concentration diffusion layer regions (source / drain regions) 32 are formed, and source / drain contacts 36 are formed. Here, although the capacitor contact 35 is shown as a single plug structure, it may be a composite plug structure of a polysilicon plug connected to the substrate and a metal plug connected to the polysilicon plug via a metal silicide. The source / drain contact 36 in the peripheral circuit portion can be a metal plug made of a laminate of a barrier film and tungsten, and a metal silicide can be formed at a connection portion with the high concentration diffusion layer region 32.

  Thereafter, by a well-known method, a conductor wiring that becomes a capacitor pad 37 in the memory cell portion and a first wiring 37a in the peripheral circuit portion is formed, covered with an etching stopper film 38, and a capacitor Cap is formed in the memory cell portion. After the capacitor is formed, the second interlayer insulating film 41, the contact plugs 42 and 42a, and the upper layer wirings 43 and 43a are formed, thereby completing the semiconductor device shown in FIGS.

In this embodiment, the second hard mask layer 7 has a three-layer structure of a silicon oxide film 7a, an amorphous carbon film 7b, and a silicon nitride film 7c, but is not limited to this. For example, the two-layer structure of the silicon oxide film 7a and the silicon nitride film 7c can be used without forming the amorphous carbon film 7b in the second hard mask layer 7. At this time, for example, the thickness of the silicon nitride film 7c is changed from 60 nm to 80 nm so that the silicon oxide film 7a is not etched in a portion other than the third groove 15 penetrating the second hard mask layer 7. To do. FIG. 53 is a process cross-sectional view of this modification example corresponding to the process of FIGS. 14 and 15. By not forming the amorphous carbon film 7b, the number of processes can be reduced. Note that by increasing the thickness of the silicon nitride film 7c without forming the amorphous carbon film 7b, a part of the silicon nitride film 7c remains at the stage where the third groove 15 is exposed to the substrate surface. After the remaining silicon nitride film 7c is removed by hot phosphoric acid, the subsequent steps can be performed.

  In the above description, an example in which the word line mWL of the DRAM and the bit-con diffusion layer 11 are formed in a self-aligned manner has been described. However, the present invention is not limited to this and can be applied to similar flows of other products.

  In that case, instead of the organic coating film such as BARC used as the first mask film 9 and the second mask film 12 in the above embodiment, a material having an etching selectivity with the first sidewall film 10 may be used. good. However, in order to form the fine space portion 9-sp, it is indispensable to prevent reflection under the photoresist, and the use of the first mask film 9, particularly BARC, is recommended. On the other hand, the second mask film 12 is not limited to the first mask film as long as it can be embedded in the concave portion 10r that is further finer than the fine space portion 9-sp.

  In the present invention, the shape and arrangement of the active regions in the memory cell portion are not limited to the layout example shown in FIG. 1, and all the active regions K are in the first direction (X ′ direction) as shown in FIG. In this case, the active regions K are arranged at a predetermined interval in the Y direction, and two word lines mWL extending in the Y direction are formed. Is arranged across the active region K, and the bit line BL extending in the X direction is disposed passing over the bit-con diffusion layer sandwiched between the two word lines mWL of each active region. In this example, the lower electrode constituting the capacitor (Cap) is arranged in six directions.

1. 1. Semiconductor substrate 2. Pad oxide film Mask 4. 4. Element isolation groove Element isolation layer 5a. First element isolation insulating film 5b. Second element isolation insulating film 6. Diffusion layer (capacity diffusion layer)
7). Second hard mask layer 7a. Silicon oxide film 7b. Amorphous carbon film 7c. 7. Silicon nitride film First hard mask layer (silicon oxide film)
9. First mask film 9a. BARC
9b. Si-BARC
9-Sp. Space part 10. First sidewall film 10r. Space (concave)
11. Bitcon diffusion layer 12. Second mask film (BARC)
13. First groove 14. Second groove 15. Third groove 16. Fourth groove (gate trench)
17. Trench diffusion layer 18. Gate insulating film 19. Conductive film 19a. TiN barrier film 19b. Tungsten film 20. Embedded insulating film 21. Gate insulating film 22. Gate polysilicon film 23. Silicon oxide film 24. Bit contact hole 25. Bit polysilicon film 25P. Bit contact 26. Metal layer 27. Cap insulating film 28. Silicon oxide film 29. Second sidewall film 29S. First LDD sidewall 29BS. Bit line sidewall 30. LDD region 31. Third sidewall film 31S. Second LDD sidewall 32. High concentration diffusion layer region 33. Cover nitride film 34. First interlayer insulating film 35. Capacitive contact 36. Source / drain contact 37. Capacitance pad 37a. First wiring 38. Etching stopper film 39. Lower electrode 40. Upper electrode 41. Second interlayer insulating films 42, 42a. Contact plugs 43, 43a. Upper layer wiring Active region mWL. Word line (buried gate electrode)
BL. Bit line Cap. Capacitor PG. Peripheral gate electrodes PR1-7. Photo resist

Claims (20)

Forming a first mask film on the semiconductor substrate;
Forming a space portion penetrating a part of the first mask film;
Forming a sidewall film so as to cover an upper surface of the first mask film and a side surface of the first mask film in the space portion;
Ion implantation into a portion of the semiconductor substrate corresponding to the space portion and directly under the space excluding the sidewall film covering the side surface of the first mask film;
Filling the space with a second mask film;
The sidewall film is selectively removed using the first mask film and the second mask film as a mask, and transferred to the semiconductor substrate between the first mask film and the second mask film. Forming a groove of 1;
A method for manufacturing a semiconductor device, comprising: Forming a first hard mask layer between the first mask film and the semiconductor substrate;
The first hard mask layer is selectively removed using the first mask film and the second mask film as a mask, and the first groove is transferred into the first hard mask layer to form a second The method for manufacturing a semiconductor device according to claim 1, wherein the groove is formed. Forming a second hard mask layer between the first hard mask layer and the semiconductor substrate;
Using the first hard mask layer as a mask, the second hard mask layer is selectively removed, and the second groove is transferred into the second hard mask layer to form a third groove. The method of manufacturing a semiconductor device according to claim 2.   4. The fourth groove is formed by selectively removing the semiconductor substrate using the second hard mask layer as a mask and transferring the third groove into the semiconductor substrate. The manufacturing method of the semiconductor device as described in 2.   The method for manufacturing a semiconductor device according to claim 4, wherein a conductive film is formed in the fourth groove.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the conductive film is etched back so that the height of the outermost surface is lower than the height of the outermost surface of the semiconductor substrate.   The method for manufacturing a semiconductor device according to claim 6, wherein after the conductive film is etched back, an insulating film is formed so as to cover the conductive film. Forming a plurality of active regions on the semiconductor substrate having the same shape by an element isolation layer, extending in a first direction, and aligned in a second direction intersecting the first direction; Have
The space portion formed in the first mask film is a groove pattern extending in the second direction, and each central point of a plurality of active regions arranged in alignment in the second direction is defined as a space pattern. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is straddled.   The step of filling the space with the second mask film includes forming the second mask film on the sidewall film and then setting the height of the outermost surface of the second mask film to the outermost surface of the sidewall film. The method of manufacturing a semiconductor device according to claim 1, wherein the etching back is performed so as to match the height of the semiconductor device.   10. The semiconductor device according to claim 1, wherein the first mask film is a stacked film in which a BARC layer not containing Si and a BARC layer containing Si are sequentially formed. Production method. The first hard mask layer is a silicon oxide film;
The second hard mask layer is a laminated film in which a silicon oxide film, amorphous carbon, and a silicon nitride film are sequentially formed, or a laminated film in which a silicon oxide film and a silicon nitride film are sequentially formed. A method for manufacturing a semiconductor device according to any one of claims 3 to 7.   The method for manufacturing a semiconductor device according to claim 1, wherein the sidewall film is a silicon oxide film formed by a low temperature plasma CVD method. Forming a plurality of active regions on a semiconductor substrate having the same shape by an element isolation layer, extending in a first direction, and aligned in a second direction intersecting the first direction; ,
Forming a plurality of line patterns extending in the second direction with a first mask film on the semiconductor substrate;
Forming a sidewall film so as to cover an upper surface and a side surface of the line pattern;
A step of ion-implanting into a part of the plurality of active regions corresponding to a space portion between the line patterns and directly under a space portion excluding a sidewall film covering a side surface of the first mask film;
A method of manufacturing a semiconductor device, characterized in that each of the space portions straddles each central point within the same space portion with respect to a plurality of active regions arranged in alignment in the second direction. Burying the plurality of spaces with a second mask film;
A sidewall film is selectively removed using the first mask film and the second mask film as a mask, and transferred to the semiconductor substrate between the first mask film and the second mask film. Forming a groove of
The method of manufacturing a semiconductor device according to claim 13, comprising: Forming a first hard mask layer between the first mask film and the semiconductor substrate;
The first hard mask layer is selectively removed using the first mask film and the second mask film as a mask, and the first groove is transferred into the first hard mask layer to form a second The method of manufacturing a semiconductor device according to claim 14, wherein a groove is formed. Forming a second hard mask layer between the first hard mask layer and the semiconductor substrate;
Using the first hard mask layer as a mask, the second hard mask layer is selectively removed, and the second groove is transferred into the second hard mask layer to form a third groove. The method of manufacturing a semiconductor device according to claim 15.   17. The fourth groove is formed by selectively removing the semiconductor substrate using the second hard mask layer as a mask and transferring the third groove into the semiconductor substrate. The manufacturing method of the semiconductor device as described in 2.   The fourth groove includes two fourth grooves from the first part to the third part of each of the plurality of active regions arranged on the semiconductor substrate and arranged in the second direction. The second part sandwiched between the two fourth grooves corresponds to the ion-implanted part, and is a diffusion layer formed in the first part and the third part. The method for manufacturing a semiconductor device according to claim 17, wherein a deeper diffusion layer is formed.   19. The method of manufacturing a semiconductor device according to claim 18, wherein a first contact plug is formed on the second portion, and a second contact plug is formed on the first portion and the third portion. .   20. The method of manufacturing a semiconductor device according to claim 19, wherein a bit wiring is formed on the first contact plug, and a capacitor is formed on the second contact plug.

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