JP2014119822A - Constant current generation circuit and microprocessor including the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem with a conventional semiconductor device, in which a constant current having high-precision temperature characteristics cannot be generated.SOLUTION: A constant current generation circuit includes: a reference voltage generation unit 12 that corrects a curvature of a first fluctuating voltage Vf to temperature and generates, on the basis of the first fluctuating voltage Vf, a second fluctuating voltage Vrefc having a fluctuation rate to temperature according to the temperature characteristics of a current setting resistor that sets the current value of an output current Iout; and a current generation unit 13 that generates output current on the basis of the second fluctuating voltage Vrefc and the current setting resistor Ri.

Description

  The present invention relates to a constant current generation circuit and a microprocessor including the constant current generation circuit, and more particularly to a constant current generation circuit that outputs a current having a stable current value against temperature fluctuation and a microprocessor including the constant current generation circuit.

  In a semiconductor device, elements such as a transistor, a resistor, and a capacitor are formed on a semiconductor substrate. Each element has a temperature characteristic that changes depending on the substrate temperature. The circuit characteristics may change depending on the temperature characteristics of each element. For example, in an oscillation circuit that determines the oscillation frequency of an output signal using a time constant determined by the resistance value of a resistor and the capacitance value of a capacitor, the oscillation frequency varies according to the temperature characteristics of the resistor. In such an oscillation circuit, in order to suppress fluctuations in the oscillation frequency, it is necessary to take measures such as suppressing fluctuations in resistance value due to temperature characteristics.

  Therefore, Patent Document 1 discloses a technique for suppressing the oscillation frequency due to the temperature characteristic of the resistor. In the oscillation circuit described in Patent Document 1, two resistors having different temperature characteristics are used, and the oscillation frequency is determined according to the difference between the resistance values of the two resistors. At this time, in the oscillation circuit described in Patent Document 1, the resistance values of the two resistors are set so that the temperature fluctuation of the first resistance value is offset by the temperature fluctuation of the second resistance value, thereby depending on the temperature. Reduce oscillation frequency fluctuations.

JP-T-2006-510309

  In the technique described in Patent Document 1, temperature fluctuations in the resistance values of each other are offset by two resistances having different rates of change with respect to the temperature. However, since the resistors having different rates of temperature change are formed from different members, they are different. The manufacturing variation is shown. For this reason, when such different manufacturing variations occur, it is difficult to inspect which resistance error or voltage error is caused by the manufacturing variation of the resistor, and it is difficult to inspect by a correction means such as trimming. The resistance value cannot be corrected. That is, the technique described in Patent Document 1 has a problem that the temperature variation of the resistance value cannot be sufficiently suppressed.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the constant current generation circuit corrects the curvature of the first fluctuation voltage with respect to the temperature, and changes the fluctuation ratio with respect to the temperature according to the temperature characteristic of the current setting resistor that sets the current value of the output current. A reference voltage generation unit that generates a second fluctuation voltage based on the first fluctuation voltage, and a current generation unit that generates an output current based on the second fluctuation voltage and a current setting resistor. .

  In addition, what replaced the apparatus of the said embodiment with the method and the system, etc. are effective as an aspect of this invention.

  According to the constant current generation circuit and the microprocessor including the same according to the present invention, the temperature fluctuation of the output current can be accurately improved by the adjustment process.

1 is a block diagram of a constant current generation circuit according to a first exemplary embodiment; 6 is a graph showing the resistance value dependency of the second resistance of the temperature fluctuation of the forward voltage of the temperature fluctuation voltage generation unit according to the first embodiment; 6 is a graph showing the resistance value dependency of the second resistance of the curvature of the forward voltage of the temperature fluctuation voltage generation unit according to the first embodiment; 6 is a graph showing a difference in temperature fluctuation of the second fluctuation voltage due to a difference in output tap of the slope adjustment unit of the constant current generation circuit according to the first exemplary embodiment; 3 is a graph showing a temperature variation of a current setting resistor of a current generation unit of the constant current generation circuit according to the first exemplary embodiment; 6 is a graph showing a difference in temperature fluctuation of an output current due to a difference in voltage extraction point of a second fluctuation voltage in the slope adjustment unit of the constant current generation circuit according to the first exemplary embodiment; 4 is a graph showing a difference in temperature variation of output current depending on the presence or absence of a sealing material of a semiconductor chip on which the constant current generating circuit according to the first embodiment is formed. 3 is a flowchart showing a setting value setting procedure in the constant current generation circuit according to the first exemplary embodiment; 3 is a flowchart illustrating a procedure for setting a curvature setting value in the constant current generation circuit according to the first exemplary embodiment; 3 is a flowchart showing a procedure for setting a slope setting value in the constant current generation circuit according to the first exemplary embodiment; FIG. 3 is a block diagram of a constant current generation circuit according to a second exemplary embodiment. FIG. 6 is a block diagram of a microprocessor according to a third embodiment. FIG. 6 is a block diagram illustrating an example of an oscillation circuit according to a third embodiment. 14 is a timing chart illustrating an operation of the oscillation circuit illustrated in FIG. 13. FIG. 6 is a block diagram showing another example of the oscillation circuit according to the third exemplary embodiment. 16 is a timing chart showing an operation of the control circuit of the oscillation circuit shown in FIG. 16 is a timing chart showing an operation of the oscillation circuit shown in FIG. 10 is a flowchart illustrating a startup procedure of a microprocessor according to a third embodiment; FIG. 6 is a circuit diagram of a delay circuit according to a fourth embodiment; 10 is a timing chart illustrating an operation of the delay circuit according to the fourth exemplary embodiment; FIG. 10 is a circuit diagram of an output circuit according to a fifth embodiment;

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In addition, each element described in the drawings as a functional block for performing various processes can be configured by a CPU, a memory, and other circuits in terms of hardware. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a constant current generation circuit 1 according to the first exemplary embodiment. As illustrated in FIG. 1, the constant current generation circuit 1 includes a temperature fluctuation voltage generation unit 10, a reference voltage generation unit (for example, a constant voltage generation unit 11), a reference voltage generation unit 12, and a current generation unit 13.

  The temperature fluctuation voltage generation unit 10 generates a first fluctuation voltage whose voltage value fluctuates with respect to temperature. In the present embodiment, the temperature fluctuation voltage generation unit 10 includes a diode Di, and outputs the forward voltage Vf of the diode Di as the first fluctuation voltage (hereinafter referred to as the first fluctuation voltage Vf). The diode has a cathode connected to a first power supply terminal (for example, a ground terminal), and generates a first fluctuation voltage Vf at the anode. The first fluctuation voltage Vf generated by the diode Di is a forward voltage of the diode and has a fluctuation rate of about −2 mV / ° C. (temperature characteristic negative with respect to temperature). The temperature fluctuation voltage generator 10 may generate a first fluctuation voltage having a positive temperature characteristic, and the fluctuation rate of the first fluctuation voltage with respect to the temperature is a characteristic of an element or circuit to be used. It can be set according to.

  As the diode Di, a PN junction diode between the emitter and base of a parasitic PNP bipolar transistor using a standard CMOS process PMOS transistor structure can be used. By using an emitter-base PN junction diode as the diode Di], the diode Di can be formed in the chip without adding a process in the manufacturing process.

  The constant voltage generator 11 generates a reference voltage Vconst that has a smaller fluctuation amount than the first fluctuation voltage Vf with respect to the temperature. In the present embodiment, a band gap voltage source that generates the reference voltage Vconst based on the band gap voltage is used as the constant voltage generation unit 11. The reference voltage Vconst has a substantially constant voltage with respect to the temperature, with the fluctuation with respect to the temperature being much smaller than the first fluctuation voltage Vf. The reference voltage Vconst may be generated by a circuit other than the band gap voltage source (for example, a resistance voltage dividing circuit).

  The reference voltage generator 12 generates a second fluctuation voltage Vrefc based on the first fluctuation voltage Vf. More specifically, the reference voltage generation unit 12 generates the second fluctuation voltage Vrefc based on the reference voltage Vconst and the first fluctuation voltage Vf. At this time, the reference voltage generation unit 12 corrects the curvature component with respect to the temperature among the fluctuation components of the first fluctuation voltage, and further, the fluctuation ratio with respect to the temperature of the second fluctuation voltage Vrefc and a current setting resistance Ri described later. A difference between the variation rate of the resistance value with respect to the temperature is set within a preset first specified range.

  The reference voltage generation unit 12 includes a first error amplifier (for example, error amplifier 21), an output transistor P1, a first resistor R1, a second resistor R2, a slope adjustment unit 22, and a curvature correction unit 25. The reference voltage generation unit 12 includes an amplifier whose amplification factor is set based on the ratio between the first resistance and the second resistance using these components. In this embodiment, this amplifier is an inverting amplifier.

  The output transistor P1 has one terminal (for example, source) connected to the second power supply. The first resistor R1 and the second resistor R2 are connected in series between the other terminal (for example, the drain) of the output transistor P1 and the anode of the diode Di. The error amplifier 21 is connected to the control terminal (for example, gate) of the output transistor P1 based on the difference between the feedback voltage generated at the node connecting the first resistor R1 and the second resistor R2 and the reference voltage Vcont. Give a control signal. In the present embodiment, in the error amplifier 21, the feedback voltage is input to the non-inverting input terminal, and the reference voltage Vconst is input to the inverting input terminal. That is, the error amplifier 21, the output transistor P1, the first resistor R1, and the second resistor R2 constitute an inverting amplifier that operates using the reference voltage Vconst as a bias voltage and the first fluctuation voltage Vf as an input voltage.

  In the reference voltage generation unit 12, a plurality of slope adjustment voltages generated at connection points of a plurality of slope adjustment resistors R11 to R1m (m is an integer) constituting the first resistor R1 as an output signal of the inverting amplifier. A voltage selected from (e.g., slope adjustment voltages V11 to V1m and V0) is output. The variation gradient of the resistance value with respect to the temperature of the plurality of gradient adjustment voltages V11 to V1m is the same as the variation gradient of the resistance value with respect to the temperature of the current setting resistor Ri. When the fluctuation slope of the first fluctuation voltage Vf with respect to the temperature and the fluctuation slope of the resistance value of the current setting resistor Ri are in the same fluctuation direction, the fluctuation inclination with respect to the temperature of the plurality of inclination adjustment voltages V11 to V1m is the first. The fluctuation direction is the same as the fluctuation slope of the fluctuation voltage Vf. On the other hand, when the fluctuation slope with respect to the temperature of the first fluctuation voltage Vf and the fluctuation slope of the resistance value of the current setting resistor Ri are in opposite fluctuation directions, the fluctuation inclination with respect to the temperature of the plurality of inclination adjustment voltages V11 to V1m is: The inclination direction is opposite to the fluctuation slope of the first fluctuation voltage Vf. That is, the inclination direction of the variation rate with respect to the temperature of the plurality of inclination adjustment voltages V11 to V1m is determined according to the inclination direction of the current setting resistor Ri. Note that the slope adjustment voltage V0 is practically the same voltage value as the reference voltage Vconst and has very little variation with respect to temperature.

  The inclination adjusting unit 22 adjusts an inclination component with respect to the temperature among the fluctuation components of the first fluctuation voltage Vf, and the difference between the resistance value of the current setting resistor Ri and the fluctuation rate with respect to the temperature is within a preset specified range. A second fluctuation voltage Vrefc having a fluctuation rate with respect to the temperature of the voltage value is output. More specifically, the inclination adjusting unit 22 outputs a voltage selected from the plurality of inclination adjusting voltages V11 to V1m and V0 generated in the first resistor as the second fluctuation voltage Vrefc.

  The inclination adjusting unit 22 includes a first decoder 23, a first storage unit (for example, a memory 24), and switches SW11 to SW1m and SW0. The memory 24 is a storage unit that stores inclination setting values. The memory 24 may be a non-volatile memory such as a flash memory, a fuse circuit that holds a value due to destruction of a physical element, or a volatile memory such as a DRAM. This inclination setting value is determined based on the value measured in the inspection process, and is written in the memory 24. Further, although the memory 24 is illustrated in FIG. 1 as a separate block from the memory 27 described later, the memory 24 and the memory 27 may be mounted as separate areas in the same memory.

  One ends of the switches SW11 to SW1m are respectively connected to output taps (connection points connecting the slope setting resistors R11 to R1m) where the slope adjustment voltages V11 to V1m are generated. One end of the switch SW0 is connected to an output tap for generating the slope adjustment voltage V0.

  The first decoder 23 selects any one of the switches SW11 to SW1m and SW0 based on the inclination setting value read from the memory 24, and closes the selected switch. In other words, the slope control unit 22 selects one of the plurality of slope adjustment voltages generated at the plurality of output taps provided at the connection points of the plurality of resistors constituting the first resistor R1, and performs the second variation. Output as voltage Vrefc. The slope setting value sets the slope of the second fluctuation voltage.

  The curvature correction unit 25 switches the magnitude of the current flowing per unit area of the diode Di according to the curvature setting value that determines the magnitude of the current flowing in the diode Di. Then, the curvature correction unit 25 corrects the curvature component with respect to the temperature among the fluctuation components of the first fluctuation voltage Vf. More specifically, the curvature correction unit 25 controls the current flowing through the second resistor R2 according to the curvature setting value. The curvature correction unit 25 realizes the above function by including a decoder (for example, the second decoder 26), a second storage unit (for example, the memory 27), and a plurality of switches. The curvature setting value is a value for setting a correction amount of the curvature component.

  In the first embodiment, the second resistor R2 is configured by a plurality of curvature adjusting resistors R21 to R2n (n is an integer) connected in series. Therefore, in Embodiment 1, each of the plurality of switches is connected in parallel with any one of the plurality of curvature adjustment resistors R21 to R2n. The plurality of switches are configured by NMOS transistors MN11 to MN1n.

  The second decoder 26 controls the open / closed states of the plurality of switches according to the curvature setting value. More specifically, the second decoder 26 determines which of the NMOS transistors MN11 to MN1n is turned on according to the curvature setting value, and the NMOS transistors MN11 to MN1n that are turned on. Control the number.

  The memory 27 is a storage unit that stores a curvature setting value. The memory 27 may be a non-volatile memory such as a flash memory, a fuse circuit that holds a value due to destruction of a physical element, or a volatile memory such as a DRAM. This curvature setting value is determined based on the value measured in the inspection process and written in the memory 27. Further, the memory 27 may be implemented as a single storage unit including the memory 24. In this case, the memory 27 is defined as a part of the storage unit.

  The current generator 13 includes a current setting resistor Ri whose resistance value varies with temperature, and generates an output current Iout based on the second variable voltage Vrefc and the current setting resistor Ri. The current generator 13 includes a second error amplifier (for example, error amplifier 25), a first transistor (for example, PMOS transistor P2), a second transistor (for example, PMOS transistor P3), and a current setting resistor Ri.

  For example, the current setting resistor Ri has a temperature characteristic in which the resistance value is positive with respect to the temperature. The PMOS transistor P2 has a drain connected to a first power source (for example, a power source that supplies the ground voltage VSS) via a current setting resistor Ri, and a source to a second power source (for example, a power source that supplies the power source voltage VDD). Is connected. The error amplifier 25 gives an error voltage to the gate of the PMOS transistor P2 based on the voltage difference between the current setting voltage generated at the node between the PMOS transistor P2 and the current setting resistor Ri and the second fluctuation voltage Vrefc. Then, the PMOS transistor P2 outputs a current to the current setting resistor so that the voltage generated at both ends of the current setting resistor Ri based on the error voltage becomes the second fluctuation voltage Vrefc. Here, in the current generator 13, the current setting voltage generated at the node between the drain of the PMOS transistor P 2 and the current setting resistor Ri is the same voltage as the second fluctuation voltage Vrefc due to the virtual short circuit of the error amplifier 25. Value.

  The PMOS transistor P3 is connected to the PMOS transistor P2 as a current mirror. The PMOS transistor P3 outputs a current proportional to the current that the PMOS transistor P2 passes through the current setting resistor Ri as an output current. The ratio of the current flowing through the PMOS transistor P2 and the current flowing through the PMOS transistor P3 is determined by the transistor size ratio of the two transistors. For example, when the transistor size ratio is 1: 1, the current flowing through the PMOS transistor P2 is the same as the current flowing through the PMOS transistor P3. When the transistor size ratio is 1: 2, the current flowing through the PMOS transistor P3 is This is twice the current flowing through the PMOS transistor P2. The transistor size ratio is determined by the ratio of the gate widths if the gate lengths of the PMOS transistors P2 and P3 are the same. When a PNP transistor is used instead of the PMOS transistors P2 and P3, the transistor size is determined by the area ratio of the emitter of the PNP transistor.

  Next, the operation of the constant current generation circuit 1 according to the first embodiment will be described. First, the characteristics of the temperature fluctuation voltage generation unit 10 (for example, the diode Di) that generates the first fluctuation voltage Vf will be described. Therefore, FIG. 2 is a graph showing the resistance dependence of the second resistor R2 on the temperature variation of the forward voltage (for example, the first temperature variation voltage Vf) of the temperature variation voltage generator 10 according to the first embodiment. Show.

  In the graph shown in FIG. 2, the reference voltage Vconst that sets the voltage at the connection point where the second resistor R2 and the first resistor R1 are connected is made constant, and the resistance value of the second resistor R2 is changed. It is a thing. The set width of the second resistor R2 is extremely larger than the normally used set width. In the reference voltage generator 12, the current flowing through the diode Di is changed by changing the resistance value of the second resistor R2, and the curvature of the first fluctuation voltage Vf is corrected. This is to make it easier.

  As shown in FIG. 2, the forward voltage (first fluctuation voltage Vf) of the diode Di decreases as the temperature increases. The first fluctuation voltage Vf increases as the second resistance R2 increases, that is, as the current flowing through the diode Di decreases. Furthermore, the first variable voltage Vf has a characteristic that the curvature increases as the current flowing through the diode Di increases. A graph showing the change in curvature is shown in FIG.

  FIG. 3 shows the first fluctuation voltage Vf when the temperature Tj of the semiconductor substrate is kept constant at 55 ° C. and the current flowing through the diode Di is changed (that is, when the resistance value of the second resistor R2 is changed). Is a graph of the curvature of. As shown in FIG. 3, the curvature of the first fluctuation voltage has a feature that the smaller the current flowing through the diode Di, the smaller the curvature. That is, the diode Di generates the first fluctuation voltage Vf having a different curvature by increasing or decreasing the current flowing per unit area of the diode Di. In the constant current generation circuit 1 according to the first embodiment, the curvature of the first fluctuation voltage Vf with respect to the temperature is corrected by adjusting the current flowing through the diode Di by the curvature correction unit 25.

  Next, FIG. 4 is a graph showing a difference in temperature fluctuation of the second fluctuation voltage Vrefc due to a difference in voltage selected by the slope adjustment unit 22 of the constant current generation circuit 1. In the example shown in FIG. 4, the resistance value of the inclination adjusting resistor constituting the first resistor R1 is set to the same resistance value. As shown in FIG. 4, the slope adjustment voltages V11 to V1m, V0 have different slopes with respect to temperature fluctuations depending on the ratio of the upper resistance and the lower resistance of the node provided with the output tap. On the other hand, the gradient adjustment voltages V11 to V1m generated in the first resistor R1 all have a positive gradient in temperature characteristics (a gradient in which the voltage value increases as the temperature rises).

  Subsequently, FIG. 5 shows a graph showing the temperature variation of the current setting resistor Ri of the current generator 13 of the constant current generator 1 according to the first embodiment. As shown in FIG. 5, the current setting resistor Ri has a positive temperature characteristic in which the resistance value increases as the temperature rises.

  In the constant current generation circuit 1 according to the first exemplary embodiment, the slope adjustment unit 22 selects any one of the voltages illustrated in FIG. 4 and outputs the selected voltage as the second fluctuation voltage Vrefc. The second fluctuation voltage Vrefc can be considered as a voltage obtained by adjusting the rate of change of the first fluctuation voltage Vf with respect to the temperature fluctuation. In the constant current generating circuit 1 according to the first embodiment, the output tap voltage to be output as the second fluctuation voltage Vrefc is selected based on the slope setting value stored in the memory 24. Then, the constant current generation circuit 1 selects, as the second fluctuation voltage Vrefc, the voltage having the same fluctuation rate with respect to the temperature fluctuation as the current setting resistance Ri, according to the slope setting value. By doing so, the current value of the output current Iout becomes constant regardless of temperature fluctuations.

Here, the principle that the output current Iout is constant will be described using equations. First, the output current Iout when the transistor size ratio of the PMOS transistors P2 and P3 is 1: 1 can be expressed by the equation (1). In equation (1), the current value of the output current is represented by Iout, the voltage value of the second fluctuation voltage is represented by Vrefc, the resistance value of the current setting resistor is represented by Ri, and the temperature fluctuation of the second fluctuation voltage. The rate of change with respect to is represented by x, and the rate of change of the current setting resistance with respect to temperature variation is represented by y.
Iout = (Vrefc * x) / (Ri * y) (1)
Here, if x = y, equation (1) can be transformed into equation (2).
Iout = Vrefc / Ri (2)

  According to the equations (1) and (2), if the rate of variation with respect to the temperature variation of the second variation voltage Vrefc and the current setting resistor Ri is the same, the current value of the output current Iout may not be affected by the temperature variation. Recognize.

  Next, FIG. 6 is a graph showing a difference in temperature fluctuation of the output current Iout due to a difference in output tap for extracting the second fluctuation voltage Vrefc in the slope adjustment unit of the constant current generation circuit according to the first embodiment. In the example shown in FIG. 6, it can be seen that the output current Iout becomes constant regardless of temperature fluctuations by taking out the second fluctuation voltage Vrefc from the output tap from which the voltage V12 is output. This is because the variation rate with respect to the temperature variation of the voltage V12 shown in FIG. 4 is the same as the variation rate with respect to the temperature variation of the current setting resistor Ri.

  Next, a method for setting the output current Iout in the constant current generation circuit 1 according to the first embodiment will be described. From the equation (2), it can be seen that the constant current generation circuit 1 can set the current value of the output current Iout by changing the value of the current setting resistor Ri. The output tap inclination adjustment voltages V11 to V1m and V0 for extracting the second fluctuation voltage Vrefc have different voltage values. Therefore, depending on the voltage selected as the second fluctuation voltage Vrefc, the current value of the output current Iout may exceed a preset specified range. In such a case, the current value of the output current Iout can be set within a specified range by trimming the resistance value of the current setting resistor Ri.

  As the current setting resistor Ri, a polysilicon resistor (positive temperature characteristic), an N-well resistor (negative temperature characteristic), a tungsten resistor (positive temperature characteristic) formed on a semiconductor substrate, or an external component A provided resistor can be used. However, considering the reduction in the number of terminals of the semiconductor device and the stability of the output current, it is preferable to use a tungsten resistor formed on the semiconductor substrate as the current setting resistor Ri.

  This is because the resistance value of the tungsten resistor is stable even with respect to the stress change to the semiconductor substrate. FIG. 7 shows a graph showing the difference in temperature variation of the output current depending on the presence / absence of the sealing material (for example, mold resin) of the semiconductor chip on which the constant current generating circuit according to the first embodiment is formed. In the example shown in FIG. 7, the rate of change of the output current depending on the presence or absence of a mold resin when a tungsten resistor is used as the current setting resistor Ri, and the output depending on the presence or absence of a mold resin when a polysilicon resistor is used as the current setting resistor Ri. The rate of change of current was shown. As shown in FIG. 7, the tungsten resistance has an error of less than 0.5% between the output current when there is no mold resin and the output current when there is mold resin. On the other hand, the polysilicon resistor has an error of about 2% at the maximum between the output current when there is no mold resin and the output current when there is mold resin. A semiconductor device is formed by sealing a semiconductor chip with a mold resin, and this mold resin gives stress to the semiconductor chip. That is, it can be seen from FIG. 7 that the tungsten resistance can maintain more stable characteristics against the stress on the semiconductor chip than the polysilicon resistance. Since stress on the semiconductor chip changes due to temperature change of the mold resin, warpage of the mounting substrate when mounted, etc., it is preferable to use a tungsten resistor as the current setting resistor Ri in order to obtain a more stable output current Iout. .

  Next, a method for setting the curvature setting value and the slope setting value in the constant current generation circuit 1 according to the first embodiment will be described. First, in the constant current generation circuit 1, the curvature setting value and the inclination setting value are determined before normal use and are stored in the memory 24. However, the curvature setting value and inclination setting value to be stored must be determined in the shipping test before shipping. FIG. 8 is a flowchart showing a procedure for setting the curvature setting value and the inclination setting value in the shipping test. In executing the setting procedure shown in FIG. 8, it is assumed that the curvature setting value and the inclination setting value are set to initial values that are uniformly set regardless of the temperature fluctuation of the output current Iout.

  As shown in FIG. 8, when setting the setting value according to the first embodiment, first, after setting the curvature setting value (step S1), the inclination setting value is determined (step S2). Hereinafter, the setting procedure of the curvature setting value and the setting procedure of the inclination setting value will be described in detail.

  FIG. 9 is a flowchart showing the procedure for setting the curvature setting value. As shown in FIG. 9, when determining the curvature setting value, first, the temperature of the semiconductor substrate on which the constant current generating circuit 1 is formed is set to a first temperature (step S11). This first temperature is a temperature lower than a second temperature and a third temperature described later. Then, a current value (first output current measurement value) of the output current Iout of the constant current generation circuit 1 formed on the semiconductor substrate set to the first temperature is acquired (step S12).

  Subsequently, the temperature of the semiconductor substrate is set to a second temperature (step S13). The second temperature is lower than a third temperature described later and higher than the first temperature. Then, the current value (second output current measurement value) of the output current Iout of the constant current generation circuit 1 formed on the semiconductor substrate set to the second temperature is acquired (step S14).

  Subsequently, the temperature of the semiconductor substrate is set to a third temperature (step S15). The third temperature is higher than the first temperature and the third temperature. Then, the current value (third output current measurement value) of the output current Iout of the constant current generation circuit 1 formed on the semiconductor substrate set to the third temperature is acquired (step S16).

  Subsequently, the curvature of the diode voltage (for example, the first fluctuation voltage Vf) is calculated from the first output current measurement value based on the third output current measurement value (step S17). The magnitude of this curvature is performed by a test apparatus for testing a semiconductor device. Then, a switch (for example, NMOS transistors MN11 to MN1n) to be selected is determined according to the magnitude of the curvature calculated in step S17, and the curvature setting value is updated with a value corresponding to the determined switch. Note that the test apparatus for inspecting the semiconductor substrate on which the constant current generation circuit 1 is formed has, for example, a database showing the correspondence between the magnitude of curvature and the curvature setting value, and corresponds to the magnitude of curvature from the database. Select the curvature setting value.

  Next, FIG. 10 is a flowchart showing the procedure for setting the slope setting value in the constant current generation circuit according to the first embodiment in FIG. As shown in FIG. 10, in the slope setting value setting procedure, first, the temperature of the semiconductor substrate on which the constant current generating circuit 1 is formed is set to a fourth temperature (step S21). This fourth temperature is a temperature lower than a fifth temperature described later. Then, the current value (fifth output current measurement value) of the output current Iout of the constant current generation circuit 1 formed on the semiconductor substrate set to the fourth temperature is acquired (step S22).

  Subsequently, the temperature of the semiconductor substrate is set to a fifth temperature (step S3). The fifth temperature is higher than the fourth temperature. Then, the current value (fourth output current measurement value) of the output current Iout of the constant current generation circuit 1 formed on the semiconductor substrate set to the fifth temperature is acquired (step S24).

  Subsequently, a difference value between the fourth output current measurement value and the fifth output current measurement value is calculated (step S25). This calculation is performed by a test device or the like for testing a semiconductor device including the constant current generation circuit 1. Subsequently, it is determined whether or not the difference value calculated in step S25 is within a preset specified range (step S26). The output current Iout ideally has a fluctuation rate of zero with respect to temperature fluctuations, but the slope adjustment voltages V11 to V1m and V0 generated by the fluctuation slope adjustment unit 12 are discrete voltage values. It is not realistic to set the variation rate of the output current Iout to the temperature variation to zero. Therefore, in this step S26, the specified range is defined by the upper limit value and the lower limit value, and the standard is satisfied if the difference value is within the specified range.

  As the fourth temperature and the fifth temperature, the first temperature and the third temperature used in the curvature setting value setting flow can be used. That is, the first output current measurement value and the second output current measurement value can be used as the fourth output current measurement value and the fifth output current measurement value. As a result, the number of times the semiconductor device is cooled and overheated and the number of measurements can be reduced, and the test process can be simplified.

  If it is determined in step S6 that the difference value is outside the specified range, the process of step S27 is performed. In step S27, the switch (for example, switches SW11 to SW1m, SW0) selected by the first decoder 23 is determined according to the magnitude of the difference value, and the slope setting value is updated with a value corresponding to the determined switch. For example, when the difference value is below the lower limit value, the slope setting value is set to a value that selects a switch corresponding to the output tap that generates a voltage higher than the current value according to the amount of deviation from the lower limit value of the difference value. Update. On the other hand, if it is determined in step S26 that the difference value is within the specified range, the process ends.

  From the above description, in the constant current generation circuit 1 according to the first embodiment, the slope adjustment unit 12 determines the resistance value of the current setting resistor Ri from the first fluctuation voltage Vf having a predetermined fluctuation rate with respect to the temperature fluctuation. A second fluctuation voltage Vrefc having a fluctuation rate that matches the fluctuation rate with respect to the temperature fluctuation is generated. At this time, the inclination adjusting unit 12 adjusts the variation rate of the second variation voltage Vrefc with respect to the temperature variation only by switching the output tap that generates the voltage output as the second variation voltage. In the constant current generation circuit 1 according to the first embodiment, the curvature correction unit 25 corrects the curvature of the temperature variation of the voltage of the first variation voltage Vf by adjusting the current flowing through the diode Di. At this time, the curvature correction unit 25 adjusts the curvature related to the temperature fluctuation of the first fluctuation voltage Vf only by switching the conduction state of the NMOS transistors MN11 to MN1n functioning as a switch with the current flowing through the diode Di. That is, in the constant current generation circuit 1, not only the inclination of the second fluctuation voltage Vrefc with respect to the temperature fluctuation but also the change of the second fluctuation voltage Vrefc is corrected by correcting the curvature component of the change of the second fluctuation voltage Vrefc. It can be corrected to be more linear. Thereby, in the constant current generation circuit 1, the stability of the output current Iout with respect to the temperature can be increased as compared with the case where only the adjustment of the slope of the second fluctuation voltage Vrefc is performed.

Embodiment 2
FIG. 11 is a block diagram of the constant current generation circuit 2 according to the second embodiment. As illustrated in FIG. 11, the constant current generation circuit 2 according to the second embodiment includes a temperature variation voltage generation unit 10 a that is another form of the temperature variation voltage generation unit 10 and the curvature correction unit 25 according to the first embodiment, and A curvature correction unit 25a is provided. In the second embodiment, the second resistor R2 may be divided. However, since the second resistor R2 is not provided with a switch connected in parallel to the second resistor R2, the second resistor R2 is not provided in FIG. The example provided as one resistance was shown. In the description of the constant current generation circuit 2 according to the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals as those in the first embodiment and the description thereof is omitted.

  As illustrated in FIG. 11, the temperature variation voltage generation unit 10a of the constant current generation circuit 2 according to the second embodiment includes a plurality of diodes Di1 to Din. The diodes Di1 to Din may have the same size or different sizes.

  The curvature correction unit 25a includes a plurality of switches (for example, NMOS transistors MN21 to MN2n), a decoder (for example, the second decoder 26a), and a memory 27. The NMOS transistors MN21 to MN2n have one end connected in series with any one of the diodes Di1 to Din and the other end connected to the second resistor R2. More specifically, the NMOS transistors MN21 to MN2n have their sources connected to the anodes of the corresponding diodes and their drains connected to one end of the second resistor R2. That is, the set of NMOS transistors MN21 to MN2n and diodes Di1 to Din are connected in parallel to each other and connected in series to the second resistor R2.

  The second decoder 26a controls the open / closed state of the plurality of switches according to the curvature setting value. More specifically, the second decoder 26a switches which of the NMOS transistors MN21 to MN2n is turned on and the number of NMOS transistors MN21 to MN2n to be turned on according to the curvature setting value. .

  The memory 27 is a storage unit that stores a curvature setting value. The memory 27 may be a non-volatile memory such as a flash memory, a fuse circuit that holds a value due to destruction of a physical element, or a volatile memory such as a DRAM. This curvature setting value is determined based on the value measured in the inspection process and written in the memory 27. Further, the memory 27 may be implemented as a single storage unit including the memory 24. In this case, the memory 27 is defined as a part of the storage unit.

  In the constant current generation circuit 2 according to the second exemplary embodiment, the temperature correction voltage generation unit 10 is switched via the second resistor R2 by switching the conductive transistor among the NMOS transistors MN21 to MN2n by the curvature correction unit 25a. To which diode the current flowing in the current flows. That is, the curvature correction unit 25 switches the current flowing through which diode or the number of diodes through which the current flows based on the curvature setting value. Thereby, in the constant current generation circuit 2, the amount of current flowing per unit area of the diodes Di1 to Din is switched according to the curvature setting value. That is, the constant current generation circuit 2 according to the second exemplary embodiment corrects the curvature of the first fluctuation voltage Vf according to the curvature setting value, similarly to the constant current generation circuit 1 according to the first exemplary embodiment.

  From the above description, the constant current generation circuit 2 according to the second embodiment switches the number of diodes Di1 to Din connected in parallel according to the curvature setting value while maintaining the resistance value of the second resistor R2 constant. . Thereby, the constant current generation circuit 2 according to the second exemplary embodiment can correct the curvature of the first variable voltage Vf according to the curvature setting value in the same manner as the constant current generation circuit 1 according to the first exemplary embodiment. . In addition, since the constant current generation circuit 2 according to the second embodiment has a constant resistance value of the second resistor R2, the setting of the slope setting value is easier than the constant current generation circuit 2 according to the first embodiment. become.

Embodiment 3
FIG. 12 is a block diagram of the microprocessor 3 according to the third embodiment. As shown in FIG. 12, the microprocessor 3 includes an operation core PE, a memory (for example, a flash memory MEM), and a clock generation circuit CG. The clock generation circuit CG includes the oscillation circuit 30 and the constant current generation circuit 1 according to the first embodiment. The clock generation circuit CG generates the clock signal CLK with less variation with respect to temperature by using the highly accurate output current Iout generated by the oscillation circuit 30 in the constant current generation circuit 1. In the example shown in FIG. 12, the clock signal CLK output from the clock generation circuit CG is supplied to the arithmetic core PE and the flash memory MEM. However, the clock signal CLK may be output to the outside.

  Next, the microprocessor 3 according to the third embodiment will be described in detail. In the following description, the constant current generation circuit 1 is substantially the same as that described in the first embodiment, and thus detailed description thereof is omitted.

  A program and setting values are stored in the flash memory MEM. The arithmetic core PE performs arithmetic processing based on a program stored in the flash memory. The clock generation circuit CG generates an output signal (clock signal CLK) whose oscillation frequency is determined based on the output current Iout generated by the constant current generation circuit 1 by the oscillation circuit 30. The flash memory MEM, the arithmetic core PE, and the clock generation circuit CG are connected to each other by an internal bus.

  Here, details of the oscillation circuit 30 will be described. A block diagram of an oscillation circuit 30a, which is an example of the oscillation circuit 30, is shown in FIG. The oscillation circuit 30a includes an inverter 31, capacity driving circuits 32 and 34, comparators 33 and 35, an SR latch circuit 36, and capacitors C1 and C2.

  The capacity driving circuit 32 includes an NMOS transistor N1 and a PMOS transistor P4. The source of the NMOS transistor N1 is connected to the ground terminal, and the drain is connected to the drain of the PMOS transistor P4. A connection point between the drain of the PMOS transistor P4 and the drain of the NMOS transistor N1 is an output node of the capacitance driving circuit 32. The output current Iout output from the constant current generation circuit 1 is input to the source of the PMOS transistor P4. The gate of the PMOS transistor P4 and the gate of the NMOS transistor N1 are connected in common, and the clock signal CLK output from the oscillation circuit 30a is input via the inverter 31. The inverter 31 outputs a signal obtained by inverting the clock signal CLK to the capacity driving circuit 32.

  Capacitor C1 is connected between the output node of capacitance drive circuit 32 and the ground terminal. Further, a voltage Vcp1 is generated at the output node according to the amount of charge accumulated in the capacitor C1.

  In the comparator 33, the voltage Vcp1 is input to the non-inverting input terminal, and the oscillation reference voltage VREF is input to the inverting input terminal. The comparator 33 switches the logic level of the reset signal R according to the magnitude relationship between the voltage Vcp1 and the oscillation reference voltage VREF. More specifically, the comparator 33 sets the reset signal R to a low level when the voltage Vcp1 is larger than the voltage VREF. On the other hand, the comparator 33 sets the reset signal R to the high level when the voltage Vcp1 is smaller than the oscillation reference voltage VREF. The comparator 33 is preferably a hysteresis comparator in order to stably switch the logic level of the reset signal R to be output. The hysteresis comparator switches the reset signal R from the low level to the high level when the voltage Vcp1> the oscillation reference voltage VREF, and sets the reset signal R high when the voltage Vcp1 + dh <the oscillation reference voltage VREF, assuming that the hysteresis width is dh. Switch from level to low level.

  The capacity driving circuit 34 includes an NMOS transistor N2 and a PMOS transistor P5. The source of the NMOS transistor N2 is connected to the ground terminal, and the drain is connected to the drain of the PMOS transistor P5. A connection point between the drain of the PMOS transistor P5 and the drain of the NMOS transistor N2 is an output node of the capacitance driving circuit 34. The output current Iout output from the constant current generation circuit 1 is input to the source of the PMOS transistor P5. The gate of the PMOS transistor P5 and the gate of the NMOS transistor N2 are connected in common, and the clock signal CLK output from the oscillation circuit 30a is input.

  Capacitor C2 is connected between the output node of capacitance drive circuit 34 and the ground terminal. Further, a voltage Vcp2 is generated at the output node according to the amount of charge accumulated in the capacitor C2.

  In the comparator 35, the voltage Vcp2 is input to the non-inverting input terminal, and the oscillation reference voltage VREF is input to the inverting input terminal. The comparator 35 switches the logic level of the set signal S according to the magnitude relationship between the voltage Vcp2 and the oscillation reference voltage VREF. More specifically, the comparator 35 sets the set signal S to a low level when the voltage Vcp2 is larger than the oscillation reference voltage VREF. On the other hand, the comparator 35 sets the set signal S to a high level when the voltage Vcp2 is smaller than the oscillation reference voltage VREF. The comparator 35 is preferably a hysteresis comparator in order to stably switch the logic level of the set signal S to be output. When the hysteresis width is dh, the hysteresis comparator switches the set signal S from the low level to the high level when the voltage Vcp2> the oscillation reference voltage VREF, and sets the set signal S high when the voltage Vcp1 + dh <the oscillation reference voltage VREF. Switch from level to low level.

  The SR latch circuit 36 receives the set signal S and the reset signal R and outputs an output signal Q. This output signal Q becomes the clock signal CLK. The SR latch circuit 36 raises the clock signal CLK according to the rising edge of the set signal S, and falls the clock signal CLK according to the rising edge of the reset signal R.

  The oscillation circuit 30a receives the oscillation reference voltage VREF. The oscillation reference voltage VREF is the voltage at the non-inverting input terminal of the error amplifier 21 of the constant current generation circuit 1. The voltage at the non-inverting input terminal of the error amplifier 21 is substantially the same as the reference voltage Vconst. However, when the error amplifier 21 has an input offset, a voltage difference is generated between the reference voltage Vconst and the voltage at the non-inverting input terminal of the error amplifier 21. The voltage at the non-inverting input terminal of the error amplifier 21 is a voltage that serves as a reference for the second fluctuation voltage. That is, the voltage at the non-inverting input terminal of the error amplifier 21 has a higher correlation with the output current Iout of the constant current generation circuit 1 than with the reference voltage Vconst. The oscillation frequency of the oscillation circuit 30a is determined according to the amount of output current Iout of the constant current generation circuit 1. For this reason, by operating the oscillation circuit 30a based on the oscillation reference voltage VREF, the oscillation circuit 30a can reduce an error from an expected value of the oscillation frequency.

  Here, a timing chart showing the operation of the oscillation circuit 30a is shown in FIG. First, the operation of the oscillation circuit 30a during the period when the clock signal CLK is at a low level will be described. In the period in which the clock signal CLK is at the low level, in the capacitance driving circuit 32, the PMOS transistor P4 is turned off and the NMOS transistor N1 is turned on. Then, the capacity driving circuit 32 pulls out the charge from the capacitor C1 by the NMOS transistor N1, and lowers the voltage level of the voltage Vcp1. Thereafter, when the voltage level of the voltage Vcp1 drops from the oscillation reference voltage VREF and falls below a predetermined voltage (for example, VREF−hysteresis width), the comparator 33 switches the reset signal R from the high level to the low level.

  In the period in which the clock signal CLK is at a low level, the PMOS transistor P5 is turned on and the NMOS transistor N2 is turned off in the capacity driving circuit 34. Then, the capacitance driving circuit 34 applies the output current Iout to the capacitor C2 via the PMOS transistor P5, and increases the amount of charge accumulated in the capacitor C2, thereby increasing the voltage level of the voltage Vcp2. Thereafter, when the voltage level of the voltage Vcp2 reaches the oscillation reference voltage VREF, the comparator 35 switches the set signal S from the low level to the high level (timing T1, T3).

  Next, the operation of the oscillation circuit 30a during the period when the clock signal CLK is at a high level will be described. In the period in which the clock signal CLK is at a high level, in the capacity driving circuit 32, the PMOS transistor P4 is turned on and the NMOS transistor N1 is turned off. Then, the capacity driving circuit 32 applies the output current Iout to the capacitor C1 via the PMOS transistor P4, and increases the amount of charge accumulated in the capacitor C1, thereby increasing the voltage level of the voltage Vcp1. Thereafter, when the voltage level of the voltage Vcp1 reaches the oscillation reference voltage VREF, the comparator 33 switches the reset signal R from the low level to the high level (timing T2).

  In the period in which the clock signal CLK is at a high level, the PMOS transistor P5 is turned off and the NMOS transistor N2 is turned on in the capacitor driving circuit 34. Then, the capacity driving circuit 34 pulls out charges from the capacitor C2 by the NMOS transistor N2, and lowers the voltage level of the voltage Vcp2. Thereafter, when the voltage level of the voltage Vcp2 drops from the oscillation reference voltage VREF and falls below a predetermined voltage (for example, VREF−hysteresis width), the comparator 35 switches the set signal S from the high level to the low level.

  The SR latch circuit 36 switches between a high level and a low level of the clock signal in accordance with the rising edge of the set signal S and the rising edge of the reset signal R.

Here, in the oscillation circuit 30a, the rate of voltage rise (dV / dt) of the voltages Vcp1 and Vcp2 can be expressed as a function of the output current Iout. This function is shown in equation (3). In the equation (3), C is a capacitance value of the capacitors C1 and C2.
dV / dt = Iout / C (3)
In the oscillation circuit 30a, the oscillation frequency is determined by the time until the voltages Vcp1 and Vcp2 reach the oscillation reference voltage VREF from the ground voltage level. From the equation (3), if the capacitance values of the capacitors C1 and C2 are constant, the rising speeds of the voltages Vcp1 and Vcp2 are determined by the magnitude of the output current Iout. That is, the frequency of the clock signal output from the oscillation circuit 30a is determined by the current value of the output current Iout.

  The output current Iout generated by the constant current generation circuit 1 according to the first embodiment can set the variation rate with respect to the temperature variation to zero. That is, the oscillation circuit 30a in FIG. 13 in which the oscillation frequency is determined based on the output current Iout output from the constant current generation circuit 1 can achieve high frequency accuracy (for example, a variation width of less than 1%).

  Next, another example of the oscillation circuit 30 will be described. A block diagram showing an oscillation circuit 30b, which is another example of the oscillation circuit 30, is shown in FIG. As shown in FIG. 15, the oscillation circuit 30b includes a frequency detection circuit 40, a differential amplifier 42, an oscillator 44 (for example, a voltage controlled oscillator), a control circuit 45, and a filter capacitor Cpump.

  The frequency detection circuit 40 generates a frequency detection voltage Vcap whose voltage level changes according to the length of the cycle of the clock signal CLK based on the timing control signal output from the control circuit 45. The timing control signal includes a charge reset signal INIT, a ramp control signal RAMP, and a hold control signal HOLD. The frequency detection circuit 40 generates a frequency detection voltage Vcap according to these signals.

  As shown in FIG. 15, the frequency detection circuit 40 includes a ramp and hold circuit 41 and a frequency setting capacitor C. The ramp-and-hold circuit 41 receives the output current Iout from the constant current generation circuit 1. That is, in the lamp and hold circuit 41, the current value of the charge / discharge current is set by the output current Iout.

  The ramp and hold circuit 41 supplies charge / discharge current to the frequency setting capacitor C and resets the charge accumulated in the frequency setting capacitor C based on the timing control signal. The ramp and hold circuit 41 includes an NMOS transistor N3 and PMO transistors P6 and P7. The PMOS transistors P6 and P7 constitute a differential pair. That is, the sources of the PMOS transistors P6 and P7 are commonly connected. The output current Iout is supplied to the sources (common connection points) of the PMOS transistors P6 and P7. The ramp control signal RAMP is input to the gate of the PMOS transistor P6, and the hold control signal HOLD is input to the gate of the PMOS transistor P7. The drain of the PMOS transistor P6 is connected to the drain of the NMOS transistor N3 and serves as an output terminal of the ramp and hold circuit 41. The drain of the PMOS transistor P7 is connected to the ground terminal. The charge reset signal INIT is input to the gate of the NMOS transistor N3. The source of the NMOS transistor N3 is connected to the ground terminal.

  The frequency setting capacitor C is connected between the output terminal of the ramp and hold circuit 41 and the ground terminal. The frequency setting capacitor C generates the frequency detection voltage Vcap according to the amount of accumulated charge. The frequency detection voltage Vcap is generated at a node serving as an output terminal of the ramp and hold circuit 41.

  The ramp and hold circuit 41 turns on the NMOS transistor N3 when the charge reset signal INIT is enabled (for example, high level). The ramp-and-hold circuit 41 resets the charge accumulated in the frequency setting capacitor by discharging the charge accumulated in the frequency setting capacitor C. The ramp-and-hold circuit 41 turns off the NMOS transistor N3 and the PMOS transistor P6 when the charge reset signal INIT is disabled (for example, low level) and the ramp control signal RAMP is enabled (for example, low level). Turn on. As a result, the lamp and hold circuit 41 accumulates charges in the frequency setting capacitor C by the charge / discharge current. The ramp and hold circuit 41 turns off the PMOS transistor P6 when the ramp control signal RAMP is disabled (for example, high level) and the hold control signal HOLD is enabled (for example, low level), and The PMOS transistor P7 is turned on. As a result, the ramp and hold circuit 41 stops charging the frequency setting capacitor C and maintains the frequency detection voltage Vcap generated by the charge accumulated in the frequency setting capacitor C.

  The differential amplifier 42 continuously varies the oscillation frequency setting current Icp according to the voltage difference between the frequency detection voltage Vcap and the oscillation reference voltage VREF, and outputs it to the filter capacitor Cpump. More specifically, the differential amplifier 42 includes an amplifying unit 43 and a switch circuit SW. The frequency detection voltage Vcap is input to the inverting input terminal of the amplifying unit 43, and the oscillation reference voltage VREF is input to the non-inverting input terminal. The amplifying unit 43 is, for example, a transconductance amplifier, and outputs an oscillation frequency setting current Icp having a current value corresponding to a voltage difference between the frequency detection voltage Vcap and the oscillation reference voltage VREF.

  In the present embodiment, as the oscillation reference voltage VREF, the voltage at the non-inverting input terminal of the error amplifier 21 of the constant current generation circuit 1 is used as the oscillation reference voltage VREF. The voltage at the non-inverting input terminal of the error amplifier 21 is substantially the same as the reference voltage Vconst. However, when the error amplifier 21 has an input offset, a voltage difference is generated between the reference voltage Vconst and the voltage at the non-inverting input terminal of the error amplifier 21. The voltage at the non-inverting input terminal of the error amplifier 21 is a voltage that serves as a reference for the second fluctuation voltage. That is, the voltage at the non-inverting input terminal of the error amplifier 21 has a higher correlation with the output current Iout of the constant current generation circuit 1 than with the reference voltage Vconst. The oscillation frequency of the oscillation circuit 30b is determined according to the amount of the output current Iout of the constant current generation circuit 1. Therefore, by operating the oscillation circuit 30b based on the oscillation reference voltage VREF, the oscillation circuit 30b can reduce an error from an expected value of the oscillation frequency.

  The switch circuit SW is provided between the output terminal of the amplifying unit 43 and the filter capacitor Cpump, and the conduction state is switched according to the pump control signal PULSE included in the timing control signal. More specifically, the switch circuit SW is in a conductive state when the pump control signal PULSE is in an enabled state (for example, high level), and is in a cutoff state when the pump control signal PULSE is in a disabled state (for example, low level).

  The oscillator 44 controls the oscillation frequency of the clock signal CLK according to the voltage level of the oscillation frequency control voltage Vcp.

  The control circuit 45 generates a timing control signal whose logic level is switched based on the cycle of the clock signal CLK. This timing control signal includes a charge reset signal INIT, a ramp control signal RAMP, a hold control signal HOLD, and a pump control signal PULSE. The control circuit 45 generates a divided signal obtained by dividing the clock signal CLK, and switches the logic level of the control signal based on a count value obtained by counting the number of clocks of the divided signal. Details of the timing for switching the logic level of the timing control signal will be described later.

  Next, FIG. 16 shows a timing chart showing the operations of the frequency detection circuit 40 and the control circuit 45. Then, with reference to FIG. 16, the control circuit 45 will explain the logic level switching timing of the timing control signal and the operation of the frequency detection circuit 40.

  As shown in FIG. 16, the control circuit 45 divides the clock signal CLK to generate a divided signal FD. In the example shown in FIG. 16, the frequency-divided signal FD is generated by dividing the clock signal CLK by two. In addition, the control circuit 45 counts the number of clocks of the frequency-divided signal FD and generates a count value COUNT. In the example shown in FIG. 16, the count value COUNT is a 2-bit value and a value from 0 to 3. Then, the control circuit 45 switches the logic level of the timing control signal in accordance with the count value COUNT.

  Specifically, when the count value is 0, the control circuit 45 sets the charge reset signal INIT to a high level (enabled state), sets the ramp control signal RAMP to a high level (disabled state), and holds the hold control signal HOLD. Is set to the low level (enabled state), and the pump control signal PULSE is set to the low level (disabled state). Hereinafter, the period in which the count value is 0 is referred to as a charge reset period Tinit.

  When the count value is 1, the control circuit 45 sets the charge reset signal INIT to the low level (disable state), sets the ramp control signal RAMP to the low level (enable state), and sets the hold control signal HOLD to the high level (disable state). ) And the pump control signal PULSE is set to a low level (disabled state). Hereinafter, the period in which the count value is 1 is referred to as a ramp period Tramp.

  When the count value is 2, the control circuit 45 sets the charge reset signal INIT to the low level (disabled state), sets the ramp control signal RAMP to the high level (disabled state), and sets the hold control signal HOLD to the low level (enabled state). ) And the pump control signal PULSE is set to a low level (disabled state). Hereinafter, the period in which the count value is 2 is referred to as a hold period Thold.

  When the count value is 3, the control circuit 45 sets the charge reset signal INIT to the low level (disabled state), sets the ramp control signal RAMP to the high level (disabled state), and sets the hold control signal HOLD to the low level (enabled state). ) And the pump control signal PULSE is set to the high level (enabled state). Hereinafter, the period in which the count value is 3 is referred to as a pump period Tpump.

  Next, the operation of the frequency detection circuit 40 will be described. In the charge reset period Tinit, the frequency detection circuit 40 conducts the NMOS transistor N3 based on the charge reset signal INIT to reset the charge stored in the frequency setting capacitor C to a charge amount corresponding to the ground voltage. As a result, the frequency detection voltage Vcap becomes substantially equal to the ground voltage. At this time, the PMOS transistor P6 is turned off in response to the ramp control signal RAMP, and the PMOS transistor P7 is turned on in response to the hold control signal HOLD.

  In the ramp period Tramp, the frequency detection circuit 40 turns off the NMOS transistor N3 according to the charge reset signal INIT, turns on the PMOS transistor P6 according to the ramp control signal RAMP, and turns on the PMOS transistor according to the hold control signal HOLD. Turn P7 off. That is, the frequency detection circuit 40 charges the frequency setting capacitor C based on the charge / discharge current during the ramp period Tramp. As a result, the voltage level of the frequency detection voltage Vcap gradually increases. The slope at which the frequency detection voltage Vcap increases is determined by the magnitude of the charge / discharge current and the capacitance value of the frequency setting capacitor C. For example, the slope (dVcap / dt) of the frequency detection voltage Vcap is represented by dVcap / dt = Iout / C. In the ramp period Tramp, the voltage level of the frequency detection voltage Vcap increases, but the voltage decrease rate is constant. Therefore, the voltage drop amount dVcap of the frequency detection voltage Vcap during the ramp period Tramp is determined by the length of the ramp period Tramp (the oscillation frequency of the clock signal CLK).

  In the hold period Thold, the frequency detection circuit 40 turns off the NMOS transistor N3 in response to the charge reset signal INIT, turns off the PMOS transistor P6 in response to the ramp control signal RAMP, and turns on the PMOS transistor in response to the hold control signal HOLD. Turn on P7. That is, the frequency detection circuit 40 sets the node to which the frequency setting capacitor C is connected to the high impedance state in the hold period Thold, and maintains the voltage level of the frequency detection voltage Vcap generated by the frequency setting capacitor C.

  In the pump period Tpump, the oscillation frequency setting current Icp is supplied to the filter capacitor Cpump by the differential amplifier 42. At this time, the charge reset signal INIT, the ramp control signal RAMP, and the hold control signal HOLD supplied to the frequency detection circuit 40 are the same in the hold period Thold and the pump period Tpump. Therefore, the voltage level of the frequency detection voltage Vcap is not changed by the frequency detection circuit 40 during the pump period Tpump.

  Next, the overall operation of the oscillation circuit 30b shown in FIG. 15 will be described. FIG. 17 shows a timing chart showing the operation of the oscillation circuit 30b shown in FIG. In the timing chart shown in FIG. 17, only changes in the frequency detection voltage Vcap, the oscillation frequency control voltage Vcp, and the clock signal CLK are shown. In FIG. 17, the operation of the oscillation circuit 30b is started at the origin of the time axis (horizontal axis).

  As shown in FIG. 17, the oscillation circuit 30b increases the oscillation frequency control voltage Vcp every period TM1 to TM7. Each of the periods TM1 to TM7 includes a set of a charge reset period Tinit, a ramp period Tramp, a hold period Thold, and a pump period Tpump shown in FIG. Further, since the frequency of the clock signal CLK increases every period, the period TM1 to the period TM7 are gradually shortened. This is because the timing control signal is generated based on the cycle of the clock signal CLK. Note that periods TM11 to TM17 shown in FIG. 17 are periods corresponding to the pump period Tpump.

  Then, after the period TM7 has elapsed, the high level side voltage of the frequency detection voltage Vcap becomes substantially the same as the oscillation reference voltage VREF. Thereby, in the oscillation circuit 30b, the oscillation frequency setting current Icp output from the differential amplifier 42 becomes substantially zero. Therefore, the state is maintained after the high-level voltage of the frequency detection voltage Vcap becomes substantially the same as the oscillation reference voltage VREF. Further, since the frequency detection voltage Vcap is maintained at a constant voltage, the oscillation frequency of the clock signal CLK is also maintained constant. That is, in the oscillation circuit 30b, jitter does not occur in the clock signal CLK after the oscillation frequency of the clock signal CLK reaches the target value.

  From the above description, in the oscillation circuit 30b, the filter capacitor Cpump generates the oscillation frequency control voltage Vcp according to the oscillation frequency setting current Icp. At this time, in the oscillation circuit 30b, the differential amplifier 42 outputs the oscillation frequency setting current Icp whose value continuously changes according to the voltage difference between the frequency detection voltage Vcap and the oscillation reference voltage VREF. That is, if there is a voltage difference between the frequency detection voltage Vcap and the oscillation reference voltage VREF, the oscillation frequency setting current Icp has a magnitude corresponding to the voltage difference, and the voltage difference between the frequency detection voltage Vcap and the oscillation reference voltage VREF. If not, the oscillation frequency setting current Icp is substantially zero. As a result, in the oscillation circuit 30b, even if the pump control signal PULSE is enabled in a state where the frequency of the clock signal CLK matches the target value (for example, a state where the frequency detection voltage Vcap matches the oscillation reference voltage VREF). The oscillation frequency control voltage Vcp does not vary. Thereby, in the oscillation circuit 30b, the voltage value of the oscillation frequency control voltage Vcp does not fluctuate after the oscillation frequency of the clock signal CLK matches the target value, and the oscillator 44 according to the voltage value of the oscillation frequency control voltage Vcp. Therefore, the oscillation frequency of the clock signal CLK determined by is not shifted. That is, the oscillation circuit 30b can reduce the jitter of the clock signal CLK.

  In the oscillation circuit 30b, the differential amplifier 43 has a switch circuit SW. The switch circuit SW is controlled to be in a cut-off state except for a period (for example, a pump period Tpump) that reflects the differential voltage amplification result of the input signal of the differential amplifier 42. In the oscillation circuit 30b, the frequency detection voltage Vcap has a voltage value that is different from the voltage reflecting the clock signal CLK in the charge reset period Tinit and the ramp period Tramp. However, since the switch circuit SW is controlled to be in the cut-off state except for the pump period, it is possible to prevent the deviation of the frequency detection voltage Vcap in the charge reset period Tinit and the ramp period Tramp from being reflected in the oscillation frequency. Thereby, the oscillation circuit 30b can stabilize the oscillation frequency in any period.

  The oscillation frequency is set in the oscillation circuit 30b based on the output current Iout output from the constant current generation circuit 1. Therefore, if the variation rate of the output current Iout output from the constant current generation circuit 1 with respect to the temperature change is substantially zero, the variation rate of the oscillation frequency of the oscillation circuit 30b with respect to the temperature variation can be substantially zero. . Further, the constant current generating circuit 1 can accurately set the current value of the output current Iout by trimming the current setting resistor Ri. Therefore, the oscillation circuit 30b increases the setting accuracy of the current value of the output current Iout output from the constant current generation circuit 1, thereby increasing the setting value of the oscillation frequency of the clock signal CLK with high accuracy (for example, a variation width of less than 1%). ) Can be set.

  From the above description, in the microprocessor 3 according to the second embodiment, by setting the frequency of the clock signal CLK using the output current Iout output from the constant current generation circuit 1, the variation rate with respect to the temperature variation of the clock signal CLK, Of the fluctuation components with respect to the temperature of the first fluctuation voltage, the curvature component and the frequency can be set with high accuracy. For example, in the microprocessor 3 according to the second embodiment, the variation rate and the frequency with respect to the temperature variation of the clock signal CLK can be within a range of deviation of about 1%. The microprocessor 3 can operate based on such a highly accurate clock signal.

  Subsequently, a startup sequence of the microprocessor 3 according to the second embodiment will be described. FIG. 18 is a flowchart showing the procedure of the startup process of the microprocessor 3 according to the second embodiment.

  As shown in FIG. 18, when the microprocessor 3 starts the activation process, first, the first decoder 23 switches any one switch based on the initial inclination setting value stored in advance in the memory 24 in the inclination control unit 22. Is selected (step S30). In step S30, the second decoder 26 reads the initial curvature setting value in advance into the memory 27 in the curvature correction unit 25, and turns on the NMOS transistor designated by the initial curvature setting value from the NMOS transistors MN11 to MN1n. As a result, the constant current generating circuit 1 starts operating and outputs an output current Iout. Then, the oscillation circuit 30 generates the clock signal CLK based on the output current Iout. Here, it is preferable that the initial inclination setting value and the curvature setting value set at the time of start-up are values with the smallest output current Iout. This is because the microprocessor 3 is unstable in various voltages, circuit states, and the like in the initial stage of start-up. This is because the possibility of malfunction is low.

  Subsequently, the calculation core PE reads the inclination setting value and the curvature setting value used in the normal state from the flash memory MEM, and gives the read inclination setting value and the curvature setting value to the memory 24 and the memory 27 (step S32). In the constant current generation circuit 1, the decoder 23 selects any one switch based on the updated slope setting value (step S33). In step S33, the decoder 26 turns on the NMOS transistor corresponding to the curvature setting value. Thereby, the constant current generation circuit 1 generates the output current Iout used in the normal state. Then, the oscillation circuit 30 changes the frequency of the clock signal CLK to the frequency in the normal state based on the output current Iout in the normal state (step S34).

  As described above, in the microprocessor 3 according to the second embodiment, the output current Iout and the clock signal CLK are generated based on the preset inclination setting value for starting, and the microprocessor 3 generates the clock signal CLK based on the clock signal CLK. After the operation is started, the output current Iout and the clock signal CLK are generated based on the slope setting value used in the normal state. By adopting such a startup procedure, it is not necessary to provide means for storing the slope setting value used in the normal state in the memory 24 in the constant current generation circuit 1. This is because the inclination setting value used in the normal state may be stored in a non-volatile memory such as a flash memory in which the value can be rewritten relatively easily. Note that the slope setting value used in the start-up process may be a value determined without taking into account the temperature variation of the output current Iout and the like, and can be set at the circuit design stage.

Embodiment 4
In the fourth embodiment, a delay circuit 50 that delays a signal by a delay amount determined by the amount of output current Iout generated by the constant current generation circuit 1 will be described. A circuit diagram of the delay circuit 50 is shown in FIG. As shown in FIG. 19, the delay circuit 50 includes NMOS transistors N10 to N14, PMOS transistors P10 to P13, and a capacitor Cd.

  The source of the NMOS transistor N10 is connected to the ground terminal, and the drain and gate are connected. The output current Iout of the constant current generation circuit 1 is input to the drain of the NMOS transistor N10. This output current Iout is hereinafter referred to as current I1. The NMOS transistors N11 and N12 form a current mirror circuit together with the NMOS transistor N10.

  The source of the PMOS transistor P10 is connected to the ground terminal, and the drain and gate are connected. The drain of the PMOS transistor P10 is connected to the drain of the NMOS transistor N11. The current I2 flowing through the NMOS transistor N11 is input to the drain of the PMOS transistor P10. This current I2 is generated based on the current I1 by a current mirror composed of NMOS transistors N10 and N11. The PMOS transistor P11 forms a current mirror circuit together with the PMOS transistor P10.

  The source of the NMOS transistor N13 is connected to the drain of the NMOS transistor N12. The drain of the NMOS transistor N13 is connected to the drain of the PMOS transistor P12. The source of the PMOS transistor P12 is connected to the drain of the PMOS transistor P11. The gate of the NMOS transistor N12 and the gate of the PMOS transistor P12 are connected to each other, and an input signal Vin is supplied to these gates. A connection point between the drain of the PMOS transistor P12 and the drain of the NMOS transistor N13 is an intermediate output node (a node where the intermediate voltage Vc is generated). Further, the current I4 generated by the current mirror circuit configured by the NMOS transistors N10 and N12 based on the current I1 flows through the NMOS transistor N13. A current I3 generated by the current mirror circuit configured by the PMOS transistors N10 and N11 based on the current I2 flows through the PMOS transistor N12.

  Capacitor Cd is connected between the intermediate output node and the ground terminal. The source of the NMOS transistor N14 is connected to the ground terminal. The drain of the NMOS transistor N14 is connected to the drain of the PMOS transistor P13. The source of the PMOS transistor P13 is connected to the power supply terminal. The gate of the NMOS transistor N14 and the gate of the PMOS transistor P13 are connected to each other, and an intermediate output node is connected to these gates.

Is connected. A connection point between the drain of the PMOS transistor P12 and the drain of the NMOS transistor N13 is an output terminal of the delay circuit 50, and an output signal Vout is output. That is, the NMOS transistor N14 and the PMOS transistor P13 constitute an output inverter of the delay circuit 50.

  Next, the operation of the delay circuit 50 will be described. A timing chart showing the operation of the delay circuit 50 is shown in FIG. As shown in FIG. 20, in the delay circuit 50, the NMOS transistor N13 is turned off and the PMOS transistor P12 is turned on while the input signal Vin is at a low level. Then, charges are accumulated in the capacitor Cd by the current I3 flowing through the PMOS transistor P12. As a result, the intermediate voltage Vc gradually increases. Thereafter, when the intermediate voltage Vc exceeds the threshold voltage Vth of the output inverter, the output signal Vout falls.

  In the delay circuit 50, the NMOS transistor N13 is turned on and the PMOS transistor P12 is turned off while the input signal Vin is at a high level. Then, the electric charge accumulated in the capacitor Cd is discharged by the current I4 flowing through the NMOS transistor N13. As a result, the intermediate voltage Vc gradually decreases. Thereafter, when the intermediate voltage Vc falls below the threshold voltage Vth of the output inverter, the output signal Vout rises.

  Here, in the delay circuit 50, the capacitor Cd is charged by the current I3, and the capacitor Cd is discharged by the current I4. The currents I3 and I4 are both generated by the current mirror circuit based on the current I1. When the current mirror ratio is 1: 1 in any current mirror circuit, the currents I3 and I4 have the same current value as the current I1. Therefore, the rising slope and falling slope of the intermediate voltage Vc can be expressed by dVc / dt = Iout / C.

  From the above description, in the delay circuit 50, the delay time Td is the time from the rising edge or falling edge of the input signal Vin until the intermediate voltage Vc exceeds the threshold voltage Vth of the output inverter. That is, the delay circuit 50 can keep the delay time Td constant regardless of the temperature if the variation rate of the output current Iout (current I1) with respect to the temperature variation is practically zero. Further, the delay circuit 50 can set the delay time Td with high accuracy if the current value of the output current Iout is set with high accuracy. Such a delay circuit 50 may be incorporated in the microprocessor 3 according to the second embodiment. When the delay circuit 50 is built in the microprocessor 3, the circuit can be operated by the startup process shown in FIG.

Embodiment 5
In the fifth embodiment, a description will be given of an output circuit 60 in which a load driving current applied to a load element is determined by the amount of output current Iout generated by the constant current generation circuit 1. A circuit diagram of the output circuit 60 is shown in FIG. As shown in FIG. 21, the output circuit 60 includes an inverter 61 and NMOS transistors N20 to N24. The output circuit 60 drives the load element 62 connected between the output terminal Tout and the power supply terminal with a drive current.

  The NMOS transistor N20 receives the output current Iout output from the constant current generation circuit 1 at its drain. The source of the NMOS transistor N20 is connected to the drain of the NMOS transistor N21. An enable signal EN is input to the gate of the NMOS transistor N20.

  The drain of the NMOS transistor N21 is connected to the gate of the NMOS transistor N21. The source of the NMOS transistor N21 is connected to the ground terminal. The NMOS transistor N22 forms a current mirror circuit together with the NMOS transistor N21. The drain of the NMOS transistor N22 is connected to the output terminal Tout.

  The inverted signal of the enable signal EN is input to the gate of the NMOS transistor N24 via the inverter 61. The source of the NMOS transistor N24 is connected to the ground terminal. The drain of the NMOS transistor N24 is connected to the gate of the NMOS transistor N21.

  Next, the operation of the output circuit 60 will be described. In the output circuit 60, when the enable signal EN is in an enable state (for example, high level), the NMOS transistor N20 is turned on and the NMOS transistor N24 is turned off. As a result, the output current Iout flows through the NMOS transistor N21 as the current I10. Then, a current I11 is generated based on the current I10 by a current mirror circuit composed of NMOS transistors N21 and N22. This current I11 is a drive current applied to the load element 62.

  On the other hand, in the output circuit 60, when the enable signal EN is in a disable state (for example, low level), the NMOS transistor N20 is turned off and the NMOS transistor N24 is turned on. As a result, the output current Iout is blocked by the NMOS transistor N20. Further, since the NMOS transistor N24 is turned on, the gates of the NMOS transistors N21 and N22 become the ground voltage, and the current mirror circuit configured by the NMOS transistors N21 and N22 is stopped. That is, the current I11 does not flow.

  From the above description, in the output circuit 60, the drive current for driving the load element 62 is determined by the output current Iout output from the constant current generation circuit 1. Therefore, if the variation rate of the output current Iout with respect to the temperature variation is zero, the output circuit 60 can keep the drive current constant regardless of the temperature variation. Further, the output circuit 60 can keep the amplitude of the voltage generated at both ends of the load element 62 constant regardless of the temperature fluctuation. Further, the constant current generation circuit 1 sets and outputs the current value of the output current Iout with high accuracy, whereby the amplitude of the voltage generated at both ends of the load element 62 can be set with high accuracy.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

DESCRIPTION OF SYMBOLS 1, 2 Constant current generation circuit 3 Microprocessor 10 Temperature fluctuation voltage generation part 11 Constant voltage generation part 12 Reference voltage generation part 13 Current generation part 21, 28 Error amplifier 22 Inclination adjustment part 23 1st decoder 24 Memory 25, 25a Curvature Correction unit 26, 26a Second decoder 27 Memory 30, 30a, 30b Oscillation circuit 31 Inverter 32, 34 Capacitance drive circuit 33, 35 Comparator 36 SR latch circuit 40 Frequency detection circuit 41 Ramp and hold circuit 42 Differential amplifier 43 Amplification unit 44 oscillator 45 control circuit 50 delay circuit 60 output circuit 61 inverter 62 load element C frequency setting capacitor C1, C2, Cd capacitor Cpump filter capacitor CLK clock signal COUNT count value Di diode HOLD hold Control signal INIT Charge reset signal PULSE Pump control signal RAMP Lamp control signal Iout Output current MEM Flash memory CG Clock generation circuit PE Operation core Rb Resistor Ri Current setting resistor SW Switch circuit SW0, SW11 to SW1m Switch Tout Output terminal Vconst Reference voltage VREF Oscillation Reference voltage Vrefc Second fluctuation voltage

Claims (19)

A temperature fluctuation voltage generator including a diode and outputting a forward voltage of the diode as a first fluctuation voltage;
A reference voltage generator that generates a second variable voltage based on the first variable voltage;
A current generation unit that includes a current setting resistor whose resistance value varies with temperature, and that generates an output current based on the second variable voltage and the current setting resistor;
The reference voltage generator is
A curvature correction unit that switches the magnitude of the current that flows per unit area of the diode according to a curvature setting value that determines the magnitude of the current that flows to the diode;
The inclination component with respect to the temperature of the fluctuation component of the first fluctuation voltage is adjusted, and the difference between the resistance value of the current setting resistor and the fluctuation rate with respect to the temperature is within a preset specified range with respect to the temperature of the voltage value. A slope adjusting unit that outputs the second fluctuation voltage having a fluctuation rate;
A constant current generating circuit.   The constant current generation circuit according to claim 1, wherein the curvature correction unit corrects a curvature component with respect to a temperature among fluctuation components of the first fluctuation voltage. The reference voltage generator is
An output transistor having one terminal connected to a second power source;
A first resistor and a second resistor connected in series between the other end of the output transistor and the anode of the diode;
Based on a difference between a feedback voltage generated at a node connecting the first resistor and the second resistor, and a reference voltage having a variation rate of a voltage value with respect to a temperature smaller than the first variation voltage. A first error amplifier that provides a control signal to the control terminal of the output transistor;
The constant current generation circuit according to claim 2, wherein the curvature correction unit controls a current flowing through the second resistor in accordance with the curvature setting value. The second resistor includes a plurality of curvature adjusting resistors connected in series,
The curvature correction unit
A plurality of switches each connected in parallel with any one of the plurality of curvature adjusting resistors;
The constant current generation circuit according to claim 3, further comprising a decoder that controls open / close states of the plurality of switches according to the curvature setting value. The diode includes a plurality of diodes,
The curvature correction unit
A plurality of switches having one end connected in series with any one of the plurality of diodes and the other end connected to the second resistor;
The constant current generation circuit according to claim 3, further comprising a decoder that controls open / close states of the plurality of switches according to the curvature setting value. The curvature correction unit has a storage unit for storing the curvature setting value,
The constant current generation circuit according to claim 3, wherein the curvature setting value is determined based on a value measured in an inspection process and written in the storage unit. The first resistor includes a plurality of slope adjustment resistors connected in series, and generates a plurality of slope adjustment voltages at connection points of the plurality of slope adjustment resistors,
The inclination adjusting unit is
The constant current generation circuit according to claim 3, wherein one voltage selected from the plurality of slope adjustment voltages based on the slope setting value is used as the second fluctuation voltage.   The constant current generation circuit according to claim 7, wherein the slope of the fluctuation rate of the voltage value with respect to the temperature of the slope adjustment voltage is in the same direction as the fluctuation slope of the current setting resistor with respect to temperature. The tilt adjustment unit includes a storage unit that stores the tilt setting value.
The constant current generation circuit according to claim 8, wherein the inclination setting value is determined based on a value measured in an inspection process and written in the storage unit. The reference voltage generator is
An amplifier configured by the first error amplifier, the output transistor, the first resistor, and the second resistor, wherein an amplification factor is set based on a ratio between the first resistor and the second resistor; The constant current generation circuit according to claim 3.   The constant current generation circuit according to claim 3, further comprising a reference voltage generation unit that generates the reference voltage based on a band gap voltage. The current generator is
A first transistor having a drain connected to a first power supply via the current setting resistor and a source connected to a second power supply;
A second error voltage is applied to the gate of the first transistor based on a voltage difference between a current setting voltage generated at a node between the first transistor and the current setting resistor and the second fluctuation voltage. An error amplifier;
A second transistor connected to the first transistor in a current mirror,
The first transistor outputs a current to the current setting resistor so that a voltage generated at both ends of the current setting resistor based on the error voltage becomes the second fluctuation voltage,
2. The constant current generation circuit according to claim 1, wherein the second transistor outputs, as the output current, a current proportional to a current that the first transistor passes through the current setting resistor. A memory for storing programs and setting values;
An arithmetic core that performs arithmetic processing based on the program stored in the memory;
A constant current generation circuit,
The constant current generation circuit includes:
A temperature fluctuation voltage generator including a diode and outputting a forward voltage of the diode as a first fluctuation voltage;
A reference voltage generator that generates a second variable voltage based on the first variable voltage;
A current generation unit that includes a current setting resistor whose resistance value varies with temperature, and that generates an output current based on the second variable voltage and the current setting resistor;
The reference voltage generator is
A curvature correction unit that switches the magnitude of the current that flows per unit area of the diode according to a curvature setting value that determines the magnitude of the current that flows to the diode;
The inclination component with respect to the temperature of the fluctuation component of the first fluctuation voltage is adjusted, and the difference between the resistance value of the current setting resistor and the fluctuation rate with respect to the temperature is within a preset specified range with respect to the temperature of the voltage value. A microprocessor that includes a slope adjustment unit that outputs the second fluctuation voltage having a fluctuation rate.   The microprocessor according to claim 13, wherein the curvature correction unit corrects a curvature component with respect to a temperature among fluctuation components of the first fluctuation voltage. The reference voltage generator is
An output transistor having one terminal connected to a second power source;
A first resistor and a second resistor connected in series between the other end of the output transistor and the anode of the diode;
Based on a difference between a feedback voltage generated at a node connecting the first resistor and the second resistor, and a reference voltage having a variation rate of a voltage value with respect to a temperature smaller than the first variation voltage. A first error amplifier that provides a control signal to the control terminal of the output transistor;
The microprocessor according to claim 14, wherein the curvature correction unit controls a current flowing through the second resistor in accordance with the curvature setting value.   The microprocessor according to claim 13, further comprising: an oscillation circuit that determines an oscillation frequency of an output signal based on the output current generated by the constant current generation circuit. The inclination adjusting unit includes a first storage unit that stores an inclination setting value for setting an inclination of the second fluctuation voltage,
The curvature correction unit includes a second storage unit that stores a curvature setting value for setting a correction amount of a curvature component with respect to temperature among the variation components of the first variation voltage,
The constant current generation circuit includes:
Generate the output current based on a preset initial slope setting value and initial curvature setting value,
The oscillation circuit generates the output signal based on the output current generated based on the initial slope setting value and the initial curvature setting value,
The arithmetic core operates based on the output signal output from the oscillation circuit, reads the slope setting value and the curvature setting value from the memory, and writes them to the first storage unit and the second storage unit,
After the inclination setting value and the curvature setting value are set in the first storage unit and the second storage unit, the constant current generation circuit sets the inclination setting value and the curvature setting value to be set. The microprocessor of claim 16, wherein the microprocessor generates the output current based on the microprocessor.   The microprocessor according to claim 13, further comprising a delay circuit in which a delay time is set based on the output current generated by the constant current generation circuit.   The microprocessor according to claim 13, further comprising an output circuit that determines a current value of a load drive current based on the output current generated by the constant current generation circuit.

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