JP2014110605A - Phase shift circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase shift circuit that implements a compact circuit size and higher design accuracy.SOLUTION: The phase shift circuit includes: a field effect transistor 2 connected between an input/output terminal 1a and an input/output terminal 1b; a capacitor 3 having one end connected to the input/output terminal 1a; a capacitor 4 having one end connected to the input/output terminal 1b and the other end connected to the other end of the capacitor 3; an inductor 5 having one end connected to the other ends of the capacitors 3, 4; an inductor 6 having one end connected to the other end of the inductor 5 and the other end grounded; and a field effect transistor 7 having one end connected to the other end of the inductor 5 and the other end grounded.

Description

  The present invention relates to, for example, a phase shift circuit that changes the passage phase of a microwave.

For example, the conventional phase shift circuit disclosed in the following Patent Document 1 includes three field effect transistors (switching elements) and an inductor or a capacitor such as a high impedance line as shown in FIG. Yes.
In the conventional phase shift circuit, the circuit state is set to a high-pass filter or a band-pass filter by switching the on / off state of the three field effect transistors, and required depending on the difference in the pass phase between the two circuit states. The amount of phase shift is obtained.

In addition, since the inductance and the capacitance value required for the phase shift circuit become smaller as the frequency becomes higher, the field effect transistor occupies most of the size of the phase shift circuit.
Further, the field effect transistor cannot ideally pass / cut off the path, and the influence of parasitic components such as the field effect transistor becomes more significant as the frequency becomes higher.

Japanese Patent Laid-Open No. 2002-344201 (FIG. 11)

  Since the conventional phase shift circuit is configured as described above, the circuit state can be set to a high-pass filter or a band-pass filter by switching the on / off states of the three field effect transistors. However, since it is necessary to mount three field effect transistors that occupy most of the circuit, there is a problem that it is difficult to reduce the circuit size and improve the design accuracy.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a phase shift circuit capable of reducing the circuit size and improving the design accuracy.

  The phase shift circuit according to the present invention has a first switching element connected between the first input / output terminal and the second input / output terminal, and one end connected to the first input / output terminal. A first capacitor; one end connected to the second input / output terminal; the other end connected to the other end of the first capacitor; and one end other than the first and second capacitors. A first inductor connected to one end, a second inductor having one end connected to the other end of the first inductor and the other end grounded to the ground, and one end connected to the other end of the first inductor. And a second switching element connected at the other end to the ground.

  According to this invention, the first switching element connected between the first input / output terminal and the second input / output terminal, and the first switching element having one end connected to the first input / output terminal. A capacitor, one end connected to the second input / output terminal, the other end connected to the other end of the first capacitor, and one end connected to the other ends of the first and second capacitors A first inductor, one end connected to the other end of the first inductor, the other end connected to the ground, and one end connected to the other end of the first inductor, Since the second switching element having the other end grounded to the ground is provided, the circuit size can be reduced and the design accuracy can be improved.

It is a block diagram which shows the phase shift circuit by Embodiment 1 of this invention. It is an equivalent circuit which shows a phase shift circuit in the phase shift reference state. It is an equivalent circuit showing a phase shift circuit in a phase shift delay state. It is a block diagram which shows the phase shift circuit by Embodiment 2 of this invention. It is an equivalent circuit which shows a phase shift circuit in the phase shift reference state. It is an equivalent circuit showing a phase shift circuit in a phase shift delay state. It is a block diagram which shows the phase shift circuit by Embodiment 3 of this invention. It is a block diagram which shows the other phase shift circuit by Embodiment 3 of this invention. It is a block diagram which shows the other phase shift circuit by Embodiment 3 of this invention. It is a block diagram which shows the other phase shift circuit by Embodiment 3 of this invention. It is a block diagram which shows the conventional phase shift circuit currently disclosed by patent document 1. FIG.

Embodiment 1 FIG.
1 is a block diagram showing a phase shift circuit according to Embodiment 1 of the present invention.
In FIG. 1, a field effect transistor 2 is connected between an input / output terminal 1a (first input / output terminal) and an input / output terminal 1b (second input / output terminal), and a control voltage of 0 V is applied to a gate terminal. When applied to the gate terminal, the element is turned on and equivalently represented by a resistance, while when a control voltage equal to or lower than the pinch-off voltage is applied to the gate terminal, the element turned off and equivalently represented by a capacitance It is.
Hereinafter, the resistance of the field effect transistor 2 in the on state is referred to as “on resistance”, and the capacitance of the field effect transistor 2 in the off state is referred to as “off capacitance”.
The field effect transistor 2 constitutes a first switching element.

The capacitor 3 is a first capacitor having one end connected to the input / output terminal 1a.
The capacitor 4 is a second capacitor having one end connected to the input / output terminal 1 b and the other end connected to the other end of the capacitor 3.
The inductor 5 is a first inductor whose one end is connected to the other ends of the capacitors 3 and 4.
The inductor 6 is a second inductor having one end connected to the other end of the inductor 5 and the other end grounded to the ground.

The field effect transistor 7 has one end connected to the other end of the inductor 5 and the other end grounded to the ground. Like the field effect transistor 2, the field effect transistor 7 is turned on when a control voltage of 0 V is applied to the gate terminal. On the other hand, when a control voltage equal to or lower than the pinch-off voltage is applied to the gate terminal, the element is turned off and equivalently represented by a capacitance.
The field effect transistor 7 constitutes a second switching element.

Next, the operation will be described.
The phase shift circuit of FIG. 1 can set the circuit state to the phase shift reference state or the phase shift delay state by switching the on / off states of the field effect transistors 2 and 7.
That is, when the field effect transistor 2 is turned off and the field effect transistor 7 is turned on, the circuit state becomes the phase shift reference state, and when the field effect transistor 2 is turned on and the field effect transistor 7 is turned off, the circuit state Enters the phase shift delay state.

FIG. 2 is an equivalent circuit showing a phase shift circuit in the phase shift reference state.
When the field effect transistor 2 is turned off, the field effect transistor 7 is turned on, and the circuit state of the phase shift circuit becomes the phase shift reference state, an equivalent circuit of the phase shift circuit is expressed as shown in FIG.
In Figure 2, it represents the off capacitance of the field effect transistor 2 at _{C 1OFF,} represents the on-resistance of the field effect transistor 7 _{R 2ON.}

When the circuit state of the phase shift circuit is the phase shift reference state, _{assuming that} the impedance of the off-capacitance _C1OFF of the field effect transistor 2 is sufficiently large at the required frequency (for example, the off-capacitance of the field-effect transistor 2 at a frequency of 10 GHz) _When the impedance of C _1OFF is about 0.1 pF), the off-capacitance C _1OFF of the field effect transistor 2 can be regarded as an almost open circuit.
On the other hand, when the on-resistance R _2ON of the field effect transistor 7 is sufficiently small (for example, when the on-resistance R _2ON is about 2Ω), the on-resistance R _2ON of the field effect transistor 7 is substantially a through circuit. Can be considered.

At this time, the phase shift circuit of FIG. 2 operates as a T-type high-pass filter composed of three elements of the capacitors 3 and 4 and the inductor 5.
By appropriately setting the circuit constants of the capacitors 3 and 4 and the inductor 5, the pass phase can be advanced in the range of 0 ° to 90 ° at the pass center frequency of the T-type high-pass filter.
Therefore, if the circuit constants of the capacitors 3 and 4 and the inductor 5 are set so that the pass phase becomes a lead phase of 90 ° at the pass center frequency of the high-pass filter, the pass phase can be advanced by 90 °.
In addition, if the circuit constants of the capacitors 3 and 4 and the inductor 5 are set so that the passing phase becomes a leading phase of 45 ° at the passing center frequency of the high-pass filter, the passing phase can be advanced by 45 °.
Since the method of setting the circuit constants of the capacitors 3 and 4 and the inductor 5 is a known technique, detailed description thereof is omitted.

FIG. 3 is an equivalent circuit showing a phase shift circuit in the phase shift delay state.
When the field effect transistor 2 is turned on, the field effect transistor 7 is turned off, and the circuit state of the phase shift circuit becomes a phase shift delay state, an equivalent circuit of the phase shift circuit is expressed as shown in FIG.
In Figure 3, it represents the on-resistance of the field effect transistor 2 at _{R 1ON,} represents the off capacitance of the field effect transistor 7 in _{C 2off.}

When the on-resistance R _1ON of the field effect transistor 2 is sufficiently small when the circuit state of the phase shift circuit is a phase-shift delay state (for example, when the on-resistance R _1ON is about 2Ω), the field effect transistor 2 on-resistance R _1ON can be regarded as almost-through circuit.
On the other hand, _{assuming that} the impedance of the off-capacitance C _2OFF of the field effect transistor 7 is sufficiently large at the required frequency (for example, the frequency is 10 GHz and the impedance of the off-capacitance C _2OFF of the field effect transistor 7 is about 0.1 pF). ), The off-capacitance _C2OFF of the field effect transistor 7 can be regarded as an almost open circuit.

At this time, in the phase shift circuit of FIG. 3, a parallel resonator is constituted by the inductor 6 and the off-capacitance _C2OFF of the field effect transistor 7, and this parallel resonator operates as a band pass filter.
This band pass filter is a filter whose pass phase is 0 ° at the pass center frequency.
Therefore, the phase shift circuit of FIG. 1 can switch the circuit state to the phase shift reference state or the phase shift delay state by switching the on / off states of the field effect transistors 2 and 7.

  As apparent from the above, according to the first embodiment, the field effect transistor 2 connected between the input / output terminal 1a and the input / output terminal 1b and one end thereof are connected to the input / output terminal 1a. The capacitor 3, one end connected to the input / output terminal 1b, the other end connected to the other end of the capacitor 3, the inductor 5 connected to the other end of the capacitors 3 and 4, and one end Is connected to the other end of the inductor 5, the other end is grounded to the ground, and a field effect transistor 7 having one end connected to the other end of the inductor 5 and the other end grounded to the ground. With this configuration, the circuit state can be switched to the phase shift reference state or the phase shift delay state by simply mounting the two field effect transistors 2 and 7, and as a result, the circuit size can be changed. An effect that it is possible to improve the miniaturization and design accuracy of.

Embodiment 2. FIG.
4 is a block diagram showing a phase shift circuit according to Embodiment 2 of the present invention. In the figure, the same reference numerals as those in FIG.
The inductor 11 is a first inductor having one end connected to the input / output terminal 1a.
The inductor 12 is a second inductor having one end connected to the input / output terminal 1 b and the other end connected to the other end of the inductor 11.
The capacitor 13 is a first capacitor whose one end is connected to the other ends of the inductors 11 and 12.
The capacitor 14 is a second capacitor having one end connected to the other end of the capacitor 13 and the other end grounded to the ground.

Next, the operation will be described.
The phase shift circuit of FIG. 4 can set the circuit state to the phase shift reference state or the phase shift delay state by switching the on / off states of the field effect transistors 2 and 7.
That is, when the field effect transistor 2 is turned on and the field effect transistor 7 is turned off, the circuit state becomes the phase shift reference state, and when the field effect transistor 2 is turned off and the field effect transistor 7 is turned on, the circuit state is changed. Enters the phase shift delay state.

FIG. 5 is an equivalent circuit showing a phase shift circuit in the phase shift reference state.
When the field effect transistor 2 is turned on, the field effect transistor 7 is turned off, and the circuit state of the phase shift circuit becomes the phase shift reference state, an equivalent circuit of the phase shift circuit is expressed as shown in FIG.
In Figure 5, represents the on-resistance of the field effect transistor 2 at _{R 1ON,} represents the off capacitance of the field effect transistor 7 in _{C 2off.}

When the on-resistance R _1ON of the field effect transistor 2 is sufficiently small when the circuit state of the phase shift circuit is the phase shift reference state (for example, when the on-resistance R _1ON is about 2Ω), the field effect transistor 2 on-resistance R _1ON can be regarded as almost-through circuit.
On the other hand, _{assuming that} the impedance of the off-capacitance C _2OFF of the field effect transistor 7 is sufficiently large at the required frequency (for example, the frequency is 10 GHz and the impedance of the off-capacitance C _2OFF of the field effect transistor 7 is about 0.1 pF). ), The off-capacitance _C2OFF of the field effect transistor 7 can be regarded as an almost open circuit.

At this time, in the phase shift circuit of FIG. 5, a parallel resonator is configured by the inductor 14 and the off-capacitance _C2OFF of the field effect transistor 7, and this parallel resonator operates as a bandpass filter.
This band pass filter is a filter whose pass phase is 0 ° at the pass center frequency.

FIG. 6 is an equivalent circuit showing the phase shift circuit in the phase shift delay state.
When the field effect transistor 2 is turned off, the field effect transistor 7 is turned on, and the circuit state of the phase shift circuit becomes a phase shift delay state, an equivalent circuit of the phase shift circuit is expressed as shown in FIG.
In Figure 6, it represents the off capacitance of the field effect transistor 2 at _{C 1OFF,} represents the on-resistance of the field effect transistor 7 _{R 2ON.}

When the circuit state of the phase shift circuit is a phase shift delay state, if the off-capacitance C _1OFF of the field effect transistor 2 is sufficiently large at the required frequency (for example, the frequency is 10 GHz and the off-capacitance C _1OFF of the field effect transistor 2 is In other _words, the off-capacitance C _1OFF of the field effect transistor 2 can be regarded as an almost open circuit.
On the other hand, when the on-resistance R _2ON of the field effect transistor 7 is sufficiently small (for example, when the on-resistance R _2ON is about 2Ω), the on-resistance R _2ON of the field effect transistor 7 is substantially a through circuit. Can be considered.

At this time, the phase shift circuit of FIG. 6 operates as a T-type low-pass filter including three elements of the inductors 11 and 12 and the capacitor 13.
By appropriately setting the circuit constants of the inductors 11 and 12 and the capacitor 13, the pass phase can be delayed in the range of 0 ° to 90 ° at the pass center frequency of the T-type low-pass filter.
Therefore, if the circuit constants of the inductors 11 and 12 and the capacitor 13 are set so that the passing phase becomes a delayed phase of 90 ° at the passing center frequency of the low-pass filter, the passing phase can be delayed by 90 °.
Further, if the circuit constants of the inductors 11 and 12 and the capacitor 13 are set so that the passing phase is a delayed phase of 45 ° at the passing center frequency of the low-pass filter, the passing phase can be delayed by 45 °.
Since the method of setting the circuit constants of the inductors 11 and 12 and the capacitor 13 is a known technique, detailed description thereof is omitted.
Therefore, the phase shift circuit of FIG. 4 can switch the circuit state to the phase shift reference state or the phase shift delay state by switching the on / off states of the field effect transistors 2 and 7.

  As apparent from the above, according to the first embodiment, the field effect transistor 2 connected between the input / output terminal 1a and the input / output terminal 1b and one end thereof are connected to the input / output terminal 1a. Inductor 11, one end connected to input / output terminal 1b, the other end connected to the other end of inductor 11, capacitor 13, one end connected to the other end of inductors 11 and 12, and one end Is connected to the other end of the capacitor 13, the other end is grounded to the ground, and a field effect transistor 7 having one end connected to the other end of the capacitor 13 and the other end grounded to the ground. Since it is configured as described above, the circuit state can be switched to the phase shift reference state or the phase shift delay state simply by mounting the two field effect transistors 2 and 7. As a result, an effect that it is possible to improve the miniaturization and design accuracy of the circuit size.

Embodiment 3 FIG.
7 is a block diagram showing a phase shift circuit according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in FIG.
The capacitor 21 is an element connected in parallel with the field effect transistor 2.
The capacitor 22 is an element connected in parallel with the field effect transistor 7.

Compared with the phase shift circuit of FIG. 1 in the first embodiment, the difference is that capacitors 21 and 22 are connected in parallel with field effect transistors 2 and 7.
When the field effect transistor 2 is in the off state, the off-capacitance of the parallel circuit composed of the field-effect transistor 2 and the capacitor 21 is expressed as a combined capacity of the off-capacitance C _1OFF of the field-effect transistor 2 and the capacity of the capacitor 21.
For this reason, the size of the field effect transistor 2 can be made smaller than in the first embodiment.
That is, the off-capacitance of the parallel circuit represented by the combined capacitance of the off-capacitance C _1OFF of the field effect transistor 2 and the capacitance of the capacitor 21 becomes the same value as the off-capacitance C _1OFF of the field effect transistor 2 in the first embodiment. Therefore, the size of the field effect transistor 2 in the third embodiment can be reduced. In general, the size of a fixed-capacitance capacitor is sufficiently smaller than the size of a transistor for obtaining an equivalent capacitance value, so that an equivalent capacitance value can be realized with a small circuit size.

Similarly, when the field effect transistor 7 is in the off state, the off capacitance of the parallel circuit including the field effect transistor 7 and the capacitor 22 is _expressed as a combined capacitance of the off capacitance C _2OFF of the field effect transistor 7 and the capacitance of the capacitor 22. Is done.
For this reason, the size of the field effect transistor 7 can be made smaller than in the first embodiment.
That is, the off-capacitance of the parallel circuit represented by the combined capacitance of the off-capacitance C _2OFF of the field effect transistor 7 and the capacitance of the capacitor 22 becomes the same value as the off-capacitance C _2OFF of the field effect transistor 7 in the first embodiment. Therefore, the size of the field effect transistor 7 in the third embodiment can be reduced.

When the field effect transistors 2 and 7 are in the off state, if the off-capacitances C _1OFF and C _2OFF of the field effect transistors 2 and 7 are sufficiently large at the required frequency, as in the first embodiment, the field effect transistors The off capacitances C _1OFF and C _2OFF of 2 and 7 can be regarded as almost open circuits.
On the other hand, if the field effect transistor 2 and 7 is on, the field effect transistor 2 and 7 of the on-resistance _{R 1ON,} when _{R 2ON} is sufficiently small, the ON resistance of the FET 2 and 7 _{R 1ON, R 2ON} is Can be regarded as a nearly through circuit.

  As apparent from the above, according to the third embodiment, since the capacitors 21 and 22 are connected in parallel with the field effect transistors 2 and 7, an operation equivalent to that of the first embodiment is realized. However, the size of the field effect transistors 2 and 7 can be reduced and the circuit size can be further reduced as compared with the first embodiment.

  In the third embodiment, the capacitors 21 and 22 are connected in parallel with the field effect transistors 2 and 7. However, as shown in FIG. 8, resistors 23 and 24 are connected in parallel with the field effect transistors 2 and 7, respectively. You may make it connect, and there can exist the same effect.

In the third embodiment, the capacitors 21 and 22 are connected in parallel with the field effect transistors 2 and 7 of the phase shift circuit of FIG. 1 in the first embodiment, but as shown in FIG. The capacitors 21 and 22 may be connected in parallel with the field effect transistors 2 and 7 of the phase shift circuit of FIG. 4 in the second embodiment, and similar effects can be obtained.
Moreover, as shown in FIG. 10, resistors 23 and 24 may be connected in parallel with the field effect transistors 2 and 7 of the phase shift circuit of FIG. Can do.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  1a input / output terminal (first input / output terminal), 1b input / output terminal (second input / output terminal), 2 field effect transistor (first switching element), 3 capacitor (first capacitor), 4 capacitor ( Second capacitor), 5 inductor (first inductor), 6 inductor (second inductor), 7 field effect transistor (second switching element), 11 inductor (first inductor), 12 inductor (second inductor) Inductor, 13 capacitor (first capacitor), 14 capacitor (second capacitor), 21, 22 capacitor, 23, 24 resistance.

Claims (8)

A first switching element connected between the first input / output terminal and the second input / output terminal;
A first capacitor having one end connected to the first input / output terminal;
A second capacitor having one end connected to the second input / output terminal and the other end connected to the other end of the first capacitor;
A first inductor having one end connected to the other end of the first and second capacitors;
A second inductor having one end connected to the other end of the first inductor and the other end grounded to ground;
A second switching element having one end connected to the other end of the first inductor and the other end grounded to the ground.   When the first switching element is in the off state and the second switching element is in the on state, the passing phase by the filter composed of the first and second capacitors and the first inductor becomes a leading phase of 90 degrees. 2. The phase shift circuit according to claim 1, wherein circuit constants of the first and second capacitors and the first inductor are set.   When the first switching element is in the OFF state and the second switching element is in the ON state, the passing phase by the filter composed of the first and second capacitors and the first inductor becomes a 45-degree lead phase. 2. The phase shift circuit according to claim 1, wherein circuit constants of the first and second capacitors and the first inductor are set. A first switching element connected between the first input / output terminal and the second input / output terminal;
A first inductor having one end connected to the first input / output terminal;
A second inductor having one end connected to the second input / output terminal and the other end connected to the other end of the first inductor;
A first capacitor having one end connected to the other end of the first and second inductors;
A second capacitor having one end connected to the other end of the first capacitor and the other end grounded to ground;
A second switching element having one end connected to the other end of the first capacitor and the other end grounded to the ground.   When the first switching element is in the off state and the second switching element is in the on state, the passing phase by the filter composed of the first and second inductors and the first capacitor becomes a delayed phase of 90 degrees. 5. The phase shift circuit according to claim 4, wherein circuit constants of the first and second inductors and the first capacitor are set.   When the first switching element is in the off state and the second switching element is in the on state, the passing phase by the filter composed of the first and second inductors and the first capacitor becomes a delayed phase of 45 degrees. 5. The phase shift circuit according to claim 4, wherein circuit constants of the first and second inductors and the first capacitor are set.   The phase shift circuit according to any one of claims 1 to 6, wherein a capacitor is connected in parallel with at least one of the first switching element and the second switching element.   The phase shift circuit according to claim 1, wherein a resistor is connected in parallel with at least one of the first switching element and the second switching element.

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