JP2014107891A - Dc-dc converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DC-DC converter that allows obtaining both accuracy and high responsiveness of a DC output voltage.SOLUTION: A control circuit 4 includes a feedback control section 5, a lower-limit-side feedforward control section 14, and a logic circuit 16. The feedback control section 5 adjusts the duty ratio of a first control signal Vc1 on the basis of an integral value obtained by integrating a difference ΔV between a voltage value of a DC output voltage Vout and a target voltage value V0. The lower-limit-side feedforward control section 14 switches a second control signal Vc2 from Low to High when the voltage value of the DC output voltage Vout is lower than a lower-limit voltage value Vth1. The logic circuit 16 supplies a switching signal Vsw according to the logical sum of the first control signal Vc1 and the second control signal Vc2 to a gate of a transistor Q.

Description

  The present invention relates to a DC-DC converter that converts a voltage using a switching element.

  As a DC-DC converter, a switching element that switches a DC input voltage and a control circuit that controls the switching element, and supplies a DC output voltage to a load in accordance with the ON / OFF duty ratio of the switching element are known. (For example, refer to Patent Document 1). In a general DC-DC converter, in order to reduce the steady-state deviation with respect to the target voltage value, the deviation between the voltage value of the DC output voltage and the target voltage value is integrated, and the duty ratio is controlled according to the integrated value. Yes. On the other hand, in the DC-DC converter described in Patent Document 1, in order to obtain a high-speed response of the DC output voltage, the voltage drop value of the reactor (choke coil) connected to the output side of the switching element is used as a reference value. In comparison, a control signal for the switching element is generated.

JP 2005-218157 A

  By the way, in the DC-DC converter using the general integration control, when the load current changes rapidly, it cannot respond instantaneously, and a voltage drop may occur in the DC output voltage during that time. Depending on the level of such a voltage drop, there is a risk of causing problems in the load-side system.

  On the other hand, in the DC-DC converter described in Patent Document 1, since feedforward control is performed, responsiveness can be improved as compared with the case where integral control is used. However, since the control signal of the switching element is generated according to the voltage drop value of the reactor, if the element variation occurs in the reactor, the DC output voltage also varies accordingly, and the accuracy with respect to the target voltage value tends to be low. . In consideration of this point, when the variation in the reactor elements is reduced, it is necessary to use a highly accurate reactor, and there is a problem that the component cost and the product cost increase. Furthermore, in order to detect the voltage drop of the reactor, it is necessary to perform time-series sampling, and there is a problem that the processing of the control circuit becomes complicated.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a DC-DC converter capable of obtaining both the accuracy and high responsiveness of a DC output voltage.

  In order to solve the above-mentioned problem, the invention of claim 1 includes a switching element that switches a DC input voltage and a control circuit that controls the switching element, and according to a duty ratio of ON and OFF of the switching element. A DC-DC converter that supplies a DC output voltage to a load, wherein the control circuit sets a duty ratio of the switching element according to an integral value obtained by integrating a difference between a voltage value of the DC output voltage and a target voltage value. A feedback control unit that outputs a first control signal to be adjusted; and a second control signal that turns on the switching element when the voltage value of the DC output voltage falls below a predetermined lower limit voltage value. A lower limit side feedforward control unit for outputting, and the switching element when the voltage value of the DC output voltage is higher than the lower limit voltage value. The first outputs the control signal has a configuration in which the voltage value of the DC output voltage and a logic circuit for outputting the second control signal to the switching element when less than the lower limit voltage value.

  According to a second aspect of the present invention, the control circuit outputs an upper limit for outputting a third control signal that turns off the switching element when the voltage value of the DC output voltage rises above a predetermined upper limit voltage value. A side feedforward control unit, wherein the logic circuit controls the switching element when the voltage value of the DC output voltage falls within a range between the upper limit voltage value and the lower limit voltage value. A signal is output, and when the voltage value of the DC output voltage is lower than the lower limit voltage value, the second control signal is output to the switching element, and the voltage value of the DC output voltage is higher than the upper limit voltage value. When the voltage is high, the third control signal is output to the switching element.

  In the invention of claim 3, the output side of the switching element is directly connected to the load.

  According to a fourth aspect of the present invention, the output side of the switching element is indirectly connected to the load via a transformer.

  According to the first aspect of the invention, when the voltage value of the DC output voltage is higher than the lower limit voltage value, the logic circuit outputs the first control signal to the switching element. At this time, since the duty ratio of the switching element is adjusted according to the integral value obtained by integrating the difference between the voltage value of the DC output voltage and the target voltage value, the steady deviation between the voltage value of the DC output voltage and the target voltage value is The accuracy of the DC output voltage can be increased.

  On the other hand, when the voltage value of the DC output voltage is lower than the lower limit voltage value, the logic circuit outputs the second control signal to the switching element. At this time, since the switching element is turned on, the DC output voltage can be quickly increased. For this reason, even when the load current changes abruptly, the voltage drop generated in the DC output voltage can be quickly compensated, and the responsiveness can be improved.

  According to the invention of claim 2, when the voltage value of the DC output voltage falls within the range between the upper limit voltage value and the lower limit voltage value, the logic circuit outputs the first control signal to the switching element. At this time, the voltage value of the DC output voltage is close to the target voltage value between the upper limit voltage value and the lower limit voltage value. For this reason, the logic circuit outputs the first control signal to the switching element, can reduce the steady deviation between the voltage value of the DC output voltage and the target voltage value, and can increase the accuracy of the DC output voltage. .

  Further, when the voltage value of the DC output voltage is lower than the lower limit voltage value, the logic circuit outputs the second control signal to the switching element, so that the DC output voltage can be quickly increased by turning on the switching element. it can. On the other hand, when the voltage value of the DC output voltage is higher than the upper limit voltage value, the logic circuit outputs the third control signal to the switching element. Therefore, the switching element is turned off to quickly reduce the DC output voltage. it can. For this reason, even when the load current suddenly increases or decreases and the DC output voltage changes, this change can be quickly compensated, and the responsiveness can be improved.

  According to the invention of claim 3, since the output side of the switching element is directly connected to the load, it can be applied to a non-insulated DC-DC converter.

  According to the invention of claim 4, since the output side of the switching element is indirectly connected to the load via the transformer, it can be applied to an insulation type DC-DC converter.

1 is a circuit diagram showing a DC-DC converter according to a first embodiment of the present invention. It is explanatory drawing which shows the time change of an output current and output voltage when load current increases. It is a characteristic diagram which shows the time change of an output voltage when load current increases. It is a circuit diagram which shows the DC-DC converter by the 2nd Embodiment of this invention. It is explanatory drawing which shows the time change of an output current and output voltage when load current reduces. It is a circuit diagram which shows the DC-DC converter by the 3rd Embodiment of this invention.

  Hereinafter, a DC-DC converter according to an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a DC-DC converter 1 according to the first embodiment. The DC-DC converter 1 includes a DC power source 2, a capacitor Cin, a transistor Q, a diode D, a choke coil L, a capacitor Cout, a control circuit 4, and the like, and constitutes a non-insulated DC-DC converter.

  The DC power supply 2 supplies a DC input voltage Vin. The DC power supply 2 has one end connected to the source of the transistor Q and the other end connected to the ground. An input side capacitor Cin is connected to the DC power source 2 in parallel. For this reason, the capacitor Cin is connected between one end of the DC power supply 2 and the ground.

  The transistor Q is, for example, an n-channel field effect transistor (n-type MOSFET) and constitutes a switching element. The drain of the transistor Q is connected to one end of the choke coil L, and the other end of the choke coil L is connected to the output terminal Po. The transistor Q switches the DC input voltage Vin to convert it to a pulse voltage.

  The diode D has a cathode connected to one end of the choke coil L and an anode connected to the ground. The diode D constitutes a free wheel diode and releases energy stored in the choke coil L. The other end of the choke coil L is connected to the ground via an output-side capacitor Cout that is a smoothing capacitor.

  A load 3 and a control circuit 4 are connected to the output terminal Po. The control circuit 4 includes a feedback control unit 5, a lower limit side feedforward control unit 14, and a logic circuit 16.

  The feedback control unit 5 includes a detection circuit 6, an integration calculation unit 7, and a PWM control unit 10. The detection circuit 6 includes resistors R1 and R2 connected in series between the output terminal Po and the ground. The detection circuit 6 divides the DC output voltage Vout by the resistors R 1 and R 2 and outputs the divided detection voltage Vs to the error amplifier 8 of the integration calculation unit 7.

  The integration calculation unit 7 includes an error amplifier 8 and a phase compensator 9. The error amplifier 8 compares the detection voltage Vs with the reference voltage Vref and calculates a difference ΔV between the voltage value of the DC output voltage Vout and the target voltage value V0. At this time, the reference voltage Vref is set as a voltage value corresponding to the target voltage value V0, for example, a value obtained by dividing the target voltage value V0 by the resistors R1 and R2. The error amplifier 8 is constituted by, for example, a differential amplifier, amplifies the difference between the detection voltage Vs and the reference voltage Vref, and outputs an error signal. The phase compensator 9 compensates the phase shift of the feedback control unit 5 by integrating the error signal. Therefore, the integral calculation unit 7 calculates an integral value obtained by integrating the difference ΔV between the voltage value of the DC output voltage Vout and the target voltage value V0, and outputs an integral signal Vint corresponding to the integral value.

  The PWM control unit 10 includes a PWM comparator 11, an oscillator 12, and a switch driver 13, and adjusts the duty ratio of the transistor Q according to the integration signal Vint. Here, the oscillator 12 outputs a sawtooth signal Vramp having a predetermined frequency. The PWM comparator 11 compares the sawtooth signal Vramp from the oscillator 12 and the integral signal Vint, and turns on when the sawtooth signal Vramp is larger than the integral signal Vint, for example, and is sawtooth than the integral signal Vint. When the signal Vramp is small, the PWM signal Vp turned off is output. At this time, the duty ratio of the PWM signal Vp decreases as the integrated signal Vint increases, and the duty ratio of the PWM signal Vp increases as the integrated signal Vint decreases. The PWM signal Vp is converted into a voltage for switching the transistor Q by the switch driver 13 and output as the first control signal Vc1. The oscillator 12 is not limited to the sawtooth wave signal, and may output a triangular wave signal, for example.

  The lower limit side feedforward control unit 14 includes a lower limit voltage detector 15. The lower limit voltage detector 15 is configured by, for example, a comparator, compares the DC output voltage Vout with a predetermined lower limit voltage value Vth1, and outputs a second control signal Vc2 corresponding to the comparison result. Here, the lower limit voltage value Vth1 is, for example, a value lower than the lower limit of the allowable range (for example, when ± 2 to 5% of the target voltage value V0 is the allowable range of fluctuation of the DC output voltage Vout at the normal time) (for example, It is set to a value of about -7 to 20% of the target voltage value V0). The lower limit voltage value Vth1 is set to a value higher than this voltage value in order to prevent the DC output voltage Vout from becoming lower than the target voltage value V0 and causing a problem in the behavior of the load 3. Has been.

  When the voltage value of the DC output voltage Vout is higher than the lower limit voltage value Vth1, the lower limit voltage detector 15 outputs the second control signal Vc2 that is Low. On the other hand, when the voltage value of the DC output voltage Vout falls below the lower limit voltage value Vth1, the lower limit voltage detector 15 switches the second control signal Vc2 from Low to High.

  The logic circuit 16 is configured by, for example, an OR gate 17. The OR gate 17 receives the first control signal Vc1 and the second control signal Vc2, and outputs a switching signal Vsw corresponding to the logical sum of these signals to the gate of the transistor Q. Here, at the normal time when the DC output voltage Vout is near the target voltage value V0, the voltage value of the DC output voltage Vout is higher than the lower limit voltage value Vth1, and therefore the second control signal Vc2 by the lower limit side feedforward control unit 14 is used. Is Low. At this time, the OR gate 17 outputs the switching signal Vsw corresponding to the first control signal Vc1 to the gate of the transistor Q. Thereby, the transistor Q is repeatedly turned on and off according to the PWM signal Vp whose duty ratio is feedback controlled.

  On the other hand, when the DC output voltage Vout falls below the lower limit voltage value Vth1, the second control signal Vc2 from the lower limit side feedforward control unit 14 becomes High. At this time, the OR gate 17 outputs the switching signal Vsw which becomes High corresponding to the second control signal Vc2 to the gate of the transistor Q. Thereby, the transistor Q is fixed on.

  The DC-DC converter 1 according to the present embodiment is configured as described above. During normal times when the voltage value of the DC output voltage Vout is higher than the lower limit voltage value Vth1, the control circuit 4 includes a feedback control unit 5. The transistor Q is controlled by the first control signal Vc1. At this time, since the duty ratio of the first control signal Vc1 is adjusted according to an integral value obtained by integrating the difference ΔV between the voltage value of the DC output voltage Vout and the target voltage value V0, the transistor Q ON and OFF are repeated according to the control signal Vc1. As a result, the load 3 is supplied with the DC output voltage Vout subjected to feedback control in the vicinity of the target voltage value V0, so that the steady-state deviation between the voltage value of the DC output voltage Vout and the target voltage value V0 can be reduced. The accuracy of the DC output voltage Vout can be increased.

  On the other hand, as shown in FIG. 2, when the load 3 fluctuates and the load current increases greatly in a short time (current difference + ΔI occurs), insufficient charge occurs and a large voltage drop occurs in the DC output voltage Vout. There are things to do. When the DC output voltage Vout drops below the lower limit voltage value Vth1 due to such a voltage drop, the control circuit 4 fixes the transistor Q on by the second control signal Vc2 from the lower limit side feedforward control unit 14. As a result, the DC output voltage Vout rises, so that the response can be improved and the voltage drop can be compensated quickly. As a result, problems on the load 3 side due to voltage drop can be prevented in advance, and the load 3 can be operated stably.

  FIG. 3 shows the time change of the DC output voltage Vout when the load current increases from 2 A to 10 A, for example, in the comparative example in which the lower limit side feedforward control unit 14 is omitted and the present embodiment. As shown in FIG. 3A, in the case of the comparative example, a voltage drop of 79.5 mV occurs, and 30 μs is required as a recovery time until the voltage returns to the vicinity of the target voltage value V0. On the other hand, as shown in FIG. 3B, in the present embodiment, the voltage drop can be suppressed to 39.5 mV, and the recovery time can be shortened to about 20 μs.

  Next, FIG. 4 shows a second embodiment of the present invention. The feature of the second embodiment is that the control circuit includes an upper limit side feedforward control unit that outputs a third control signal that turns off the switching element when the voltage value of the DC output voltage rises above the upper limit voltage value. It is to prepare further. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The DC-DC converter 21 includes a DC power source 2, a capacitor Cin, a transistor Q, a diode D, a choke coil L, a capacitor Cout, a control circuit 22, and the like, almost the same as the DC-DC converter 1 according to the first embodiment. . The control circuit 22 includes a feedback control unit 5, a lower limit side feedforward control unit 14, an upper limit side feedforward control unit 23, and a logic circuit 25.

  The upper limit side feedforward control unit 23 includes an upper limit voltage detector 24. The upper limit voltage detector 24 is constituted by, for example, a comparator, compares the DC output voltage Vout with a predetermined upper limit voltage value Vth2, and outputs a third control signal Vc3 according to the comparison result. Here, the upper limit voltage value Vth2 is, for example, a value higher than the upper limit of the allowable range (for example, when ± 2 to 5% of the target voltage value V0 is the allowable range of fluctuation of the DC output voltage Vout in the normal state) It is set to a value of about +8 to 20% of the target voltage value V0). Further, the upper limit voltage value Vth2 is set to a value lower than this voltage value in order to prevent the DC output voltage Vout from becoming higher than the target voltage value V0 and causing a problem in the behavior of the load 3. Has been.

  When the voltage value of the DC output voltage Vout is lower than the upper limit voltage value Vth2, the upper limit voltage detector 24 outputs the third control signal Vc3 that is High. On the other hand, when the voltage value of the DC output voltage Vout rises above the upper limit voltage value Vth2, the upper limit voltage detector 24 switches the third control signal Vc3 from High to Low.

  The logic circuit 25 includes an OR gate 26 and an AND gate 27, for example. The OR gate 26 receives the first control signal Vc1 and the second control signal Vc2. The output signal of the OR gate 26 and the third control signal Vc3 are input to the AND gate 27, and a switching signal Vsw corresponding to the logical product of these is output to the gate of the transistor Q.

  Here, at the normal time when the DC output voltage Vout is near the target voltage value V0, the second control signal Vc2 by the lower limit side feedforward control unit 14 is Low, and the third control by the upper limit side feedforward control unit 23 is performed. The signal Vc3 is High. At this time, since the voltage value of the DC output voltage Vout becomes a value within the range between the upper limit voltage value Vth2 and the lower limit voltage value Vth1, the OR gate 26 outputs a signal corresponding to the first control signal Vc1. At the same time, the AND gate 27 outputs a switching signal Vsw corresponding to the output signal of the OR gate 26 to the gate of the transistor Q. Thereby, the transistor Q is repeatedly turned on and off according to the PWM signal Vp whose duty ratio is feedback controlled.

  When the DC output voltage Vout is lower than the lower limit voltage value Vth1, the second control signal Vc2 by the lower limit side feedforward control unit 14 is switched to High. At this time, the OR gate 26 outputs a signal that becomes High corresponding to the second control signal Vc2, and the AND gate 27 outputs the switching signal Vsw corresponding to the output signal of the OR gate 26 to the gate of the transistor Q. Output to. Thereby, the transistor Q is fixed on.

  Further, when the DC output voltage Vout rises above the upper limit voltage value Vth2, the third control signal Vc3 by the upper limit side feedforward control unit 23 becomes Low. At this time, the OR gate 26 outputs a signal corresponding to the first control signal Vc1. On the other hand, since the third control signal Vc3 is Low, the AND gate 27 outputs the switching signal Vsw corresponding to the third control signal Vc3 to the gate of the transistor Q. Thereby, the transistor Q is fixed off.

  Thus, the second embodiment can provide the same effects as those of the first embodiment. Further, as shown in FIG. 5, when the load 3 fluctuates and the load current is greatly reduced in a short time (current difference −ΔI is generated), surplus charges are generated and the DC output voltage Vout is greatly increased. May occur. On the other hand, in the second embodiment, when the voltage value of the DC output voltage Vout is higher than the upper limit voltage value Vth2, the logic circuit 25 outputs the third control signal Vc3 to the transistor Q. The DC output voltage Vout can be quickly reduced by turning it off. For this reason, even when the load current rapidly decreases and the DC output voltage Vout changes, this change can be compensated quickly, and the responsiveness can be improved.

  Next, a third embodiment of the present invention is shown in FIG. The feature of the third embodiment is that it is applied to an isolated DC-DC converter. In the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  The DC-DC converter 31 includes a DC power supply 2, a capacitor Cin, a diode D1, a capacitor C, a resistor R, a transistor Q, a transformer 32, diodes D2 and D3, a choke coil L, a capacitor Cout, a control circuit 4, and the like.

  The DC power source 2, the capacitor Cin, the diode D 1, the capacitor C, the resistor R, and the transistor Q are connected to the primary side coil 32 A of the transformer 32. Here, the DC power source 2 has one end connected to one end of the primary coil 32A and the other end connected to the ground. The other end of the primary coil 32A is connected to the ground via a transistor Q. An input side capacitor Cin is connected to the DC power source 2 in parallel.

  Further, a reset circuit 33 is connected in parallel to the primary coil 32A. The reset circuit 33 releases the energy stored in the transformer 32 when the transistor Q is turned off. The reset circuit 33 is configured by connecting a diode D1 in series to a parallel connection circuit of a capacitor C and a resistor R. At this time, the anode of the diode D1 is connected to the connection point between the primary coil 32A and the transistor Q.

  One end of the secondary coil 32B of the transformer 32 is connected to the anode of the diode D2, and the cathode of the diode D2 is connected to the output terminal Po through the choke coil L. The connection point between the diode D2 and the choke coil L is connected to the cathode of the diode D3, and the anode of the diode D3 is connected to the ground.

  The output side of the transistor Q is indirectly connected to the load 3 via the transformer 32. At this time, the transistor Q is controlled to be turned on and off by the control circuit 4 as in the first embodiment. When the transistor Q is turned on, an electromotive force is generated in the primary side coil 32A and the secondary side coil 32B of the transformer 32, and a current flows toward the load 3 through the diode D2. On the other hand, when the transistor Q is turned off, an electromotive force is generated in the choke coil L, the stored energy is released, and a current flows toward the load 3 through the commutation diode D3.

  Thus, the third embodiment can provide the same operational effects as those of the first embodiment.

  The third embodiment has been described by taking the case where it is applied to the first embodiment as an example, but may be applied to the second embodiment. In the third embodiment, the case where the present invention is applied to an isolated forward converter has been described as an example. However, for example, the present invention may be applied to a flyback converter or the like, and may be applied to various types of isolated DC-DC converters. be able to.

  In each of the above embodiments, the case where an n-type MOSFET is used as the switching element has been described as an example. However, a p-type MOSFET or a bipolar transistor may be used, and various elements that perform switching can be used.

1,21,31 DC-DC converter 2 DC power supply 3 Load 4,22 Control circuit 5 Feedback control unit 14 Lower limit side feed forward control unit 15 Lower limit voltage detector 16, 25 Logic circuit 17, 26 OR gate 23 Upper limit side feed forward Control unit 24 Upper limit voltage detector 27 AND gate 32 Transformer 32A Primary side coil 32B Secondary side coil Q Transistor (switching element)
D, D1 ~ D3 Diode L Choke coil

Claims (4)

A DC-DC converter comprising a switching element that switches a DC input voltage and a control circuit that controls the switching element, and that supplies a DC output voltage to a load in accordance with a duty ratio of ON and OFF of the switching element. ,
The control circuit outputs a first control signal for adjusting a duty ratio of the switching element according to an integral value obtained by integrating a difference between a voltage value of the DC output voltage and a target voltage value; and
A lower limit side feedforward control unit that outputs a second control signal that turns on the switching element when the voltage value of the DC output voltage is lower than a predetermined lower limit voltage value;
The first control signal is output to the switching element when the voltage value of the DC output voltage is higher than the lower limit voltage value, and the switching is performed when the voltage value of the DC output voltage is lower than the lower limit voltage value. A DC-DC converter comprising a logic circuit that outputs the second control signal to an element. The control circuit further includes an upper limit side feedforward control unit that outputs a third control signal for turning off the switching element when the voltage value of the DC output voltage rises above a predetermined upper limit voltage value. Prepared,
The logic circuit outputs the first control signal to the switching element when a voltage value of the DC output voltage falls within a range between the upper limit voltage value and the lower limit voltage value, and the DC output voltage The second control signal is output to the switching element when the voltage value of the DC output voltage is lower than the lower limit voltage value, and the second control signal is output to the switching element when the voltage value of the DC output voltage is higher than the upper limit voltage value. The DC-DC converter according to claim 1, wherein the DC-DC converter is configured to output three control signals.   The DC-DC converter according to claim 1 or 2, wherein an output side of the switching element is directly connected to the load.   The DC-DC converter according to claim 1 or 2, wherein an output side of the switching element is indirectly connected to the load via a transformer.

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