JP2014107377A - Manufacturing method of reverse conducting igbt - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that, in a reverse conducting IGBT, namely, in an IGBT with an incorporated flyback diode, a number of dot-like diode cathode regions are formed in a distributed manner on a rear side of a device chip, the diode cathode regions are introduced by forming a pattern of a resist film on a rear side of a wafer by normal lithography and using the pattern as a mask of ion implantation but such introduction of lithography into a rear-side process is complicated in a process manner in a system for forming a ring-like thick portion in a peripheral part of the wafer, namely, in a peripheral thick ring thin film wafer processing system and may increase process costs.SOLUTION: In a method of manufacturing a reverse conducting IGBT in accordance with a peripheral thick ring thin film wafer processing system, an impurity is selectively introduced to a rear side of a wafer by ion implantation using an external mask.

Description

  The present application relates to a method of manufacturing a semiconductor integrated circuit device (or a semiconductor device), and can be applied to a manufacturing process of a power semiconductor device such as a reverse conducting IGBT (Insulated Gate Bipolar Transistor). is there.

  Japanese Unexamined Patent Publication No. 2004-103765 (Patent Document 1) relates to an IGBT using a single crystal silicon wafer by FZ (Floating Zone) method. There is disclosed a technique for eliminating the warpage of a wafer by holding a thin film wafer having a polyimide film or the like formed on the surface under high humidity conditions.

  Japanese Unexamined Patent Publication No. 2007-335659 (Patent Document 2) discloses a semiconductor wafer having a rim (thick part) in the peripheral part on the back surface of the wafer by etching.

  Japanese Unexamined Patent Publication No. 2011-155092 (Patent Document 3) relates to a reverse conducting IGBT. There is a reverse conducting IGBT having a built-in FWD (Fly Wheel Diode) by forming a plurality of dot-like N-type impurity regions in the P-type collector region on the back surface of the device by a combination of photolithography and ion implantation. It is disclosed.

JP 2004-103765 A JP 2007-335659 A JP 2011-155092 A

  In a reverse conducting IGBT, that is, a flyback diode built-in IGBT, a large number of dot-shaped diode cathode regions are dispersedly formed on the back surface of the device chip. The introduction of the diode cathode region is usually performed by forming a resist film pattern on the back surface of the wafer by ordinary lithography and using it as a mask for ion implantation. However, the introduction of lithography into such a backside process is a process in which a ring-shaped thick part is formed in the peripheral part of the wafer (hereinafter referred to as “peripheral thick ring thin film wafer processing method”). However, there is a problem that the process cost increases.

  Means for solving such problems will be described below, but other problems and novel features will become apparent from the description of the present specification and the accompanying drawings.

  An outline of representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, an outline of an embodiment of the present application is that, in a manufacturing method using a reverse conducting IGBT peripheral peripheral ring thin film wafer processing method, selective impurity introduction into the back surface of the wafer is performed by ion implantation using an external mask. Is to be executed.

  The effects obtained by the representative ones of the embodiments disclosed in the present application will be briefly described as follows.

  That is, according to one embodiment of the present application, the back surface process in the peripheral thick ring thin film wafer processing method can be simplified.

It is a principal part circuit diagram which shows an example of a circuit when reverse conduction type IGBT which is the object device of one embodiment of this invention is applied to a motor drive circuit. It is a schematic circuit diagram for demonstrating the basic structure of reverse conduction type IGBT which is the object device of the said one Embodiment of this invention. It is a chip | tip top view of reverse conduction type IGBT which is the object device of the said one Embodiment of this invention. FIG. 4 is an enlarged plan view of a cell region internal wide area cutout portion R1 of FIG. 3. FIG. 5 is a device cross-sectional view of the cell region internal unit periodic cutout part R <b> 2 of FIG. 4. FIG. 5 is a device cross-sectional process flow diagram (at the time of completion of a surface side process) corresponding to the cell region internal unit periodic cutout part R2 of FIG. 4; FIG. 5 is a device cross-sectional process flow diagram (BG tape pasting) corresponding to the cell region internal unit periodic cutout part R2 of FIG. 4; FIG. 5 is a device cross-sectional process flow diagram (back grinding) corresponding to the cell region internal unit periodic cutout part R2 of FIG. 4; FIG. 6 is a device cross-sectional process flow diagram (formation of a P + collector region and an N-type field stop region) corresponding to the cell region internal unit periodic cutout part R2 of FIG. 4; FIG. 5 is a device cross-sectional process flow diagram (ion implantation into a diode cathode region) corresponding to the cell region internal unit periodic cutout part R2 of FIG. 4; FIG. 5 is a device cross-sectional process flow diagram (anneal after ion implantation) corresponding to the cell region internal unit periodic cutout part R2 of FIG. FIG. 5 is a device cross-sectional process flow diagram (collector metal electrode formation) corresponding to the cell region internal unit periodic cutout part R2 of FIG. 4; FIG. 6 is a device cross-sectional process flow diagram (dicing tape pasting) corresponding to the cell region internal unit periodic cutout part R2 of FIG. 4; FIG. 5 is a device cross-sectional process flow diagram (dicing) corresponding to the cell region internal unit periodic cutout part R2 of FIG. 4; It is a back surface whole view for demonstrating the detail of the back grinding process of the said one Embodiment of this application. FIG. 16 is an overall cross-sectional view of the wafer corresponding to the B-B ′ cross section of FIG. 15. It is the whole surface view of the external mask for demonstrating the detail of the external mask used for the said one Embodiment of this application. FIG. 18 is an overall cross-sectional view of the external mask corresponding to the B-B ′ cross section of FIG. 17. FIG. 19 is an overall cross-sectional view of a wafer and an external mask (corresponding to FIG. 18) showing a mutual relationship between the wafer and the external mask in the ion implantation of FIG. FIG. 20 is an overall cross-sectional view of a wafer and an external mask showing the mutual relationship between the wafer and the external mask at the time of 10 ion implantation corresponding to FIG. 19 for explaining a modification of the external mask used in the embodiment of the present application is there. FIG. 5 is a device cross-sectional view corresponding to the cell region internal unit periodic cutout part R2 of FIG. 4 for explaining the principle of the target device of the present invention. It is a back surface diode cathode distribution map (basic layout: orthogonal lattice whole surface spread system) of reverse conduction type IGBT which is an object device of one embodiment of the invention in this application. It is a characteristic view which shows the device characteristic of reverse conduction type IGBT which is the object device of one embodiment of this invention. FIG. 23 is a plan view of a wide area corresponding to FIG. 22 (basic layout: orthogonal lattice entire surface spread method). FIG. 23 is a plan view of a wide area corresponding to FIG. 22 (basic layout: micro holes & spreading method). FIG. 23 is a plan view of a wide area corresponding to FIG. 22 (basic layout: inclined grid entire surface spread method). It is the whole wafer upper surface for demonstrating the outline of the manufacturing method of the reverse conduction type IGBT of the said one Embodiment of this application, and the whole wafer and external mask sectional drawing which shows the mode of the C-C 'cross section.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method for manufacturing a reverse conducting IGBT including the following steps:
(A) preparing a semiconductor wafer having a first main surface and a second main surface, wherein a plurality of unit chip regions are formed in a matrix on the first main surface;
(B) a step of thinning the inner region of the second main surface of the semiconductor wafer by grinding to leave a ring-shaped thick region around the semiconductor wafer;
(C) After the step (b), ion implantation is performed from the second main surface side of the semiconductor wafer with an external mask attached to the second main surface of the semiconductor wafer. The step of selectively introducing impurity ions into the second main surface of the semiconductor wafer.

2. The method for manufacturing a reverse conducting IGBT according to Item 1 further includes the following steps:
(D) removing the external mask from the semiconductor wafer;
(E) A step of performing laser annealing for activating the impurity ions after the step (d).

3. The manufacturing method of the reverse conducting IGBT according to Item 2 further includes the following steps:
(F) A step of forming a metal back electrode on the second main surface of the semiconductor wafer after the step (e).

4). The method for manufacturing a reverse conducting IGBT according to Item 3 further includes the following steps:
(G) A step of irradiating the semiconductor wafer with an electron beam after the step (f).

5. The method for manufacturing a reverse conducting IGBT according to Item 4 further includes the following steps:
(H) After the step (g), removing the ring-shaped thick region;
(I) A step of dividing the semiconductor wafer into individual unit chip regions after the step (h).

  6). In the method for manufacturing a reverse conducting IGBT according to any one of Items 1 to 5, the impurity ions are introduced into a portion to be a cathode region of the reverse conducting diode on the second main surface of the semiconductor wafer.

  7). In the method of manufacturing a reverse conducting IGBT according to any one of Items 1 to 6, the external mask is fitted into a circular recess inside the ring-shaped thick region during ion implantation.

  8). In the method for manufacturing a reverse conducting IGBT according to any one of Items 1 to 7, the ion implantation mask region of the external mask is formed of a polyimide film.

  9. In the manufacturing method of the reverse conducting IGBT according to Item 8, the periphery of the ion implantation mask region of the external mask is held by a ring-shaped frame body of the external mask.

  10. In the method of manufacturing a reverse conducting IGBT according to Item 9, the ring-shaped thick region of the semiconductor wafer and the ring-shaped frame body of the external mask are fixed to each other with an adhesive tape at the time of ion implantation. Has been.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Further, in the present application, the term “semiconductor device” mainly refers to various transistors (active elements) alone, or a device in which resistors, capacitors, etc. are integrated on a semiconductor chip or the like (for example, a single crystal silicon substrate). Say. Here, as a representative of various transistors, a MISFET (Metal Insulator Semiconductor Effect Transistor) typified by a MOSFET (Metal Oxide Field Effect Transistor) can be exemplified. At this time, typical examples of various single transistors include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors). These are categorized into power semiconductor devices, and include power MOSFETs, IGBTs, bipolar power transistors, thyristors, power diodes, and the like.

  A typical form of the power MOSFET is a double diffused vertical power MOSFET having a source electrode on the front surface and a drain electrode on the back surface. This double diffusion type vertical power MOSFET can be mainly classified into two types, the first is a planar gate type described mainly in the embodiment, and the second is a trench (such as a U-MOSFET) ( (Trench Gate) gate type.

  Other power MOSFETs include LD-MOSFETs (Lateral-Diffused MOSFETs).

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  Similarly, “silicon oxide film”, “silicon oxide insulating film” and the like are not only relatively pure undoped silicon oxide but also other silicon oxide as main components. Including membrane. For example, a silicon oxide insulating film doped with impurities such as TEOS-based silicon oxide (TEOS-based silicon oxide), PSG (phosphorus silicon glass), BPSG (borophosphosilicate glass) is also a silicon oxide film. In addition to a thermal oxide film and a CVD oxide film, a coating system film such as SOG (Spin On Glass) or nano-clustering silica (NSC) is also a silicon oxide film or a silicon oxide insulating film. In addition, a low-k insulating film such as FSG (Fluorosilicate Glass), SiOC (Silicon Oxide silicide), carbon-doped silicon oxide (OSD), or OSG (Organosilicate Glass) is similarly used. It is a membrane. Further, a silica-based Low-k insulating film (porous insulating film, including “porous” or “porous”) including a hole in a member similar to these is also a silicon oxide film or silicon oxide. It is a system insulating film.

  In addition to silicon oxide insulating films, silicon nitride insulating films that are commonly used in the semiconductor field include silicon nitride insulating films. Materials belonging to this system include SiN, SiCN, SiNH, SiCNH, and the like. Here, “silicon nitride” includes both SiN and SiNH unless otherwise specified. Similarly, “SiCN” includes both SiCN and SiCNH, unless otherwise specified.

  3. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor integrated circuit device (same as a semiconductor device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  4). The figure, position, attribute, and the like are preferably illustrated, but it is needless to say that the present invention is not strictly limited to this unless it is clearly indicated otherwise and the context clearly does not. Therefore, for example, “square” includes a substantially square, “orthogonal” includes a case where the two are substantially orthogonal, and “match” includes a case where the two substantially match. The same applies to “parallel” and “right angle”. Therefore, for example, a deviation of about 10 degrees from perfect parallel belongs to parallel.

  In addition, for a certain region, “whole”, “whole”, “whole area” and the like include cases of “substantially whole”, “substantially general”, “substantially whole area” and the like. Therefore, for example, 80% or more of a certain area can be referred to as “whole”, “whole”, and “whole area”. The same applies to “all circumferences”, “full lengths”, and the like.

  Further, regarding the shape of a certain object, “rectangular” includes “substantially rectangular”. Therefore, for example, if the area of the portion different from the rectangle is less than about 20% of the whole, it can be said to be a rectangle. In this case, the same applies to “annular” and the like. In this case, when the annular body is divided, a portion obtained by interpolating or extrapolating the divided element portion is a part of the annular body. In the present application, the term “annular” or “ring-shaped” for the frame of the external mask, the peripheral thick portion of the wafer, etc. basically means a closed ring.

  Also, with regard to periodicity, “periodic” includes almost periodic, and for each element, for example, if the deviation of the period is less than about 20%, each element can be said to be “periodic”. . Furthermore, if what is out of this range is, for example, less than about 20% of all the elements to be periodic, it can be said to be “periodic” as a whole.

  Note that the definitions in this section are general, and when there are different definitions in the following individual descriptions, priority is given to the individual descriptions for this part. However, the definition, provisions, etc. of this section are still valid for parts that are not stipulated in the individual description part, unless explicitly denied.

  5. In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  6). In the present application, an “external mask” refers to an ion implantation mask in which a pattern is formed in advance for use on a wafer, which can be attached and detached and used multiple times. On the other hand, a normal mask, that is, an “internal mask” is a mask that subsequently forms a pattern on a film applied or adhered to a wafer. The external mask is a concept different from an aperture that is installed outside the wafer and partially blocks the ion path.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

  In addition, regarding the designation in the case of the alternative, when one is referred to as “first” or the like and the other is referred to as “second” or the like, it is exemplified in association with the representative embodiment. Of course, for example, “first” is not limited to the illustrated option.

1. Description of application circuit and the like of flyback diode built-in IGBT which is a reverse conducting IGBT (semiconductor device) which is a target device according to an embodiment of the present application (mainly FIG. 1 and FIG. 2)
The application example shown below is merely an example, and it goes without saying that it can also be applied to a device intended for other applications.

  FIG. 1 is a principal circuit diagram showing an example of a circuit when a reverse conducting IGBT, which is a target device according to an embodiment of the present invention, is applied to a motor drive circuit. FIG. 2 is a schematic circuit diagram for explaining the basic structure of a reverse conducting IGBT which is a target device according to an embodiment of the present invention. Based on these, an application example of a flyback diode built-in IGBT which is a reverse conducting IGBT (semiconductor device) which is a target device according to an embodiment of the present application will be described.

  FIG. 1 shows an example of a specific application circuit (three-phase motor driving circuit) of the IGBTs 3a, 3b, 3c, 3d, 3e, and 3f with built-in flyback diodes. As shown in FIG. 1, this three-phase motor drive circuit uses a IGBT 3a, 3b, 3c, 3d, 3e, 3f with built-in flyback diodes to switch the output from the DC power supply 6 at a high speed, thereby making the three-phase motor 7 is driven. Each of the IGBTs 3a, 3b, 3c, 3d, 3e, and 3f incorporated in the flyback diode is a combination of the IGBT element parts 4a, 4b, 4c, 4d, 4e, and 4f and the flyback diode parts 5a, 5b, 5c, 5d, 5e, and 5f. It consists of

  Here, as shown in FIG. 2, each flyback diode built-in IGBT element 3 (reverse conducting IGBT) is composed of an IGBT element part 4 and a flyback diode part 5. Each terminal of the reverse conducting IGBT element 3 is referred to as an emitter terminal E, a collector terminal C, a gate terminal G, or the like for convenience, corresponding to the terminal of a conventional bipolar transistor (or power MOSFET). It does not correspond to the operation of the internal transistor.

2. Description of the device structure of a reverse conducting IGBT (semiconductor device) which is the target device of the one embodiment of the present application (mainly FIGS. 3 to 5)
In this section, an example of the chip of the reverse conducting IGBT element 3 shown in FIG. 2 will be described. Normally, taking the reverse conducting IGBT element 3 having a withstand voltage of 600 volts as an example, the average chip size is 3 to 6 mm square. Here, for convenience of explanation, a chip having a length of 4 millimeters (Y direction in FIG. 3) and a width of 5.2 millimeters (X direction in FIG. 3) will be described as an example. Here, description will be made assuming that the breakdown voltage of the device is about 600 volts, for example.

  FIG. 3 is a top view of a chip of a reverse conducting IGBT which is a target device according to an embodiment of the present invention. FIG. 4 is an enlarged plan view of the internal wide area cutout portion R1 of the cell region 8 of FIG. FIG. 5 is a device sectional view of the internal unit periodic cutout portion R2 of the cell region 8 of FIG. Based on these, the device structure of a reverse conducting IGBT (semiconductor device), which is a target device according to an embodiment of the present application, will be described. The size of the IGBT cell region 8 is, for example, about 3 mm in length and 4 mm in width for a chip having a length of 4 mm and a width of 5.2 mm.

  First, an outline of the structure of the upper surface 1a (device surface or first main surface) of the chip will be described with reference to FIG. As shown in FIG. 3, an annular guard ring 9 is provided in the peripheral region of the chip 2 of the reverse conducting IGBT, and a gate pad G and an emitter pad E are provided therein. Here, as an example, the length is about 4 millimeters and the width is about 5.2 millimeters.

  Next, FIG. 4 shows an enlarged plan view of the cell region internal wide area cutout portion R1 of FIG. As shown in FIG. 4, the cell region 8 (IGBT cell region) has a continuous translation property (that is, a linear gate structure) in the X direction, and a period T (cell region repeating structure) in the Y direction. (Unit period) periodic structure. In other words, linear gate electrodes 11 (for example, polysilicon trench gate electrodes) having the same width are arranged at regular intervals in the Y direction, and N + emitter regions 12 are arranged along the trench gate electrodes 11. Is provided. Further, a P + body contact region 14 is provided so as to straddle a pair of adjacent N + emitter regions 12.

  Next, FIG. 5 shows a cross-sectional structure of the cell region internal unit periodic cutout portion R2 of FIG. As shown in FIG. 5, for example, an aluminum-based emitter metal electrode 10 is formed on the device surface 1 a of the N− type single crystal silicon substrate 1, for example. The surface region of the device surface 1 a of the silicon substrate 1 is surrounded by an N + emitter region 12, a P-type body region 13, a P + body contact region 14, and an insulating film such as a silicon oxide film (a side portion is a gate insulating film 15). A trench gate electrode 11 is formed surrounded by. On the other hand, a collector metal electrode 18 is formed on the back surface 1b of the silicon substrate 1, and a P + collector region 17 (second conductivity type collector region) is formed on almost the entire surface region on the back surface 1b side of the silicon substrate 1. Is formed. The region that occupies the main portion of the silicon substrate 1 between the P-type body region 13 and the P + collector region 17 is an N− type drift region 16 (first conductivity type drift region). An N-type field stop region 21 having a concentration higher than that of the N− type drift region 16 is provided on almost the entire surface of the end portion on the P + collector region 17 side. Further, a collector region through N + region 19 (diode cathode region) is provided so as to penetrate the P + collector region 17 and connect to the N-type field stop region 21. The IGBT element portion 4 and the flyback diode portion 5 are enclosed by a one-dot broken line in the figure. In addition, the area | region enclosed here is simplified for description and does not include all the area | regions which perform such an effect | action.

Here, an example of the dimensions and impurity concentration of each part is as follows. That is, the trench width is about 0.35 to 0.5 micrometers, the gate electrode pitch is about 2 to 3 micrometers, the trench depth is about 1.5 micrometers, and the depth of the p body region 13 is about 1 micrometer (impurity concentration). : Boron 2 × 10 ¹⁷ / cm ³ or so). Furthermore, depth about 0.25 micrometers of the emitter region 12 (impurity concentration: arsenic 2x10 ²⁰ / cm ³ order), P + depth of about 1.3 micrometers of the body region 14 (impurity concentration: boron 2x10 ²⁰ / cm ³ ), the collector region 17 has a thickness of about 0.6 micrometers, and the N-type field stop region 21 has a thickness of about 0.9 micrometers.

3. Description of the main part of the manufacturing process of the reverse conducting IGBT (semiconductor device) of the one embodiment of the present application (mainly FIGS. 6 to 14)
Here, the wafer process will be described. Here, a description will be given mainly using a 200φ wafer of an N-type silicon single crystal (for example, a phosphorus concentration of about 2 × 10 ¹⁴ / cm ³ ) as an example. However, what is described here also applies almost directly to wafers of various diameters such as 150φ, 100φ, 300φ, and 450φ. In addition, although the example which uses the notch 20 (FIG. 15) as a crystal orientation display part which shows a crystal orientation was shown, you may use an orientation flat instead of the notch 20. FIG.

  FIG. 6 is a device cross-sectional process flow diagram (at the time of completion of the surface side process) corresponding to the cell region internal unit periodic cutout part R2 of FIG. FIG. 7 is a device cross-sectional process flow diagram (BG tape pasting) corresponding to the cell region internal unit periodic cutout portion R2 of FIG. FIG. 8 is a device cross-sectional process flow diagram (back grinding) corresponding to the cell region internal unit periodic cutout part R2 of FIG. FIG. 9 is a device cross-sectional process flow diagram (formation of P + collector region and N-type field stop region) corresponding to the cell region internal unit periodic cutout portion R2 of FIG. FIG. 10 is a device cross-sectional process flow diagram (ion implantation into the diode cathode region) corresponding to the cell region internal unit periodic cutout portion R2 of FIG. FIG. 11 is a device cross-sectional process flow diagram (annealing after ion implantation) corresponding to the cell region internal unit periodic cutout part R2 of FIG. FIG. 12 is a device cross-sectional process flow diagram (collector metal electrode formation) corresponding to the cell region internal unit periodic cutout portion R2 of FIG. FIG. 13 is a device cross-sectional process flow diagram (dicing tape attachment) corresponding to the cell region internal unit periodic cutout portion R2 of FIG. FIG. 14 is a device cross-sectional process flow diagram (dicing) corresponding to the cell region internal unit periodic cutout part R2 of FIG. Based on these, the main part of the manufacturing process of the reverse conducting IGBT (semiconductor device) according to the embodiment of the present application will be described.

  Here, in the wafer process, the final passivation formation and the necessary opening formation (gate opening, emitter opening) to the final passivation film shown in FIG. 6 and subsequent drawings will be described (the figure shows the opening of the final passivation film in the cell region). The final passivation film does not appear because it hits the part). As the uppermost member of the final passivation film, for example, a surface-protective organic open resin film such as a polyimide organic resin film is preferably used. This is because it is effective in protecting the surface side of the wafer from mechanical damage in the process after peeling of the BG tape or the like.

  When the necessary opening formation in the final passivation film is completed, a BG (Back Gringing) tape 31 (for example, a thickness of about several hundreds of micrometers) is attached to the surface 1a of the wafer 1 as shown in FIG.

  Next, as shown in FIG. 8, with the BG tape 31 side adsorbed to the adsorption stage of the back grinding apparatus, the rotating grinding wheel is pressed against the back surface 1b of the wafer 1 (ie, the N-type substrate portion 1s). Then, the backgrinding process is executed on the portion 22 to be removed by the backgrinding in FIG. 7 to remove the portion. At this time, the thickness of the original wafer 1 is, for example, about 725 micrometers, but after back grinding, it is about 50 to 150 micrometers. Thereafter, the BG tape 31 that has become unnecessary is peeled off. Next, if necessary, spin etching (for example, about 2 micrometers) is performed on the back surface 1b side of the wafer 1.

Next, as shown in FIG. 9, with the front surface 1a side of the wafer 1 being adsorbed to the wafer stage of the ion implantation apparatus, the collector region with respect to almost the entire back surface 1b (N− type substrate portion 1s) of the wafer 1. Boron ion implantation 52 (for example, boron, 40 KeV, about 5 × 10 ¹⁴ / cm ² ) to form 17 (FIG. 10) is performed. Further, phosphorus ion implantation 53 (for example, phosphorus, about 350 Kev, 4 × 10 ¹² / cm ² ) for forming the field stop region 21 (FIG. 10) and an annealing process for activation thereof, for example, laser annealing are performed. .

Next, as shown in FIG. 10, the front surface 1 a side of the wafer 1 with the external mask 23 for ion implantation into the collector region penetrating N + region (that is, the diode cathode region) attached to the back surface 1 b side of the wafer 1. Is adsorbed on the wafer stage of the ion implantation apparatus. Then, phosphorus ion implantation 54 (for example, about phosphorus, 250 Kev, 5 × 10 ¹⁴ / cm ² and 125 KeV, 1 × 10 ¹⁵ / cm ² ) is performed through the collector region through N + region through the opening 23 p of the ion implantation mask region 23 b of the external mask 23. To do. As a result, impurity ions are introduced into a region to be the cathode region of the reverse conducting diode. Thereafter, the external mask 23 that is no longer needed is removed. In this manner, selective ion implantation can be performed relatively easily on the back surface of the wafer.

  Next, as shown in FIG. 11, the diode cathode region 19 is formed by activating the impurities introduced by ion implantation, for example, by laser annealing (activation annealing) or the like. Thus, since laser annealing is performed with the external mask 23 removed, deterioration of the external mask and contamination of the wafer can be prevented.

  Next, if necessary, surface treatment such as spin etching treatment is performed on the back surface 1b side of the wafer 1 using a hydrofluoric acid etching solution or the like, and then, for example, as shown in FIG. The collector metal electrode 18 is formed by sputtering film formation or the like in a state where the surface 1a side is placed on the wafer stage of the sputtering apparatus. The configuration of the collector metal electrode 18 can be exemplified as a suitable example of a nickel film, a titanium film, a nickel film, a gold film, etc. from the side close to the wafer. Thereafter, if necessary, electron beam irradiation for annealing of minority carriers and annealing treatment thereof are performed. In this way, processes involving heating such as laser annealing, metal back electrode formation, and electron beam irradiation can be performed on the upper body with the external mask removed, so that it is possible to avoid deterioration of the external mask and contamination of the wafer. Have

  Next, as shown in FIG. 13, a dicing tape 33 is attached to the back surface 1b of the wafer 1, and the wafer 1 is fixed to the dicing frame through the dicing tape 33. In this state, first, the ring-shaped thick region 42 is cut and removed by, for example, a dicing blade.

  Next, in the state shown in FIG. 14, the wafer 1 is divided into individual chips 2 by performing dancing. As a result, a chip as shown in FIG. 3 is obtained.

4). Details of the main process of the one embodiment of the present application and description of modifications of the external mask (mainly FIGS. 15 to 20)
In this section, the details of the external mask used in the back grinding process (FIG. 8) described in section 3, the diode cathode introduction process, and modifications of the external mask will be described.

  FIG. 15 is an overall view of the back surface of the wafer for explaining the details of the back grinding process according to the embodiment of the present application. FIG. 16 is an overall cross-sectional view of the wafer corresponding to the B-B ′ cross section of FIG. 15. FIG. 17 is a general view of the surface of the external mask for explaining details of the external mask used in the embodiment of the present application. FIG. 18 is an overall cross-sectional view of the external mask corresponding to the B-B ′ cross section of FIG. 17. FIG. 19 is an overall cross-sectional view of the wafer and the external mask (corresponding to FIG. 18) showing the mutual relationship between the wafer and the external mask at the time of ion implantation in FIG. FIG. 20 shows the mutual relationship between the wafer and the external mask in the ion implantation of FIG. 10 corresponding to FIG. 19 for explaining a modification of the external mask used in the one embodiment of the present application. It is whole sectional drawing. Based on these, the details of the main process of the one embodiment of the present application and a modified example of the external mask will be described.

(1) Detailed description of the back grinding process of the one embodiment of the present application (mainly FIGS. 15 and 16):
As shown in FIGS. 15 and 16, in the back grinding process, for example, the grinding wheel 51 (rotary wheel) is placed inside the back surface 1b of the wafer 1 with the BG tape 31 attached to the front surface 1a of the wafer. Only the region 30 is ground to form the circular recess 41 and the ring-shaped thick region 42 in the peripheral portion. Note that “only the inner region 30” does not exclude performing back-grinding on the entire back surface 1b of the wafer 1 in advance in order to thin the entire wafer 1 in advance. Further, the notch 20 for displaying the crystal orientation is provided around the wafer 1, but the crystal orientation display is not limited to the notch and may be an orientation flat.

  Here, in order to make the example shown here more concrete, an example of the dimension of each part is shown below. That is, the initial thickness of the wafer 1 is, for example, about 725 micrometers (the range is, for example, about 400 to 1000 micrometers), and the thickness of the circular recess 41 is, for example, about 75 micrometers (for the range). For example, depending on the withstand voltage, it is about 30 to 150 micrometers). In this example, the thickness of the ring-shaped thick region 42 is substantially the same as the initial thickness of the wafer 1, but needless to say, it may be different. The width of the ring-shaped thick region 42 is, for example, about 2 millimeters (the range is, for example, about 1.5 to 2.5 millimeters).

(2) Detailed description of the external mask (basic form) of the one embodiment of the present application (mainly FIGS. 17 to 19):
The detailed structure of the external mask 23 (basic form) of FIG. 10 is shown in FIGS. As shown in FIGS. 17 and 18, the external mask 23 is configured by an ion implantation mask region 23 b that is a substantially circular thin film, a ring-shaped frame body 23 r (or a ring-shaped frame portion) that adheres and holds the mask, and the like. Yes. As described above, since the periphery of the ion implantation mask region 23b is held by the ring-shaped frame 23r, it is possible to effectively avoid mask displacement due to mechanical impact or the like. However, the ion implantation mask region 23b is flat except for the portion of the opening 23p. In addition, as a material of the ion implantation mask area | region 23b, heat resistant organic resin films, such as a polyimide-type resin film (thickness, for example, about 20 micrometers), can be illustrated as a suitable thing, for example. Moreover, as a material of the ring-shaped frame 23r, for example, a metal plate such as stainless steel (thickness, for example, about 1 mm, and the width of the ring portion is, for example, about 1.5 mm) is exemplified as a suitable material. be able to. Thus, since the ion implantation mask region 23b is composed of a heat-resistant organic resin film such as polyimide resin, it is possible to avoid deterioration of mask characteristics due to a temperature rise or the like during ion implantation.

  Next, the state of the wafer 1 and the external mask 23 in use is shown in FIG. As shown in FIG. 19, the external mask 23 is attached so that the back surface 23 f of the external mask 23 is in close contact with the circular recess 41 (internal region 30) of the back surface 1 b of the wafer 1. That is, the external mask 23 is fitted in the circular recess 41 inside the ring-shaped thick region 42 during ion implantation. As described above, the external mask 23 is inserted into the circular concave portion 41 in the ring-shaped thick region 42 at the time of ion implantation, so that mask displacement at the time of implantation and conveyance is minimized. In addition to being able to suppress, wearing is easy. The ring-shaped thick region 42 of the wafer 1 and the ring-shaped frame body 23r (or ring-shaped frame portion) of the external mask 23 are fixed to each other by a fixing adhesive tape 43. Here, as the adhesive tape 43 for fixing, for example, a heat-resistant organic resin adhesive tape such as a polyimide resin tape can be exemplified as a suitable one. That is, in this example, the ion implantation mask region 23b of the external mask 23 is constituted by a polyimide film. In addition, as a dimension of a polyimide resin tape, for example, the width is, for example, about 5 millimeters, the length is, for example, about 10 millimeters, and the thickness is, for example, about 50 micrometers. Can do.

  Such a mask structure has a merit that applicability such as automatic transfer is high because the overall thickness of the wafer and mask assembly at the time of attachment is relatively close to the thickness of the wafer.

  In the ion implantation of the diode cathode, for example, in the state of FIG. 19, the surface 1a side of the wafer 1 is held in a state of being attracted to the wafer stage of the ion implantation apparatus by the electrostatic chuck. Ion implantation is performed from the surface 23 d side of the external mask 23. In the case of a single wafer apparatus, for example, a beam is scanned in the X direction, and the wafer is scanned (translated) at a relatively low speed in the Y direction, whereby impurities are introduced into the entire wafer. On the other hand, in a batch apparatus, while a plurality of wafers set on the circumference rotate (revolve) at high speed, the center of the circle moves in parallel at a relatively low speed, and impurities are introduced into the entire wafer. Therefore, a single wafer apparatus is advantageous from the viewpoint of minimizing mask displacement, and a batch apparatus is advantageous from the viewpoint of processing capability.

  Needless to say, the use of an adhesive tape is not necessarily required if there is no problem in mechanical stability.

(3) Description of a modified example (L-shaped cross section) of the external mask according to the embodiment of the present application (mainly FIG. 20)
FIG. 20 shows a state of using a modified external mask (L-shaped cross-section type) external mask 23 with respect to the basic external mask 23 (FIGS. 17, 18 and 19). As shown in FIG. 20, the other forms and materials are the same except that the cross-section of the ring-shaped frame body 23r (or the ring-shaped frame portion) is L-shaped. As the material of the ring-shaped frame 23r, for example, stainless steel (thickness, for example, the thinner one is about 1 millimeter and thicker is, for example, about 2 millimeters, and the width of the ring portion is, for example, 1.5 millimeters for the inside. A metal plate having a thickness of about 3.5 mm, for example, can be exemplified as a suitable one.

  By adopting such a configuration, the wafer 1 and the external mask 23 are firmly fixed, and there is a merit that the possibility of mask displacement or the like during processing can be further reduced.

5. Description of principle of reverse conducting IGBT (semiconductor device), which is a target device of one embodiment of the present application, layout of basic diode cathode region, modification, etc. (mainly FIGS. 21 to 26)
In this section, the specific formation method, layout (basic and modified examples) of the collector region penetrating N + region 19 (diode cathode region) described in FIGS. 5, 10, and 11, the relationship between the device surface and the back surface, etc. explain.

  FIG. 21 is a device cross-sectional view corresponding to the cell region internal unit periodic cutout portion R2 of FIG. 4 for explaining the principle of the target device of the present invention. FIG. 22 is a back surface diode cathode distribution diagram (basic layout: orthogonal lattice whole surface spread method) of a reverse conducting IGBT which is a target device according to an embodiment of the present invention. FIG. 23 is a characteristic diagram showing device characteristics of a reverse conducting IGBT which is a target device according to an embodiment of the present invention. FIG. 24 is a plan view of a wide area corresponding to FIG. 22 (basic layout: orthogonal lattice entire surface spread method). FIG. 25 is a plan view of a wide area corresponding to FIG. 22 (basic layout: micro holes & spreading method). FIG. 26 is a plan view of a wide area corresponding to FIG. 22 (basic layout: inclined grid entire surface spread method). Based on these, the principle of a reverse conducting IGBT (semiconductor device), which is a target device according to an embodiment of the present application, a layout of a basic diode cathode region, a modification, and the like will be described.

  Next, a description will be given with reference to FIG. 21 (device sectional view of a unit period portion of the cell region 8 corresponding to FIG. 5) and FIG. As shown in FIG. 21, when the emitter reference gate potential Vge exceeds the threshold voltage of the internal MOSFET portion 24, electrons are injected from the emitter region 12 into the drift region 16, and these electrons cross the drift region 16 and cross. Then, it flows into the diode cathode region 19 along the N-type field stop region 21 and finally reaches the collector electrode 18. However, if the density of the diode cathode region 19 is too high, the resistance component 25 in the N-type field stop region is small, so that when the emitter reference collector potential Vce increases with a positive value, the collector of the internal PNP transistor Since the potential difference at the terminal-side PN junction 26 does not rise sufficiently, the terminal-side PN junction 26 does not turn on smoothly, and so-called snap back occurs. On the other hand, if the density of the diode cathode region 19 is too low, the forward voltage drop of the diode 5 (FIG. 5) increases. In order to eliminate this trade-off, in this example, as shown in FIG. 22, the pitch XP in the X-axis direction (extension direction of the linear gate electrode) of the diode cathode region 19 and the Y-axis direction (repetition of the gate electrode). By making the pitch YP different in the direction), it is possible to achieve both an increase in the potential difference of the collector terminal side PN junction 26 of the internal PNP transistor and a suppression of the forward voltage drop of the diode. That is, the pitch XP in the X direction is set to a sufficiently high density so that the forward voltage drop characteristic of the diode is sufficiently low, and the pitch YP in the Y direction is set to a sufficiently low density so that the internal PNP transistor is turned on smoothly. Set.

  Thus, when the density of the diode cathode region 19 in each direction of XY is optimally set in each direction, as shown in FIG. 23, the IGBT element portion 4 is turned on (the emitter reference gate potential Vge is a positive value). Good characteristics can be obtained both in Vge (+), the emitter reference collector potential Vce is also a positive value Vce (+)), and in the state where the reverse diode 5 is on.

  Next, the macro features of the two-dimensional layout (basic layout) of the diode cathode region 19 shown in FIG. 22 will be described. As shown in FIG. 24, the dot-shaped diode cathode regions 19 (in FIGS. 24 to 26, for convenience of illustration, the number of dot-shaped diode cathode regions in the X-axis direction is approximately ¼ and displayed. Are arranged on the entire back surface 1b of the wafer 1 so as to form orthogonal two-dimensional lattices having lattice constants XP in the X direction and YP in the Y direction. By doing so, even when the chip position (relative position between the optical mask and the wafer) in the backside exposure is different as in the chip 2a and the chip 2b, the diode cathode region 19 included in the unit chip region 2 Variation in the total number can be kept low.

  In particular, the length of the side of the chip 2 in the X-axis direction is approximately an integral multiple of the pitch XP in the X direction, and the length of the side of the chip 2 in the Y-axis direction is approximately an integral multiple of the pitch YP in the Y direction. As a result, the variation in the total number of diode cathode regions 19 included in the single chip region 2 can be further reduced. Of course, this is not essential.

  In this example, since the pitch XP in the X direction is much shorter than the pitch YP in the Y direction, the total number of diode cathode regions 19 included in the single chip region 2 is less than the deviation of the chip 2 in the X direction. Not sensitive. Accordingly, by making only the length of the side of the chip 2 in the Y-axis direction substantially an integral multiple of the pitch YP in the Y direction, the variation in the total number of diode cathode regions 19 included in the single chip region 2 can be sufficiently increased. It can be kept down considerably. Of course, this is not essential.

  The two-dimensional layout of the diode cathode region 19 is not limited to a spread lattice (FIG. 24), that is, a region that occupies almost all lattice points, and is relatively free. Then, when considering circles S1 and S2 whose diameter is about half of the short side of the chip region (provided that all the circles are in the chip region), etc., these circles (referred to as “macro reference circles”) It is effective from the viewpoint of controlling variation in element characteristics to lay out the diode cathode region 19 so that the total number of diode cathode regions 19 included in the circle does not vary greatly. Of course, this point is not essential, but it is distributed macroscopically relatively uniformly (that is, an XY two-dimensional lattice with a diode cathode region is formed almost in front of the second main surface of the chip). In addition to being easy to design, there are advantages that alignment between the front and back surfaces is not necessary. That is, the main axis direction of the chip 2 can be made to coincide with the lattice direction of the lattice formed by the diode cathode region 19 only by aligning the orientation of the wafer 1.

  Therefore, as shown in FIG. 25 (micro sampling type), the density can be adjusted by extracting some of the lattice points. That is, the two-dimensional layout of the diode cathode region 19 can be configured by arbitrarily combining the filled row 29p and the unfilled row 29u. Also in this case, the macro reference circle lays out so that the total number of the diode cathode regions 19 included in the circle does not vary greatly regardless of the position in the chip region, thereby controlling the variation in the characteristics of the elements. It is effective from the viewpoint. The example of FIG. 25 is a modification of the example of FIG. 24 (orthogonal spread type), and the portions not described here are the same as the description of FIG. As described above, since the microscopic sampling is performed in units of lattice points, the area is equivalent to the chip, and therefore, the area becomes relatively uniform. Therefore, the diode cathode region 19 does not exist over one to several macro portions for each chip. Compared with making the portion, the variation in the forward characteristics of the reverse diode can be reduced. This merit is common to the examples of FIGS. That is, since the density of the diode cathode region 19 is adjusted in unit cell units (in a micro region), regardless of the relative positional relationship between the many chip regions 2 on the wafer 1 and the mask 72 (FIG. 19), Since the total number of diode cathode regions 19 per unit chip is substantially constant, the IGBT characteristics can be optimized without worrying about variations in the forward characteristics of the reverse diode.

  Furthermore, as a modified example of the layout of FIG. 24 (orthogonal spread type), an inclined spread type layout can be illustrated in FIG. In this example, each row 29 of the diode cathode region 19 is composed of only the filling rows 29, but the XY lattice is an inclined lattice. Considering the ease of layout, the inclination angle is preferably 5 degrees or more and less than 30 degrees. Note that an inclination angle of less than 5 degrees is substantially included in the orthogonal lattice. Also in this case, the macro reference circle lays out so that the total number of the diode cathode regions 19 included in the circle does not vary greatly regardless of the position in the chip region, thereby controlling the variation in the characteristics of the elements. It is effective from the viewpoint. Further, by combining this with the example of FIG. 25, an inclined sampling layout can be obtained.

That is, the setting of the diode cathode region density in the XY direction at the unit cell level as shown in FIGS. 24 to 26 (the Y-direction density is made lower than the X-direction density, or the Y-direction pitch is set lower than the X-direction pitch). By making it longer, the smooth operation of the internal bipolar transistor can be ensured while maintaining macro uniformity. As a design procedure, the following methods can be exemplified.
(1) First, an appropriate XY two-dimensional lattice structure is selected according to the description with reference to FIGS.
(2) The pitch in the Y direction is determined so as to ensure smooth operation of the internal bipolar transistor. In this example, it is about 400 micrometers, for example. An example of a suitable range under normal conditions is about 300 to 500 micrometers.
(3) Next, the X direction pitch is determined so as to ensure the forward characteristics of the reverse diode. In this example, it is about 80 micrometers, for example. An example of a suitable range under normal conditions is about 50 to 200 micrometers.
(4) The planar shape and area of each diode cathode region 19 are determined in consideration of the pitch in the X direction. In this example, for example, it is a circle having a diameter of about 45 micrometers. An example of a suitable range under normal conditions is about 10 to 100 micrometers.
(5) If necessary, the relationship between the length of each side of the chip and the Y-direction pitch or the X-direction pitch is adjusted in order to further suggest variations in the forward characteristics of the reverse diode in (2).

6). Supplementary explanation about the above-described embodiment (including modifications) and general consideration (mainly FIG. 27)
FIG. 27 is an overall cross-sectional view of the wafer and an external mask showing the overall top surface of the wafer and the CC ′ cross-section for explaining the outline of the manufacturing method of the reverse conducting IGBT of the one embodiment of the present application. is there. Based on this, a supplementary explanation regarding the above-described embodiment (including modifications) and a general consideration will be given.

(1) Consideration of peripheral thick ring thin film wafer processing method:
The peripheral thick ring thin film wafer processing method using the wafer 1 having the peripheral thick ring on the back surface and processing with reduced warpage of the wafer has an advantage that the process can be executed without using a reinforcing glass substrate or the like. . However, according to a study by the inventors of the present application, it has been clarified that application of a normal mask (internal mask) to the back surface of the wafer has various problems due to the presence of the peripheral thick ring.

(2) Outline of manufacturing method of reverse conducting IGBT according to one embodiment (mainly FIG. 27):
Therefore, in the method of manufacturing the reverse conducting IGBT according to the embodiment, as shown in FIG. That is, the outline of the manufacturing method of the reverse conducting IGBT of the embodiment is as follows:
(2-1) First, a step of preparing a wafer on which a large number of unit chip regions 2 are formed in a matrix form;
(2-2) A step of grinding the inner region 30 of the back surface 1b of the wafer 1 to reduce the thickness and leave the ring-shaped thick region 42;
(2-3) Manufacture of reverse conducting IGBT including a step of attaching an external mask 23 to the back surface 1b of the wafer 1 and implanting ions into the back surface 1b of the wafer 1 with the ring-shaped thick region 42 remaining. Is the method.

  By doing so, the external mask 23 can be used a plurality of times, so that the step of forming the internal mask can be omitted one by one. Also, various process problems associated with the peripheral thick ring thin film wafer processing system can be avoided.

7). Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited thereto, and it goes without saying that various modifications can be made without departing from the scope of the invention. .

  For example, in the above embodiment, the IGBT structure having a trench gate structure such as a U-MOSFET has been specifically described as an example. However, the invention of the present application is not limited thereto, and the same applies to a planar structure or the like. Needless to say, it can be applied.

  In the above embodiment, the N channel device is mainly formed on the upper surface of the N epitaxial layer on the N + silicon single crystal substrate. However, the present invention is not limited to this, and P + A P channel device may be formed on the upper surface of the N epitaxial layer on the silicon single crystal substrate.

  In the above-described embodiment, the description has focused on the N-channel IGBT (or NPN system). However, regarding the P-channel IGBT (or PNP system), an operation for replacing the PN in all regions (in terms of structure) (PN inversion) is executed.

  In the above-described embodiment, the description has been made centering on a device having a drift region composed of a single conductivity type region, but it goes without saying that the drift region may have a super junction structure.

  Furthermore, in the above-described embodiment, an example in which a non-epitaxial wafer is used and a high concentration impurity layer is formed from the back surface after back grinding has been described. However, the invention of the present application is not limited thereto, and the epitaxial wafer Needless to say, the present invention can also be applied to those manufactured using the above.

  Although the punch-through type IGBT has been specifically described in the above embodiment, the invention of the present application is not limited thereto, and it can be applied to a non-punch-through type IGBT without a field stop layer as it is. Needless to say.

1 Semiconductor substrate (or wafer)
1a Device surface (semiconductor substrate) (first main surface)
1b Back surface (second main surface) of the semiconductor substrate
1s N-type substrate portion of wafer 2 Chip or chip region 3, 3a, 3b, 3c, 3d, 3e, 3f Flyback diode built-in IGBT
4, 4a, 4b, 4c, 4d, 4e, 4f IGBT element portion 5, 5a, 5b, 5c, 5d, 5e, 5f Flyback diode portion 6 DC power supply 7 Three-phase motor 8 Cell region 9 Guard ring 10 Emitter metal electrode DESCRIPTION OF SYMBOLS 11 Trench gate 12 N + emitter area | region 13 P type body area | region 14 P + body contact area | region 15 Gate insulating film 16 N-type drift area | region 17 P + collector area | region 18 Collector metal electrode 19 Diode cathode area | region (N + area | region through collector area | region)
20 Notch 21 N-type field stop region 22 Part removed by backgrinding 24 Internal MOSFET portion 23 External mask 23b External mask ion implantation mask region 23d External mask surface 23f External mask back surface 23p External mask ion implantation mask region 23r Ring-shaped frame (or ring-shaped frame) of external mask
25 Resistance component in N-type field stop region 26 Collector terminal side PN junction of internal PNP transistor 29 Collector region through N + region row (diode cathode region row)
29p N + region row through collector region (diode cathode region filling row)
29u Collector region through N + region row (diode cathode region unfilled row)
30 Internal region of wafer 31 BG tape 33 Dicing tape 41 Circular recess 42 Ring-shaped thick region 43 Adhesive tape for fixing 51 Grinding wheel 52 Boron ion implantation to collector region 53 Phosphorus ion implantation to field stop region 54 Collector region penetration Phosphorus ion implantation into N + region C Collector terminal E Emitter terminal (emitter pad)
G Gate terminal (gate pad)
Ice Emitter-collector current PX Pitch in X direction PY Pitch in Y direction R1 Cell region internal wide area cutout portion R2 Cell area internal unit periodic cutout portion S1, S2 Circle whose diameter is about half the short side of the chip T Cell region repeat structure Unit period Vce Emitter reference collector potential Vge Emitter reference gate potential

Claims (10)

A method for manufacturing a reverse conducting IGBT including the following steps:
(A) preparing a semiconductor wafer having a first main surface and a second main surface, wherein a plurality of unit chip regions are formed in a matrix on the first main surface;
(B) a step of thinning the inner region of the second main surface of the semiconductor wafer by grinding to leave a ring-shaped thick region around the semiconductor wafer;
(C) After the step (b), ion implantation is performed from the second main surface side of the semiconductor wafer with an external mask attached to the second main surface of the semiconductor wafer. The step of selectively introducing impurity ions into the second main surface of the semiconductor wafer. The method of manufacturing a reverse conducting IGBT according to claim 1, further comprising the following steps:
(D) removing the external mask from the semiconductor wafer;
(E) A step of performing laser annealing for activating the impurity ions after the step (d). The method of manufacturing a reverse conducting IGBT according to claim 2, further comprising the following steps:
(F) A step of forming a metal back electrode on the second main surface of the semiconductor wafer after the step (e). 4. The method of manufacturing a reverse conducting IGBT according to claim 3, further comprising the following steps:
(G) A step of irradiating the semiconductor wafer with an electron beam after the step (f). 5. The method of manufacturing a reverse conducting IGBT according to claim 4, further comprising the following steps:
(H) After the step (g), removing the ring-shaped thick region;
(I) A step of dividing the semiconductor wafer into individual unit chip regions after the step (h).     6. The method of manufacturing a reverse conducting IGBT according to claim 5, wherein the impurity ions are introduced into a portion to be a cathode region of a reverse conducting diode on the second main surface of the semiconductor wafer.     7. The method of manufacturing a reverse conducting IGBT according to claim 6, wherein the external mask is fitted into a circular recess inside the ring-shaped thick region during ion implantation.     8. The method of manufacturing a reverse conducting IGBT according to claim 7, wherein the ion implantation mask region of the external mask is made of a polyimide film.     9. The method of manufacturing a reverse conducting IGBT according to claim 8, wherein the periphery of the ion implantation mask region of the external mask is held by a ring-shaped frame body of the external mask.     10. The method of manufacturing a reverse conducting IGBT according to claim 9, wherein the ring-shaped thick region of the semiconductor wafer and the ring-shaped frame of the external mask are fixed to each other with an adhesive tape at the time of ion implantation. Has been.

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