JP2014107320A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a general-purpose semiconductor device manufacturing method which can prevent the occurrence of voids even when a size of a semiconductor chip, a type and a size of a bump electrode, a wiring width, a pitch, a level difference and the like of a wiring board are different from each other.SOLUTION: In a semiconductor device manufacturing method of joining a surface of a semiconductor chip on a bump electrode side with a surface of a wiring board on an insulating resin sheet side, to which the insulating resin sheet is attached on a pad electrode side of the wiring board, and electrically connecting the bump electrodes and the pad electrodes by application of heat and pressure, when assuming that displacement of the semiconductor chip with respect to the wiring board when the bump electrodes contact the insulating resin sheet and application of pressure starts is 0, displacement when the displacement becomes constant is d and a temperature at which a time (represented as t) from the start of application of pressure until reaching displacement 0.8d becomes minimum is T(T<250°C), the application of heat and pressure is performed at a temperature (T) which satisfies t(T)≤t(T)≤3 t(T).

Description

  The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor chip is flip-chip mounted on a wiring substrate, and more particularly to a method for manufacturing a semiconductor device using a wiring substrate on which an insulating resin sheet has been pasted.

  When flip-chip mounting a semiconductor chip on a wiring board, in order to alleviate thermal stress caused by the difference in linear expansion coefficient between the semiconductor chip and the wiring board, insulation called so-called underfill is provided in the gap between the semiconductor chip and the wiring board. A method of filling a liquid resin has been taken. However, when the gap between the semiconductor chip and the wiring substrate is narrowed by fine connection, there is a problem that it takes a long time to fill the insulating liquid resin using the capillary phenomenon. Further, there has been a problem that it becomes difficult to remove and remove the flux residue at the time of connection using solder or the like. On the other hand, an insulating liquid resin is applied to the wiring board in advance or an insulating resin sheet is pasted, and the bump electrode of the semiconductor chip and the pad electrode of the wiring board are electrically connected by heating and pressurization, and the insulating resin A manufacturing method of a semiconductor device for performing curing is performed. In particular, in order to minimize the mounting area by controlling the amount of insulating resin and the amount of fillet, a method of attaching an insulating resin sheet has become the mainstream.

  A method of attaching the insulating resin sheet will be described with reference to FIG. First, a wiring board having a pad electrode and wiring formed on one main surface is prepared (FIG. 1A). Next, an insulating resin sheet is temporarily attached to the wiring board using a pressure jig, a roller, a laminator, etc. (not shown) (FIG. 1B). Next, a semiconductor chip having a bump electrode formed on one main surface is prepared (FIG. 1C). Thereafter, the bump electrode and the pad electrode are made to face each other, and the semiconductor chip is pressed while being heated to a first temperature that is equal to or higher than the temperature at which the insulating resin sheet is softened using a holding jig (not shown), and the bump electrode reaches the pad electrode. Thereafter, the temperature is raised to a second temperature necessary for electrical connection between the two, and the electrical connection and the insulating resin sheet are cured (FIG. 1D).

  On the other hand, there is a problem that voids (bubbles) are left in the stepped part of the wiring board when the insulating resin sheet is pasted due to the finer and narrower pitch of the wiring. There are proposed a method of making the shape difficult to contain (see Patent Document 1) and a method of temporarily fixing the insulating resin sheet using a holding jig having a protrusion (see Patent Document 2). However, in these methods, if the size of the semiconductor chip, the type and size of the bump electrode, the wiring width, pitch, and level difference of the wiring substrate are different, the effect of preventing the occurrence of voids may be reduced or cannot be obtained. Therefore, when the size of the semiconductor chip is different, the effect is confirmed, and when the effect is not obtained, a new optimal opening shape of the protective film of the wiring board and an optimal protrusion shape of the holding jig are determined. There was a need to do.

Japanese Patent Laid-Open No. 2008-311443 (pages 4-5, FIG. 1) JP 2010-251652 (pages 6-9, FIG. 8)

  The present invention provides a general-purpose semiconductor device manufacturing method capable of preventing the occurrence of voids even when the size of a semiconductor chip, the type and size of bump electrodes, the wiring width, pitch, and level difference of a wiring board are different. For the purpose.

The manufacturing method of the present invention includes a wiring board with an insulating resin sheet in which an insulating resin sheet is bonded to a surface on a bump electrode side of a semiconductor chip having a bump electrode and a surface on the pad electrode side of a wiring board having a pad electrode. A method of manufacturing a semiconductor device in which the bump electrode and the pad electrode are electrically connected by heating and pressurizing together with the surface on the insulating resin sheet side, the bump electrode being attached to the insulating resin sheet The displacement of the semiconductor chip with respect to the wiring substrate when the pressurization is started upon contact is 0, the displacement when the displacement becomes constant is d, and from the start of pressurization until the displacement reaches 0.8d. T _0.8d (T _c ) ≦ t _0.8d (T) ≦ 3t _0.8d (T _c ) where T _c (T _c <250 ° C.) is the temperature at which the time (t _0.8d is minimum). ) Satisfying temperature (T) And performing heating and pressing.

  According to the present invention, a semiconductor device free from voids can be obtained even when the size of the semiconductor chip, the type and size of the bump electrode, the wiring width of the wiring substrate, the pitch, the step, and the like are different.

Sectional drawing explaining the manufacturing method of the conventional semiconductor device Sectional drawing explaining the manufacturing method of the semiconductor device of this invention FIG. 1 is a diagram for explaining a method for determining a pressurization temperature in a method for manufacturing a semiconductor device according to the present invention FIG. 2 is a diagram for explaining a method for determining a pressurization temperature in the method for manufacturing a semiconductor device of the present invention FIG. 3 is a diagram for explaining a method for determining a pressurization temperature in the method for manufacturing a semiconductor device of the present invention

  As a result of intensive studies on the prevention of voids described above, the present inventors have obtained the following results. That is, it has been found that there is a temperature region in which there is almost no void generation (void is 1% or less of the chip area) centering on the temperature at which the displacement change of the semiconductor chip relative to the wiring substrate at the beginning of pressurization is the largest. More specifically, when the displacement of the semiconductor chip relative to the wiring board is 0, and the displacement when the displacement becomes constant is d, the time from the start of pressurization to the displacement 0.8d is the minimum time. It has been found that there is almost no generation of voids in a temperature range in which the displacement reaches 0.8 d within a time three times the minimum time centering on the above temperature.

That is, the method for manufacturing a semiconductor device according to the present invention includes an insulating resin in which an insulating resin sheet is bonded to a surface on a bump electrode side of a semiconductor chip having a bump electrode and a surface on the pad electrode side of a wiring substrate having a pad electrode. A method of manufacturing a semiconductor device in which the bump electrode and the pad electrode are electrically connected by heating and pressurizing together with the surface on the insulating resin sheet side of the wiring board with sheet, wherein the bump electrode The displacement of the semiconductor chip relative to the wiring board when the pressurization is started in contact with the insulating resin sheet is 0, the displacement when the displacement becomes constant is d, and the displacement is 0.8d from the start of pressurization. T _0.8d (T _c ) ≦ t _0.8d (T) ≦ 3t ₀ , where T _c (T _c <250 ° C.) is the temperature at which the time to reach (t _0.8d ) is the minimum _.8d (T ) And performing heating and pressurization at a temperature (T) that satisfies.

  In the method for manufacturing a semiconductor device of the present invention, an insulating resin sheet in which an insulating resin sheet is bonded to the bump electrode side surface of a semiconductor chip having a bump electrode and the pad electrode side surface of a wiring substrate having a pad electrode Match the surface of the attached wiring board with the surface of the insulating resin sheet. For example, the steps described in the background art with reference to FIGS. 1A to 1C can be performed in the same manner.

  Next, the bump electrode and the pad electrode are electrically connected by heating and pressing. At that time, it is preferable that pressurization is started while heating the semiconductor chip at a first temperature that is equal to or higher than the temperature at which the insulating resin sheet softens, and the tip of the bump electrode is brought into contact with the insulating resin sheet. An example is shown in FIG. Next, it is preferable to further pressurize and lower the bump electrode while pushing away the softened insulating resin. An example is shown in FIG. When the tip of the bump electrode reaches the surface of the wiring, the displacement of the semiconductor chip with respect to the wiring substrate becomes constant. An example is shown in FIG.

In the present invention, at this time, the first temperature is determined as follows. That is, the displacement of the semiconductor chip relative to the wiring board when the bump electrode comes into contact with the insulating resin sheet and the pressurization is started is 0, and the displacement when the displacement becomes constant is d. T _c (T _c <250 ° C.) is the temperature at which the time from the start of pressure to the displacement 0.8d (t _0.8d ) is minimized, and t _0.8d at temperatures T and T _c is t _{0.8d (T),} as _{t 0.8d (T c), t} 0.8d a _{(T c) ≦ t 0.8d (} T) temperature satisfying _{≦ 3t 0.8d (T c) (} T) first The temperature is 1.

  Thereafter, as in the background art, it is preferable that after the bump electrode reaches the pad electrode, the temperature is raised to a second temperature necessary for electrical connection between the two to cure the electrical connection and the insulating resin sheet.

  Hereinafter, the method for determining the first temperature will be described with reference to FIGS.

FIG. 3 shows the relationship between the displacement of the semiconductor chip relative to the wiring board at a certain temperature and the time from the start of pressurization. As described above, when the tip of the bump electrode reaches the surface of the wiring, the displacement of the semiconductor chip with respect to the wiring substrate becomes constant (FIG. 2C), but the time required for this in the practical temperature range is usually 1-5 seconds. When the displacement that becomes constant after 5 seconds is defined as d, a time t _0.8d required for the displacement to change to 0.8 d is _obtained for each heating temperature.

FIG. 4 shows an example in which the time t _0.8d required for the obtained displacement at each heating temperature to change to _0.8d is plotted. FIG. 5 shows a ratio t _0.8d / t _0.8d (T _c ) with respect to the minimum value at this time (in this example, t _0.8d (200 ° C.)). In FIG. 5, the temperature at which t _0.8d / t _0.8d (T _c ) is 3 or less can be selected as the first temperature.

  In the embodiment of the present invention, the first 80% of the displacement from the time when the heating and pressurization is started and the bump electrode contacts the insulating resin sheet until the tip of the bump electrode reaches the surface of the wiring. Based on the case of the temperature that reaches the earliest, it has become clear from various examinations that there is almost no void if the time to reach the first 80% displacement is up to three times that time.

Even when t _0.8d / t _0.8d (T _c ) is 3 or less, voids due to degassing frequently occur when the heating temperature is equal to or higher than the heat resistance temperature of the wiring substrate (for example, 250 ° C.). A heating temperature higher than the heat resistance temperature cannot be selected.

  In the production method of the present invention, it is preferable that at least the surface of the pad electrode contains one or more metals selected from Au, Sn and solder. By using Au as the surface, oxidation of the pad electrode can be prevented and good bonding can be obtained. Further, since Sn or solder is provided on the surface, Sn or solder on the pad electrode is melted during bonding, and a bond can be easily formed.

  In the production method of the present invention, it is preferable that at least the surface of the bump electrode contains one or more metals selected from Au, Cu and solder.

  In the manufacturing method of the present invention, it is preferable that at least the surface of the pad electrode and / or at least the surface of the bump electrode contains solder, and the heating temperature (T) is lower than the melting point of the solder. By setting the heating temperature (T) below the melting point of the solder, the resin sheet between the bump electrode and the pad electrode can be eliminated and a bond can be formed.

  According to the manufacturing method of the present invention, a general-purpose semiconductor device capable of preventing the generation of voids even when the size of the semiconductor chip, the type and size of the bump electrode, the wiring width, pitch, and level difference of the wiring board are different. Can achieve an excellent industrial effect.

  Hereinafter, the present invention will be described with reference to examples, but the present invention is not limited to these examples. The materials and evaluation methods used in Examples 1 to 30 and Comparative Examples 1 to 7 are shown below. Table 1 shows the levels and evaluation results of each example and each comparative example.

<Thermosetting adhesive film> (insulating resin sheet)
The following (a) polyimide, (b) epoxy resin, (c) curing accelerator, (e) insulating filler are mixed, and (d) the solvent is appropriately adjusted so that the coating film thickness becomes uniform. In addition, a thermosetting adhesive film was prepared by coating and drying on a release plastic film (polyethylene terephthalate film). (A), (b), (c), and (e) were mixed at a weight ratio of 25: 10: 25: 50. The thickness of the produced thermosetting adhesive film was 45 μm.

  (C) is a microcapsule type curing accelerator dispersed in an epoxy resin, and the weight ratio is microcapsule type curing accelerator / epoxy resin = 33/67. The proportion of c) is calculated based on the total amount of (c), and the epoxy resin in (c) is not included in the proportion of (b).

(A) Polyimide An organic solvent-soluble polyimide synthesized by the following process was used.

  First, 24.54 g (0.067 mol) of 2,2-bis (3-amino-4-hydroxyphenyl) hexafluoropropane and 1,3-bis (3-aminopropyl) tetramethyldisiloxane under a dry nitrogen stream 4.97 g (0.02 mol) and 2.18 g (0.02 mol) of 3-aminophenol as an end-capping agent were dissolved in 80 g of N-methyl-2-pyrrolidone (hereinafter referred to as NMP). . Here, 31.02 g (0.1 mol) of bis (3,4-dicarboxyphenyl) ether dianhydride was added together with 20 g of NMP, reacted at 20 ° C. for 1 hour, and then stirred at 50 ° C. for 4 hours. Thereafter, 15 g of xylene was added, and the mixture was stirred at 180 ° C. for 5 hours while water was azeotroped with xylene. After the stirring was completed, the solution was poured into 3 L of water to obtain a white precipitated polymer. The precipitate was collected by filtration, washed with water three times, and then dried at 80 ° C. for 20 hours using a vacuum dryer.

(B) Epoxy resin A solid epoxy compound (Japan Epoxy Resin Co., Ltd., Epicoat 157S70) was used.

(C) Curing accelerator A microcapsule-type curing accelerator (manufactured by Asahi Kasei Chemicals Corporation, NovaCure HX-3941HP) was used.

(D) Solvent Methyl ethyl ketone / toluene = 4/1 (weight ratio) was used.

(E) Insulating inorganic filler SO-E2 (trade name, manufactured by Admatechs Co., Ltd., spherical silica particles, average particle size 0.5 μm) was used.

<Semiconductor chip structure>
An aluminum wiring having a thickness of 1 μm is formed on an oxide film on a silicon substrate, chromium is formed in an opening of a silicon nitride insulating film having a thickness of 1 μm formed thereon, and a post having a height of 10 μm is formed of copper. A manufactured semiconductor chip was produced. As bump surface states, three types were prepared: a semiconductor chip having no coating (a semiconductor chip having a copper film), a semiconductor chip having a gold film, and a solder film (SnAg, melting point 220 ° C.). The bump diameter is 25, 30, 35, 40 μm, and the bump pitch is 75, 80, 85, 90 μm for each bump diameter. Further, 138, 150, 162, and 174 bumps are formed for each pitch. The aluminum wiring is patterned so that the connection resistance can be measured for each bump structure after mounting on the wiring board. The chip size is 7 mm × 7 mm, and the chip thickness is 100 μm.

<Wiring board>
A wiring plate (thickness: 300 μm) having a structure in which a copper wiring of 15 μm thickness and a pad electrode are formed as a wiring board, and the pad electrode is exposed from an opening of a solder resist of 20 μm thickness formed thereon. did. All pad electrodes are formed at positions corresponding to the bump electrodes of the semiconductor chip. As the surface state of the pad electrode, three types were produced: a wiring board having a tin film, a wiring board having a solder film (SnAg, melting point 220 ° C.), and a wiring board having a gold film. This wiring board forms a daisy chain by mounting the semiconductor chip, and the junction resistance between the bump electrode and the pad electrode can be measured through the lead electrode. The size of the wiring board is 12 mm × 12 mm, and a 300 μmφ lead electrode pad for measuring the conduction resistance of the daisy chain is formed in an area where no chip is mounted.

<Lamination of thermosetting adhesive film on wiring board>
The lamination of the thermosetting adhesive film to the wiring board was performed using a vacuum pressure laminator (Nichigo Morton Co., Ltd., CVP-300T). The thermosetting adhesive film formed on the polyethylene terephthalate film is cut into the same size as the semiconductor chip, and the surface of the thermosetting adhesive film is pressed against the wiring board at 80 ° C. for 30 seconds in a vacuum. Lamination was performed under conditions of 5 MPa.

<Calculation of _Tc >
First, using a bonding apparatus (manufactured by Toray Engineering Co., Ltd., FC3000S), the semiconductor chip stored in the chip tray with the surface having the bump electrode facing downward was picked up by a heat tool set at 50 ° C. . Next, the heat tool that adsorbed the semiconductor chip was conveyed to above the wiring board on which the thermosetting adhesive material film placed on the stage at 80 ° C. was laminated. Next, the alignment recognition camera entered between the semiconductor chip and the wiring board so that the bump electrodes of the semiconductor chip and the pad electrodes on the wiring board overlapped at predetermined positions, and the respective alignment marks were detected.

After the alignment mark was detected, pressing was performed for 5 seconds with a load of 50 N at each temperature of 120 ° C. to 280 ° C. At this time, the height of the head was measured and recorded, the displacement amount of the head 5 seconds after the start of mounting was set as d, and the time for the head to reach 0.8d was set as t _0.8d (T). When the temperature at which t _0.8d is minimum in the above temperature range was determined, T _c = 200 ° C. and t _0.8d (T _c ) = 0.5 s. FIG. 5 shows t _0.8d (T) / t _0.8d (T _c ) at each temperature.

  The temperature inside the thermosetting adhesive film during mounting was calibrated in advance using a temperature recorder (manufactured by Keyence Corporation, NR100) and a K thermocouple.

<Mountability evaluation>
The mountability was evaluated by void bite evaluation and conduction evaluation (measurement of daisy chain conduction resistance).

  Evaluation of void biting was performed by observing with a microscope after removing the semiconductor chip by polishing. If the void was 1% or less of the chip area, it was evaluated as ◎ if it was larger than 1% and 5% or smaller, and × if it contained more voids.

  The semiconductor chip and the wiring board used in the evaluation of each example are designed to be electrically connected to each bump pitch through connecting portions of 138, 150, 162, and 174, respectively. ing. If there is a portion where even one bump electrode and one pad electrode are not in contact, connection failure occurs.

  For the continuity evaluation, a measurement terminal of DIGITAL VOLMETER (made by HEWLETT PACKARD, 3455A) was connected, and the resistance value was measured. The resistance value includes not only the connection portion between the bump electrode and the pad electrode but also the resistance inside the semiconductor chip and the value of the lead electrode. It was determined whether or not all measured resistance values were less than 100 kΩ for each bump pitch daisy chain. Of the three samples implemented, all three samples had a measured daisy chain resistance value of less than 100 kΩ. ◎ One sample or two samples had a daisy chain resistance value of 100 kΩ or more. The case where the resistance value of the daisy chain was 100 kΩ or more in all three samples was judged as x.

Example 1
<Preparation of mountability evaluation sample>
A wiring substrate having a tin film on the pad electrode surface and a semiconductor chip having a solder film (SnAg, melting point 220 ° C.) on the bump surface were used.

  First, the semiconductor chip housed in the chip tray with the bonding electrode (Toray Engineering Co., Ltd., FC3000S) faced down with the bump electrode faced down was picked up with a heat tool set at 50 ° C. and picked up. Next, the heat tool that adsorbed the semiconductor chip was conveyed to above the wiring board on which the thermosetting adhesive material film placed on the stage at 80 ° C. was laminated. Next, the alignment recognition camera entered between the semiconductor chip and the wiring board so that the bump electrodes of the semiconductor chip and the pad electrodes on the wiring board overlapped at predetermined positions, and the respective alignment marks were detected.

  After detection of the alignment mark, pressing was performed for 1 second at a temperature of 150 ° C. and a load of 50 N (step 1). Next, the temperature was raised to 250 ° C., and pressing was performed with a load of 50 N for 10 seconds (step 2).

  The temperature inside the thermosetting adhesive film during mounting was calibrated in advance using a temperature recorder (manufactured by Keyence Corporation, NR100) and a K thermocouple.

<Mountability evaluation>
The void biting evaluation was ○, and the conduction evaluation was ◎.

Example 2
Evaluation was performed in the same manner as in Example 1 except that a wiring substrate having a solder film (SnAg, melting point 220 ° C.) on the pad electrode surface and a semiconductor chip having a copper film on the bump surface were used. The void biting evaluation was ○, and the conduction evaluation was ◎.

Example 3
Evaluation was performed in the same manner as in Example 1 except that a wiring substrate having a gold film on the pad electrode surface and a semiconductor chip having a gold film on the bump surface were used. The void biting evaluation was ○, and the conduction evaluation was ◎.

Examples 4-6
Evaluations were made in the same manner as in Examples 1 to 3, except that the temperature in Step 1 was 160 ° C. Both void biting evaluation and conduction evaluation were ◎.

Examples 7-9
Evaluations were made in the same manner as in Examples 1 to 3, except that the temperature in Step 1 was 170 ° C. Both void biting evaluation and conduction evaluation were ◎.

Examples 10-12
Evaluations were made in the same manner as in Examples 1 to 3 except that the temperature in Step 1 was 180 ° C. Both void biting evaluation and conduction evaluation were ◎.

Examples 13-15
Evaluations were made in the same manner as in Examples 1 to 3, except that the temperature in Step 1 was 190 ° C. Both void biting evaluation and conduction evaluation were ◎.

Examples 16-18
Evaluations were made in the same manner as in Examples 1 to 3, except that the temperature in Step 1 was 200 ° C. Both void biting evaluation and conduction evaluation were ◎.

Examples 19-21
Evaluations were made in the same manner as in Examples 1 to 3, except that the temperature in Step 1 was 210 ° C. Both void biting evaluation and conduction evaluation were ◎.

Examples 22-24
Evaluations were made in the same manner as in Examples 1 to 3, except that the temperature in Step 1 was 220 ° C. The void biting evaluation was ◎ in all of Examples 22 to 24. The continuity evaluation is ○ when there is a solder film (SnAg, melting point 220 ° C.) on the bump surface (Example 22), and the resistance value of the daisy chain becomes 100 kΩ or more for one sample. Both were ◎.

Examples 25-27
Evaluations were made in the same manner as in Examples 1 to 3, except that the temperature in Step 1 was 230 ° C. The void biting evaluation was ◎ in all of Examples 25 to 27. In the case of having a solder film (SnAg, melting point of 220 ° C.) on the bump surface (Example 25), the continuity evaluation is “Good” when the resistance value of the daisy chain is 100 kΩ or more for one sample. Both were ◎.

Examples 28-30
Evaluations were made in the same manner as in Examples 1 to 3, except that the temperature in Step 1 was 240 ° C. Evaluation of void biting was ◎ in all of Examples 28 to 30. In the case of having a solder film (SnAg, melting point of 220 ° C.) on the bump surface (Example 28), the continuity evaluation is “Good” in some cases where the resistance value of the daisy chain is 100 kΩ or more for two samples. Both were ◎.

  When the bump electrode is solder, as in Examples 22, 25, and 28, when heating and pressurization is performed at a temperature higher than the melting point of the solder, the resistance is slightly increased in the conduction evaluation, and the solder is deformed by losing the hardness of the resin. It was observed.

Comparative Example 1
Evaluation was performed in the same manner as in Example 1 except that the temperature in Step 1 was 120 ° C. The void biting evaluation was x, and the conduction evaluation was ◎.

Comparative Example 2
Evaluation was performed in the same manner as in Example 1 except that the temperature in Step 1 was 130 ° C. The void biting evaluation was x, and the conduction evaluation was ◎.

Comparative Example 3
Evaluation was performed in the same manner as in Example 1 except that the temperature in Step 1 was 140 ° C. The void biting evaluation was x, and the conduction evaluation was ◎.

Comparative Example 4
Evaluation was performed in the same manner as in Example 1 except that the temperature in Step 1 was 250 ° C. The void bite evaluation was x. In the continuity evaluation, there was a case where the resistance value of the daisy chain was less than 100 kΩ in only one sample.

Comparative Example 5
Evaluation was performed in the same manner as in Example 1 except that the temperature in Step 1 was 260 ° C. Both void biting evaluation and conduction evaluation were x.

Comparative Example 6
Evaluation was performed in the same manner as in Example 1 except that the temperature in Step 1 was 270 ° C. Both void biting evaluation and conduction evaluation were x.

Comparative Example 7
Evaluation was performed in the same manner as in Example 1 except that the temperature in Step 1 was 280 ° C. Both void biting evaluation and conduction evaluation were x.

DESCRIPTION OF SYMBOLS 1 Bump electrode 2 Semiconductor chip 3 Pad electrode 4 Wiring board 5 Insulating resin sheet 6 Wiring

Claims (4)

The surface on the side of the bump electrode of the semiconductor chip having the bump electrode and the surface on the side of the insulating resin sheet of the wiring substrate with the insulating resin sheet in which the insulating resin sheet is bonded to the surface on the side of the pad electrode of the wiring substrate having the pad electrode The bump electrode and the pad electrode are electrically connected by heating and pressurizing, and the bump electrode contacts the insulating resin sheet and the pressurization is performed. The displacement of the semiconductor chip relative to the wiring board when started is 0, the displacement when the displacement becomes constant is d, and the time from the start of pressurization to the displacement 0.8d (t _0.8d ) Is the temperature that _satisfies t _0.8d (T _c ) ≦ t _0.8d (T) ≦ 3t _0.8d (T _c ), where T _c (T _c <250 ° C.) is the minimum temperature (T) Heating and pressurizing with The method of manufacturing a semiconductor device according to claim. 2. The method of manufacturing a semiconductor device according to claim 1, wherein at least a surface of the pad electrode contains one or more metals selected from Au, Sn, and solder. 2. The method of manufacturing a semiconductor device according to claim 1, wherein at least a surface of the bump electrode contains one or more metals selected from Au, Cu, and solder. 4. At least the surface of the pad electrode and / or at least the surface of the bump electrode contains solder, and the heating temperature (T) is lower than the melting point of the solder. The manufacturing method of the semiconductor device as described in any one of.

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