JP2014103238A - Semiconductor light-emitting element manufacturing method and semiconductor light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element which inhibits cracking in a semiconductor layer.SOLUTION: A semiconductor light-emitting element manufacturing method of the present embodiment comprises: a coating film formation process of forming a mask which coats a partial region on a laminated semiconductor layer including a luminescent layer emitting light by energization and composed of a group III nitride and which is composed of a material different from a material of the laminated semiconductor layer on a semiconductor multilayered substrate in which the laminated semiconductor layer is laminated on a substrate; a surface laser process of locally removing the laminated semiconductor layer from the side where the mask is formed so as to reach the substrate thereby to form a first irradiation line and a second irradiation line which cross on the mask and divide the laminated semiconductor layer in a plurality of regions on the semiconductor multilayered substrate where the mask is formed; and a wet etching process of performing wet etching on the semiconductor multilayer substrate on which the mask, the first irradiation line and the second irradiation line are formed.

Description

  The present invention relates to a method for manufacturing a semiconductor light emitting device and a semiconductor light emitting device.

2. Description of the Related Art A semiconductor light emitting device in which a group III nitride semiconductor layer including a light emitting layer that emits light when energized is laminated on a substrate is known.
In such a semiconductor light emitting device, the side surface of the group III nitride semiconductor layer is inclined outward with respect to the normal line of the upper surface of the substrate so that the cross-sectional shape of the group III nitride semiconductor layer becomes narrower toward the substrate side. Thus, there is a technique for improving the light extraction efficiency in the semiconductor light emitting device (see Patent Document 1).

JP 2007-116114 A

By the way, when the side surface of the semiconductor layer is inclined outward with respect to the normal line of the upper surface of the substrate in the semiconductor light emitting device, there is a concern that the end of the semiconductor layer is likely to be cracked.
An object of this invention is to provide the semiconductor light-emitting device which suppressed the crack of the semiconductor layer.

The method for manufacturing a semiconductor light emitting device of the present invention is different from a semiconductor laminated substrate in which a semiconductor layer composed of a group III nitride including a light emitting layer that emits light when energized is laminated on the substrate. A covering portion forming step for forming a covering portion that is made of a material and covers a part of the region on the semiconductor layer; and the semiconductor layer is formed on the semiconductor laminated substrate on which the covering portion is formed. A dividing groove forming step of forming a plurality of dividing grooves that intersect at the covering portion and divide the semiconductor layer into a plurality of regions by locally removing the substrate so as to reach the substrate from the formed side; And a wet etching step of performing wet etching on the semiconductor laminated substrate on which the covering portion and the dividing groove are formed.
In the method of manufacturing a semiconductor light emitting element according to the present invention, in the covering portion forming step, the covering portion formed of an insulating film having an insulating property is formed, and the insulating layer is formed on the semiconductor layer. Forming another covering portion that covers a region different from the covering portion, and forming the plurality of dividing grooves that intersect at the covering portion and do not pass through the other covering portion in the dividing groove forming step. Can be a feature.
Furthermore, in the method for manufacturing a semiconductor light emitting device of the present invention, before the covering portion forming step, a part of the semiconductor layer is locally removed from the side opposite to the substrate with respect to the semiconductor laminated substrate, The semiconductor layer further includes a semiconductor removing step of forming a plurality of grooves that are recessed toward the substrate side and intersect with each other to separate the opposite side of the semiconductor layer from the substrate into a plurality of regions. In the part forming step, the covering portion is formed at an intersecting portion where the plurality of groove portions intersect, and in the dividing groove forming step, the plurality of dividing grooves are formed along the plurality of groove portions and intersecting at the intersecting portion. It can be characterized by.

  In another aspect of the method for manufacturing a semiconductor light emitting device of the present invention, the method for manufacturing a semiconductor light emitting device of the present invention includes a light emitting layer that emits light when energized on a substrate and is composed of a group III nitride. Altered region formation that forms a denatured region by altering a partial region of the semiconductor layer by processing the semiconductor layer from the side opposite to the substrate with respect to the semiconductor laminated substrate in which the semiconductor layers are laminated A step of removing the semiconductor layer locally from the side where the altered region is formed until reaching the substrate with respect to the semiconductor laminated substrate on which the altered region is formed. A dividing groove forming step of forming a plurality of dividing grooves that intersect and divide the semiconductor layer into a plurality of regions, and a wet etching with respect to the altered region and the semiconductor laminated substrate on which the plurality of dividing grooves are formed. And a wet etching step of performing ring.

  Further, when the present invention is regarded as a semiconductor light emitting device, the semiconductor light emitting device of the present invention is a semiconductor light emitting device including a semiconductor layer including a light emitting layer that emits light when energized, and the semiconductor layer includes a semiconductor bottom surface and the semiconductor bottom surface. A semiconductor side surface rising above the semiconductor layer from the first peripheral edge of the bottom surface, and a semiconductor upper surface facing upward by extending from the second peripheral edge above the semiconductor side surface toward the inside of the semiconductor layer. The second peripheral edge has a plurality of linear portions extending linearly and a plurality of connecting portions connecting the adjacent linear portions, and each of the connecting portions extends from a direction perpendicular to the upper surface of the semiconductor. When viewed, the semiconductor side surface is located on the inner side of the intersection of the extension lines of the two linear portions connected by the connection portion, and the semiconductor side surface extends from the first peripheral edge to the second peripheral edge. A straight portion side surface that rises toward the straight portion, and a connection side surface that rises from the first periphery toward the connection portion at the second periphery, and the connection side surface extends from the first periphery to the connection portion. An outer inclined surface that inclines upward and outward from the semiconductor layer, and an inward that inclines upward and inward from the upper end of the outer inclined surface toward the connection portion at the second peripheral edge And an inclined surface.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor light-emitting device which suppressed the crack of the semiconductor layer can be provided.

It is an example of the perspective view of the semiconductor light-emitting device to which this Embodiment is applied. It is an example of the top view of the semiconductor light-emitting device shown in FIG. It is an example of the longitudinal cross-sectional view of the board | substrate and laminated semiconductor layer to which this Embodiment is applied. It is an example of the longitudinal cross-sectional view of the semiconductor light-emitting device to which this Embodiment is applied. It is an example of the longitudinal cross-sectional view of the semiconductor light-emitting device to which this Embodiment is applied. It is a figure for demonstrating the structure of the vicinity of the connection part and connection side surface of a lower side semiconductor layer to which this Embodiment is applied. It is a flowchart which shows an example of the manufacturing method of the semiconductor light-emitting device to which this Embodiment is applied. It is the figure which showed the semiconductor laminated substrate after 1st groove part obtained by performing a semiconductor removal process, 2nd groove part, p electrode, and n electrode. It is the figure which showed the semiconductor laminated substrate after mask and protective film formation obtained by performing a film formation process. It is the figure which showed the semiconductor laminated substrate after forming the 1st irradiation line and the 2nd irradiation line obtained by performing a surface laser process. It is the figure which showed the semiconductor laminated substrate obtained by performing a wet etching process. It is a figure for demonstrating progress of the wet etching in a lower side semiconductor layer. It is a figure for demonstrating progress of the wet etching in a lower side semiconductor layer. It is a figure for demonstrating progress of the wet etching in a lower side semiconductor layer. It is the figure which showed the other shape of the mask formed in a film formation process.

  Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, the size, thickness, and the like of each part in the drawings referred to in the following description may be different from the dimensions of an actual semiconductor light emitting element or the like.

(Structure of semiconductor light emitting device)
FIG. 1 is an example of a perspective view of a semiconductor light emitting device 1 to which the present embodiment is applied, and FIG. 2 is an example of a top view of the semiconductor light emitting device 1 shown in FIG.
As shown in FIGS. 1 and 2, the semiconductor light emitting device 1 according to the present embodiment includes a substrate 100, a laminated semiconductor layer 200 as an example of a semiconductor layer laminated on the substrate 100, and the laminated semiconductor layer 200. The p electrode 300 and the n electrode 400 are formed.

  In addition, the stacked semiconductor layer 200 of this embodiment includes a lower semiconductor layer 210 stacked on the substrate 100 and an upper semiconductor layer 250 stacked on the lower semiconductor layer 210. In this example, the p-electrode 300 is formed on the upper semiconductor layer 250 (an upper semiconductor upper surface 253 described later), and the n-electrode 400 is formed on the lower semiconductor layer 210 (a semiconductor exposed surface 213a described later). Is formed.

As shown in FIG. 1, the semiconductor light emitting device 1 of the present embodiment has a substantially rectangular parallelepiped shape. As shown in FIG. 2, the semiconductor light emitting device 1 has a substantially rectangular shape having a long side and a short side when viewed from the side where the p-electrode 300 and the n-electrode 400 are formed. Have.
In the present embodiment, when the semiconductor light emitting device 1 is viewed from the side where the p-electrode 300 and the n-electrode 400 are formed, the direction along the long side is defined as the first direction x, and the direction along the short side is defined as the first direction x. Let it be two directions y. A direction perpendicular to the first direction x and the second direction y and from the substrate 100 side to the laminated semiconductor layer 200 side in the semiconductor light emitting element 1 is defined as a third direction z.

Furthermore, as shown in FIG. 1, the substrate 100 of the present embodiment has a substantially rectangular parallelepiped shape. Then, as shown in FIG. 2, the substrate 100 has a long side along the first direction x and a second direction y when viewed along the third direction z from the side where the laminated semiconductor layer 200 is laminated. It has a substantially rectangular shape with a short side along. Therefore, the substrate 100 includes four substrate side surfaces, a substrate upper surface 113 on which the laminated semiconductor layer 200 is stacked, and a substrate bottom surface 114 (see FIG. 3 described later) facing the substrate upper surface 113 through the four substrate side surfaces. Have. The substrate top surface 113 and the substrate bottom surface 114 each have a rectangular shape having two long sides along the first direction x and two short sides along the second direction y.
In the present embodiment, of the four substrate side surfaces, the two long side substrate side surfaces along the first direction x are referred to as first substrate side surfaces 111, respectively, and two short sides along the second direction y. The side substrate side surfaces are referred to as second substrate side surfaces 112, respectively.

In this example, a sapphire single crystal having a C-plane as the substrate upper surface 113 is used as the substrate 100. Note that as the plane orientation of the substrate upper surface 113, it is desirable to use a C plane of sapphire single crystal from which a high-quality laminated semiconductor layer 200 can be easily obtained. As the substrate upper surface 113, it is more desirable to use a surface to which a minute off angle is given with respect to the C surface of the sapphire single crystal. When providing an off angle, 1 ° or less is applied as the off angle. In the present embodiment, the substrate upper surface 113 is simply referred to as the C plane, including the case where such an off angle is provided. Furthermore, the sapphire single crystal used as the substrate 100 may contain a small amount of impurities.
Further, as the substrate 100, a substrate other than a sapphire single crystal may be used. For example, a substrate 100 made of GaN, SiC, silicon or the like can be used.

The lower semiconductor layer 210 of the present embodiment has a substantially rectangular parallelepiped shape as shown in FIGS. Accordingly, the lower semiconductor layer 210 is an example of a lower semiconductor upper surface 213 as an example of a semiconductor upper surface on which the upper semiconductor layer 250 is stacked, and an example of a semiconductor lower surface facing the lower semiconductor upper surface 213 and in contact with the substrate upper surface 113. The lower semiconductor bottom surface 214 (see FIG. 4 described later), the periphery of the lower semiconductor top surface 213 (upper surface periphery 230 described later), and the periphery of the lower semiconductor bottom surface 214 (bottom surface periphery 240 described later) are provided. It has a lower semiconductor side surface (not shown) as an example of the semiconductor side surface.
In the present embodiment, the area of the lower semiconductor bottom surface 214 in the lower semiconductor layer 210 is smaller than the area of the substrate upper surface 113 in the substrate 100. In addition, the area of the lower semiconductor upper surface 213 in the lower semiconductor layer 210 is smaller than the area of the substrate upper surface 113. Therefore, the peripheral edge of the substrate upper surface 113 of the substrate 100 is exposed to the outside, and when the semiconductor light emitting element 1 is viewed from the side where the p electrode 300 and the n electrode 400 are formed as shown in FIG. The peripheral edge of the exposed substrate upper surface 113 can be visually recognized.
Furthermore, in this example, the area of the lower semiconductor bottom surface 214 is formed smaller than the area of the lower semiconductor upper surface 213.

  As shown in FIGS. 1 and 2, a semiconductor exposed surface 213a exposed by cutting out a part of the upper semiconductor layer 250 is formed on the lower semiconductor upper surface 213 of the present embodiment. The n-electrode 400 is provided on the semiconductor exposed surface 213a as described above.

As shown in FIG. 2, the lower semiconductor upper surface 213 of the present embodiment has a shape (so-called rounded rectangle) that approximates a rectangle in which four corners have arc shapes. That is, the upper surface peripheral edge 230 of the lower semiconductor upper surface 213 includes a linear first linear portion 231 along the first direction x, a linear second linear portion 232 along the second direction y, and a first linear portion 231. And an arc-shaped connecting portion 233 that connects the second straight portion 232 to each other. In the present embodiment, two first straight portions 231 and two second straight portions 232 are provided, and four connection portions 233 are provided.
Here, the upper surface periphery 230 is an example of a second periphery, and in the present embodiment, the first straight portion 231 and the second straight portion 232 correspond to the straight portion.

Further, the lower semiconductor side surface of the lower semiconductor layer 210 includes two first lower semiconductor side surfaces 211 extending from the first linear portion 231 of the lower semiconductor upper surface 213 toward the substrate upper surface 113, as shown in FIG. , Two second lower semiconductor side surfaces 212 extending from the second linear portion 232 of the lower semiconductor upper surface 213 toward the substrate upper surface 113. Further, the lower semiconductor side surface of the lower semiconductor layer 210 extends from the connection portion 233 of the lower semiconductor upper surface 213 toward the substrate upper surface 113, and the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 adjacent to each other. Are provided with four connecting side surfaces 235. In the present embodiment, the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 correspond to the straight portion side surfaces.
Furthermore, the bottom surface periphery 240 in the lower semiconductor bottom surface 214 of the present embodiment is an example of a first periphery, and has a rectangular shape as shown in FIG.
The detailed structure of the lower semiconductor layer 210 will be described later.

Furthermore, as shown in FIGS. 1 and 2, the upper semiconductor layer 250 of the present embodiment has a substantially rectangular parallelepiped shape. Therefore, the upper semiconductor layer 250 is opposed to the upper semiconductor upper surface 253 via the four upper semiconductor side surfaces (not shown), the upper semiconductor upper surface 253 on which the p-electrode 300 is stacked, and the four upper semiconductor side surfaces. The semiconductor layer 210 has an upper semiconductor bottom surface (not shown) in contact with the lower semiconductor upper surface 213. In the present embodiment, of the four upper semiconductor side surfaces in the upper semiconductor layer 250, the two upper semiconductor side surfaces along the first direction x are referred to as first upper semiconductor side surfaces 251 and 2 along the second direction y. The two upper semiconductor side surfaces are respectively referred to as second upper semiconductor side surfaces 252. Of the two second upper semiconductor side surfaces 252, one second upper semiconductor side surface 252 has a curved portion along the semiconductor exposed surface 213a of the lower semiconductor upper surface 213.
In the present embodiment, the two first upper semiconductor side surfaces 251 and the two second upper semiconductor side surfaces 252 are provided substantially perpendicular to the lower semiconductor upper surface 213 in the lower semiconductor layer 210, respectively.

Here, in the present embodiment, the area of the upper semiconductor bottom surface in the upper semiconductor layer 250 is smaller than the area of the lower semiconductor upper surface 213 in the lower semiconductor layer 210. Accordingly, a part of the lower semiconductor upper surface 253 of the lower semiconductor layer 210 is exposed to the outside.
Although not shown in FIGS. 1 and 2, the upper semiconductor layer 250 of the present embodiment is covered with a protective film 51 (see FIG. 10 and the like described later) made of, for example, SiO ₂ or the like. . Specifically, the protective film 51 is stacked on the upper semiconductor upper surface 253, the first upper semiconductor side surface 251, and the second upper semiconductor side surface 252 of the upper semiconductor layer 250.

Next, a stacked structure of the substrate 100 and the stacked semiconductor layer 200 in the semiconductor light emitting device 1 of the present embodiment will be described.
FIG. 3 is an example of a vertical cross-sectional view of the substrate 100 and the stacked semiconductor layer 200 to which this embodiment is applied. In the present embodiment, a cross section along a direction (third direction z) perpendicular to the substrate upper surface 113 of the substrate 100 may be referred to as a vertical cross section.

As shown in FIG. 3, the substrate 100 of the present embodiment has a plurality of protrusions 113 a that protrude toward the laminated semiconductor layer 200 on a flat substrate upper surface 113. The width of each protrusion 113a is preferably 0.05 μm to 5 μm, and the height of each protrusion 113a is preferably in the range of 0.05 μm to 5 μm.
Note that the protrusion 113 a is not necessarily provided on the substrate upper surface 113 of the substrate 100, but from the viewpoint of improving the crystallinity of the stacked semiconductor layer 200 stacked on the substrate 100 and the light emission efficiency in the semiconductor light emitting device 1. Is preferably provided with a plurality of convex portions 113a on the upper surface 113 of the substrate.

As shown in FIG. 3, the stacked semiconductor layer 200 according to the present embodiment is stacked on the substrate upper surface 113 of the substrate 100 and the convex portion 113 a formed on the substrate upper surface 113.
The stacked semiconductor layer 200 according to the present embodiment includes an intermediate layer 201 stacked on the substrate 100, a base layer 202 stacked on the intermediate layer 201, and an n-type semiconductor layer stacked on the base layer 202. 203, a light emitting layer 204 laminated on the n-type semiconductor layer 203, a p-type semiconductor layer 205 laminated on the light-emitting layer 204, and a transparent conductive layer 206 laminated on the p-type semiconductor layer 205. ing.

The n-type semiconductor layer 203 includes an n-contact layer 203a stacked on the base layer 202 and an n-cladding layer 203b stacked on the n-contact layer 203a. The n contact layer 203a can also serve as the n clad layer 203b.
The p-type semiconductor layer 205 includes a p-cladding layer 205a stacked on the light emitting layer 204 and a p-contact layer 205b stacked on the p-cladding layer 205a. The p contact layer 205b can also serve as the p clad layer 205a.

  In the present embodiment, the lower semiconductor layer 210 is constituted by a part of the intermediate layer 201, the base layer 202, and the n contact layer 203a on the base layer 202 side. Further, the upper semiconductor layer 250 includes a part of the n contact layer 203a on the n clad layer 203b side, the n clad layer 203b, the light emitting layer 204, the p clad layer 205a, the p contact layer 205b, and the transparent conductive layer 206. .

Subsequently, each layer constituting the laminated semiconductor layer 200 will be described.
In the following description, AlGaN and GaInN may be described in a form in which the composition ratio of each element is omitted.
<Intermediate layer>
The intermediate layer 201 is provided to alleviate the difference in lattice constant between the substrate 100 and the base layer 202. The intermediate layer 201 is easy to form a c-axis oriented single crystal layer on the C plane ((0001) plane) of the substrate 100, particularly when the substrate 100 is composed of a sapphire single crystal having a C plane as a main surface. There is work to make. Therefore, by forming the intermediate layer 201, the crystallinity of the base layer 202 stacked thereon can be improved.

The intermediate layer 201 of the present embodiment is made of AlN. The intermediate layer 201 is made of polycrystalline Al _x Ga _1-x N (0 ≦ x ≦ 1) or single crystal Al _x Ga _1-x N (0 ≦ x ≦ 1) other than AlN. May be used.
The thickness of the intermediate layer 201 is preferably in the range of 0.01 μm to 0.5 μm. If the thickness of the intermediate layer 201 is less than 0.01 μm, the intermediate layer 201 may not sufficiently obtain an effect of relaxing the difference in lattice constant between the substrate 100 and the base layer 202. Further, if the thickness of the intermediate layer 201 exceeds 0.5 μm, the film forming process time of the intermediate layer 201 becomes longer and the productivity may be lowered, although the function as the intermediate layer 201 is not changed. There is.

<Underlayer>
As the underlayer 202, Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1) can be used.
The thickness of the underlayer 202 is preferably 0.1 μm or more, more preferably 0.5 μm or more, and most preferably 1 μm or more. By setting the thickness of the underlayer 202 to 1 μm or more, it becomes easy to obtain the underlayer 202 with good crystallinity.
In order to improve the crystallinity of the base layer 202, it is preferable that the base layer 202 is not doped with impurities. However, when p-type or n-type conductivity is required, acceptor impurities or donor impurities can be added.

  Here, as a suitable example of the intermediate layer 201 and the base layer 202, a material containing AlGaN can be used for the intermediate layer 201, and a material containing GaN and InGaN can be used for the base layer 202. Further, a dopant may be added to the intermediate layer 201 or the base layer 202. In this case, it is desirable to change the kind of dopant to be added and the doping amount between the intermediate layer 201 and the base layer 202.

<N contact layer>
The n contact layer 203 a is a layer for providing the n electrode 400.
The n contact layer 203a is preferably composed of an Al _x Ga _1-x N layer (0 ≦ x <1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1).
The n contact layer 203a is preferably doped with an n-type impurity. When an n-type impurity is contained at a concentration of 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ , preferably 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ³ , the n-type impurity can be easily obtained. It is preferable at the point which can maintain ohmic contact. Examples of the n-type impurity include Si, Ge, and Sn, and preferably Si and Ge.

  The thickness of the n contact layer 203a is preferably 0.5 μm to 5 μm, and more preferably set to a range of 1 μm to 3 μm. When the thickness of the n contact layer 203a is in the above range, the crystallinity of the light emitting layer 204 and the like is maintained well. Further, when the thickness of the n contact layer 203a is within this range, the electric resistance is lowered, which is effective in reducing the operating voltage (VF). Note that if the thickness of the n-contact layer 203a is too thick, the productivity is reduced.

<N clad layer>
The n-clad layer 203b is a layer that performs carrier injection and carrier confinement into the light-emitting layer 204.
The n-clad layer 203b can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. When the n-cladding layer 203b is formed of GaInN, it is desirable to make it larger than the GaInN band gap of the light emitting layer 204.

The n-type impurity concentration of the n-clad layer 203b is preferably 1 × 10 ¹⁷ / cm ³ to 1 × 10 ²⁰ / cm ³ , more preferably 1 × 10 ¹⁸ / cm ³ to 1 × 10 ¹⁹ / cm ³ . When the impurity concentration is within this range, it is preferable from the viewpoint of improving the light emission efficiency by maintaining good crystallinity and reducing the operating voltage of the device.
The thickness of the n-clad layer 203b is preferably 5 nm to 500 nm, more preferably 50 nm to 200 nm.

When the n clad layer 203b is a layer including a superlattice structure, the composition differs between the n-side first layer made of a group III nitride semiconductor having a thickness of 10 nm or less and the n-side first layer. In addition, a structure in which an n-side second layer made of a group III nitride semiconductor having a thickness of 10 nm or less is stacked may be included.
The n-clad layer 203b may include a structure in which n-side first layers and n-side second layers are alternately and repeatedly stacked. In this case, an alternate structure of GaInN and GaN. Alternatively, an alternate structure of GaInN having different compositions is preferable.

<Light emitting layer>
As the light emitting layer 204 laminated on the n-clad layer 203b, a single quantum well structure or a multiple quantum well structure can be adopted.
As a well layer having a quantum well structure, a group III nitride semiconductor layer made of Ga _1-y In _y N (0 <y <0.4) adjusted so as to obtain a desired emission wavelength is usually used. When the light emitting layer 204 having a multiple quantum well structure is used, the Ga _1-y In _y N is used as a well layer, and Al _z Ga _1-z N (0 ≦ z <0. 3) is a barrier layer. The well layer and the barrier layer may be doped with impurities by design or may not be doped with impurities.

<P-clad layer>
The p-cladding layer 205a is a layer that performs confinement of carriers and injection of carriers in the light-emitting layer 204.
The p clad layer 205a is not particularly limited as long as it has a composition larger than the band gap energy of the light emitting layer 204 and can confine carriers in the light emitting layer 204. For example, Al _x Ga _1-x N (0 It is desirable to use <x ≦ 0.4). When the p-clad layer 205a is made of such AlGaN, it is preferable in terms of confining carriers in the light-emitting layer 204.

The p-type impurity concentration of the p-clad layer 205a is preferably 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ / cm ³ to 1 × 10 ²⁰ / cm ³ . When the p-type impurity concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.
Further, the p-cladding layer 205a may have a superlattice structure similarly to the n-cladding layer 203b described above. In this case, a structure in which AlGaN having different composition ratios and other AlGaN are alternately stacked or a structure in which AlGaN and GaN having different compositions are alternately stacked is preferable.
The thickness of the p-cladding layer 205a is not particularly limited, but is preferably 1 nm to 400 nm, more preferably 5 nm to 100 nm.

<P contact layer>
The p contact layer 205 b is a layer for providing the p electrode 300 through the transparent conductive layer 206. The p contact layer 205b is preferably made of Al _x Ga _1-x N (0 ≦ x ≦ 0.4). When the Al composition is in the above range, it is preferable in that good crystallinity and good ohmic contact with the p-electrode 300 can be maintained.
The p-type impurity concentration of the p-contact layer 205b is preferably 1 × 10 ¹⁸ / cm ³ to 1 × 10 ²¹ / cm ³ , more preferably 5 × 10 ¹⁹ / cm ^{3 to} 5 × 10 ²⁰ / cm ³ . A p-type impurity concentration in the above range is preferable in that good ohmic contact and good crystallinity can be maintained. Although it does not specifically limit as a p-type impurity, For example, Mg etc. are mentioned.
The thickness of the p contact layer 205b is not particularly limited, but is preferably 10 nm to 500 nm, and more preferably 50 nm to 200 nm. When the thickness of the p-contact layer 205b is in the above range, it is preferable in terms of light emission output and operating voltage.

<Transparent conductive layer>
The transparent conductive layer 206 preferably has a small contact resistance with the p-type semiconductor layer 205 (p contact layer 205b). Further, in the semiconductor light emitting device 1 of the present embodiment, since the light output from the light emitting layer 204 is taken out to the side where the p electrode 300 is formed, the transparent conductive layer 206 corresponds to the light output from the light emitting layer 204. It is preferable that it is excellent in permeability. Furthermore, it is preferable that the transparent conductive layer 206 has excellent conductivity in order to diffuse current uniformly over the entire surface of the p-type semiconductor layer 205.

From the above, as a material constituting the transparent conductive layer 206, for example, it is preferable to use a light-transmitting conductive material made of a conductive oxide containing at least In. As the conductive oxide containing In, for example, ITO (indium tin oxide (In ₂ O ₃ —SnO ₂ )), IZO (indium zinc oxide (In ₂ O ₃ —ZnO)), IGO (indium gallium oxide (In ₂ O ₃ —Ga ₂ O ₃ )), ICO (indium cerium oxide (In ₂ O ₃ —CeO ₂ )) and the like. In these, impurities such as fluorine may be added.
The thickness of the transparent conductive layer 206 is not particularly limited, but is preferably in the range of 10 nm to 500 nm, for example.

(Description of detailed structure of lower semiconductor layer)
Next, the detailed structure of the lower semiconductor layer 210 in the semiconductor light emitting device 1 of the present embodiment will be described.
FIG. 4 is an example of a longitudinal sectional view of the semiconductor light emitting element 1 to which the present exemplary embodiment is applied. 4A is a cross-sectional view taken along the line IVA-IVA in FIG. 2, and FIG. 4B is a cross-sectional view taken along the line IVB-IVB in FIG.

As shown in FIG. 4A and FIG. 1, the first lower semiconductor side surface 211 of the lower semiconductor layer 210 is a first vertical extending from the first linear portion 231 of the lower semiconductor upper surface 213 toward the substrate 100 side. A surface 211a and a first inclined surface 211b that is inclined with respect to the first vertical surface 211a and extends from the lower end of the first vertical surface 211a toward the substrate upper surface 113 in an inward direction of the lower semiconductor layer 210. Have.
In the present embodiment, the first vertical surface 211a is provided along the third direction z, and the angle formed by the first vertical surface 211a and the first inclined surface 211b is an obtuse angle. Yes.

As shown in FIG. 4A, if the angle formed by the lower semiconductor upper surface 213 and the first vertical surface 211a of the first lower semiconductor side surface 211 is θ1a, θ1a is approximately 90 in this embodiment. °.
Furthermore, if the angle formed by the lower semiconductor bottom surface 214 and the first inclined surface 211b of the first lower semiconductor side surface 211 is θ1b, θ1b is an obtuse angle (θ1b> 90 °). That is, the first inclined surface 211 b is provided to be inclined with respect to a plane perpendicular to the substrate upper surface 113.

As shown in FIG. 4B and FIG. 1, the second lower semiconductor side surface 212 of the lower semiconductor layer 210 is a second vertical extending from the second linear portion 232 of the lower semiconductor upper surface 213 toward the substrate 100 side. A second inclined surface 212b that is inclined with respect to the second vertical surface 212a and extends inwardly from the lower end of the second vertical surface 212a toward the upper surface 113 of the substrate toward the lower semiconductor layer 210. Have.
In the present embodiment, the second vertical surface 212a is provided along the third direction z, and the angle formed by the second vertical surface 212a and the second inclined surface 212b is an obtuse angle. Yes.

As shown in FIG. 4B, when the angle formed between the lower semiconductor upper surface 213 and the second vertical surface 212a of the second lower semiconductor side surface 212 is θ2a, θ2a is approximately 90 in the present embodiment. °.
Furthermore, if the angle formed by the lower semiconductor bottom surface 214 and the second inclined surface 212b of the second lower semiconductor side surface 212 is θ2b, θ2b is an obtuse angle (θ2b> 90 °). That is, the second inclined surface 212 b is provided to be inclined with respect to a plane perpendicular to the substrate upper surface 113.

  Here, in the lower semiconductor layer 210 of the present embodiment, the first lower semiconductor side surface 211 has the first vertical surface 211a, and the second lower semiconductor side surface 212 has the second vertical surface 212a. As shown in FIGS. 4A and 4B, the first straight portion 231 and the second straight portion 232 (see also FIG. 1) of the upper surface periphery 230 have a thickness.

Next, the configuration of the connection part 233 and the connection side surface 235 in the lower semiconductor layer 210 will be described. 5 is a cross-sectional view taken along the line VV in FIG. 2, and is a vertical cross-sectional view of the semiconductor light emitting element 1 cut so as to pass through the connection portion 233 and the connection side surface 235. FIG. 6 is a diagram for explaining the structure in the vicinity of the connection portion 233 and the connection side surface 235 of the lower semiconductor layer 210 to which the present embodiment is applied. FIG. FIG. 6B is a view of the lower semiconductor layer 210 in FIG. 6A viewed from the VIB direction.
In FIG. 6B, illustration of the substrate 100 and the upper semiconductor layer 250 is omitted.

As shown in FIGS. 5 and 6A, the connection side surface 235 of the lower semiconductor layer 210 extends forwardly from the connection portion 233 toward the substrate 100 and extends outwardly from the lower semiconductor layer 210. It has a surface 235a and an inversely inclined surface 235b extending inclining inward of the lower semiconductor layer 210 from the lower end of the forward inclined surface 235a toward the substrate upper surface 113.
In other words, the connection side surface 235 extends from the substrate upper surface 113 to the upper side of the lower semiconductor layer 210 and outwardly, and from the upper end of the reverse inclined surface 235b to the upper side and lower side of the lower semiconductor layer 210. And a forward inclined surface 235a that rises. In the present embodiment, the reverse inclined surface 235b corresponds to the outward inclined surface, and the forward inclined surface 235a corresponds to the inward inclined surface.
As shown in FIG. 6A, the connection side surface 235 is a boundary between the forward inclined surface 235 a and the reverse inclined surface 235 b and protrudes outward from the lower semiconductor layer 210. Is formed.
In the semiconductor light emitting device 1 according to the present embodiment, a mask 55 (shown later) is stacked near the connection portion 233 in the lower semiconductor layer 210 on the lower semiconductor layer 210 in the manufacturing process of the semiconductor light emitting device 1 described later. 9) may remain and adhere.

  As shown in FIG. 1, the forward inclined surface 235 a connects the first vertical surface 211 a on the first lower semiconductor side surface 211 and the second vertical surface 212 a on the second lower semiconductor side surface 212. Similarly, the reverse inclined surface 235 b connects the first inclined surface 211 b on the first lower semiconductor side surface 211 and the second inclined surface 212 b on the second lower semiconductor side surface 212.

Here, as shown in FIG. 6A, when the angle formed between the lower semiconductor upper surface 213 and the forward inclined surface 235a of the connection side surface 235 is θ3a, in this embodiment, θ3a is an obtuse angle ( θ3a> 90 °).
When the angle formed by the lower semiconductor bottom surface 214 and the reverse inclined surface 235b of the connection side surface 235 is θ3b, θ3b is an obtuse angle (θ3b> 90 °).
Furthermore, θ3c is an obtuse angle (θ3c> 90 °) where θ3c is an angle formed by the forward inclined surface 235a and the reverse inclined surface 235b in the connection side surface 235.

Further, as described above, the connection portion 233 of the lower semiconductor upper surface 213 has an arc shape when viewed from the third direction z. Furthermore, the boundary portion 235c of the connection side surface 235 has an arc shape when viewed from the third direction z.
As shown in FIG. 6B, the connection part 233 and the boundary part 235c have an extension line of the first straight part 231 and an extension line of the second straight part 232 when viewed from the third direction z. It is located inside the intersecting intersection. Thereby, the connection part 233 and the boundary part 235c are the extension line of the 1st straight line part 231 and the 1st straight line part 231, and the 2nd straight line part 232 and the 2nd straight line part when it sees along the 3rd direction z. It is located inside the rectangle surrounded by the extension line of 232 (see also FIG. 2).

Further, as described above, the forward inclined surface 235 a is provided to be inclined from the connection portion 233 toward the outside of the lower semiconductor layer 210. On the other hand, the reverse inclined surface 235b is provided to be inclined from the lower end of the forward inclined surface 235a toward the inside of the lower semiconductor layer 210.
Accordingly, when the connection side surface 235 is viewed from the third direction z, as shown in FIG. 6B, the connection portion 233 is located on the inner side of the boundary portion 235c. When the connection side surface 235 is viewed from the third direction z, only the forward inclined surface 235a and the boundary portion 235c on the connection side surface 235 can be visually recognized, and the reverse inclined surface 235b cannot be visually recognized.

Here, conventionally, in the semiconductor light emitting device 1 having the structure in which the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 of the lower semiconductor layer 210 are inclined with respect to the direction perpendicular to the substrate upper surface 113, There was a tendency for the lower semiconductor layer 210 and the like to break easily. In FIGS. 6A and 6B, an example of the outer edge of the lower semiconductor layer 210 in the conventional semiconductor light emitting device 1 having such an inclined structure is indicated by a broken line.
In the conventional semiconductor light emitting device 1 having the structure in which the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212 are inclined with respect to the direction perpendicular to the substrate upper surface 113, the lower semiconductor upper surface 213 in the lower semiconductor layer 210. Has a substantially rectangular shape. That is, the lower semiconductor upper surface 213 in the conventional semiconductor light emitting device 1 does not have the connection portion 233 as shown by a broken line in FIG. 6B, and the first straight portion 231 and the second straight portion 232. Is crossing. That is, in the conventional semiconductor light emitting device 1, the lower semiconductor upper surface 213, the first lower semiconductor side surface 211, and the second lower semiconductor side surface 212 are directly connected, and the lower semiconductor upper surface 213 and the first lower side are connected. At the boundary between the semiconductor side surface 211 and the second lower semiconductor side surface 212, a sharp corner (hereinafter referred to as a pointed portion) is formed toward the outside of the lower semiconductor layer 210.

  The side surfaces of the lower semiconductor layer 210 (the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212) are inclined with respect to a plane perpendicular to the lower semiconductor upper surface 213 and the lower semiconductor bottom surface 214. Therefore, at the pointed portion located at the boundary between the lower semiconductor upper surface 213, the first lower semiconductor side surface 211, and the second lower semiconductor side surface 212, as shown by the broken line in FIG. The thickness decreases from the center of the side semiconductor layer 210 toward the outside. Thereby, in the conventional semiconductor light emitting device 1, the strength of the pointed portion of the lower semiconductor layer 210 is lower than that of other regions.

Further, in the conventional semiconductor light emitting device 1, the pointed portion of the lower semiconductor layer 210 protrudes as compared with other portions. For example, when the semiconductor light emitting device 1 is manufactured or the semiconductor light emitting device 1 is applied to a lamp. During the operation, the tip of the lower semiconductor layer 210 is likely to collide with other members.
Here, generally, in a member having a pointed shape, when an external force is applied to the pointed portion, the force is difficult to disperse and the force tends to concentrate on the pointed portion. For example, in the conventional semiconductor light emitting device 1, when the lower semiconductor layer 210 hits another member or the like and a force is applied to the lower semiconductor layer 210 from the outside, the force is applied to the lower semiconductor layer 210. It is easy to concentrate on the tip.
In the conventional semiconductor light emitting device 1, since the tip of the lower semiconductor layer 210 is thin as described above, the lower semiconductor layer 210 is chipped at the tip when an external force is concentrated. There is a concern that it will be easier.

On the other hand, in the semiconductor light emitting device 1 of the present embodiment, the connection portion 233 is provided between the first straight portion 231 and the second straight portion 232 at the upper surface periphery 230 (see FIG. 2) of the lower semiconductor upper surface 213. Is formed. Furthermore, in the semiconductor light emitting device 1 of the present embodiment, the connection side surface having the forward inclined surface 235a, the reverse inclined surface 235b, and the boundary portion 235c between the first lower semiconductor side surface 211 and the second lower semiconductor side surface 212. 235 is formed. The connection part 233 and the boundary part 235c are located inside the intersection of the extension line of the first straight part 231 and the extension line of the second straight part 232 when viewed from the third direction z.
That is, in the semiconductor light emitting device 1 of the present embodiment, in the lower semiconductor layer 210, the lower semiconductor upper surface 213, the first lower semiconductor side surface 211, and the second lower semiconductor side surface 212 do not cross each other directly. The pointed portion as in the semiconductor light emitting device 1 is not formed. In the semiconductor light emitting device 1 according to the present embodiment, compared to the conventional semiconductor light emitting device 1, the boundary between the lower semiconductor upper surface 213, the first lower semiconductor side surface 211, and the second lower semiconductor side surface 212 is used. The protruding amount of the lower semiconductor layer 210 is small.

  Thereby, in the semiconductor light emitting device 1 of the present embodiment, the lower semiconductor layer 210 can be prevented from colliding with another semiconductor light emitting device 1 or another member. In the semiconductor light emitting device 1 of the present embodiment, the lower semiconductor layer 210 is prevented from colliding with other members and the like, so that the stacked semiconductor layer 200 (lower side) is compared with the case where this configuration is not adopted. Generation of cracks and chips in the semiconductor layer 210) can be suppressed.

In the semiconductor light emitting device 1 of the present embodiment, the angle θ3a formed by the lower semiconductor upper surface 213 and the forward inclined surface 235a and the angle θ3c formed by the forward inclined surface 235a and the reverse inclined surface 235b are obtuse angles. Thus, when the lower semiconductor layer 210 is viewed from the direction perpendicular to the lower semiconductor upper surface 213 (third direction z), the connection portion 233 is located on the inner side of the lower semiconductor layer 210 than the boundary portion 235c in the connection side surface 235. Is located.
Thereby, in the semiconductor light emitting element 1 according to the present embodiment, the connection portion 233 collides with other members and the like as compared with the case where the connection portion 233 is positioned outside the lower semiconductor layer 210 with respect to the boundary portion 235c. Can be further suppressed. As a result, it is possible to further suppress the occurrence of cracking and chipping of the laminated semiconductor layer 200 (lower semiconductor layer 210) as compared with the case where this configuration is not adopted.

Furthermore, in the semiconductor light emitting device 1 of the present embodiment, the connection part 233 and the boundary part 235c in the lower semiconductor layer 210 have an arc shape when viewed from the third direction z. That is, the connection part 233 and the boundary part 235c have a shape in which force is easily dispersed as compared with a case where the connection part 233 and the boundary part 235c have a sharp shape.
Thereby, in this Embodiment, even if it is a case where force is applied from the exterior to the connection part 233 or the boundary part 235c, compared with the case where this structure is not employ | adopted, the connection part 233 or the boundary part 235c, for example. It is possible to suppress the concentration of power on the screen. As a result, in the semiconductor light emitting device 1 according to the present embodiment, another semiconductor light emitting device 1 or another member collides with the connection portion 233 or the boundary portion 235c of the lower semiconductor layer 210. In addition, it is possible to suppress the occurrence of cracking and chipping of the laminated semiconductor layer 200 (lower semiconductor layer 210) as compared with the case where this configuration is not adopted.

Furthermore, in the semiconductor light emitting device 1 of the present embodiment, as described above, the first lower semiconductor side surface 211 has the first vertical surface 211a and the first inclined surface 211b, and the second lower semiconductor side surface 212. Has a second vertical surface 212a and a second inclined surface 212b.
Thereby, in the semiconductor light emitting device 1 of the present embodiment, for example, the first lower semiconductor side surface 211 does not have the first vertical surface 211a, and the first inclined surface 211b and the lower semiconductor upper surface 213 are directly connected. Compared to the case where the second lower semiconductor side surface 212 does not have the second vertical surface 212a and the second inclined surface 212b is directly connected to the lower semiconductor upper surface 213, the first linear portion 231 is used. In addition, the thickness of the lower semiconductor layer 210 in the second linear portion 232 is increased.
As a result, in the semiconductor light emitting device 1 of the present embodiment, it is possible to increase the strength of the lower semiconductor layer 210 in the vicinity of the first straight line portion 231 and the second straight line portion 232 as compared with the case where this configuration is not adopted. Thus, it is possible to further suppress the occurrence of cracks and chips in the lower semiconductor layer 210.

In the present embodiment, the shape of the connection portion 233 when viewed from the third direction z is an arc shape, but the shape of the connection portion 233 is not limited to this. As described above, if the connection part 233 is located inside the intersection of the extension line of the first straight line part 231 and the extension line of the second straight line part 232, the connection part 233 viewed from the third direction z will be described. The shape may be, for example, a linear shape, a curved shape, a polygonal line shape, or a combination thereof.
Similarly, the shape of the boundary portion 235c viewed from the third direction z is not limited to the arc shape, and may be, for example, a linear shape, a curved shape, a polygonal line shape, or a combination thereof.
In addition, the first straight portion 231 and the second straight portion 232 described above do not have to be strictly perfectly straight, and even if a part that is bent or uneven is formed as a whole, Any form that can approximate a straight line is acceptable.

In the present embodiment, the semiconductor light emitting element 1 has a substantially rectangular parallelepiped shape, and the semiconductor light emitting element 1 is substantially rectangular when viewed from the side where the p electrode 300 and the n electrode 400 are formed. Although demonstrated, the shape of the semiconductor light-emitting device 1 is not restricted to this.
For example, if the lower semiconductor layer 210 has the connection part 233 and the connection side surface 235 as described above, the shape of the semiconductor light emitting element 1 viewed from the side where the p electrode 300 and the n electrode 400 are formed is a square or It may be a shape approximated to a parallelogram, or may be a shape approximated to a polygon other than a quadrangle (such as a triangle or a hexagon).

(Manufacturing method of semiconductor light emitting device)
Then, the manufacturing method of the semiconductor light-emitting device 1 of this Embodiment is demonstrated. In the present embodiment, the laminated semiconductor layer 200 is laminated on the wafer-like substrate 100, and a plurality of p-electrodes 300, n-electrodes 400, and the like are formed on the laminated semiconductor layer 200, and are divided into a plurality of pieces. Thus, a plurality of semiconductor light emitting elements 1 are obtained. FIG. 7 is a flowchart showing an example of a method for manufacturing the semiconductor light emitting device 1 to which the present exemplary embodiment is applied.

In this example, first, a semiconductor lamination process is performed in which a laminated semiconductor layer 200 is laminated on a wafer-like substrate 100 to form a wafer-like semiconductor laminated substrate 20 (see FIG. 8 described later) (step 101).
Next, a plurality of first groove portions 71 and a plurality of second groove portions 72 (both will be described later with reference to FIG. 8) by removing a part of the stacked semiconductor layer 200 from the semiconductor stacked substrate 20 formed in step 101. ) And a semiconductor removal step of forming a plurality of p-electrodes 300 and a plurality of n-electrodes 400 on the stacked semiconductor layer 200 (step 102).
Subsequently, with respect to the semiconductor multilayer substrate 20 in which the plurality of first groove portions 71 and the plurality of second groove portions 72 are formed in Step 102, the stacked semiconductor layer 200 surrounded by the first groove portions 71 and the second groove portions 72. A film forming step of forming a protective film 51 (see FIG. 9 described later) on the upper surface and forming a mask 55 at an intersection 73 (see FIGS. 8 and 9) where the first groove 71 and the second groove 72 intersect. Is executed (step 103).

Next, with respect to the semiconductor laminated substrate 20 on which the protective film 51 and the mask 55 are formed in Step 103, the first direction x and the second direction from the surface side of the semiconductor laminated substrate 20 on which the protective film 51 and the mask 55 are formed. A surface laser process is performed to form a first irradiation line 81 and a second irradiation line 82 (both refer to FIG. 10 described later) by irradiating laser light along the direction y (step 104).
Subsequently, a wet etching process is performed in which wet etching is performed on the semiconductor laminated substrate 20 on which the first irradiation line 81 and the second irradiation line 82 are formed in Step 104 (Step 105).
Next, the semiconductor multilayer substrate 20 that has been wet-etched in Step 105 is divided along the first irradiation line 81 and the second irradiation line 82, thereby dividing the plurality of semiconductor light emitting elements 1 (FIG. 1). (See step 106) is performed (step 106).
In the present embodiment, the film forming process in step 103 corresponds to the covering portion forming process and the altered region forming process, and the surface laser process in step 104 corresponds to the divided groove forming process.

Then, the process of each step mentioned above is demonstrated in order.
(Semiconductor lamination process)
In the semiconductor lamination process of step 101, first, a wafer-like substrate 100 (see FIG. 1) made of a sapphire single crystal having a C-plane as a main surface is prepared, and surface processing is performed. As the surface processing, for example, wet etching, dry etching, sputtering, or the like is used to form a plurality of convex portions 113a (see FIG. 3) on the substrate upper surface 113 (see FIG. 1) of the wafer-like substrate 100. .

  Next, an intermediate layer 201 (see FIG. 3) made of AlN is formed on the wafer-like substrate 100 subjected to surface processing by sputtering or the like. Note that the intermediate layer 201 can be formed not only by sputtering but also by MOCVD.

Subsequently, with respect to the wafer-like substrate 100 on which the intermediate layer 201 is formed, a base layer 202 made of group III nitride, an n-type semiconductor layer 203 (n-contact layer 203a, n-cladding layer 203b), light-emitting layer 204, p Type semiconductor layer 205 (p-cladding layer 205a, p-contact layer 205b) and transparent conductive layer 206 are laminated in this order, and semiconductor laminated substrate 20 in which laminated semiconductor layer 200 is laminated on wafer-like substrate 100 (see FIG. 8 described later). ) (See FIG. 3).
As a method for laminating these layers, methods such as MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy), and sputtering can be used. it can. A particularly preferable lamination method is MOCVD from the viewpoint of film thickness controllability and mass productivity.

Here, in the present embodiment, a plurality of convex portions 113 a are formed on the substrate upper surface 113 of the substrate 100. When the intermediate layer 201 made of AlN, the base layer 202 made of a group III nitride semiconductor layer such as GaN, the n-contact layer 203a, and the like are laminated on the substrate upper surface 113 of the substrate 100, first, the substrate is perpendicular to the substrate upper surface 113. A plurality of island-like crystals extending in a certain direction are formed. When the lamination is further continued, the group III nitride grows in a direction perpendicular to the substrate upper surface 113, and a plurality of island-like crystals are connected to each other, so that a flat crystal growth surface is obtained.
Therefore, the intermediate layer 201, the base layer 202, the n contact layer 203a, and the like in the lower semiconductor layer 210 of this embodiment are gradually increased from the lower semiconductor bottom surface 214 side to the lower semiconductor upper surface 213 side. It is formed so that the crystallinity of the group nitride is improved.
As a result, the lower semiconductor layer 210 as a whole is formed so that the crystallinity of the group III nitride gradually improves from the lower semiconductor bottom surface 214 side toward the lower semiconductor upper surface 213 side.

  Further, in the present embodiment, when the laminated semiconductor layer 200 is laminated on the substrate 100 made of sapphire by the MOCVD method, the group III nitride constituting the laminated semiconductor layer 200 is an N-polar plane (000− 1) The crystal faces so that the surface faces the substrate upper surface 113 side of the substrate 100 and the (0001) surface, which is a group III element polar surface (for example, Ga polar surface), faces the upper semiconductor upper surface 253 side of the upper semiconductor layer 250. grow up.

(Semiconductor removal process)
Next, the semiconductor removal process in step 102 will be described.
FIG. 8 is a view showing the semiconductor multilayer substrate 20 after the first groove portion 71, the second groove portion 72, the p-electrode 300, and the n-electrode 400 are formed, which is obtained by executing the semiconductor removal process of step 102. FIG. 8A is a top view of the semiconductor multilayer substrate 20 after the first groove 71, the second groove 72, the p electrode 300 and the n electrode 400 are formed, as viewed from the side where the p electrode 300 and the n electrode 400 are formed. FIG. 8B is a sectional view taken along line VIIIB-VIIIB in FIG.

In the semiconductor removal process of step 102, first, a part of the stacked semiconductor layer 200 in the semiconductor stacked substrate 20 obtained in the semiconductor stacking process of step 101 is locally removed from the side opposite to the substrate 100, so that n A part of the contact layer 203a (see FIG. 3) is exposed. Thereby, the 1st groove part 71, the 2nd groove part 72, and the semiconductor exposed surface 213a are formed.
In the present embodiment, the first groove 71 and the second groove 72 correspond to the groove.

As shown in FIG. 8A, a plurality of first groove portions 71 are formed, and each is provided along the first direction x. The respective first groove portions 71 are arranged substantially parallel to each other so that the distances between the adjacent first groove portions 71 are equal. Similarly, a plurality of second groove portions 72 are formed, and each is provided along the second direction y. The respective second groove portions 72 are arranged substantially parallel to each other so that the distance between the adjacent second groove portions 72 is equal.
Furthermore, as shown in FIG. 8A, a plurality of semiconductor exposed surfaces 213a are formed. In this example, the plurality of exposed semiconductor surfaces 213 a are arranged side by side along the second direction y, and each of them is connected to the second groove portion 72.

  As shown in FIGS. 8A and 8B, the plurality of first groove portions 71 and the plurality of second groove portions 72 are formed, so that the stacked semiconductor layer 200 is provided over the entire area of the substrate upper surface 113. A lower semiconductor layer 210 and an upper semiconductor layer 250 provided on the lower semiconductor layer 210 and separated into a plurality of regions by the plurality of first groove portions 71 and the plurality of second groove portions 72 are formed.

Here, in the present embodiment, the interval between the adjacent first groove portions 71 is narrower than the interval between the adjacent second groove portions 72. As a result, as shown in FIG. 8A, the shape of each upper semiconductor layer 250 separated into a plurality of regions when viewed from the direction perpendicular to the substrate upper surface 113 (third direction z) is the first direction x. Is a rectangle having a long side along the second direction and a short side along the second direction y.
In this example, the interval between adjacent first groove portions 71 is 270 μm, and the interval between adjacent second groove portions 72 is 700 μm. Moreover, in this Embodiment, the width | variety of each 1st groove part 71 and each 2nd groove part 72 is 20 micrometers. That is, each upper semiconductor layer 250 separated into a plurality of regions has a rectangular shape with a short side of 250 μm and a long side of 680 μm when viewed from the third direction z.

As a method for removing a part of the laminated semiconductor layer 200 in order to form the first groove 71, the second groove 72, and the semiconductor exposed surface 213a, a known photolithography technique and a known etching technique can be used. In particular, as a means for forming the first groove 71, the second groove 72, and the semiconductor exposed surface 213a, it is preferable to use an etching method such as wet etching or dry etching. This is because the etching method is less likely to damage a portion of the stacked semiconductor layer 200 that is not removed as compared with other methods.
As an etching method, for example, dry etching, a reactive ion etching, ion milling, focused beam etching, ECR etching, or the like can be used. For wet etching, for example, sulfuric acid and phosphoric acid are used. Mixed acids can be used. However, before etching, a predetermined resist or the like is formed on the surface of the laminated semiconductor layer 200 so as to obtain a desired chip shape.

As a method for forming the first groove portion 71 and the second groove portion 72, a known method such as a dicing method or a laser irradiation method can be used without any limitation other than the etching method.
In the present embodiment, the semiconductor exposed surface 213a is formed simultaneously with the formation of the first groove portion 71 and the second groove portion 72, but these may be formed in separate steps.

In the semiconductor removal step of step 102, subsequently, the p-electrode 300 is formed at a predetermined position on each upper semiconductor layer 250, and the n-electrode 400 is formed on each semiconductor exposed surface 213a.
As the p-electrode 300 and the n-electrode 400, various compositions and structures are known, and these known compositions and structures can be used without any limitation.
As a means for forming the p-electrode 300 and the n-electrode 400, a known method such as a vacuum deposition method or a sputtering method can be used without any limitation.

(Film formation process)
Then, the film formation process of step 103 is demonstrated.
FIG. 9 is a view showing the semiconductor laminated substrate 20 after the formation of the mask 55 and the protective film 51, which is obtained by executing the film forming process of Step 103. As shown in FIG. FIG. 9A is a top view of a part of the semiconductor laminated substrate 20 (see FIG. 8) after forming the mask 55 and the protective film 51 as viewed from the side on which the mask 55 and the protective film 51 are formed. 9B is a cross-sectional view taken along the line IXB-IXB in FIG. 9A, FIG. 9C is a cross-sectional view taken along the line IXC-IXC in FIG. 9A, and FIG. FIG. 10 is a cross-sectional view taken along IXD-IXD in FIG.

In the film forming process in step 103, a mask 55 as an example of the covering part and other covering parts are formed in a part of the region on the laminated semiconductor layer 200 of the semiconductor laminated substrate 20 obtained in the semiconductor removing process in step 102. As an example, the protective film 51 is formed.
As shown in FIGS. 9A and 9B, the mask 55 is provided at an intersection 73 where the first groove 71 and the second groove 72 intersect.
In the present embodiment, each mask 55 has a circular shape when viewed from the third direction z. The diameter of each mask 55 is, for example, 12 μm. The shape and size of the mask 55 are not limited to this. The shape and size of the mask 55 will be described later. In this example, the thickness of the mask 55 is 87 nm. The thickness of the mask 55 is preferably in the range of 2 nm to 5 μm, for example, and more preferably in the range of 10 nm to 1 μm.

Further, as shown in FIGS. 9A to 9D, the protective film 51 is formed except for a part of the region on the p-electrode 300 and a part of the region on the n-electrode 400 (opening; not shown). The upper semiconductor layer 250 is provided so as to cover substantially the entire surface. Specifically, as illustrated in FIGS. 9B to 9D, the protective film 51 includes an upper surface (upper semiconductor upper surface 253; see FIG. 1) and side surfaces (first upper semiconductor side surfaces 251, The second upper semiconductor side surface 252 (see FIG. 1) is provided. Further, as shown in FIG. 9A, the shape of the protective film 51 viewed from the third direction z is a rectangular shape that follows the shape of the upper semiconductor layer 250.
In this example, the interval between adjacent protective films 51 is 14 μm.
In the present embodiment, each mask 55 and protective film 51 are not connected to each other and are provided independently of each other.

The mask 55 is used to adjust the shape, thickness, and the like of the laminated semiconductor layer 200 (lower semiconductor layer 210) that is removed by the wet etching process in a wet etching process in step 105 described later.
Here, by forming the mask 55 at the intersecting portion 73 in the film forming process of step 103, the lower semiconductor layer 210 at the intersecting portion 73 where the mask 55 is laminated is altered. As a result, an altered region 210a (see FIG. 14 described later) in which the lower semiconductor layer 210 is altered is formed at the intersection 73.
As the mask 55, a material that can modify the lower semiconductor layer 210 to form the altered region 210a is used. In the present embodiment, SiO ₂ is used as the mask 55. However, the material constituting the mask 55 is not limited to this, and a metal thin film or the like may be used, for example.

The protective film 51 is provided to protect the upper semiconductor layer 250.
As the protective film 51, an insulating material is used. Further, when manufacturing a so-called face-up type semiconductor light emitting device 1 as the semiconductor light emitting device 1, a material having transparency to the light output from the light emitting layer 204 (see FIG. 3) is used as the protective film 51. Is preferred. In the present embodiment, SiO ₂ is used as the protective film 51 in the same manner as the mask 55.
By configuring the mask 55 and the protective film 51 with the same material, the mask 55 and the protective film 51 can be formed in the same process. Compared with the case where this configuration is not adopted, the semiconductor light emitting device 1 The manufacturing process can be simplified.

As a method for forming the mask 55 and the protective film 51, a conventionally known CVD method, vapor deposition method, sputtering method or the like can be used.
Specifically, after forming SiO ₂ on the entire surface of the laminated semiconductor layer 200 of the semiconductor laminated substrate 20, a resist pattern is formed on the SiO ₂ by a conventionally known photolithography method, and a conventionally known etching method or the like is performed. By removing the portion of SiO ₂ that is not covered with the resist, the mask 55 and the protective film 51 having the above-described shape can be formed.
In addition, the formation method of the mask 55 and the protective film 51 is not restricted to this, A conventionally well-known method can be used suitably.

(Surface laser process)
Next, the surface laser process in step 104 will be described.
FIG. 10 is a view showing the semiconductor laminated substrate 20 after the first irradiation line 81 and the second irradiation line 82 are formed, which is obtained by executing the surface laser process of Step 104. In FIG. 10A, the first irradiation line 81 and the second irradiation line 82 are formed on a part of the semiconductor laminated substrate 20 (see FIG. 8) after the first irradiation line 81 and the second irradiation line 82 are formed. It is the top view seen from the side. 10B is a cross-sectional view taken along the line XB-XB in FIG. 10A, FIG. 10C is a cross-sectional view taken along the line XC-XC in FIG. 10A, and FIG. It is XD-XD sectional drawing of Fig.10 (a).

In the surface laser process of step 104, the semiconductor laminated substrate 20 is irradiated with laser light from the laminated semiconductor layer 200 side along the first groove 71 and the second groove 72 formed in the semiconductor removal process of step 102. The plurality of first irradiation lines 81 and the plurality of second irradiation lines 82 are formed by removing part of the laminated semiconductor layer 200 until reaching the substrate 100.
In the present embodiment, the first irradiation line 81 and the second irradiation line 82 correspond to the division grooves.

As shown in FIG. 10A, a plurality of first irradiation lines 81 are formed along the first groove 71 and along the first direction x. Each first irradiation line 81 is formed so as to separate the stacked semiconductor layer 200 (lower semiconductor layer 210) as shown in FIG. 10D, and reaches the inside of the substrate 100. Yes.
Similarly, as shown in FIG. 10A, a plurality of second irradiation lines 82 are formed along the second groove 72 and along the second direction y. Each second irradiation line 82 is formed so as to separate the laminated semiconductor layer 200 as shown in FIG. 10C and reaches the inside of the substrate 100.
Thereby, the lower semiconductor layer 210 is separated by a plurality of first irradiation lines 81 and a plurality of second irradiation lines 82 into a plurality of regions each having a rectangular shape when viewed from the third direction z.

Further, as described above, the mask 55 is provided at the intersection 73 where the first groove 71 and the second groove 72 intersect, and the first irradiation line 81 and the second irradiation line 82 correspond to the mask 55. At the intersection. Then, as shown in FIGS. 10A and 10B, the mask 55 is separated into a plurality (four in this example) of regions by the first irradiation line 81 and the second irradiation line 82. Along with this, a plurality of alteration regions 210a (see FIG. 14) formed below the mask 55 at the intersection 73 are also formed by the first irradiation line 81 and the second irradiation line 82 (four in this example). Separated into regions.
As shown in FIG. 10A, the masks 55 separated into a plurality of regions are positioned at the four corners of each lower semiconductor layer 210 separated into a plurality of regions having a rectangular shape.

(Wet etching process)
Next, the wet etching process in step 105 will be described.
FIG. 11 is a view showing the semiconductor laminated substrate 20 obtained by performing the wet etching process of Step 105. FIG. 11A is a top view of a part of the semiconductor laminated substrate 20 (see FIG. 8) after the wet etching is viewed from the side on which the protective film 51 is formed. 11 (b) is a cross-sectional view taken along the line XIB-XIB in FIG. 11 (a), FIG. 11 (c) is a cross-sectional view taken along the line XIC-XIC in FIG. 11 (a), and FIG. FIG. 11 is a cross-sectional view of XID-XID in FIG.

  In the wet etching process of step 105, the semiconductor substrate 20 on which the first irradiation line 81 and the second irradiation line 82 are formed in the surface laser process of step 104 is wet-etched, so that the first vertical surface 211a and the first inclined surface are formed. A first lower semiconductor side surface 211 having a surface 211b, a second lower semiconductor side surface 212 having a second vertical surface 212a and a second inclined surface 212b, and a forward inclined surface 235a, a reverse inclined surface 235b, and a boundary portion 235c. A connection side surface 235 is formed.

The wet etching is performed by immersing the semiconductor laminated substrate 20 on which the first irradiation line 81 and the second irradiation line 82 are formed in an etching solution such as orthophosphoric acid heated to a predetermined temperature.
When the semiconductor laminated substrate 20 on which the first irradiation line 81 and the second irradiation line 82 are formed is immersed in an etching solution, the etching solution enters the first irradiation line 81 and the second irradiation line 82. In the first irradiation line 81 and the second irradiation line 82, the lower semiconductor layer 210 is exposed. Therefore, the exposed lower semiconductor layer 210 is eroded by the etchant that has entered the first irradiation line 81 and the second irradiation line 82. On the other hand, the upper semiconductor layer 250 covered with the protective film 51 is not eroded by the etchant.

  Here, in the present embodiment, the lower semiconductor layer 210 includes a side facing the upper semiconductor layer 250 (lower semiconductor upper surface 213 side) and a side facing the substrate 100 (lower semiconductor bottom surface 214 side). The ease of erosion by the etching solution is different. Specifically, compared to the lower semiconductor upper surface 213 side of the lower semiconductor layer 210, the lower semiconductor bottom surface 214 side of the lower semiconductor layer 210 is more easily eroded by the etching solution.

This is due to the following reason.
In general, the AlN constituting the intermediate layer 201 (see FIG. 3) of the present embodiment is the AlGaN or GaN constituting the base layer 202 (see FIG. 3) and the n contact layer 203a (see FIG. 3) of the present embodiment. Compared with InGaN or the like, it has a property of being easily eroded by an etching solution such as orthophosphoric acid.
Further, as described above, in this embodiment, the intermediate layer 201, the base layer 202, and the n contact layer 203 a constituting the lower semiconductor layer 210 are each in contact with the upper semiconductor layer 250 from the side close to the substrate 100. The crystallinity is gradually improved toward.
Furthermore, as described above, the group III nitride semiconductor constituting the lower semiconductor layer 210 in the present embodiment grows so that the N-polar surface faces the substrate upper surface 113 of the substrate 100. In general, when a group III nitride semiconductor is wet-etched, it is known that etching proceeds from the N-polar surface side.

  For the above reasons, the lower semiconductor layer 210 in this embodiment is more easily eroded by the etching solution on the lower semiconductor bottom surface 214 side than on the lower semiconductor upper surface 213 side. When the etchant enters the first irradiation line 81 and the second irradiation line 82, the interface between the lower semiconductor layer 210 and the substrate 100 (ie, the lower semiconductor layer 210) of the exposed lower semiconductor layer 210 is generally used. The erosion by the etchant proceeds starting from the side semiconductor bottom surface 214).

12 to 14 are diagrams for explaining the progress of wet etching in the lower semiconductor layer 210. FIG. Specifically, FIG. 12 is a view of the vicinity of the region where the mask 55 is formed in the lower semiconductor layer 210 of the semiconductor multilayer substrate 20 as viewed from the third direction z, and FIG. The lower semiconductor layer 210 before the wet etching process is shown, and FIG. 12B shows the lower semiconductor layer 210 after the wet etching process.
Moreover, Fig.13 (a) is XIIIA-XIIIA sectional drawing in Fig.12 (a), FIG.13 (b) is XIIIB-XIIIB sectional drawing in FIG.12 (b).
14A is a cross-sectional view taken along the line XIVA-XIVA in FIG. 12A, and FIG. 14B is a cross-sectional view taken along the line XIVB-XIVB in FIG.

First, the progress of wet etching in the region of the lower semiconductor layer 210 where the mask 55 is not formed when viewed in the third direction z will be described.
As described above, the lower semiconductor layer 210 is more easily eroded by the etchant on the lower semiconductor bottom surface 214 side than on the lower semiconductor upper surface 213 side. Therefore, when the semiconductor laminated substrate 20 is immersed in the etching solution and the etching solution enters the first irradiation line 81, the lower semiconductor bottom surface 214 is formed in the lower semiconductor layer 210 exposed in the first irradiation line 81. Wet etching proceeds as a starting point.

Accordingly, as shown in FIG. 13A, in the region of the lower semiconductor layer 210 on the lower semiconductor bottom surface 214 side, the lower semiconductor layer 210 becomes larger as it is closer to the lower semiconductor bottom surface 214 by wet etching. It will be scraped.
As a result, as shown in FIG. 13B, the lower semiconductor bottom surface 214 side of the lower semiconductor layer 210 is inclined and extends inward of the lower semiconductor layer 210 toward the lower semiconductor bottom surface 214. A first inclined surface 211b is formed.

On the other hand, in the region on the lower semiconductor upper surface 213 side of the lower semiconductor layer 210, as described above, erosion due to wet etching is less likely to be eroded than on the lower semiconductor bottom surface 214 side. In addition, in the region on the lower semiconductor top surface 213 side of the lower semiconductor layer 210, the crystallinity is better than that on the lower semiconductor bottom surface 214 side. There is little difference in wet etching.
As a result, on the lower semiconductor upper surface 213 side of the lower semiconductor layer 210, the lower semiconductor layer 210 is substantially uniformly cut by the wet etching process, and as shown in FIG. 13B, the first inclined surface 211b A first vertical surface 211a extending along the third direction z from the upper end toward the lower semiconductor upper surface 213 is formed.
As described above, the first lower semiconductor side surface 211 having the first inclined surface 211b on the lower semiconductor bottom surface 214 side and the first vertical surface 211a on the lower semiconductor upper surface 213 side through the first irradiation line 81. Will be formed.

FIGS. 13A and 13B show the case where the first lower semiconductor side surface 211 is formed through the first irradiation line 81 by the wet etching process, but the second lower semiconductor side surface 212 is shown. Is formed in the same manner as the first lower semiconductor side surface 211 by wet etching.
Therefore, similarly to the first lower semiconductor side surface 211 shown in FIG. 13B, the etchant enters the second irradiation line 82 by the wet etching process, and the lower semiconductor layer 210 passes through the second irradiation line 82. As a result, the second lower semiconductor side surface 212 having the second vertical surface 212a on the lower semiconductor upper surface 213 side and the second inclined surface 212b on the lower semiconductor bottom surface 214 side is formed. Become.

Next, how wet etching proceeds in the region of the lower semiconductor layer 210 where the mask 55 is formed when viewed from the third direction z will be described.
As shown in FIG. 14A, an altered region 210a is formed in a region of the lower semiconductor layer 210 where the mask 55 is stacked. Here, in the altered region 210a, the lower semiconductor layer 210 is altered, so that it is more easily eroded by the etchant than the lower semiconductor layer 210 in other regions.
As a result, when the etchant enters the first irradiation line 81 and the second irradiation line 82 in the wet etching process of Step 105, the modified region 210a is formed in addition to the lower semiconductor bottom surface 214. Wet etching proceeds from the side semiconductor upper surface 213 as a starting point.

That is, in the region of the lower semiconductor layer 210 on the lower semiconductor bottom surface 214 side, as shown in FIG. 14A, the lower semiconductor layer 210 is greatly scraped as it approaches the lower semiconductor bottom surface 214 by wet etching. .
On the other hand, in the region of the lower semiconductor layer 210 on the lower semiconductor upper surface 213 side, as shown in FIG. 14A, the lower semiconductor layer 210 is greatly scraped as it approaches the lower semiconductor upper surface 213 (modified region 210a). .

Accordingly, the lower semiconductor bottom surface 214 side of the lower semiconductor layer 210 is inclined and extended inward of the lower semiconductor layer 210 toward the lower semiconductor bottom surface 214 as shown in FIG. A reverse inclined surface 235b is formed.
Further, on the lower semiconductor upper surface 213 side of the lower semiconductor layer 210, as shown in FIG. 14 (b), the outer side of the lower semiconductor layer 210 extends from the lower semiconductor upper surface 213 toward the upper end of the reverse inclined surface 235b. A forward inclined surface 235a extending obliquely in the direction and a boundary portion 235c serving as a boundary between the forward inclined surface 235a and the reverse inclined surface 235b are formed.

Here, when the region where the mask 55 is formed in the lower semiconductor layer 210 is viewed from the third direction z, as shown in FIG. 12A, the mask 55 (modified region 210a; The wet etching proceeds inward of the lower semiconductor layer 210, starting from the corner portion of the lower semiconductor layer 210 where the lower semiconductor layer 210 is formed as shown in FIG.
In the region where the mask 55 is formed, the lower semiconductor layer 210 is cut into an arc shape as shown in FIG. As a result, the forward inclined surface 235a and the boundary portion 235c have an arcuate shape when viewed from the third direction z, and the boundary between the lower semiconductor upper surface 213 and the forward inclined surface 235a has an arc shape. A connection portion 233 (see FIG. 12) having the above is formed.

  As described above, in the wet etching process of step 105, the first lower semiconductor side surface 211 having the first vertical surface 211a and the first inclined surface 211b is obtained by performing wet etching processing on the semiconductor multilayer substrate 20. A second lower semiconductor side surface 212 having a second vertical surface 212a and a second inclined surface 212b, a connecting side surface 235 having a forward inclined surface 235a, a reverse inclined surface 235b, and a boundary portion 235c are formed, and the lower side A connection portion 233 that is a boundary between the semiconductor upper surface 213 and the connection side surface 235 is formed.

(Division process)
In the dividing step of step 106, the semiconductor laminated substrate 20 in which the first lower semiconductor side surface 211, the second lower semiconductor side surface 212, and the connection side surface 235 are formed in the lower semiconductor layer 210 by the wet etching step of step 105 is cut. The semiconductor light emitting element 1 is divided.
Before the semiconductor multilayer substrate 20 is divided into the plurality of semiconductor light emitting elements 1, the substrate bottom surface 114 (see FIG. 3) of the substrate 100 is ground and polished so that the substrate 100 in the semiconductor multilayer substrate 20 has a predetermined thickness. You may provide the process to do.
The thickness of the substrate 100 after grinding and polishing is 60 μm to 300 μm, preferably 80 μm to 250 μm, more preferably 100 μm to 200 μm. By setting the thickness of the substrate 100 within the above range, it is possible to efficiently divide the semiconductor laminated substrate 20 in the dividing step of Step 106.

In the dividing step of step 106, first, the inside of the substrate 100 along the first irradiation line 81 and the second irradiation line 82 from the substrate bottom surface 114 (see FIG. 3) side of the wafer-like substrate 100 in the semiconductor laminated substrate 20. Is irradiated with a laser. Thereby, a plurality of modified regions in which the sapphire single crystal is modified along the first irradiation line 81 and the second irradiation line 82 are formed in the substrate 100.
Subsequently, the modified region is formed by pressing the blade from the substrate bottom surface 114 side of the wafer-like substrate 100 along the modified region formed along the first irradiation line 81 and the second irradiation line 82. A crack is generated as a starting point, and the wafer-like substrate 100 is divided into a plurality of substrates 100. At this time, the lower semiconductor layer 210, the upper semiconductor layer 250, the p-electrode 300, and the n-electrode 400 exist on each divided substrate 100.
By this division, a first substrate side surface 111 and a second substrate side surface 112 (both see FIG. 1) in the substrate 100 are formed.
And the semiconductor light-emitting device 1 shown in FIG. 1 can be obtained through the above process.

Here, conventionally, when the semiconductor multilayer substrate 20 is divided into the plurality of semiconductor light emitting elements 1 in the dividing step, vibrations or the like may occur in the semiconductor multilayer substrate 20, and the lower semiconductor layer in the semiconductor multilayer substrate 20 may be generated. 210 may collide with each other and the lower semiconductor layer 210 may be chipped.
In the semiconductor laminated substrate 20 of the present embodiment, as described above, the lower semiconductor layer 210 separated into a plurality of regions by the surface laser process in step 104 and the wet etching process in step 105 is the first lower semiconductor side surface. A connection side surface 235 is formed at a portion connecting 211 and the second lower semiconductor side surface 212, and the protruding amount of the lower semiconductor layer 210 is small.
Therefore, compared with the case where this configuration is not provided, the lower semiconductor layers 210 are less likely to collide with each other in the dividing step of Step 106, and even when the lower semiconductor layers 210 collide with each other, Compared to the case where the lower semiconductor layer 210 has a sharp point as described above, the lower semiconductor layer 210 can be prevented from being cracked or chipped.

In the manufacturing process of the semiconductor light emitting device 1 according to the present embodiment, the shape of the mask 55 formed in the intersecting portion 73 in the film forming process in step 103 is a circular shape, but the shape of the mask 55 is not limited to this. .
FIG. 15 is a view showing another shape of the mask 55 formed in the film forming process of step 103 in the manufacturing process of the semiconductor light emitting device 1 of the present embodiment, and the mask 55 is viewed from the third direction z. It is a figure. Note that the shape of the mask 55 shown in FIG. 15 is an example, and the shape of the mask 55 is not limited to these.

The shape of the mask 55 viewed from the third direction z may be a quadrangle (square) with each side along the first direction x or the second direction y, as shown in FIG.
Further, the shape of the mask 55 viewed from the third direction z may be a quadrangle (square) in which each diagonal line is along the first direction x or the second direction y, as shown in FIG.
Furthermore, the shape of the mask 55 viewed from the third direction z may be a cross shape extending along the first direction x and the second direction y, as shown in FIGS.
Furthermore, when the mask 55 is made of the same material as that of the protective film 51, it may be formed connected to the protective film 51 as shown in FIGS. 15 (e) and 15 (f).

However, the shape of the mask 55 viewed from the third direction z is circular for each of the following reasons, each side is a square along the first direction x or the second direction y, or each diagonal is the first direction x or the first direction. It is preferably a square along the two directions y, and more preferably a circular shape or each side is a square along the first direction x or the second direction y.
That is, when the mask 55 has such a shape, for example, the position where the first irradiation line 81 or the second irradiation line 82 is formed in the surface laser process of step 104 is deviated from a predetermined position. Even if it exists, it is because the 1st irradiation line 81 and the 2nd irradiation line 82 will cross | intersect on the mask 55 easily.

Here, for example, when the first irradiation line 81 and the second irradiation line 82 do not intersect on the mask 55 in the surface laser process of step 104, a plurality of regions are formed by the first irradiation line 81 and the second irradiation line 82. A region where the mask 55 is not stacked is formed in the lower semiconductor layer 210 that is separated into two. In the region of the lower semiconductor layer 210 where the mask 55 is not stacked, the altered region 210a altered by the mask 55 is not formed. Therefore, in the wet etching process of step 105, the forward inclined surface on the connection side surface 235 is formed. There is a concern that 235a may not be formed.
Therefore, it is preferable that the mask 55 has the above-described shape.

When the shape of the mask 55 is circular (see FIG. 9), the diameter of the mask 55 is, for example, larger than the width of the first irradiation line 81 and the second irradiation line 82 formed in the surface laser process in step 104. It is preferably large and within the range of the width of the first groove portion 71 and the second groove portion 72 formed in the semiconductor removal step of step 102.
When the shape of the mask 55 is a square (see FIG. 15A) in which each side is in the first direction x or the second direction y, the length of each side of the mask 55 is, for example, the first irradiation. The width is preferably larger than the width of the line 81 and the second irradiation line 82 and within a range equal to or less than the distance between the adjacent protective films 51.
Furthermore, when the shape of the mask 55 is a square in which each diagonal line is in the first direction x or the second direction y (see FIG. 15B), the length of each diagonal line of the mask 55 is, for example, the first It is preferable that the width is larger than the width of the irradiation line 81 and the second irradiation line 82 and not more than twice the distance between the adjacent protective films 51.

Here, when the diameter of the mask 55 is excessively large, the area of the altered region 210a formed in the lower semiconductor layer 210 is increased accordingly. Therefore, in the wet etching process of Step 105, the area below the lower semiconductor layer 210 is increased. The side semiconductor upper surface 213 side is greatly sharpened. When the lower semiconductor upper surface 213 side of the lower semiconductor layer 210 is greatly shaved, the shape of the connecting portion 233 and the forward inclined surface 235a of the connecting side surface 235 viewed from the third direction z becomes an arc shape with a large curvature. Cheap.
When the curvature of the connecting portion 233 or the forward inclined surface 235a is increased, the connecting portion 233 or the like is compared with a case where another member or the like collides with the lower semiconductor layer 210, for example, as compared with the case where the curvature is small. There is a concern that the force tends to concentrate on the lower semiconductor layer 210 and the lower semiconductor layer 210 is likely to be cracked or chipped.

  Further, when the diameter of the mask 55 is excessively small, the area of the altered region 210a is also reduced accordingly. Therefore, in the wet etching process of Step 105, the lower semiconductor upper surface of the lower semiconductor layer 210 starting from the altered region 210a. In some cases, erosion on the 213 side is not sufficiently performed. And when the erosion starting from the altered region 210a is insufficient, the forward inclined surface 235a in the connecting portion 233 and the connecting side surface 235 is not formed, or the shape of the connecting portion 233 and the forward inclined surface 235a There is a tendency to become a large arc shape.

  Further, when the diameter of the mask 55 is excessively small, the area of the altered region 210a is also reduced accordingly, so that the first irradiation line 81 and the second irradiation line 82 formed in the surface laser process in step 104 are connected to the mask 55. It tends to be difficult to cross over. When the first irradiation line 81 and the second irradiation line 82 do not intersect on the mask 55, the lower side separated into a plurality of regions by the first irradiation line 81 and the second irradiation line 82 as described above. In the semiconductor layer 210, a region where the altered region 210a is not formed is generated. In the lower semiconductor layer 210 in which the altered region 210a is not formed, the lower semiconductor upper surface 213 side does not serve as an etching starting point in the wet etching process of step 105, and thus the forward inclined surface 235a as described above is not formed. There is.

  In the manufacturing process of the semiconductor light emitting device 1 according to the present embodiment, the stacked semiconductor layer 200 (the lower semiconductor layer 210) is altered by stacking the mask 55 at the intersection 73 in the film forming process of Step 103. Region 210 a was formed at intersection 73. However, the method of forming the altered region 210a is not limited to the lamination of the mask 55, and for example, the laminated semiconductor layer 200 (lower semiconductor layer 210) exposed at the intersection 73 is subjected to treatment such as oxidation / reduction. By applying, the altered region 210a in which the laminated semiconductor layer 200 (lower semiconductor layer 210) is altered may be formed.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor light emitting element, 20 ... Semiconductor laminated substrate, 51 ... Protective film, 55 ... Mask, 71 ... 1st groove part, 72 ... 2nd groove part, 73 ... Crossing part, 81 ... 1st irradiation line, 82 ... 2nd irradiation Line 100, substrate 200, laminated semiconductor layer 210, lower semiconductor layer, 210 a, altered region 211, first lower semiconductor side surface, 211 a, first vertical surface, 211 b, first inclined surface, 212, first. 2 lower semiconductor side surface, 212a ... second vertical surface, 212b ... second inclined surface, 213 ... lower semiconductor upper surface, 214 ... lower semiconductor bottom surface, 230 ... upper surface periphery, 231 ... first linear portion, 232 ... second Straight line portion, 233... Connection portion, 235 .. connection side surface, 235a... Forward inclined surface, 235b... Reverse inclined surface, 235c.

Claims (5)

A semiconductor laminated substrate in which a semiconductor layer including a light-emitting layer that emits light when energized and made of a group III nitride is laminated on a substrate is made of a material different from the semiconductor layer and a part of the semiconductor layer A covering portion forming step for forming a covering portion covering the region of
The semiconductor laminated substrate on which the covering portion is formed is crossed at the covering portion by locally removing the semiconductor layer so as to reach the substrate from the side on which the covering portion is formed. And a division groove forming step of forming a plurality of division grooves for dividing the semiconductor layer into a plurality of regions;
A method of manufacturing a semiconductor light emitting device, comprising: a wet etching step of performing wet etching on the semiconductor laminated substrate in which the covering portion and the dividing groove are formed. In the covering portion forming step, the covering portion made of an insulating film having an insulating property is formed, and another covering is formed of the insulating film and covers a region different from the covering portion on the semiconductor layer. Forming part,
2. The method of manufacturing a semiconductor light emitting element according to claim 1, wherein in the dividing groove forming step, the plurality of dividing grooves that intersect at the covering portion and do not pass through the other covering portion are formed. Before the covering portion forming step, a part of the semiconductor layer is locally removed from the side opposite to the substrate with respect to the semiconductor laminated substrate, and the semiconductor layer is recessed toward the substrate side and A semiconductor removing step of separating the opposite side of the semiconductor layer from the substrate into a plurality of regions by forming a plurality of intersecting grooves;
In the covering portion forming step, the covering portion is formed at an intersecting portion where the plurality of groove portions intersect,
3. The method of manufacturing a semiconductor light emitting element according to claim 1, wherein in the dividing groove forming step, the plurality of dividing grooves are formed along the plurality of groove portions and intersecting at the intersecting portions. By processing the semiconductor layer from the side opposite to the substrate, the semiconductor layered substrate in which a semiconductor layer including a light-emitting layer that emits light when energized and composed of a group III nitride is stacked, A modified region forming step of forming a modified region obtained by modifying a partial region of the semiconductor layer;
The semiconductor layered substrate in which the altered region is formed is crossed in the altered region by locally removing the semiconductor layer from the side on which the altered region is formed until reaching the substrate. A division groove forming step of forming a plurality of division grooves for dividing the semiconductor layer into a plurality of regions;
A method for manufacturing a semiconductor light emitting device, comprising: a wet etching step of performing wet etching on the semiconductor laminated substrate in which the altered region and the plurality of dividing grooves are formed. A semiconductor light emitting device including a semiconductor layer including a light emitting layer that emits light when energized,
The semiconductor layer includes a semiconductor bottom surface, a semiconductor side surface rising above the semiconductor layer from a first peripheral edge of the semiconductor bottom surface, and an inward direction of the semiconductor layer from a second peripheral edge above the semiconductor side surface. A semiconductor upper surface facing upward,
The second peripheral edge has a plurality of linear portions extending linearly and a plurality of connection portions connecting the adjacent linear portions, and each connection portion is viewed from a direction perpendicular to the upper surface of the semiconductor. In the case where it is located on the inner side of the intersection of the extension lines of the two linear portions connected by the connection portion,
The semiconductor side surface includes a straight portion side surface that rises from the first peripheral edge toward the straight portion at the second peripheral edge, and a connection side surface that rises from the first peripheral edge toward the connection portion at the second peripheral edge. And
The connection side surface is an outer inclined surface that is inclined upward and outward from the first peripheral edge from the first peripheral edge, and an upper end of the outer inclined face toward the connection portion at the second peripheral edge. A semiconductor light emitting element having an inwardly inclined surface that inclines inward and above the semiconductor layer.

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