JP2014103137A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve a problem of film reduction in a wiring layer caused by a part of the wiring layer exposed to a through-hole being overetched when forming the through-hole reaching the wiring layer on a substrate surface from the substrate rear face and connecting a through electrode, and further caused by Ar reverse sputtering for removing a natural oxide film of the wiring layer of the exposed part.SOLUTION: After a through-hole 1H reaching a first conductor wire 41 is formed from a rear face 1B of a semiconductor substrate 1, a surface of a first metal 412 of an exposed first conductor wire 41 is nitrided to form an interposed layer 413 that is a nitride of a first metal, and thereafter, a through electrode is formed.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having an electrode penetrating a semiconductor substrate.

  2. Description of the Related Art In recent years, semiconductor devices in which a plurality of semiconductor chips are stacked and integrated in the vertical direction have been proposed with the increasing functionality and diversification of semiconductor devices. Such a semiconductor device is configured to achieve electrical continuity between the semiconductor chips by means of an electrode (through silicon via: TSV) penetrating the semiconductor substrate of each semiconductor chip.

  Japanese Patent Laying-Open No. 2012-9473 (Patent Document 1) discloses a semiconductor device including a through electrode penetrating a substrate and a manufacturing method thereof. Here, through holes are opened in the substrate and the insulating film from the back surface side of the silicon substrate so that the back surface of the pad electrode formed on the front surface side of the silicon substrate is exposed. A plating seed layer is formed in the through hole, and a through electrode is formed by a plating method. At this time, if there is a natural oxide layer at the interface between the pad electrode exposed at the bottom of the through hole and the seed layer, the contact resistance increases, so reverse sputtering with an inert gas such as argon is performed before the seed layer is formed. The process of cleaning the back surface of the pad electrode is disclosed.

JP 2012-9473 A

  When the present inventor examined such cleaning by reverse sputtering, the following was found. The pad electrode functions as an etching stopper when the silicon substrate and the interlayer insulating film are anisotropically etched to open a through hole. Usually, in order to simultaneously form a plurality of semiconductor chips on one silicon wafer, over-etching is performed in order to avoid local lack of etching when forming a through hole. Therefore, there is a concern that the film thickness may be reduced. According to the study by the present inventor, the pad electrode is formed in the same process as the wiring in the same layer, and therefore it is difficult to freely set the film thickness and material. Furthermore, when reverse sputtering is performed to clean the pad electrode as described above, the reduction in film thickness becomes more remarkable. This can cause an increase in resistance value and a connection failure.

According to one embodiment of the present invention,
A wiring layer formed on the surface of the semiconductor substrate;
A first conductor wiring comprised in the wiring layer and made of a first metal;
A through electrode penetrating the semiconductor substrate so as to be in contact with a part of the first conductor wiring from the back surface of the semiconductor substrate;
An intervening layer made of a nitride of the first metal, which is included in the first conductor wiring and formed at a boundary surface at a contact point with the through electrode;
A semiconductor device characterized by including:

Also, according to another embodiment of the present invention,
Forming a first conductor wiring containing a first metal on a surface of a semiconductor substrate;
Forming a through hole that penetrates the semiconductor substrate from the back surface of the semiconductor substrate and exposes a part of the first metal of the first conductor wiring;
Nitriding the first metal exposed at the bottom of the through hole;
Nitriding the exposed first metal and then burying a conductor film inside the through hole to form a through electrode;
A method for manufacturing a semiconductor device, comprising:

In addition, according to yet another embodiment of the present invention,
Two or more wiring layers formed on the surface of the semiconductor substrate;
A pad electrode containing a first metal in the lowermost layer on the semiconductor substrate side of the wiring layer;
A through electrode penetrating the semiconductor substrate and contacting a part of the pad electrode;
A semiconductor device comprising:
The contact surface between the pad electrode and the bottom of the through electrode constitutes a second plane farther from the semiconductor substrate than the first plane on the semiconductor substrate side that is not in contact with the through electrode of the pad electrode, There is provided a semiconductor device having an intervening layer made of a nitride of the first metal on the entire surface of the second plane.

  According to one embodiment of the present invention, a through hole for forming a through electrode is formed on a contact surface of a wiring layer (first conductor wiring) that is in contact with the through electrode formed from the back surface of the semiconductor substrate. By forming the intervening layer by nitriding the exposed metal surface, the metal surface is prevented from being oxidized in the subsequent process while suppressing further decrease in the film thickness of the first conductor wiring. Contact failure can be suppressed.

It is typical sectional drawing which shows the outline of the semiconductor package using the semiconductor device which concerns on one Embodiment of this invention. It is a typical sectional view showing the lamination state of a semiconductor device. 1A is a schematic cross-sectional view of a semiconductor device 101 according to an embodiment of the present invention, and FIG. It is process sectional drawing explaining the manufacturing method of the semiconductor device 101 which concerns on one Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 101 which concerns on one Embodiment of this invention. 6A and 6B are a process cross-sectional view (a) and a partially enlarged view (b) illustrating a method for manufacturing the semiconductor device 101 according to an embodiment of the present invention. 6A and 6B are a process cross-sectional view (a) and a partially enlarged view (b) illustrating a method for manufacturing the semiconductor device 101 according to an embodiment of the present invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 101 which concerns on one Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 101 which concerns on one Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 101 which concerns on one Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 101 which concerns on one Embodiment of this invention. FIG. 6 is a schematic cross-sectional view (a) and a partially enlarged view (b) of a semiconductor device 201 according to another embodiment of the present invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 201 which concerns on another embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 201 which concerns on another embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 201 which concerns on another embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 201 which concerns on another embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 201 which concerns on another embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device 201 which concerns on another embodiment of this invention.

  Hereinafter, exemplary embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to these exemplary embodiments, and can be appropriately modified by those skilled in the art within the scope of the present invention. Include.

Embodiment 1
First, a semiconductor package 100 using a semiconductor device according to the present invention (hereinafter referred to as a semiconductor chip) will be described.

  In this semiconductor package 100, a plurality of semiconductor chips 101 are stacked in a sandwich shape, and power is supplied and signals are transmitted and received through electrodes [TSV (Through Silicon Via): through electrodes 111] penetrating the semiconductor chips. Each semiconductor chip has a surface terminal (surface bump) 112 exposed to the outside on the circuit forming surface side and a back surface terminal (back surface bump) 113 exposed to the through electrode 111 and exposed to the outside on the back surface side. Each semiconductor chip 101 (here, five layers 101A to 101E) is stacked with the circuit formation surface facing down (face-down). For example, the lowermost semiconductor chip 101A is an interface chip, on which DRAM chips 101B to 101E are stacked. Since it is laminated face down, the uppermost layer chip 101E only needs to be able to capture the signal and power supplied from the semiconductor chip 101D into its own chip, and does not need to be supplied to the upper layer. Therefore, it is not necessary to provide the through electrode 111 in the uppermost layer chip 101E. The semiconductor chips 101A to 101D are thinned in order to provide the through electrode 111, but it is not necessary to provide the through electrode 111 in the uppermost layer chip 101E, and thus thinning to form the through electrode 111 is unnecessary. It is. Thereby, a process can be simplified. Further, the warpage of the substrate accompanying the reduction in thickness can be reduced.

  In the uppermost layer chip 101E, only the step of providing the through electrode 111 is omitted, and the memory circuit, the test terminal, the signal terminal, the multilayer wiring for connecting each through electrode to the surface terminal such as the corresponding terminal, etc. It is formed in the same way as a semiconductor chip.

  From the viewpoint of using a chip formed by aligning all the processes, a chip in which a through electrode is formed through a thinning process may be applied as the uppermost chip 101E in the same manner as other chips.

  The stacked semiconductor chips 101A to 101E are connected to the wiring substrate 102 by the lowermost interface chip 101A, and a gap between each semiconductor chip is filled with an underfill resin 103. Further, it is packaged with a mold resin 104. Solder balls 105 for connecting the semiconductor package 100 to a desired circuit board are provided in an array on the back surface of the wiring board 102.

  It should be noted that whether the circuit formation surface is facing upward or downward is not related to the operational effects of the present invention, and the configuration of this embodiment may be face-up. In that case, a chip in which the through electrode 111 is formed is applied to the uppermost chip 101E as well as other chips. In the face-up configuration, the wiring layer 4 connected to a semiconductor circuit such as a memory circuit is formed on the uppermost chip, but it is not necessary to provide the surface bump 112.

  FIG. 2 shows an enlarged cross-sectional view of the through electrode portion. Each semiconductor chip is formed in an element circuit 2, an interlayer insulating film 3, and an interlayer insulating film 3 on a surface 1A of a silicon substrate 1 as a semiconductor substrate. Wiring layer 4, passivation film 5 such as polyimide covering the chip surface, first seed layer 6, first conductor film 7, and first adhesive such as Au / Ni as surface bump 112 connected to the uppermost layer of wiring layer 4. Layer 8 is formed. On the other hand, a back surface protective film 11 is formed on the back surface 1B of the silicon substrate 1, and the insulating layer 12, the second seed layer 13, and the second seed layer are formed in the through hole 1H penetrating from the back surface 1B to the lowermost layer of the wiring layer 4. A second adhesive layer 15 made of solder such as SnAg is formed on the surfaces of the conductor film 14 and the second conductor film 14. In this example, the through electrode 111 and the back surface bump 113 are integrally formed of the second conductor film 14. Each semiconductor chip is solder bonded by aligning the front surface bump 112 and the back surface bump 113 and applying a predetermined pressure and temperature.

  Next, the semiconductor chip 101 of this embodiment example will be described in detail. FIG. 3A is a schematic cross-sectional view of each semiconductor chip 101 before packaging, and FIG. 3B is a partially enlarged view. The semiconductor chip 101 is roughly divided into an element region in which the element circuit 2 is formed and a TSV region in which the through electrode 111 is formed in plan view. The feature of the present invention is that the first conductor wiring (pad electrode) 41 in the lowermost layer of two or more wiring layers 4 and the through electrode 111 are in contact with each other as shown in the partially enlarged view of FIG. In addition, an intervening layer 413 that is a nitride of the first metal exists on the boundary surface between the first conductor wiring 41 and the first metal 412. Here, when tungsten (W) is used as the first metal 412, the intervening layer 413 is made of tungsten nitride (WN).

  Next, the detail of each structural member is demonstrated, referring a manufacturing process. 4 to 11 are process cross-sectional views illustrating the manufacturing process of the semiconductor chip 101 of this embodiment example.

  First, as shown in FIG. 4, the surface 1A side of the silicon substrate 1 is processed. A circuit element 2 is formed on the substrate surface by a known method and covered with an interlayer insulating film 3 (first interlayer insulating film). A silicon oxide film can be used as the first interlayer insulating film. A first conductor wiring 41 including a first metal 412 is formed on the first interlayer insulating film. Further, the lamination of the interlayer insulating film 3 and the wiring formation are repeated to form the wiring layer 4. As the wiring conductor (wiring and via plug), tungsten (W), aluminum (Al), copper (Cu) or the like can be used, and barrier films (for example, tungsten nitride (WN), titanium nitride (TiN), titanium (Ti) ) Etc.) may be included. A silicon nitride film is used as the uppermost layer of the interlayer insulating film 3. The first conductor wiring 41 functions as an etching stopper at the time of forming a through hole, which will be described later, and has a blank portion that becomes an outer peripheral portion around a region exposed to the bottom of the through hole (contact portion with the through electrode 111). It is formed in a shape and prevents punching into the upper layer. When the punching is not a problem, the first wiring conductor may be a line pattern or a lattice pattern. In any case, as the first metal 412 included in the first conductor wiring 41, a metal having a relatively good etching resistance against the anisotropic etching of silicon or an oxide film can be used. A metal having a problem in resistance and a metal material in which a nitride of a first metal formed by a nitriding process described later exhibits good conductivity can be given. The first metal is preferably a metal that can be nitrided at a low temperature that does not affect the semiconductor element formed on the substrate surface side. In particular, the first metal has a catalytic action capable of decomposing ammonia into hydrogen and nitrogen. W which is easily formed is more preferable because it can be efficiently nitrided at a low temperature. Here, a W film is formed as the first metal wiring 412 on the WN barrier film 411 as the first conductor wiring 41.

  After forming the uppermost interlayer insulating film 3, a polyimide film is formed as the passivation film 5. Subsequently, the polyimide film and the uppermost interlayer insulating film 3 are sequentially patterned to form an opening that exposes the uppermost wiring surface of the wiring layer 4. After a first seed layer (Cu / Ti) 6 is formed on the entire surface by sputtering, a surface bump formation mask (not shown) is formed of a photoresist (PR), and the first conductor is formed as a surface bump 112 by electroplating. A film (Cu) 7 and a first adhesive layer (Au / Ni) 8 are formed. The structure shown in FIG. 4 is obtained by removing the exposed first seed layer 6 after removing the surface bump forming mask. Thus, the processing on the front surface 1A side is completed, and then the processing on the back surface side is performed.

  In performing the processing on the back surface side, a holding member is used in order to improve the handleability of the substrate (wafer). Here, a wafer support system (WSS) is provided that adheres and holds the wafer surface side to a transparent support 10 such as a glass substrate by using an adhesive layer 9 including an adhesive whose adhesiveness is changed by light irradiation. Use. For the sake of explanation, FIG. 5 and subsequent figures are shown upside down.

  As shown in FIG. 5, back grinding (BG) is performed from the back surface of the silicon substrate 1 to a predetermined thickness (for example, 40 μm) while being held in WSS, and the back surface is formed on the back surface 1B after BG. A silicon nitride film is formed as the protective film 11. BG is performed in the order of rough cutting, fine cutting, and chemical mechanical polishing (CMP), and the back surface 1B is mirror-finished.

  Next, as shown in FIG. 6, a through hole 1H reaching the first conductor wiring 41 from the back surface side is formed. A photoresist (PR) is applied on the back surface protective film 11, and an opening for forming the through hole 1H is formed by a photolithography process. Using the PR as a mask, the back surface protective film 11 / silicon substrate 1 / interlayer insulating film 3 are sequentially dry etched. Finally, the first conductor wiring 41 is used as an etch stopper. At this time, as shown in FIG. 6B, over-etching of about 30 to 40 nm is applied to the first conductor wiring 41 (for example, 50 nm in total), so that the WN barrier film 411 (for example, 10 nm in thickness) It does not remain on the bottom exposed surface of the through hole 1H. A second plane 41B that is farther from the silicon substrate than the plane of the first conductor wiring 41 on the silicon substrate side (first plane 41A) is formed.

Next, as shown in FIG. 7, the first metal 412 of the first conductor wiring 41 exposed at the bottom of the through hole 1H is nitrided. Nitriding treatment, gas and nitriding with ammonia gas (NH _3), nitrogen gas _(N 2), ammonia gas _(NH 3), NO, it is performed by plasma nitridation using nitrogen-containing gas such as _{N 2} O Can do. Here, nitriding and reduction are performed at a temperature of 180 ° C. or less in an ammonia (NH ₃ ) atmosphere. In addition, in order to perform a nitriding reaction efficiently, it is preferable to heat so that it may become temperature more than room temperature. Thereby, the intervening layer 413 made of WN is formed on the exposed first metal surface of the first conductor wiring 41. The intervening layer 413 is in contact with the WN barrier film 411 at the interface side between the first metal 412 of the WN barrier film 411 around the bottom of the through-hole 1H. Accordingly, the first metal 412 is no longer exposed in the through hole 1H. FIG.7 (b) is an enlarged view of the broken-line part of Fig.7 (a). The intervening layer 413 may be nitrided to about 1/2 or less of the thickness of the first metal 412 remaining after over-etching at the time of forming the through hole. The nitriding conditions may be adjusted as appropriate so that the thickness is about 15 nm. The intervening layer 413 formed in this way constitutes a part of the first wiring conductor 41. The surface in the through hole 1H of the intervening layer 413 becomes a new second plane 41B ′. The second plane 41B ′ is also farther from the surface 1A of the silicon substrate 1 than the first plane 41A.

  Next, as shown in FIG. 8, the insulating film 12 is formed in a sidewall shape on the side wall of the through hole 1H. A silicon oxide film, a silicon nitride film, or a laminated film thereof is formed as the insulating film 12, and then etched back to remove the insulating film 12 on the back surface protective film 11 and the bottom of the through hole 1H, thereby forming a sidewall shape. Can be formed. The insulating film 12 is formed in order to insulate and isolate the circuit element formed on the surface 1A of the silicon substrate 1 and the through electrode formed thereafter.

Subsequently, as shown in FIG. 9, after forming the insulating film 12, the intervening layer 413 at the bottom of the through hole 1H is subjected to hydrogen (H ₂ ) plasma treatment to remove residual oxygen. Since the intervening layer 413 which is a nitride film is formed before the insulating film 12 is formed, the surface of the first conductor wiring 41 hardly undergoes natural oxidation. If the insulating film 12 is formed without forming the intervening layer 413, the first metal 412 exposed by over-etching is spontaneously oxidized. Therefore, conventionally, reverse sputtering such as Ar sputtering is performed before forming the through electrode in the next process. It was necessary to clean the oxide film by removing it. For this reason, there is a problem that the over-etched first conductor wiring 41 is further thinned. In the present invention, such Ar sputtering is not necessary, and by removing residual oxygen by hydrogen (H ₂ ) plasma treatment, further reduction in film thickness is suppressed, and the first conductor wiring 41 and the through electrode are formed. An increase in contact resistance can be suppressed.

  Next, as shown in FIG. 10, a Cu / Ti film is formed as a second seed layer 13 on the entire surface by sputtering as in the case of the first seed layer 6, and then a PR mask for back bumps is formed, By plating, a Cu film as the second conductor 14 and a SnAg solder layer as the second adhesive layer 15 are successively formed. In the present embodiment, the through electrode 111 and the back surface bump 113 are integrally formed, but may be formed separately. Thereby, the bottom of the through electrode 111 is connected in contact with the intervening layer 413 which is a part of the first conductor wiring 41.

  Finally, as shown in FIG. 11, after removing the PR mask for the back bump, the exposed second seed layer 13 is removed by etching. Thereafter, the support 10 is irradiated with light to peel off the WSS from the wafer, and the remaining adhesive layer 9 is removed with a solvent. Furthermore, the semiconductor chip 101 shown in FIG. 3 is obtained by dicing each semiconductor chip.

  Thus, in the present invention, oxidation is prevented by nitriding the back surface of the first conductor wiring 41 after forming the through hole 1H. This eliminates the need for etching for removing the oxide film before forming the through electrode. The loss of the first conductor wiring 41 connecting the through electrode 111 and the surface bump 112 can be reduced, and an increase in resistance and connection failure can be reduced. As a result, the performance of the semiconductor device having the through electrode can be further improved.

  In the present invention, it is meaningful to nitride the exposed surface (first metal 412) on the back surface of the first conductor wiring 41 after the through hole 1H is formed. For example, a structure in which a nitride film is formed on the base film as the barrier film 411 when the first conductor wiring 41 is formed is known. However, according to the study of the present inventor, it is removed by anisotropic etching at the time of forming a through hole at a thickness of a barrier film applied to a normal conductor wiring. Therefore, since the effect of suppressing oxidation as in the present invention cannot be obtained, it is necessary to remove the oxide film by etching before forming the through electrode. From the same point of view, the conductor wiring of the semiconductor device formed by the above-described known technique does not have a nitride film at the contact interface with the through electrode even when such a barrier nitride film is formed. On the other hand, in the present invention, the effect of preventing oxidation is obtained by nitriding the back surface of the first conductor wiring after forming the through hole, and etching for removing the oxide film is not required before forming the through electrode. In this case, also in the final structure, the nitride film remains as an intervening layer in the first conductor wiring at the contact point with the through electrode.

Embodiment 2
In the first embodiment, the semiconductor device by the so-called via last method in which the insulating film 12 is formed on the inner wall of the through hole 1H formed from the back surface 1B of the silicon substrate 1 has been described. However, in this embodiment, the insulating film 12 is formed of silicon. A semiconductor device 201 formed by the so-called via first method, which is first formed on the surface of the substrate 1, will be described.

  FIG. 12 shows a schematic cross-sectional view (a) and a partially enlarged view (b) of a semiconductor device (semiconductor chip) 201 according to this embodiment. The difference from the semiconductor chip 101 is that the insulating film 12 is formed from the front surface 1A to the back surface 1B of the silicon substrate 1 so as to surround the through hole 1H, not the inner wall of the through hole 1H. Here, in order to distinguish from the insulating film 12 of the semiconductor chip 101, the insulating ring 12R is used in the meaning of an annular insulating film. As shown in FIG. 12B, the insulating ring 12 </ b> R is not in contact with the first conductor wiring 41. The through electrode 111 is also in contact with the WN barrier film 411 exposed on the side wall of the through hole 1H. Other configurations are the same as those of the semiconductor chip 101, and the details are omitted by giving the same reference numerals.

  13 to 18 are process cross-sectional views illustrating the manufacturing process of the semiconductor chip 201 according to this embodiment.

  First, as shown in FIG. 13, a groove for an insulating ring is formed with a depth of 40 to 50 μm and a width of 2 to 3 μm (aspect ratio 13 to 25) from the surface 1A side of the silicon substrate 1, An insulating ring 12R is formed by embedding an insulating film in the insulating film. Here, an example in which the single insulating ring 12R is formed is shown, but a multiple ring of double or more may be used.

  Thereafter, as shown in FIG. 14, the manufacturing process on the surface 1 </ b> A side is performed in the same manner as the semiconductor chip 101. Subsequently, processing on the back side is performed.

  First, as shown in FIG. 15, the back surface of the silicon substrate 1 is ground until the bottom of the insulating ring 12R is exposed. Thereby, the insulating ring 12 penetrating from the front surface 1A to the back surface 1B of the silicon substrate 1 can be formed. Thereafter, the back surface protective film 11 is formed on the surface of the back surface 1B.

  Next, as shown in FIG. 16, a through hole 1H reaching the first conductor wiring 41 from the back surface side is formed. A photoresist (PR) mask is formed on the back surface protective film 11 to form a through hole 1H.

  Similarly to the step of FIG. 7 in the first embodiment, the surface of the first conductor wiring 41 (first metal 412) exposed at the bottom of the through hole 1H is nitrided to form an intervening layer 413 that is a nitride film. Subsequently, as shown in FIG. 18, residual oxygen is removed by hydrogen plasma treatment. After that, by forming the through electrode 111 and the back surface bump 113 in the same manner as in the first embodiment, the semiconductor chip 201 shown in FIG. 12 is completed. In this embodiment, the hydrogen plasma treatment shown in FIG. 18 may be omitted because there is no insulating film formation step in the through hole 1H. Further, there is no problem even if the surface of the silicon substrate 1 exposed in the through hole 1H during nitriding is nitrided, and nitriding prevents the metal element from leaking into the silicon substrate 1 from the through electrode 111 instead. Functions as a barrier film.

  Also in the present embodiment, the second seed layer 13 is formed by nitriding the surface of the first conductor wiring 41 (first metal 412) exposed after the formation of the through hole 1H to form the intervening layer 413. Even if it is exposed to the atmosphere until then, the generation of the natural oxide film can be suppressed as compared with the case where the first metal 412 is exposed. In the present embodiment, when the insulating ring 12R is formed so as to surround the first wiring conductor 41, the surface 1A of the silicon substrate 1 is not interposed between the first wiring conductor 41 and the interlayer insulating film 3. It may be formed on top.

1. Silicon substrate 1A. Surface 1B. Back side 1H. Through hole 2. Circuit element 3. 3. Interlayer insulating film Wiring layer 41. First conductor wiring (pad electrode)
411. Barrier film (WN)
412. First metal (W)
413. Intervening layer (WN)
41A. First plane 41B, 41B ′. Second plane 5. 5. Passivation film First seed layer 7. First conductor 8. First adhesive layer (Au / Ni)
9. Adhesive layer 10. Support 11. Back surface protective film 12. Insulating film 12R. Insulation ring 13. Second seed layer 14. Second conductor 15. Second adhesive layer (SnAg)
101, 201. Semiconductor chip 102. Wiring board 103. Underfill resin 104. Mold resin 105. Solder ball 111. Through electrode 112. Surface bump 113. Back bump

Claims (20)

A wiring layer formed on the surface of the semiconductor substrate;
A first conductor wiring included in the wiring layer and including a first metal;
A through electrode penetrating the semiconductor substrate so as to be in contact with a part of the first conductor wiring from the back surface of the semiconductor substrate;
An intervening layer made of a nitride of the first metal, which is included in the first conductor wiring and formed at a boundary surface at a contact point with the through electrode;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first conductor wiring is formed on the surface of the semiconductor substrate via an interlayer insulating film. An element region formed on the surface of the semiconductor substrate;
An insulating region penetrating the semiconductor substrate, and insulatingly separating the through electrode and the element region;
The semiconductor device according to claim 1, further comprising:   The semiconductor device according to claim 3, wherein the insulating region is formed in contact with the entire side surface of the through electrode from the back surface of the semiconductor substrate to the first conductor wiring.   The semiconductor device according to claim 3, wherein the insulating region is formed from the back surface to the front surface of the semiconductor substrate so as to surround a side surface of the through electrode via a semiconductor layer.   The semiconductor device according to claim 1, wherein the first metal is tungsten.   The semiconductor device according to claim 1, wherein the first conductor wiring has a contact portion with the through electrode and an outer peripheral region thereof.   8. The semiconductor device according to claim 7, wherein a part of the contact portion of the first conductor wiring with the through electrode is located away from the semiconductor substrate side plane in the outer peripheral region in a direction opposite to the semiconductor substrate.   The semiconductor device according to claim 7, wherein an outer peripheral region of the first conductor wiring is in contact with the first metal and has a barrier film on the semiconductor substrate side.   The front surface terminal connected to the uppermost layer of the wiring layer and exposed to the outside on the front surface side of the semiconductor substrate, and the back surface terminal connected to the through electrode and exposed to the back surface side outside of the semiconductor substrate. 10. The semiconductor device according to any one of 9 above. Forming a first conductor wiring containing a first metal on a surface of a semiconductor substrate;
Forming a through hole that penetrates the semiconductor substrate from the back surface of the semiconductor substrate and exposes a part of the first metal of the first conductor wiring;
Nitriding the first metal exposed at the bottom of the through hole;
Nitriding the exposed first metal and then burying a conductor film inside the through hole to form a through electrode;
A method for manufacturing a semiconductor device, comprising:   12. The method of manufacturing a semiconductor device according to claim 11, wherein the first conductor wiring is formed on a surface of the semiconductor substrate via an interlayer insulating film.   The semiconductor device manufacturing method according to claim 12, further comprising a step of forming a sidewall-like insulating film on the inner wall of the through hole between the step of nitriding the first metal and the step of forming the through electrode. Method.   The method of manufacturing a semiconductor device according to claim 13, further comprising a step of performing a hydrogen plasma treatment on the inside of the through hole having the sidewall-like insulating film before the step of forming the through electrode.   Before the step of forming the first conductor wiring, a step of forming an annular groove of a predetermined depth around the region for forming the through hole from the surface side of the semiconductor substrate; and the annular groove Embedding an insulating film therein to form an annular insulating region, and before forming the through hole, reducing the thickness of the semiconductor substrate from the back surface of the semiconductor substrate, thereby forming the annular insulating region. The method for manufacturing a semiconductor device according to claim 11, further comprising a step of exposing the bottom.   The method of manufacturing a semiconductor device according to claim 11, wherein the step of nitriding the first metal exposed at the bottom of the through hole is performed at a temperature of 180 ° C. or less in an ammonia atmosphere. .   The method for manufacturing a semiconductor device according to claim 11, wherein the first metal is tungsten.   The first wiring conductor is a laminated film of a barrier film and the first metal from the semiconductor substrate side, and the step of forming the through hole penetrates the barrier film, The method of manufacturing a semiconductor device according to claim 11, wherein overetching is performed until a part of the semiconductor device is removed. Two or more wiring layers formed on the surface of the semiconductor substrate;
A pad electrode containing a first metal in the lowermost layer on the semiconductor substrate side of the wiring layer;
A through electrode penetrating the semiconductor substrate and contacting a part of the pad electrode;
A semiconductor device comprising:
The contact surface between the pad electrode and the bottom of the through electrode constitutes a second plane farther from the semiconductor substrate than the first plane on the semiconductor substrate side that is not in contact with the through electrode of the pad electrode, A semiconductor device having an intervening layer made of the first metal nitride on the entire surface of the second plane.   The pad electrode is a laminated film of a tungsten nitride barrier film and a tungsten film as the first metal from the semiconductor substrate side, and the intervening layer is in contact with the first metal side interface of the tungsten nitride barrier film. The semiconductor device according to claim 19.

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