JP2014099495A - Silicon carbide semiconductor device manufacturing method - Google Patents

Silicon carbide semiconductor device manufacturing method Download PDF

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JP2014099495A
JP2014099495A JP2012250326A JP2012250326A JP2014099495A JP 2014099495 A JP2014099495 A JP 2014099495A JP 2012250326 A JP2012250326 A JP 2012250326A JP 2012250326 A JP2012250326 A JP 2012250326A JP 2014099495 A JP2014099495 A JP 2014099495A
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Eiji Waki
英司 脇
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New Japan Radio Co Ltd
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Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a MOS semiconductor device which has a low interface state density at an SiO-SiC interface in a simple and inexpensive method.SOLUTION: In a manufacturing method, a MOS structure is formed by combining extremely simple and highly controllable manufacturing processes such as a process of exposing a surface of a silicon carbide semiconductor to plasma generated inside an ECR sputtering device, a process of depositing an SiOfilm by an ECR sputtering method while maintaining a vacuum state in the same device, a subsequent heat treatment process at approximately 1000°C-1200°C and a process of stacking metal films.

Description

本発明は、炭化珪素(SiC)半導体装置の製造方法に関し、特に炭化珪素半導体層表面に、界面準位密度の低い金属−絶縁体−半導体(MOS)構造を備えた半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a silicon carbide (SiC) semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a metal-insulator-semiconductor (MOS) structure having a low interface state density on the surface of a silicon carbide semiconductor layer.

炭化珪素は、半導体集積回路として広く用いられているシリコン(Si)単結晶に較べて約3倍の熱伝導率を有すると共に、約2倍の飽和電子ドリフト速度を有するという優れた物性値を有し、シリコンの材料限界を超えた特性を有するMOS構造の電界効果型トランジスタ(MOSFET)が研究開発されている。   Silicon carbide has an excellent physical property value of about three times the thermal conductivity and about twice the saturation electron drift velocity as compared with silicon (Si) single crystal widely used as a semiconductor integrated circuit. However, field-effect transistors (MOSFETs) having a MOS structure having characteristics exceeding the material limit of silicon have been researched and developed.

炭化珪素からなるMOSFET(SiC−MOSFET)では、ゲート絶縁膜とSiCの界面特性が素子特性に大きな影響を与える。例えば炭化珪素は、シリコン同様、熱酸化法により二酸化珪素(SiO2)を形成することができ、SiC−MOSFETの製造工程でも熱酸化法が採用されている。しかし熱酸化法のみでは、SiO2―SiC界面に多くの界面準位が存在することが知られている。特に熱酸化法により形成したSiO2をゲート絶縁膜としたMOSFETでは、伝導帯に近い界面準位によって、チャネル移動度がバルク内の移動度に比べて極端に低くなり、オン抵抗が増大してしまい素子特性が劣化するという問題があった。 In a MOSFET (SiC-MOSFET) made of silicon carbide, the interface characteristics between the gate insulating film and SiC greatly affect the element characteristics. For example, silicon carbide, like silicon, can form silicon dioxide (SiO 2 ) by a thermal oxidation method, and the thermal oxidation method is also employed in the manufacturing process of the SiC-MOSFET. However, it is known that many interface states exist at the SiO 2 -SiC interface only by the thermal oxidation method. In particular, in a MOSFET using SiO 2 formed by thermal oxidation as a gate insulating film, channel mobility becomes extremely lower than mobility in the bulk due to the interface state close to the conduction band, and on-resistance increases. As a result, there was a problem that the device characteristics deteriorated.

そこで、熱酸化法で形成したSiO2―SiC界面の界面準位を低減させるため、表面の結晶方位が(0001)Si面を有するSiCに対し、一酸化窒素(NO)や一酸化二窒素(N2O)雰囲気中で熱処理する方法(特許文献1)や、表面の結晶方位が(000−1)C面を有するSiCに対し、H2雰囲気で熱処理する方法(特許文献2)により、界面準位密度を低減することが試みられている。 Therefore, in order to reduce the interface state of the SiO 2 —SiC interface formed by the thermal oxidation method, nitrogen monoxide (NO) or dinitrogen monoxide (NO) is compared with SiC having a (0001) Si surface crystal orientation. N 2 O) interface (Patent Document 1) or a surface crystal orientation of (000-1) SiC having a C-plane (H 2 atmosphere) (Patent Document 2) Attempts have been made to reduce the level density.

特開2005−223003号公報JP 2005-223003 A 特開2006−196713号公報JP 2006-196713 A

特許文献1,2に記載されている方法では、高温の熱処理によって熱酸化膜中に炭素原子が析出し、界面準位が誘起されたり、酸化膜の信頼性が低下してしまうなどの問題があった。さらに、熱酸化法やその後の高温の熱処理は、雰囲気ガスの切換や温度プロファイルの厳密な制御が必要で、しかも長時間の熱処理を行う必要があり、製造コストの増大を招いてしまうという問題があった。さらに所定の処理によって改善された界面準位密度の低減効果が、その後の製造工程の加熱処理によって劣化してしまうという問題があった。本発明は、上記問題点を解消し簡便かつ安価な方法で、SiO2―SiC界面の界面準位密度が低いMOS型構造の半導体装置の製造方法を提供することを目的とする。 In the methods described in Patent Documents 1 and 2, carbon atoms are precipitated in the thermal oxide film by high-temperature heat treatment, and interface states are induced, or the reliability of the oxide film is lowered. there were. Furthermore, the thermal oxidation method and the subsequent high-temperature heat treatment require switching of the atmospheric gas and strict control of the temperature profile, and it is necessary to perform heat treatment for a long time, resulting in an increase in manufacturing cost. there were. Furthermore, there has been a problem that the effect of reducing the interface state density improved by the predetermined treatment is deteriorated by the heat treatment in the subsequent manufacturing process. An object of the present invention is to provide a method for manufacturing a semiconductor device having a MOS type structure in which the interface state density at the SiO 2 —SiC interface is low by solving the above-described problems and using a simple and inexpensive method.

上記目的を達成するため、本願発明の炭化珪素半導体装置の製造方法は、半導体基板表面に積層する炭化珪素半導体層表面を、少なくとも窒素ガスを含む雰囲気中で、ECRスパッタ装置内で発生させたプラズマに晒す工程と、その後、真空状態を保ったまま、ECRスパッタ法により前記炭化珪素半導体層表面に二酸化珪素膜を堆積させる工程と、表面に二酸化珪素膜を堆積させた前記半導体基板を加熱処理する工程と、前記加熱処理された二酸化珪素膜表面に金属膜を積層し、MOS型構造の電極を形成する工程と、を備えたことを特徴とする。   In order to achieve the above object, a method of manufacturing a silicon carbide semiconductor device according to the present invention includes a plasma generated in an ECR sputtering apparatus on a silicon carbide semiconductor layer surface laminated on a semiconductor substrate surface in an atmosphere containing at least nitrogen gas. Exposing the semiconductor substrate, then depositing a silicon dioxide film on the surface of the silicon carbide semiconductor layer by ECR sputtering while maintaining a vacuum, and heat-treating the semiconductor substrate on which the silicon dioxide film is deposited. And a step of forming a MOS structure electrode by laminating a metal film on the surface of the heat-treated silicon dioxide film.

本発明の製造方法によれば、プラズマ処理工程と、それに連続して行う半導体層に対してダメージを与えることなく緻密な膜を短時間で制御性良く積層できるECRスパッタ法による二酸化珪素膜の形成工程と、加熱処理工程とを組合せて行うことで、特性の優れたMOS型構造の半導体装置を簡便かつ安価に製造することが可能となる。   According to the manufacturing method of the present invention, a silicon dioxide film can be formed by an ECR sputtering method capable of stacking a dense film in a short time and with good controllability without damaging the plasma processing step and the semiconductor layer continuously performed thereto. By performing the process and the heat treatment process in combination, it becomes possible to easily and inexpensively manufacture a semiconductor device having a MOS structure with excellent characteristics.

また本発明の製造方法によれば、1000℃〜1200℃の熱処理を施した後MOS型構造を形成するため、その後の製造工程で行われる熱処理によって特性が劣化することもなく、信頼性の高い半導体装置を形成することが可能となる。   Further, according to the manufacturing method of the present invention, the MOS type structure is formed after the heat treatment at 1000 ° C. to 1200 ° C., so that the characteristics are not deteriorated by the heat treatment performed in the subsequent manufacturing process, and the reliability is high. A semiconductor device can be formed.

本発明の第1の実施例のMOSダイオードの説明図である。It is explanatory drawing of the MOS diode of the 1st Example of this invention. 本発明のMOS型構造の電極の製造工程の説明図である。It is explanatory drawing of the manufacturing process of the electrode of the MOS type structure of this invention. 本発明のMOSダイオードのC−V特性の測定結果のグラフである。It is a graph of the measurement result of the CV characteristic of the MOS diode of this invention. プラズマ処理の効果を調べるための界面準位密度とエネルギー準位との相関を示すグラフである。It is a graph which shows the correlation of the interface state density and energy level for investigating the effect of a plasma processing. 本発明の第2の実施例の縦型MOSFETの製造工程の説明図である。It is explanatory drawing of the manufacturing process of the vertical MOSFET of 2nd Example of this invention.

本発明は、ECRスパッタ装置内で発生させたプラズマに炭化珪素半導体表面を晒す工程と、同一装置内で真空状態を保ったまま、ECRスパッタ法によりSiO2膜を堆積させる工程と、その後の加熱処理工程と、金属膜を積層する工程という、非常に簡便で、制御性の良い製造工程を組み合わせることによって、MOS型構造を形成することができる。以下、本発明の炭化珪素半導体装置の製造方法について、詳細に説明する。 The present invention includes a step of exposing a silicon carbide semiconductor surface to plasma generated in an ECR sputtering apparatus, a step of depositing a SiO 2 film by an ECR sputtering method while maintaining a vacuum state in the same apparatus, and subsequent heating. A MOS type structure can be formed by combining a processing process and a process of laminating metal films, which are very simple and have good controllability. Hereinafter, the manufacturing method of the silicon carbide semiconductor device of this invention is demonstrated in detail.

まず、本発明の炭化珪素半導体装置の製造方法について、MOSダイオードを例にとり詳細に説明する。図1は、MOSダイオードの断面図、図2はMOS型構造の電極の製造工程の説明図である。まず、表面の結晶方位が(000−1)C面4H−SiCからなるSiC基板1上に、エピタキシャル成長法を用いてn型SiCからなるエピタキシャル層2を形成する。このエピタキシャル層2の膜厚は1〜20μm程度で、不純物濃度は1×1015〜1×1017cm-3程度とする。 First, a method for manufacturing a silicon carbide semiconductor device of the present invention will be described in detail by taking a MOS diode as an example. FIG. 1 is a cross-sectional view of a MOS diode, and FIG. 2 is an explanatory view of a manufacturing process of an electrode having a MOS type structure. First, an epitaxial layer 2 made of n-type SiC is formed on an SiC substrate 1 having a surface crystal orientation of (000-1) C-plane 4H—SiC using an epitaxial growth method. The epitaxial layer 2 has a thickness of about 1 to 20 μm and an impurity concentration of about 1 × 10 15 to 1 × 10 17 cm −3 .

次に、エピタキシャル層2表面を有機溶剤、フッ酸等により洗浄し、表面に付着する不純物や酸化膜を除去した後、基板をECRスパッタ装置内に載置する。ECRスパッタ装置内には窒素(N2)ガスを導入し、所定の真空度に達したところで、導入した窒素をプラズマ化し、エピタキシャル層2表面をプラズマ処理する(S1)。このプラズマ処理は、例えば、装置内に導入する窒素ガス流量を6sccm、真空度0.03Pa、マイクロ波電源電圧500Wの条件で発生させた窒素プラズマに、エピタキシャル層2表面を30分間晒す工程とする。このプラズマ処理により、エピタキシャル層2表面に残留した酸化物や炭素などの不純物が除去され、清浄化される。このプラズマ処理には、窒素ガスの他、アルゴン(Ar)または酸素(O2)と窒素ガスの混合ガスを用いることができる。また、異なる混合ガスを用いた処理を複数回行うことも可能である。 Next, the surface of the epitaxial layer 2 is washed with an organic solvent, hydrofluoric acid or the like to remove impurities and oxide films adhering to the surface, and then the substrate is placed in an ECR sputtering apparatus. Nitrogen (N 2 ) gas is introduced into the ECR sputtering apparatus, and when the predetermined degree of vacuum is reached, the introduced nitrogen is turned into plasma and the surface of the epitaxial layer 2 is subjected to plasma treatment (S1). This plasma treatment is, for example, a step of exposing the surface of the epitaxial layer 2 for 30 minutes to nitrogen plasma generated under conditions of a nitrogen gas flow rate introduced into the apparatus of 6 sccm, a degree of vacuum of 0.03 Pa, and a microwave power supply voltage of 500 W. . By this plasma treatment, impurities such as oxide and carbon remaining on the surface of the epitaxial layer 2 are removed and cleaned. In this plasma treatment, in addition to nitrogen gas, argon (Ar) or a mixed gas of oxygen (O 2 ) and nitrogen gas can be used. It is also possible to perform the treatment using different mixed gases a plurality of times.

次に、連続してECRスパッタ装置の真空度を破らずに、プラズマ処理を施したエピタキシャル層2表面にSiO2膜3を堆積させる(S2)。このプラズマ処理とSiO2膜3の堆積工程を連続して行うことで、清浄化した表面状態を保ったままSiO2膜を堆積することが可能となる。SiO2膜堆積工程は、例えばシリコンターゲットを用い、アルゴンガス流量を15sccm、酸素ガス流量を7sccm、真空度0.10Pa、マイクロ波電源電圧500W、高周波(RF)電源電力500W、室温条件で、3分間処理すると50nmのSiO2膜3を堆積することができる。 Next, the SiO 2 film 3 is deposited on the surface of the epitaxial layer 2 subjected to the plasma treatment without breaking the vacuum degree of the ECR sputtering apparatus (S2). By continuously performing the plasma treatment and the deposition process of the SiO 2 film 3, it is possible to deposit the SiO 2 film while maintaining the cleaned surface state. In the SiO 2 film deposition process, for example, using a silicon target, the argon gas flow rate is 15 sccm, the oxygen gas flow rate is 7 sccm, the degree of vacuum is 0.10 Pa, the microwave power supply voltage is 500 W, the radio frequency (RF) power supply power is 500 W, and the room temperature is 3 When the treatment is performed for 50 minutes, a SiO 2 film 3 of 50 nm can be deposited.

次に、ECRスパッタ装置からSiC基板を取り出し、高温炉で加熱処理を行う(S3)。この加熱処理は、窒素雰囲気中で1200℃、2時間行う。この加熱処理により、堆積したSiO2膜3とエピタキシャル層2表面のSiCとの間で化学結合が促進され、界面準位密度の低いSiO2―SiCの界面構造が形成できる。ここで、窒素雰囲気中で熱処理するため、一般的に行われている熱酸化法と異なり、SiC表面から酸化によって炭素(C)が抜けることによって生じる欠陥や、炭素がSiO2膜中に拡散することによって発生するSiO2膜の劣化や信頼性低下が生じることもない。なお、雰囲気ガスは、アルゴン(Ar)または水素(H2)ガスと窒素ガスの混合ガス等に変更することも可能である。また加熱処理の温度は、MOS界面状態の改善のために少なくとも1000℃以上の温度とし、二酸化珪素の融点1400℃を越えない温度に設定する必要がある。特に上述にように、1200℃の加熱処理によって、特性改善の効果が大きい。 Next, the SiC substrate is taken out from the ECR sputtering apparatus and heat-treated in a high temperature furnace (S3). This heat treatment is performed at 1200 ° C. for 2 hours in a nitrogen atmosphere. By this heat treatment, chemical bonding is promoted between the deposited SiO 2 film 3 and SiC on the surface of the epitaxial layer 2, and an SiO 2 —SiC interface structure having a low interface state density can be formed. Here, since the heat treatment is performed in a nitrogen atmosphere, unlike the general thermal oxidation method, defects caused by carbon (C) escaping from the SiC surface by oxidation or carbon diffuses into the SiO 2 film. As a result, the SiO 2 film is not deteriorated and the reliability is not lowered. Note that the atmospheric gas can be changed to argon (Ar) or a mixed gas of hydrogen (H 2 ) gas and nitrogen gas. Further, the temperature of the heat treatment must be set to a temperature of at least 1000 ° C. or higher for improving the MOS interface state, and set to a temperature not exceeding the melting point of silicon dioxide of 1400 ° C. In particular, as described above, heat treatment at 1200 ° C. has a large effect of improving characteristics.

次に、SiO2膜3上にダイオードのアノード電極を形成するため、アルミニウム膜を蒸着形成する。これによりエピタキシャル層2上にSiO2膜3を介して金属膜が形成され、MOS構造を完成する(S4)。最後に、SiC基板1裏面にダイオードのカソード電極5を形成するため、アルミニウム膜を蒸着形成し、MOSダイオードが完成する。 Next, in order to form an anode electrode of a diode on the SiO 2 film 3, an aluminum film is deposited. As a result, a metal film is formed on the epitaxial layer 2 via the SiO 2 film 3 to complete the MOS structure (S4). Finally, in order to form the cathode electrode 5 of the diode on the back surface of the SiC substrate 1, an aluminum film is deposited and a MOS diode is completed.

図3は、上記の製造方法により形成したMOSダイオードのC−V特性の測定結果を示すグラフである。測定は、測定周波数100kHz、アノード電極に−10〜+10Vの電圧を印加して行った。比較のため、プラズマ処理した後SiO2膜を堆積させ、加熱処理なしで測定したもの(加熱処理無し)、プラズマ処理を行わず、SiO2膜を堆積した後、加熱処理して測定したもの(プラズマ処理無し)についても表示している。 FIG. 3 is a graph showing the measurement results of the CV characteristics of the MOS diode formed by the above manufacturing method. The measurement was performed by applying a voltage of −10 to +10 V to the anode electrode at a measurement frequency of 100 kHz. For comparison, a SiO 2 film was deposited after plasma treatment and measured without heat treatment (no heat treatment), and a SiO 2 film was deposited without plasma treatment and was measured by heat treatment ( (Plasma treatment not performed) is also displayed.

図3に示すように、加熱処理なしでは、C−V特性が蓄積領域に入っても酸化膜容量(COX)まで増加していないことがわかる。一方、加熱処理のみ行ったプラズマ処理なしでは、加熱処理なしと比べて、酸化膜容量が観測されMOS界面の状態が改善されていることがわかる。これと比較し本願発明では、C−V特性の容量変化が急峻となり、特性改善が更に進んでいることがわかる。 As shown in FIG. 3, it can be seen that without the heat treatment, the CV characteristic does not increase to the oxide film capacity (C OX ) even when entering the accumulation region. On the other hand, it can be seen that the oxide film capacitance is observed and the state of the MOS interface is improved without the plasma treatment in which only the heat treatment is performed, compared with the case without the heat treatment. In comparison with this, it can be seen that the capacitance change of the CV characteristic becomes steep in the present invention, and the characteristic improvement is further advanced.

次にプラズマ処理の有無の効果を確認するため、High−Low C−V法により界面準位密度(Dit)の測定を行った。図4は、界面準位密度とエネルギー準位との相関を示すグラフである。界面準位密度は、高周波C−V特性(測定周波数100kHz)と準性的C−V特性(ステップ電圧50mV、遅延時間1sec)の容量差から見積もった。図4に示すように、プラズマ処理を行わないものに比べて、本発明のプラズマ処理を行ったものは、界面準位密度が低く、MOS界面状態が改善されていることがわかる。特に、キャリア移動度に影響する伝導帯付近のエネルギー準位(Eit=0.2eV)付近の界面準位密度を比較すると、プラズマ処理なしの場合は、5.2×1012cm-2・eV-1であるのに対し、プラズマ処理ありの場合は、6.2×1011cm-2・eV-1となり、界面準位密度が1桁程度減少していることが確認できた。 Next, in order to confirm the effect of the presence or absence of plasma treatment, the interface state density (Dit) was measured by the High-Low C-V method. FIG. 4 is a graph showing the correlation between the interface state density and the energy level. The interface state density was estimated from the capacitance difference between the high-frequency CV characteristic (measurement frequency 100 kHz) and the quasi-qualitative CV characteristic (step voltage 50 mV, delay time 1 sec). As shown in FIG. 4, it can be seen that the plasma state of the present invention is lower in the interface state density and the MOS interface state is improved than the case where the plasma treatment is not performed. In particular, when comparing the interface state density in the vicinity of the energy level (Eit = 0.2 eV) in the vicinity of the conduction band affecting the carrier mobility, it is 5.2 × 10 12 cm −2 · eV in the case of no plasma treatment. In contrast, when the plasma treatment was performed, it was 6.2 × 10 11 cm −2 · eV −1 , and it was confirmed that the interface state density was reduced by about one digit.

なお、本実施例では、SiC基板上の表面の結晶方位が(000−1)C面の4H−SiCを用いたが、(0001)Si面4H−SiCや、ポリタイプの異なる6H―SiC、3C−SiCでも同様の効果が得られる。   In this example, 4H-SiC having a (000-1) C plane crystal orientation on the surface of the SiC substrate was used, but (0001) Si plane 4H-SiC, or 6H-SiC having a different polytype, Similar effects can be obtained with 3C-SiC.

次に第2の実施例として、縦型MOSFETの製造方法について説明する。まず、表面の結晶方位が(000−1)C面4H−SiCからなるSiC基板1上に、エピタキシャル成長法を用いてn型SiCからなるエピタキシャル層2を形成する。このエピタキシャル層2の膜厚は1〜20μm程度で、不純物濃度は1×1015〜1×1017cm-3程度とする。 Next, a vertical MOSFET manufacturing method will be described as a second embodiment. First, an epitaxial layer 2 made of n-type SiC is formed on an SiC substrate 1 having a surface crystal orientation of (000-1) C-plane 4H—SiC using an epitaxial growth method. The epitaxial layer 2 has a thickness of about 1 to 20 μm and an impurity concentration of about 1 × 10 15 to 1 × 10 17 cm −3 .

次に、エピタキシャル層2表面を有機溶剤、フッ酸等により洗浄し、表面に付着する不純物や酸化膜を除去した後、ベース領域を形成するため、フォトレジストを注入マスクとして使用し、エピタキシャル層2表面にアルミニウム(Al)をイオン注入し、p型拡散領域からなるベース領域6を形成する。さらに、ベース領域6内にソース領域及びドレイン領域を形成するため、別のフォトレジストを注入マスクとして使用し、ベース領域6が形成されたエピタキシャル層2表面にリン(P)をイオン注入し、n型拡散領域からなるソース領域7を形成する。注入された不純物イオンは、例えば1650℃、1分間の加熱処理を行い、活性化する(図5a)。   Next, the surface of the epitaxial layer 2 is washed with an organic solvent, hydrofluoric acid, etc., and after removing impurities and oxide films adhering to the surface, a photoresist is used as an implantation mask to form a base region. Aluminum (Al) is ion-implanted on the surface to form a base region 6 made of a p-type diffusion region. Further, in order to form a source region and a drain region in the base region 6, another photoresist is used as an implantation mask, phosphorus (P) is ion-implanted into the surface of the epitaxial layer 2 in which the base region 6 is formed, and n A source region 7 made of a mold diffusion region is formed. The implanted impurity ions are activated by heat treatment at 1650 ° C. for 1 minute, for example (FIG. 5a).

次に第1の実施例同様、エピタキシャル層2表面を有機溶剤、フッ酸等により洗浄し、表面に付着する不純物や酸化膜を除去した後、ECRスパッタ装置内に載置する。ECRスパッタ装置内には窒素(N2)ガスを導入し、所定の真空度に達したところで、導入した窒素をプラズマ化し、エピタキシャル層2表面をプラズマ処理する。このプラズマ処理は、例えば、装置内に導入する窒素ガス流量を6sccm、真空度0.03Pa、マイクロ波電源電圧500Wの条件で発生させた窒素プラズマに、表面を30分間晒して行う。このプラズマ処理により、表面に残留した酸化物や炭素などの不純物が除去され、清浄化される。このプラズマ処理には、窒素ガスの他、アルゴン(Ar)または酸素(O2)と窒素ガスの混合ガスを用いることができる。また、異なる混合ガスを用いた処理を複数回行うことも可能である。 Next, as in the first embodiment, the surface of the epitaxial layer 2 is washed with an organic solvent, hydrofluoric acid or the like to remove impurities and oxide films adhering to the surface, and then placed in an ECR sputtering apparatus. Nitrogen (N 2 ) gas is introduced into the ECR sputtering apparatus, and when the predetermined degree of vacuum is reached, the introduced nitrogen is turned into plasma, and the surface of the epitaxial layer 2 is plasma treated. This plasma treatment is performed, for example, by exposing the surface for 30 minutes to nitrogen plasma generated under the conditions of a flow rate of nitrogen gas introduced into the apparatus of 6 sccm, a degree of vacuum of 0.03 Pa, and a microwave power supply voltage of 500 W. By this plasma treatment, impurities such as oxide and carbon remaining on the surface are removed and cleaned. In this plasma treatment, in addition to nitrogen gas, argon (Ar) or a mixed gas of oxygen (O 2 ) and nitrogen gas can be used. It is also possible to perform the treatment using different mixed gases a plurality of times.

次に、連続してECRスパッタ装置の真空度を破らずに、プラズマ処理を施したエピタキシャル層2、ベース領域6及びソース領域7表面にSiO2膜3を堆積させる。このプラズマ処理とSiO2膜3の堆積工程を連続して行うことで、清浄化した表面状態を保ったままSiO2膜を堆積することが可能となる。SiO2膜堆積工程は、例えばシリコンターゲットを用い、アルゴンガス流量を15sccm、酸素ガス流量を7sccm、真空度0.10Pa、マイクロ波電源電圧500W、高周波(RF)電源電力500W、室温の条件で、3分間処理すると50nmのSiO2膜3を堆積することできる。このSiO2膜3は、ゲート絶縁膜となる。次に、ECRスパッタ装置からSiC基板を取り出し、高温炉で加熱処理を行う。この加熱処理は、窒素雰囲気中で1200℃、2時間行い、SiO2―SiC接合を形成する(図5b)。 Next, the SiO 2 film 3 is deposited on the surfaces of the epitaxial layer 2, the base region 6 and the source region 7 that have been subjected to the plasma treatment without continuously breaking the degree of vacuum of the ECR sputtering apparatus. By continuously performing the plasma treatment and the deposition process of the SiO 2 film 3, it is possible to deposit the SiO 2 film while maintaining the cleaned surface state. In the SiO 2 film deposition process, for example, using a silicon target, the argon gas flow rate is 15 sccm, the oxygen gas flow rate is 7 sccm, the degree of vacuum is 0.10 Pa, the microwave power supply voltage is 500 W, the radio frequency (RF) power supply power is 500 W, and the room temperature is When the treatment is performed for 3 minutes, a 50 nm SiO 2 film 3 can be deposited. This SiO 2 film 3 becomes a gate insulating film. Next, the SiC substrate is taken out from the ECR sputtering apparatus and heat-treated in a high temperature furnace. This heat treatment is performed in a nitrogen atmosphere at 1200 ° C. for 2 hours to form a SiO 2 —SiC bond (FIG. 5b).

SiO2膜3上に化学的気相成長(CVD)法により、多結晶シリコン(ポリシリコン)膜を形成し、所定の形状にパターニングすることにより、ゲート電極8を形成する。その後、ゲート絶縁膜9を残し、ソース領域6上のSiO2膜3を除去し、ソース領域7表面を露出させ、露出したソース領域7表面に、ニッケル(Ni)からなるソース電極10を形成する。さらにSiC基板1裏面にドレイン電極を形成するため、ニッケルからなるドレイン電極11を形成する。ソース電極7及びドレイン電極11のオーミック接合を形成するため、窒素雰囲気中で950℃、2分間の加熱処理を行い、縦型MOSFETを完成する(図5c)。この加熱処理条件は、SiO2膜3を堆積させた後にSiO2―SiCのMOS構造の形成する際の加熱処理条件より加熱温度が低く、加熱時間も短いため、先に形成したMOS構造の界面状態が劣化することはない。 A polycrystalline silicon (polysilicon) film is formed on the SiO 2 film 3 by chemical vapor deposition (CVD), and patterned into a predetermined shape, thereby forming a gate electrode 8. Thereafter, the gate insulating film 9 is left, the SiO 2 film 3 on the source region 6 is removed, the surface of the source region 7 is exposed, and a source electrode 10 made of nickel (Ni) is formed on the exposed surface of the source region 7. . Furthermore, in order to form a drain electrode on the back surface of the SiC substrate 1, a drain electrode 11 made of nickel is formed. In order to form an ohmic junction between the source electrode 7 and the drain electrode 11, a heat treatment is performed at 950 ° C. for 2 minutes in a nitrogen atmosphere to complete a vertical MOSFET (FIG. 5c). This heat treatment condition is that the heating temperature is lower than the heat treatment condition when the SiO 2 -SiC MOS structure is formed after the SiO 2 film 3 is deposited and the heating time is shorter, so that the interface of the previously formed MOS structure The state does not deteriorate.

本実施例においても、先に説明した第1の実施例同様、界面準位密度の少ないMOS構造となるため、形成された縦型MOSFETは、チャネル移動が高まり、オン抵抗が低減し、スイッチング動作における電力変換効率(電力損失)を改善することができた。   Also in this embodiment, since the MOS structure with a low interface state density is formed as in the first embodiment described above, the formed vertical MOSFET has increased channel movement, reduced on-resistance, and switching operation. The power conversion efficiency (power loss) in can be improved.

1: SiC基板、2:エピタキシャル層、3:SiO2膜、4:アノード電極、5:カソード電極、6:ベース領域、7:ソース領域、8:ゲート電極、9:ゲート絶縁膜、10:ソース電極、11:ドレイン電極 1: SiC substrate, 2: epitaxial layer, 3: SiO 2 film, 4: anode electrode, 5: cathode electrode, 6: base region, 7: source region, 8: gate electrode, 9: gate insulating film, 10: source Electrode, 11: drain electrode

Claims (1)

半導体基板表面に積層する炭化珪素半導体層表面を、少なくとも窒素ガスを含む雰囲気中で、ECRスパッタ装置内で発生させたプラズマに晒す工程と、
その後、真空状態を保ったまま、ECRスパッタ法により前記炭化珪素半導体層表面に二酸化珪素膜を堆積させる工程と、
表面に二酸化珪素膜を堆積させた前記半導体基板を加熱処理する工程と、
前記加熱処理された二酸化珪素膜表面に金属膜を積層し、MOS型構造の電極を形成する工程と、を備えたことを特徴とする炭化珪素半導体装置の製造方法。
Exposing the silicon carbide semiconductor layer surface laminated on the semiconductor substrate surface to plasma generated in an ECR sputtering apparatus in an atmosphere containing at least nitrogen gas;
Then, a step of depositing a silicon dioxide film on the surface of the silicon carbide semiconductor layer by ECR sputtering while maintaining a vacuum state;
Heat-treating the semiconductor substrate having a silicon dioxide film deposited on the surface;
And a step of laminating a metal film on the surface of the heat-treated silicon dioxide film to form an electrode having a MOS structure.
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