JP2014099430A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which uses an oxide semiconductor layer and has less variation in electric characteristics; and provide a fine semiconductor device capable of high-speed drive and a high-speed operation, which is highly reliable and exhibits stable electric characteristics; and manufacture the semiconductor device.SOLUTION: A semiconductor device comprises: a multilayer film including an oxide semiconductor layer and an oxide layer which enwraps the oxide semiconductor layer: a laminate of a gate insulation film on the multilayer film and a gate electrode; a source electrode and a drain electrode; and a protective insulation film on the multilayer film, the gate insulation film, the gate electrode, the source electrode and the drain electrode. The multilayer film has a cross section with ends each having curvature.

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

A technique for forming a transistor (also referred to as a thin film transistor (TFT)) using a semiconductor thin film has attracted attention. The transistor is widely applied to an electronic device such as an integrated circuit (IC) or an image display device. A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

For example, a transistor using an amorphous oxide containing indium (In), gallium (Ga), and zinc (Zn) is disclosed as a channel formation region of the transistor (see Patent Document 1).

In addition, it is known that an oxide semiconductor loses oxygen during a manufacturing process and forms an oxygen vacancy (see Patent Document 2).

JP 2006-165528 A JP 2011-222767 A

During the manufacturing process, oxygen desorption or oxygen vacancies are particularly likely to occur on the side surfaces of the oxide semiconductor layer. When oxygen vacancies occur in the side surface of the oxide semiconductor layer, the resistance of the side surface is reduced, the apparent threshold voltage of the transistor fluctuates, and variations in threshold voltage increase. In addition, when the threshold voltage fluctuates, an unintended current flows between the source and drain, the off-state current of the transistor increases, and the electrical characteristics of the transistor deteriorate.

Further, in a transistor including an oxide semiconductor, it is important to reduce the size of the transistor in order to achieve high-speed operation of the transistor, low power consumption, low price, and the like.

However, miniaturization increases the influence of oxygen vacancies and the like generated during the manufacturing process, which causes deterioration of transistor electrical characteristics such as an increase in off-state current and variation in threshold voltage.

In view of such a problem, an object of one embodiment of the present invention is to provide a semiconductor device in which variation in electric characteristics is small in a semiconductor device including an oxide semiconductor layer. It is another object of the present invention to provide a highly reliable and stable semiconductor device that can be driven at high speed and operated at high speed. Another object is to provide a semiconductor device having stable electrical characteristics. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a semiconductor device with few shape defects. Another object is to provide a method for manufacturing the semiconductor device. Another object is to provide a method for manufacturing a semiconductor device with high productivity. Another object is to provide a method for manufacturing a semiconductor device with high yield.

A semiconductor device of one embodiment of the present invention includes an oxide semiconductor layer, a multilayer film including an oxide layer surrounding the oxide semiconductor layer, a stack of a gate insulating film and a gate electrode over the multilayer film, a source electrode, and a drain The semiconductor device includes an electrode and a protective film over the multilayer film, the gate insulating film, the gate electrode, the source electrode, and the drain electrode, and the multilayer film has a curvature at one end in one cross section.

The oxide semiconductor layer and the oxide layer contain at least indium, the oxide layer has a larger energy gap than the oxide semiconductor layer, and the content ratio of indium in the oxide semiconductor layer is the content ratio of indium in the oxide layer. Higher than. Typically, an oxide containing indium, zinc, and the element M may be used as the oxide semiconductor layer and the oxide layer. Further, the content ratio of the element M in the oxide layer is preferably higher than that in the oxide semiconductor layer.

As the element M, an oxide having a high content ratio such as gallium, aluminum, silicon, titanium, germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium is preferably used. These elements are strongly bonded to oxygen and have high oxygen deficiency formation energy, so that oxygen deficiency is unlikely to occur. Therefore, an oxide layer having these elements at a high atomic ratio is an oxide layer that has stable characteristics in which oxygen vacancies are less likely to occur. Therefore, by wrapping the surface of the oxide semiconductor layer with the oxide layer, oxygen vacancies are hardly formed at the end portion of the oxide semiconductor layer, and a semiconductor device having stable characteristics can be obtained.

Moreover, in one cross section of the multilayer film, the end portion has a curvature, so that the coverage of the film formed on the multilayer film can be improved. By doing so, a film formed over the multilayer film can be formed uniformly, and an impurity element enters the multilayer film from a region having a low film density or a region where no film is formed. Therefore, it is possible to suppress the deterioration of the characteristics of the semiconductor device and to obtain a semiconductor device with stable characteristics. Note that it is particularly preferable that the entire end portion, the lower end portion, or the lower end portion and the upper end portion of the multilayer film have curved surfaces.

The oxide layer includes a first oxide layer below the oxide semiconductor layer, a second oxide layer on the oxide semiconductor layer, and a third oxide layer covering a side surface of the oxide semiconductor layer. It is good also as a structure containing. Further, the distance between the surface of the oxide semiconductor layer and the surface of the oxide layer may be wider at the side portion than at the upper portion of the multilayer film. Further, the thickness of the multilayer film may be 1/50 to 50 times the curvature radius of the curved surface on the side surface. With such a structure, a decrease in reliability of the semiconductor device including the oxide layer that wraps the oxide semiconductor layer can be suppressed.

Further, a base insulating film may be provided under the multilayer film. The film thickness of the region overlapping with the multilayer film of the base insulating film is larger than that of other regions. The base insulating film includes a first region overlapping with the multilayer film, a second region surrounding the first region, and a third region surrounding the second region. The film thickness is preferably smaller than that of the first region, and the film thickness of the third region is preferably smaller than that of the second region. Since the base insulating film has a stepped shape (also referred to as a step), the step coverage of the film formed over the base insulating film and the multilayer film is improved, and the shape of the semiconductor device is improved. Defects and the like can be suppressed.

In addition, the protective insulating film preferably includes a silicon nitride layer or a silicon nitride oxide layer that releases at least one of hydrogen and nitrogen in thermal desorption gas spectroscopy. By providing such an insulating layer, the carrier density of the multilayer film can be increased and the resistance can be reduced in a region in contact with the protective insulating film. When the region is provided between the source electrode and the drain electrode of the transistor, resistance between the source electrode and the drain electrode is reduced, so that the field-effect mobility of the transistor can be increased.

Another embodiment of the present invention is a method in which a first oxide film, an oxide semiconductor film, and a second oxide film are sequentially stacked, and a resist is formed over the second oxide film. A mask is formed, and using the resist mask, first etching is performed on the second oxide film and the oxide semiconductor film to form island-shaped second oxide layers and oxide semiconductor layers. By performing the second etching on the oxide film, an island-shaped first oxide layer is formed, and a reaction product during the second etching is attached to the side surface of the oxide semiconductor layer to oxidize the oxide film. This is a method for manufacturing a semiconductor device in which a third oxide layer is formed on a side surface of a physical semiconductor layer.

Note that heat treatment may be performed in an oxidizing gas atmosphere after the resist mask is removed.

According to one embodiment of the present invention, variation in electrical characteristics of a semiconductor device including an oxide semiconductor layer can be reduced. In addition, the reliability of a fine semiconductor device capable of high-speed driving and high-speed operation can be improved, and a semiconductor device exhibiting stable electrical characteristics can be provided. In addition, the semiconductor device can be manufactured.

FIG. 6 is a cross-sectional view of a multilayer film according to one embodiment of the present invention. The figure explaining a curvature radius. FIG. 6 is a cross-sectional view illustrating a multilayer film formation mechanism according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a multilayer film formation mechanism according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a multilayer film formation mechanism according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a multilayer film formation mechanism according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a multilayer film formation mechanism according to one embodiment of the present invention. 4A and 4B illustrate the number of particles in an oxide layer and an oxide semiconductor layer according to one embodiment of the present invention. FIG. 6 shows a ToF-SIMS result of a multilayer film according to one embodiment of the present invention. 4A and 4B illustrate a band structure of a multilayer film according to one embodiment of the present invention. 4A and 4B illustrate a band structure of a multilayer film according to one embodiment of the present invention. FIG. 6 shows oxygen diffusion in a multilayer film according to one embodiment of the present invention. FIG. 6 shows CPM measurement results of a multilayer film according to one embodiment of the present invention. 4 is an electron transmission image of a multilayer film according to one embodiment of the present invention by TEM. The figure which showed a mode that sputtered particle was peeled from the target. FIG. 6 illustrates an example of a crystal structure of an In—Ga—Zn oxide. The schematic diagram which showed a mode that sputtered particle reached | attains a film-forming surface and deposited. The top view which shows an example of the film-forming apparatus. Sectional drawing which shows an example of the film-forming chamber. The figure which shows an example of a heat processing chamber. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a semiconductor device according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A and 6B are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 10 is a block diagram illustrating an example of a semiconductor device according to one embodiment of the present invention. FIG. 14 is a cross-sectional view illustrating an example of a semiconductor device of one embodiment of the present invention. FIG. 10 is a block diagram illustrating an example of a CPU according to one embodiment of the present invention. FIG. 14 illustrates an example of an electronic device according to one embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed. In addition, the present invention is not construed as being limited to the description of the embodiments below. Note that in describing the structure of the present invention with reference to drawings, the same portions are denoted by the same reference numerals in different drawings. In addition, when referring to the same thing, a hatch pattern is made the same and there is a case where it does not attach | subject a code | symbol in particular.

In an actual manufacturing process, a resist mask or the like may be unintentionally lost due to a process such as etching, but may be omitted for easy understanding.

The ordinal numbers attached as the first and second are used for convenience, and do not indicate the order of steps or the order of lamination. In addition, a specific name is not shown as a matter for specifying the invention in this specification.

In many cases, the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential.

Even when expressed as “electrically connected”, in an actual circuit, there is a case where there is no physical connection portion and the wiring is merely extended.

In addition, the functions of the source and drain may be interchanged when the direction of current changes during circuit operation. Therefore, in this specification, the terms source and drain can be used interchangeably.

Note that the contents described in this embodiment can be combined as appropriate.

1. Hereinafter, a multilayer film including an oxide semiconductor layer which has stable electrical characteristics when used in a transistor will be described.

1-1. In this section, the structure of the multilayer film will be described.

1A to 1D illustrate a cross-sectional structure of the multilayer film 106. FIG. The multilayer film 106 includes an oxide layer 106a, an oxide semiconductor layer 106b provided over the oxide layer 106a, an oxide layer 106c provided over the oxide semiconductor layer 106b, and at least an oxide semiconductor layer 106b. And an oxide layer 106d provided in contact with the side surface. Note that the oxide layer 106d has a curved surface.

In one side surface of one cross section of the multilayer film 106 illustrated in FIGS. 1A and 1B, the oxide layer 106 d has a curvature (curved surface) including one contact circle (also referred to as a curvature circle). . In addition, in one side surface of one cross section of the multilayer film 106 illustrated in FIGS. 1C and 1D, the oxide layer 106d has a curvature of one contact circle at each of an upper end portion and a lower end portion.

As shown in FIGS. 1A and 1C, the multilayer film 106 has an angle formed between the side surfaces of the oxide layer 106a, the oxide semiconductor layer 106b, and the oxide layer 106c and the lower surface of the oxide layer 106a. It may be substantially vertical, and may have an inclination (taper angle) as shown in FIG. 1 (B) and FIG. 1 (D).

In this manner, by including the oxide layer 106 d having a curved surface on a side surface that is part of the multilayer film 106, generation of a defective shape of a transistor using the multilayer film 106 can be suppressed.

1-1-1. A curved surface included in the oxide layer oxide layer 106d constituting the end portion of the multilayer film will be described with reference to FIGS.

2A is a cross-sectional view of the oxide layer 106d corresponding to one side surface of the cross section of the multilayer film 106 illustrated in FIGS. 1A and 1B. The oxide layer 106d illustrated in FIG. 2A has a curvature including a contact circle having a curvature radius r. The curvature radius is equal to the radius of the contact circle of curvature.

2B is a cross-sectional view of the oxide layer 106d corresponding to one side surface of the cross section of the multilayer film 106 illustrated in FIGS. 1C and 1D. The oxide layer 106d illustrated in FIG. 2B has curvatures of contact circles with a curvature radius r at the upper end and the lower end, respectively. In addition, the curvature of an upper end part and a lower end part may have a different curvature radius, respectively.

The oxide layer 106d illustrated in FIG. 2C has a curvature including a contact circle having a curvature radius r. Note that the oxide layer 106d may have two or three curvatures made of different contact circles.

At this time, the curvature radius r is 1/50 to 50 times the thickness t of the multilayer film 106 (the total thickness of the oxide layer 106a, the oxide semiconductor layer 106b, and the oxide layer 106c), preferably Is from 1/20 to 20 times, more preferably from 1/10 to 10 times, more preferably from 1/5 to 5 times.

1-2. Formation mechanism of multilayer film A formation mechanism of the multilayer film 106 having a curved surface 106d will be described.

1-2-1. Formation mechanism (1)
An example of a formation mechanism of the multilayer film 106 having a curved surface 106d will be described with reference to FIGS.

First, an oxide layer 136a provided over the base insulating film 132, an oxide semiconductor layer 136b provided over the oxide layer 136a, and an oxide layer 136c provided over the oxide semiconductor layer 136b, A multilayer film is prepared (see FIG. 3A).

Next, a resist mask 140 is formed over part of the oxide layer 136c (see FIG. 3B).

Next, the oxide layer 136c and the oxide semiconductor layer 136b in a region where the resist mask 140 is not provided are etched by a dry etching method to expose the oxide layer 136a (see FIG. 3C).

Next, the exposed oxide layer 136a is etched by a dry etching method (see FIG. 4A). At this time, a reaction product of the oxide layer 136a is reattached to at least a side surface of the oxide semiconductor layer 106b of the multilayer film, so that an oxide layer which is a sidewall protective film (also called a rabbit ear) is formed. Note that the reaction product of the oxide layer 136a is reattached by a sputtering phenomenon and is reattached via the plasma 150 during dry etching. The dry etching may be performed by, for example, using boron trichloride gas and chlorine gas as an etching gas and applying inductively coupled plasma (ICP) power and substrate bias power.

Subsequently, the oxide layer 136a is etched, whereby the oxide layer 106a and the oxide layer 137d are formed. At this time, part of the base insulating film 132 is also etched to form the base insulating film 133 (see FIG. 4B).

Note that since the oxide layer 137d is a reaction product of the oxide layer 136a, components (such as chlorine and boron) derived from the etching gas used during etching remain. When the component reacts with moisture in the atmosphere or the like, the oxide layer 137d is further etched.

Next, the component derived from the etching gas remaining in the etched oxide layer 137d is removed by an ashing process, so that an oxide layer to be the oxide layer 106d is formed.

Next, the resist mask 140 is removed.

Next, heat treatment is performed in an atmosphere containing an oxidizing gas, so that oxygen vacancies in the oxide layers to be the oxide layer 106a, the oxide semiconductor layer 106b, the oxide layer 106c, and the oxide layer 106d are reduced. In particular, the oxide layer to be the oxide layer 106d is formed from a reaction product at the time of etching, and thus oxygen vacancies are likely to occur. Therefore, the oxide layer to be the oxide layer 106d is formed into the oxide layer 106d with extremely low carrier density by the above-described ashing treatment and heat treatment (see FIG. 4C). Note that the oxidizing gas refers to a gas such as oxygen, nitrous oxide, or ozone. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C. The atmosphere for the heat treatment is an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. .

As described above, the multilayer film 106 including the oxide layer 106d having a curved surface can be formed. Therefore, it can be seen that a dedicated photomask or the like is not necessary for forming the oxide layer 106d in order to form the multilayer film 106 including the oxide layer 106d having a curved surface.

In addition, the oxide layer 106a, the oxide layer 106c, and the oxide layer 106d formed in this manner may not be strictly distinguishable. Therefore, the oxide layer 106a, the oxide layer 106c, and the oxide layer 106d may be collectively referred to as the oxide layer 105. As illustrated in FIG. 5A, the oxide layer 105 that surrounds the oxide semiconductor layer 106b may be combined into a multilayer film 106.

Next, the base insulating film 133 may be formed by etching the base insulating film 133 so as to have a plurality of steps (here, two steps) (see FIG. 5B). In other words, the base insulating film 102 has two steps, and the base insulating film 102 has three regions having different thicknesses.

1-2-2. Formation mechanism (2)
An example of a formation mechanism of the multilayer film 106 having a curved surface 106d will be described with reference to FIGS.

First, an oxide layer 136a provided over the base insulating film 132, an oxide semiconductor layer 136b provided over the oxide layer 136a, and an oxide layer 136c provided over the oxide semiconductor layer 136b, A multilayer film is prepared (see FIG. 6A).

Next, a resist mask 140 is formed over part of the oxide layer 136c (see FIG. 6B).

Next, the oxide layer 136c, the oxide semiconductor layer 136b, and the oxide layer 136a in the region where the resist mask 140 is not provided are etched by dry etching, and the oxide layer 156c, the oxide semiconductor layer 156b, and the oxide layer are etched, respectively. The physical layer is 156a. At this time, part of the base insulating film 132 is also etched to form the base insulating film 152 (see FIG. 6C). Note that the oxide layer 156c, the oxide semiconductor layer 156b, and the oxide layer 156a have taper angles.

Next, the oxide layer 156c, the oxide semiconductor layer 156b, and the oxide layer 156a are etched by a dry etching method to form the oxide layer 106c, the oxide semiconductor layer 106b, and the oxide layer 106a, respectively. At this time, the reaction product of the oxide layer 156a is reattached to the side surface of the multilayer film to form an oxide layer to be the oxide layer 106d which is a sidewall protective film (also called a rabbit ear). Note that the reaction product of the oxide layer 156a is reattached by a sputtering phenomenon and is reattached through plasma during dry etching. At this time, part of the base insulating film 152 is also etched to be the base insulating film 102 (see FIG. 7A).

Note that since the oxide layer to be the oxide layer 106d is a reaction product of the oxide layer 156a, components (such as chlorine and boron) derived from the etching gas used during etching remain.

Next, the component derived from the etching gas remaining in the oxide layer to be the oxide layer 106d is removed by an ashing process.

Next, the resist mask 140 is removed.

Next, heat treatment is preferably performed in an atmosphere containing an oxidizing gas to reduce oxygen vacancies in the oxide layers to be the oxide layer 106a, the oxide semiconductor layer 106b, the oxide layer 106c, and the oxide layer 106d. In particular, the oxide layer to be the oxide layer 106d is formed from a reaction product at the time of etching, and thus oxygen vacancies are likely to occur. Therefore, the oxide layer to be the oxide layer 106d is formed into the oxide layer 106d with extremely low carrier density by the above-described ashing treatment and heat treatment (see FIG. 7B).

As described above, the multilayer film 106 including the oxide layer 106d having a curved surface can be formed. Therefore, it can be seen that a dedicated photomask or the like is not necessary for forming the oxide layer 106d in order to form the multilayer film 106 including the oxide layer 106d having a curved surface.

As described above, the oxide layer 106d is formed from a reaction product of the oxide layer 136a that becomes the oxide layer 106a. Therefore, the oxide layer 106a and the oxide layer 106d may not be distinguished by analysis or the like. In other words, the oxide layer 106d may be an oxide layer having the same physical properties as the oxide layer 106a. Therefore, the description of the oxide layer 106a can be referred to when the physical properties of the oxide layer 106d are not particularly described. Further, the oxide layer 106c may be indistinguishable from the oxide layer 106d in the case where the structure is similar to that of the oxide layer 106a. Therefore, the oxide layer 106a, the oxide layer 106c, and the oxide layer 106d may be collectively referred to as the oxide layer 105. As illustrated in FIG. 7C, the oxide layer 105 that surrounds the oxide semiconductor layer 106b may be combined into a multilayer film 106.

The multilayer film 106 has a structure in which the oxide semiconductor layer 106b is surrounded (covered) by the oxide layer 106a, the oxide layer 106c, and the oxide layer 106d. Accordingly, the entry of impurities into the oxide semiconductor layer 106b can be reduced. Further, since the oxide semiconductor layer 106b does not have a level with another oxide layer, carrier mobility (electron mobility) can be increased.

1-3. In this section, the physical properties of the multilayer film will be described.

1-3-1. Hereinafter, the composition of the multilayer film 106 and the composition of the oxide layer 106a, the oxide semiconductor layer 106b, the oxide layer 106c, and the oxide layer 106d included in the multilayer film 106 will be described.

The oxide layer 106a is an oxide layer including one or more elements constituting the oxide semiconductor layer 106b, or two or more elements. Note that the oxide semiconductor layer 106b preferably contains at least indium because carrier mobility (electron mobility) is increased. Since the oxide layer 106a is formed of one or more elements or two or more elements included in the oxide semiconductor layer 106b, interface scattering is unlikely to occur at the interface between the oxide semiconductor layer 106b and the oxide layer 106a. Accordingly, the movement of carriers is not inhibited at the interface, so that the field effect mobility of the transistor is increased.

For example, the oxide layer 106a may be an oxide layer containing aluminum, titanium, silicon, gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium at a higher atomic ratio than the oxide semiconductor layer 106b. . Specifically, as the oxide layer 106a, an oxide layer containing the above-described element in an atomic ratio higher than that of the oxide semiconductor layer 106b by 1.5 times or more, preferably 2 times or more, more preferably 3 times or more. Use. The aforementioned element is strongly bonded to oxygen and thus has a function of suppressing generation of oxygen vacancies in the oxide layer. In other words, the oxide layer 106a is an oxide layer in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 106b.

Alternatively, when the oxide semiconductor layer 106b is an In-M-Zn oxide and the oxide layer 106a is also an In-M-Zn oxide, the oxide layer 106a is replaced with In: M: Zn = x ₁ : y _1. : Z ₁ [atomic number ratio] and the oxide semiconductor layer 106b is In: M: Zn = x ₂ : y ₂ : z ₂ [atomic number ratio], y ₁ / x ₁ is more than y ₂ / x ₂ The oxide layer 106a and the oxide semiconductor layer 106b to be enlarged are selected. Note that the element M is a metal element having a stronger bonding force with oxygen than In, and examples thereof include Al, Ti, Ga, Y, Zr, Sn, La, Ce, Nd, and Hf. Preferably, the oxide layer 106a and the oxide semiconductor layer 106b in which y ₁ / x ₁ is 1.5 times or more larger than y ₂ / x ₂ are selected. More preferably, the oxide layer 106a and the oxide semiconductor layer 106b in which y ₁ / x ₁ is twice or more larger than y ₂ / x ₂ are selected. More preferably, the oxide layer 106a and the oxide semiconductor layer 106b in which y ₁ / x ₁ is three times or more larger than y ₂ / x ₂ are selected. At this time, in the oxide semiconductor layer 106b, it is preferable that y1 be x1 or more because stable electrical characteristics can be imparted to the transistor. However, when y1 is 3 times or more of x1, the field-effect mobility of the transistor is lowered. Therefore, y1 is preferably the same as x1 or less than 3 times.

The oxide layer 106c includes one or more elements or two or more elements included in the oxide semiconductor layer 106b. Since the oxide layer 106c is formed using one or more elements or two or more elements included in the oxide semiconductor layer 106b, an interface state is hardly formed at the interface between the oxide semiconductor layer 106b and the oxide layer 106c. When the interface has an interface state, a second transistor having a threshold voltage different from that of the interface is formed, and the apparent threshold voltage of the transistor may fluctuate. Therefore, by providing the oxide layer 106c, variation in electrical characteristics such as threshold voltage of the transistor can be reduced.

For example, the oxide layer 106c may be an oxide layer containing aluminum, silicon, titanium, gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium at a higher atomic ratio than the oxide semiconductor layer 106b. . Specifically, the oxide layer 106c includes an oxide layer containing the above-described element in an atomic ratio higher than that of the oxide semiconductor layer 106b by 1.5 times or more, preferably 2 times or more, more preferably 3 times or more. Use. The aforementioned element is strongly bonded to oxygen and thus has a function of suppressing generation of oxygen vacancies in the oxide layer. In other words, the oxide layer 106c is an oxide layer in which oxygen vacancies are less likely to occur than in the oxide semiconductor layer 106b.

Alternatively, when the oxide semiconductor layer 106b is an In-M-Zn oxide and the oxide layer 106c is also an In-M-Zn oxide, the oxide semiconductor layer 106b is replaced with In: M: Zn = x ₂ : y. _{2: z 2} [atomic ratio], the oxide layer _{106c In: M: Zn = x} 3: y 3: When _{z 3} [atomic _ratio], than y 3 / _{x 3} is _y 2 / _{x 2} The oxide semiconductor layer 106b and the oxide layer 106c to be enlarged are selected. Note that the element M is a metal element having a stronger bonding force with oxygen than In, and examples thereof include Al, Ti, Ga, Y, Zr, Sn, La, Ce, Nd, and Hf. Preferably, the oxide semiconductor layer 106b and the oxide layer 106c in which y ₃ / x ₃ is 1.5 times or more larger than y ₂ / x ₂ are selected. More preferably, the oxide semiconductor layer 106b and the oxide layer 106c in which y ₃ / x ₃ is twice or more larger than y ₂ / x ₂ are selected. More preferably, the oxide semiconductor layer 106b and the oxide layer 106c in which y ₃ / x ₃ is three times or more larger than y ₂ / x ₂ are selected. At this time, it is preferable that y2 be x2 or more in the oxide semiconductor layer 106b because stable electrical characteristics can be imparted to the transistor. However, when y2 is 3 times or more of x2, the field effect mobility of the transistor is lowered. Therefore, y2 is preferably the same as x2 or less than 3 times.

For the oxide layer 106d, the description of the oxide layer 106a is referred to. The oxide layer 106 d is a layer that forms the side surface of the multilayer film 106. Therefore, in the case where the oxide layer 106d is a layer in which oxygen vacancies are unlikely to occur, a second transistor with a different threshold voltage using the interface as a channel is formed at the interface between the oxide layer 106d and the oxide semiconductor layer 106b. The apparent threshold voltage of the transistor may fluctuate. Therefore, by providing the oxide layer 106d, variation in electrical characteristics such as threshold voltage of the transistor can be reduced. The variation in electrical characteristics due to the second transistor becomes more significant as the channel length is shorter. Therefore, the more miniaturized transistor has a higher effect by providing the oxide layer 106d.

Note that when indium contained in the oxide layer 106c is diffused outward, the electrical characteristics of the transistor may be deteriorated; therefore, the oxide layer 106c may have a smaller atomic ratio of indium than the oxide semiconductor layer 106b. preferable.

Note that the oxide layer 106a and the oxide layer 106d are preferably oxide layers in which oxygen vacancies are less likely to occur than in the oxide layer 106c. The oxide layer 106a and the oxide layer 106d are preferably oxide layers having higher insulating properties than the oxide layer 106c. In order for the oxide layer 106a and the oxide layer 106d to have less oxygen vacancies than the oxide layer 106c and to have high insulating properties, the oxygen vacancies included in the oxide layers 106a and 106d are oxides. An element that suppresses generation in the layer or a metal element that has a strong binding force to oxygen is preferably contained at a concentration higher than that of the oxide layer 106c.

Note that the thickness of the oxide layer 106a is 3 nm to 100 nm, preferably 3 nm to 50 nm. The thickness of the oxide semiconductor layer 106b is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm. Note that the thickness of the oxide layer 106c is 3 nm to 50 nm, preferably 3 nm to 20 nm. Note that the thickness of the oxide layer 106a and the oxide layer 106d is preferably larger than that of the oxide layer 106c. In other words, the thickness of the oxide layer 106c is preferably smaller than that of the oxide layer 106a and the oxide layer 106d.

Next, an oxide layer applicable to the oxide layer 106a, the oxide layer 106c, and the oxide layer 106d used for the multilayer film 106 was formed by a sputtering method, and the number of particles of 1 μm or more was measured.

The measurement is performed using a sample formed using a gallium oxide target, a sample formed using a Ga—Zn oxide (Ga: Zn = 2: 5 [atomic ratio]) target, and an In—Ga—Zn oxide ( In: Ga: Zn = 3: 1: 2 [atomic ratio]) Sample formed using a target, In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio]) ) A sample formed using a target and a sample formed using an In—Ga—Zn oxide (In: Ga: Zn = 1: 3: 2 [atomic ratio]) target were used.

From FIG. 8, it was found that when the sample was formed using a gallium oxide target and the sample was formed using a Ga—Zn oxide target, the number of particles of 1 μm or more increased rapidly as the oxide layer became thicker. On the other hand, it was found that when the film was formed using an In—Ga—Zn oxide target, the number of particles having a size of 1 μm or more was hardly increased even when the oxide layer was thick.

Therefore, when forming a film by sputtering, it is preferable to use a target containing indium from the viewpoint of increasing the number of particles. It can also be seen that it is preferable to use an oxide target having a relatively small atomic ratio of gallium. In particular, when a target containing indium is used, the conductivity of the target can be increased, and DC discharge and AC discharge are facilitated, so that it is easy to deal with a large-area substrate. Therefore, the productivity of the semiconductor device can be increased.

1-3-2. Below the impurities in the multilayer film, the silicon concentration in each layer constituting the multilayer film 106 will be described with reference to FIG.

Here, the oxide layer 106 a is an oxide formed by a sputtering method using a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 3: 2 [atomic ratio]). Is a layer. The film was formed by using 30 sccm of argon gas and 15 sccm of oxygen gas as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 200 ° C., and a DC power of 0.5 kW.

The oxide semiconductor layer 106b is an oxide formed by a sputtering method with the use of a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio]). It is a semiconductor layer. The film was formed by using 30 sccm of argon gas and 15 sccm of oxygen gas as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 300 ° C., and DC power of 0.5 kW.

The oxide layer 106c is an oxide layer formed by a sputtering method using a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 3: 2 [atomic ratio]). It is. The film was formed by using 30 sccm of argon gas and 15 sccm of oxygen gas as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 200 ° C., and a DC power of 0.5 kW.

A multilayer film 106 is provided on a silicon wafer, and a sample without heat treatment and a sample subjected to heat treatment at 450 ° C. for 2 hours are prepared, and time-of-flight secondary ion mass spectrometry (ToF-SIMS: Time-of-flight secondary) is prepared. By ion mass spectrometer, the secondary ion intensity indicating In in the depth direction, the secondary ion intensity indicating Ga, the secondary ion intensity indicating Zn, and the SiO ₃ concentration [atoms / cm ³ ] are shown. The multilayer film 106 includes an oxide layer 106a having a thickness of 10 nm, an oxide semiconductor layer 106b having a thickness of 10 nm provided on the oxide layer 106a, and a thickness provided on the oxide semiconductor layer 106b. 10 nm oxide layer 106c.

From FIG. 9, it can be seen that the composition of each layer constituting the multilayer film 106 changes depending on the composition of the target at the time of film formation. However, a simple comparison cannot be made for the composition of each layer from FIG.

From FIG. 9, it was found that the SiO ₃ concentration was high at the interface between the silicon wafer of the multilayer film 106 and the oxide layer 106a and the upper surface of the oxide layer 106c. Further, it was found that the SiO ₃ concentration of the oxide semiconductor layer 106b was about 1 × 10 ¹⁸ atoms / cm ^3, which is the detection lower limit of ToF-SIMS. This is probably because silicon due to a silicon wafer or surface contamination does not affect the oxide semiconductor layer 106b due to the presence of the oxide layer 106a and the oxide layer 106c.

Further, it can be seen from the comparison between as-depo (sample without heat treatment) and the sample after heat treatment shown in FIG. 9 that silicon is hardly diffused by the heat treatment and mixing during film formation is mainly performed.

In order to impart stable electric characteristics to the transistor including the multilayer film 106, it is effective to highly purify and purify the oxide semiconductor layer 106b. Specifically, the carrier density of the oxide semiconductor layer 106b may be less than 1 × 10 ¹⁷ / cm ^3, less than 1 × 10 ¹⁵ / cm ³ , or less than 1 × 10 ¹³ / cm ³ . In the oxide semiconductor layer 106b, hydrogen, nitrogen, carbon, silicon, and a metal element other than the main component are impurities. In order to reduce the impurity concentration in the oxide semiconductor layer 106b, the impurity concentration in the adjacent oxide layer 106a and the oxide layer 106c is preferably reduced to the same level as that of the oxide semiconductor layer 106b.

In particular, when the oxide semiconductor layer 106b contains silicon at a high concentration, an impurity level due to silicon is formed in the oxide semiconductor layer 106b. The impurity level becomes a trap and may deteriorate the electrical characteristics of the transistor. In order to reduce deterioration in electric characteristics of the transistor, the silicon concentration of the oxide semiconductor layer 106b is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably 1 × 10 10. ^It may be less than ¹⁸ atoms / cm ³ . The silicon concentration at the interface between the oxide layer 106a and the oxide semiconductor layer 106b and the interface between the oxide semiconductor layer 106b and the oxide layer 106c is also less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 × It is less than 10 ¹⁸ atoms / cm ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

In addition, hydrogen and nitrogen in the oxide semiconductor layer 106b form donor levels and increase the carrier density. In order to make the oxide semiconductor layer 106b intrinsic or substantially intrinsic, the hydrogen concentration in the oxide semiconductor layer 106b is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ^{3 in} SIMS. cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁸ atoms / cm ³ or less. Further, the nitrogen concentration in SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10. ¹⁷ atoms / cm ³ or less.

Note that when the oxide semiconductor layer 106b contains silicon and carbon at a high concentration, the crystallinity of the oxide semiconductor layer 106b may be reduced. In order not to decrease the crystallinity of the oxide semiconductor layer 106b, the silicon concentration of the oxide semiconductor layer 106b is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably 1 It may be less than × 10 ¹⁸ atoms / cm ³ . In order not to decrease the crystallinity of the oxide semiconductor layer 106b, the carbon concentration of the oxide semiconductor layer 106b is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably. May be less than 1 × 10 ¹⁸ atoms / cm ³ . The crystallinity of the multilayer film 106 will be described later.

1-3-3. Below, the band structure of the multilayer film 106 is used to describe the oxide layer 106a, the oxide semiconductor layer 106b, the oxide layer 106c, and the oxide layer 106d included in the multilayer film 106.

When the energy at the lower end of the conduction band of the oxide layer 106a, the oxide semiconductor layer 106b, the oxide layer 106c, and the oxide layer 106d is EcS1, EcS2, EcS3, and EcS4, respectively, the relationship expressed by Equation (1) is satisfied. The oxide layer 106a, the oxide semiconductor layer 106b, the oxide layer 106c, and the oxide layer 106d are selected.

Here, the difference between the vacuum level and the energy at the bottom of the conduction band (also referred to as electron affinity) is obtained by subtracting the energy gap from the difference between the vacuum level and the energy at the top of the valence band (also referred to as ionization potential). Value. The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300). The energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus (PHI VersaProbe).

Specifically, the oxide layer 106a satisfies the above formula (1), and the energy at the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0. 0 than the oxide semiconductor layer 106b. 15 eV or more, 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less An oxide layer close to a vacuum level.

The oxide layer 106c satisfies the above formula (1), and the energy at the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more than the oxide semiconductor layer 106b. And 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

The oxide layer 106d satisfies the above formula (1), and the energy at the lower end of the conduction band is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, 0.15 eV or more, and 2 eV than the oxide semiconductor layer 106b. Hereinafter, it is an oxide layer close to a vacuum level of 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Note that the larger the energy difference at the lower end of the conduction band between the oxide layer 106d and the oxide semiconductor layer 106b (the higher the barrier), the second transistor is formed at the interface between the oxide layer 106d and the oxide semiconductor layer 106b. It becomes difficult to be done.

FIG. 10A is a cross-sectional view of the multilayer film 106 having a band structure. FIG. 10B illustrates a band structure along the dashed-dotted line G1-G2 in the multilayer film 106 illustrated in FIG. FIG. 10C illustrates a band structure along the dashed-dotted line G3-G4 in the multilayer film 106 illustrated in FIG. 10B and 10C, an insulating film (eg, a silicon oxide film) with sufficiently large energy at the bottom of the conduction band is provided in contact with the oxide layer 106a, the oxide layer 106c, and the oxide layer 106d. Will be described.

By selecting the oxide layer 106a, the oxide semiconductor layer 106b, the oxide layer 106c, and the oxide layer 106d that satisfy the relationship of Equation (1), the multilayer film 106 has the lowest energy at the bottom of the conduction band. The layer 106b has a band structure in which the oxide layer 106a, the oxide layer 106c, and the oxide layer 106d having higher energy at the lower end of the conduction band than the oxide semiconductor layer 106b are surrounded (see FIGS. 10B and 10C). )reference.).

The lower end of the conduction band is between the oxide layer 106a and the oxide semiconductor layer 106b, between the oxide semiconductor layer 106b and the oxide layer 106c, and between the oxide semiconductor layer 106b and the oxide layer 106d. The energy changes continuously. That is, there are almost no levels at these interfaces.

Therefore, in the multilayer film 106 having the band structure, electrons move mainly in the oxide semiconductor layer 106b. Therefore, even if a level exists at the interface with the insulating film that is outside the multilayer film 106, the level hardly affects the movement of electrons. In addition, since there is no or almost no level between layers constituting the multilayer film 106, movement of electrons in the region is not hindered. Therefore, the oxide semiconductor layer 106b of the multilayer film 106 has high electron mobility.

Note that as shown in FIG. 11, trap levels due to impurities and defects can be formed in the vicinity of the interface between the oxide layer 106a and the oxide layer 106c and the insulating film, but the oxide layer 106a and the oxide layer 106a are oxidized. With the physical layer 106c, the oxide semiconductor layer 106b and the trap level can be separated from each other. Note that in the case where the energy difference between EcS1 or EcS3 and EcS2 is small, electrons in the oxide semiconductor layer 106b may reach the trap level beyond the oxide layer 106a or the oxide layer 106c. By trapping electrons in the trap level, negative fixed charges are generated, and the threshold voltage of the transistor is shifted in the positive direction.

Similarly, although a trap level due to an impurity or a defect can be formed in the vicinity of the interface between the oxide layer 106d and the insulating film, the oxide semiconductor layer 106b and the trap The level can be kept away. Note that in the case where the energy difference between EcS4 and EcS2 is small, electrons in the oxide semiconductor layer 106b may reach the trap level beyond the oxide layer 106d. By trapping electrons in the trap level, negative fixed charges are generated, and the threshold voltage of the transistor is shifted in the positive direction.

Therefore, if the energy difference between EcS1, EcS3, EcS4, and EcS2 is 0.1 eV or more, preferably 0.15 eV or more, variation in the threshold voltage of the transistor is reduced, and stable electrical characteristics are obtained. ,preferable.

Here, how oxygen in the multilayer film 106 diffuses after heat treatment at 350 ° C. or 450 ° C. will be described with reference to FIG.

FIG. 12 shows the result of SIMS performed on a sample in which any one of the multilayer films 106 is formed using ¹⁸ O ₂ gas, and the concentration distribution of ¹⁸ O in the depth direction is measured.

Here, the oxide layer 106 a is an oxide formed by a sputtering method using a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio]). Is a layer.

The oxide semiconductor layer 106b is an oxide formed by a sputtering method using a target that is an In—Ga—Zn oxide (In: Ga: Zn = 3: 1: 2 [atomic ratio]). It is a semiconductor layer.

The oxide layer 106c is an oxide layer formed by a sputtering method using a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio]). It is.

Here, FIG. 12A shows an interface between the oxide layer 106a and the oxide semiconductor layer 106b of a sample in which ¹⁸ O ₂ gas is used for the oxide layer 106a and ¹⁸ O ₂ gas is not used for the other layers. ^{18 is} a concentration distribution of ¹⁸ O in the depth direction. ¹⁸ after heating at 350 ° C. (noted after heating at 350 ° C., indicated by a one-dot chain line) and after heating at 450 ° C. (noted after heating at 450 ° C., indicated by a solid line), compared with no heat treatment (noted as as-depo, dotted line) It was found that O diffused from the oxide layer 106a to the oxide semiconductor layer 106b.

Further, FIG. 12 (B) using a ¹⁸ O ₂ gas to the oxide semiconductor layer 106b, the interface between the oxide semiconductor layer 106b and the oxide layer 106c of the sample without using the other of the layers ¹⁸ O ₂ gas ^{18 is} a concentration distribution of ¹⁸ O in the depth direction. ¹⁸ after heating at 350 ° C. (noted after heating at 350 ° C., indicated by a one-dot chain line) and after heating at 450 ° C. (noted after heating at 450 ° C., indicated by a solid line), compared with no heat treatment (noted as as-depo, dotted line) It was found that O diffused from the oxide semiconductor layer 106b to the oxide layer 106c.

FIG. 12C illustrates an interface between the oxide layer 106a and the oxide semiconductor layer 106b of a sample in which ¹⁸ O ₂ gas is used for the oxide semiconductor layer 106b and ¹⁸ O ₂ gas is not used for the other layers. ^{18 is} a concentration distribution of ¹⁸ O in the depth direction. ¹⁸ after heating at 450 ° C. (noted after heating at 450 ° C., solid line), compared with no heat treatment (noted as as-depo, dotted line) and after 350 ° C. heat processing (noted after heating at 350 ° C., indicated by alternate long and short dash line) It was found that O diffused from the oxide semiconductor layer 106b to the oxide layer 106a.

As shown in FIG. 12, oxygen diffuses in the multilayer film 106. In other words, the interface formed by any combination of the oxide layer 106a, the oxide semiconductor layer 106b, the oxide layer 106c, and the oxide layer 106d is a layer in which constituent elements are mixed (also referred to as a mixed layer). It can be seen that is formed. Note that the mixed layer has an intermediate property between the mixed layers.

By reducing the localized levels in the multilayer film 106, stable electrical characteristics can be imparted to the transistor including the multilayer film 106. In the following, the localized level of the multilayer film 106 was evaluated by a constant photocurrent measurement method (CPM: Constant Photocurrent Method).

Note that in order for the transistor to have high field-effect mobility and stable electric characteristics, the absorption coefficient due to the localized levels obtained by CPM measurement in the multilayer film 106 is 1 × 10 ⁻³ cm ^{−. It} may be less than ¹ , preferably less than 3 × 10 ⁻⁴ cm ⁻¹ .

The sample which performed CPM measurement is demonstrated below.

The oxide layer 106a is an oxide layer formed by a sputtering method using a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 3: 2 [atomic ratio]). . The film was formed by using 30 sccm of argon gas and 15 sccm of oxygen gas as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 200 ° C., and a DC power of 0.5 kW.

The oxide semiconductor layer 106b is an oxide formed by a sputtering method with the use of a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio]). It is a semiconductor layer. The film was formed by using 30 sccm of argon gas and 15 sccm of oxygen gas as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 200 ° C., and a DC power of 0.5 kW.

The oxide layer 106c is an oxide layer formed by a sputtering method using a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 3: 2 [atomic ratio]). It is. The film was formed by using 30 sccm of argon gas and 15 sccm of oxygen gas as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 200 ° C., and a DC power of 0.5 kW.

Here, in order to improve the accuracy of CPM measurement, the multilayer film 106 needs to have a certain thickness. Specifically, the thickness of the oxide layer 106a included in the multilayer film 106 is 30 nm, the thickness of the oxide semiconductor layer 106b is 100 nm, and the thickness of the oxide layer 106c is 30 nm.

In the CPM measurement, the sample surface between the terminals is irradiated so that the photocurrent value is constant in a state where a voltage is applied between the first electrode and the second electrode provided in contact with the multilayer film 106 which is a sample. The light amount is adjusted, and the extinction coefficient is derived from the irradiation light amount at each wavelength. In the CPM measurement, when a sample has a defect, an extinction coefficient at an energy (converted from a wavelength) corresponding to the level where the defect exists is increased. By multiplying the increase in the extinction coefficient by a constant, the defect density of the sample can be derived.

FIG. 13A shows the result of fitting the absorption coefficient (dotted line) measured by the spectrophotometer and the absorption coefficient (solid line) measured by the CPM in an energy range equal to or larger than the energy gap of each layer of the multilayer film 106. . In addition, the Arbach energy obtained from the absorption coefficient measured by CPM was 78.7 meV. The background (thin dotted line) was subtracted from the absorption coefficient measured by CPM in the energy range surrounded by the broken-line circle in FIG. 13A to derive an integral value of the absorption coefficient in the energy range (see FIG. 13B). ). As a result, it was found that the absorption coefficient due to the localized level of this sample was 2.02 × 10 ⁻⁴ cm ⁻¹ .

The localized levels obtained here are considered to be levels caused by impurities and defects. Therefore, it was found that the multilayer film 106 has very few levels due to impurities and defects. That is, it can be seen that a transistor using the multilayer film 106 has high field-effect mobility and stable electric characteristics.

1-3-4. Hereinafter, the crystallinity of the oxide layer 106a, the oxide semiconductor layer 106b, the oxide layer 106c, and the oxide layer 106d included in the multilayer film 106 will be described.

In the multilayer film 106, the oxide layer 106a, the oxide semiconductor layer 106b, the oxide layer 106c, and the oxide layer 106d are amorphous or crystalline. Here, crystalline means a microcrystal, a polycrystal, a single crystal, or the like. Moreover, when a crystal part is contained, it is all crystalline.

In the multilayer film 106, at least the oxide semiconductor layer 106b is preferably crystalline. In particular, a CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) is preferable.

Note that the CAAC-OS is not completely single crystal nor completely amorphous. A CAAC-OS is an oxide semiconductor having a crystal-amorphous mixed phase structure where a crystal part and an amorphous part are included in an amorphous phase. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm.

The crystal part included in the CAAC-OS has a c-axis aligned in a direction parallel to the normal vector of the deposition surface or the upper surface normal vector of the CAAC-OS and is viewed from a direction perpendicular to the ab plane. It has a triangular or hexagonal atomic arrangement, and metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers as seen from the direction perpendicular to the c-axis. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, a simple term “perpendicular” includes a range from 85 ° to 95 °. In addition, a simple term “parallel” includes a range from −5 ° to 5 °.

Note that in the CAAC-OS, the distribution of crystal parts may not be uniform. For example, the CAAC-OS crystal part may have a higher proportion of crystal part in the vicinity of the top surface than in the vicinity of the deposition surface. Further, when an impurity is added to the CAAC-OS, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

In a transistor using a CAAC-OS, change in electrical characteristics due to irradiation with visible light or ultraviolet light is small. Thus, the transistor has stable electrical characteristics.

In order to use the CAAC-OS for the oxide semiconductor layer 106b, the base oxide layer 106a is preferably crystalline or amorphous similar to the CAAC-OS. In addition, when the oxide semiconductor layer 106b is a CAAC-OS, the oxide layer 106c using the oxide semiconductor layer 106b as a base is likely to have a crystallinity similar to that of the CAAC-OS. However, the oxide layer 106c is not limited to be crystalline, and may be amorphous.

Note that the oxide layer 106d may be either amorphous or crystalline.

In the transistor including the multilayer film 106, the oxide semiconductor layer 106b is a layer serving as a channel; therefore, it is preferable that the oxide semiconductor layer 106b have high crystallinity because stable electrical characteristics can be imparted to the transistor.

Here, with respect to the crystallinity of the multilayer film 106, the atomic arrangement was evaluated by a transmission electron microscope (TEM: Transmission Electron Microscope). This will be described below with reference to FIG.

Here, the oxide layer 106 a is an oxide formed by a sputtering method using a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 3: 2 [atomic ratio]). Is a layer. The film was formed by using 30 sccm of argon gas and 15 sccm of oxygen gas as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 200 ° C., and a DC power of 0.5 kW.

The oxide semiconductor layer 106b is an oxide formed by a sputtering method with the use of a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio]). It is a semiconductor layer. The film was formed by using 30 sccm of argon gas and 15 sccm of oxygen gas as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 400 ° C., and DC power of 0.5 kW.

The oxide layer 106c is an oxide layer formed by a sputtering method using a target that is an In—Ga—Zn oxide (In: Ga: Zn = 1: 3: 2 [atomic ratio]). It is. The film was formed by using 30 sccm of argon gas and 15 sccm of oxygen gas as a film forming gas, a pressure of 0.4 Pa, a substrate temperature of 200 ° C., and a DC power of 0.5 kW.

FIG. 14 is a transmission electron image of each sample including the multilayer film 106 provided on the silicon oxide film provided on the silicon wafer. Note that each sample was not heat-treated. The transmission electron image was measured using a Hitachi transmission electron microscope H-9500.

Here, in the multilayer film 106, the oxide layer 106a is an In—Ga—Zn oxide with a thickness of 20 nm, the oxide semiconductor layer 106b is an In—Ga—Zn oxide with a thickness of 15 nm, and the oxide layer 106c was an In—Ga—Zn oxide having a thickness of 5 nm. FIG. 14A illustrates a transmission electron image including the oxide layer 106a, the oxide semiconductor layer 106b, and the oxide layer 106c. 14B is an enlarged view of the vicinity of the interface between the oxide semiconductor layer 106b and the oxide layer 106c, and FIG. 14C is an enlarged view of the vicinity of the interface between the oxide layer 106a and the oxide semiconductor layer 106b. FIG. 14D is an enlarged view of the vicinity of the interface between the silicon oxide film and the oxide layer 106a.

FIG. 14 shows that the oxide layer 106a is amorphous. Note that the oxide layer 106c was found to be crystalline having a crystal part in the vicinity of the interface with the oxide semiconductor layer 106b. Further, it was found that the oxide semiconductor layer 106b is crystalline having high crystallinity from the interface with the oxide layer 106a. Note that the atomic arrangement of crystal parts of the oxide semiconductor layer 106b was found to form a layered arrangement in a plane parallel to the upper surface of the oxide semiconductor layer 106b. In addition, a clear crystal grain boundary was not observed between the crystal parts of the oxide semiconductor layer 106b.

That the oxide semiconductor layer 106b is crystalline is compatible with the result of ToF-SIMS shown in FIG. That is, it is considered that the oxide layer 106a and the oxide layer 106c reduce the entry of impurities such as silicon into the oxide semiconductor layer 106b, so that the crystallinity of the oxide semiconductor layer 106b does not decrease.

In this manner, the oxide semiconductor layer 106b in which a channel is formed has high crystallinity and is considered to have few levels due to impurities, defects, and the like; thus, a transistor including the multilayer film 106 has stable electric characteristics. It can be seen that it has characteristics.

Here, a model in which an oxide semiconductor layer having high crystallinity is formed over an insulating surface, an amorphous film, or an amorphous insulating film will be described with reference to FIGS.

FIG. 15A is a schematic diagram illustrating a state where ions 1001 collide with a target 1000 including a polycrystalline oxide semiconductor having high orientation and a sputtered particle 1002 having crystallinity is separated. The crystal grains have a cleavage plane parallel to the surface of the target 1000. Further, the crystal grain has a portion having a weak bond between atoms. When the ion 1001 collides with the crystal grain, the interatomic bond is broken at a portion where the interatomic bond is weak. Therefore, the sputtered particle 1002 is cut by a cleavage plane and a portion having a weak bond between atoms, and peeled off in a flat plate shape (or a pellet shape). The c-axis direction of the sputtered particle 1002 is a direction perpendicular to the plane of the sputtered particle 1002 (see FIG. 15B). Note that the plane equivalent circle diameter of the sputtered particles 1002 is 1/3000 or more and 1/20 or less, and preferably 1/1000 or more and 1/30 or less, of the average grain size of crystal grains. The equivalent circle diameter of a surface means a diameter of a perfect circle that is equal to the area of the surface.

Alternatively, part of the crystal grains is separated from the cleavage plane as particles and exposed to plasma 1005, whereby bonds are broken from portions where bonds between atoms are weak, and a plurality of sputtered particles 1002 are generated.

By using an oxygen cation as the ion 1001, plasma damage during film formation can be reduced. Specifically, when the ions 1001 collide with the surface of the target 1000, it is possible to suppress the crystallinity of the target 1000 from being lowered or becoming amorphous.

Here, as an example of the target 1000 including a polycrystalline oxide semiconductor having high orientation, a crystal of an In—Ga—Zn oxide as viewed in parallel with the ab plane of the crystal in FIG. The structure is shown. Further, in FIG. 16A, a portion surrounded by a broken line is enlarged and shown in FIG.

For example, in a crystal grain included in the In—Ga—Zn oxide, a first layer including a gallium atom and / or a zinc atom and an oxygen atom, a gallium atom and / or a zinc atom, and an oxygen atom illustrated in FIG. A plane between the second layer having atoms is a cleavage plane. This is because oxygen atoms having negative charges in the first layer and the second layer are located at a short distance (see a box in FIG. 16B). Thus, the cleavage plane is a plane parallel to the ab plane. In addition, since the crystal of the In—Ga—Zn oxide illustrated in FIG. 16 is a hexagonal crystal, the above-described tabular crystal grains are likely to have a hexagonal column shape having a regular hexagonal surface with an inner angle of 120 °.

The sputtered particles 1002 are preferably charged. Note that it is preferable that charges having the same polarity exist at the corners of the sputtered particle 1002 because interaction occurs (repels) so that the shape of the sputtered particle 1002 is maintained (see FIG. 15B). It is conceivable that the sputtered particles 1002 are positively charged, for example. The timing of charging is not particularly limited, but specifically, it may be positively charged by receiving a charge when the ion 1001 collides. Alternatively, when the plasma 1005 is generated, the sputtered particles 1002 may be positively charged by being exposed to the plasma 1005. Alternatively, the ion 1001 which is an oxygen cation may be positively charged by bonding to the side surface, the upper surface, or the lower surface of the sputtered particle 1002.

Hereinafter, how the sputtered particles are deposited on the film formation surface will be described with reference to FIG. In FIG. 17, the sputtered particles that have already been deposited are indicated by dotted lines.

FIG. 17A illustrates an oxide semiconductor layer 1003 formed by depositing sputtering particles 1002 over an amorphous film 1004. As shown in FIG. 17A, when the sputtered particles 1002 are positively charged by being exposed to the plasma 1005, the sputtered particles 1002 are deposited in a region where the other sputtered particles 1002 are not deposited. This is because the sputtered particles 1002 are positively charged and the sputtered particles 1002 repel each other. Such sputtering particles can be deposited on an insulating surface or an amorphous insulating film.

FIG. 17B is a cross-sectional view corresponding to the dashed-dotted line X-Y in FIG. The oxide semiconductor layer 1003 is formed by orderly depositing tabular sputtered particles 1002 whose c-axis direction is perpendicular to a plane. Therefore, the oxide semiconductor layer 1003 is a CAAC-OS in which c-axes of crystals are aligned in a direction perpendicular to a formation surface. By taking the model shown above, a CAAC-OS can be formed with high crystallinity even on an insulating surface, an amorphous film, or an amorphous insulating film.

1-4. When the concentration of impurities contained in the oxide semiconductor layer 106b in the manufacturing apparatus is low, the electrical characteristics of the transistor are stabilized. In addition, since the oxide semiconductor layer 106b has high crystallinity, the electrical characteristics of the transistor are more stable than in the case where the oxide semiconductor layer 106b is amorphous. Hereinafter, a film formation apparatus for forming the oxide semiconductor layer 136b which is the oxide semiconductor layer 106b with low impurity concentration and high crystallinity will be described.

First, a structure of a film formation apparatus in which impurities hardly enter during film formation will be described with reference to FIG.

FIG. 18A is a top view of a multi-chamber film formation apparatus. The film forming apparatus includes an atmosphere side substrate supply chamber 71 having three cassette ports 74 for accommodating substrates, a load lock chamber 72a and an unload lock chamber 72b, a transfer chamber 73, a transfer chamber 73a, and a transfer chamber 73b. A substrate heating chamber 75, a film forming chamber 70a, and a film forming chamber 70b. The atmosphere side substrate supply chamber 70 is connected to the load lock chamber 72a and the unload lock chamber 72b. The load lock chamber 72a and the unload lock chamber 72b are connected to the transfer chamber 73 via the transfer chamber 73a and the transfer chamber 73b. The substrate heating chamber 75, the film formation chamber 70a, and the film formation chamber 70b are connected only to the transfer chamber 73. In addition, a gate valve (GV) is provided at a connection portion of each chamber, and each chamber can be maintained in a vacuum state independently of the atmosphere side substrate supply chamber 71. The atmosphere-side substrate supply chamber 70 and the transfer chamber 73 have one or more substrate transfer robots 76 and can transfer a substrate. Here, it is preferable that the substrate heating chamber 75 also serves as a plasma processing chamber. Since the single-wafer multi-chamber film forming apparatus can transfer a substrate without exposing the substrate between processes, the adsorption of impurities to the substrate can be suppressed. In addition, the order of film formation and heat treatment can be established freely. Note that the number of transfer chambers, film formation chambers, load lock chambers, unload lock chambers, and substrate heating chambers is not limited to the above-described numbers, and may be determined as appropriate in accordance with installation space and processes.

FIG. 18B is a top view of a multi-chamber film formation apparatus having a structure different from that in FIG. The film forming apparatus includes an atmosphere side substrate supply chamber 81 having a cassette port 84, a load / unload lock chamber 82, a transfer chamber 83, a substrate heating chamber 85, a film forming chamber 80a, and a film forming chamber 80b. And a film forming chamber 80c and a film forming chamber 80d. The atmosphere-side substrate supply chamber 81, the substrate heating chamber 85, the film formation chamber 80 a, the film formation chamber 80 b, the film formation chamber 80 c, and the film formation chamber 80 d are connected via the transfer chamber 83.

Note that a gate valve (GV) is provided at a connecting portion of each chamber, and each chamber can be kept in a vacuum state independently of the atmosphere side substrate supply chamber 81. The atmosphere side substrate supply chamber 81 and the transfer chamber 83 have one or more substrate transfer robots 86, and can transfer a glass substrate.

Here, the details of the deposition chamber (sputtering chamber) illustrated in FIG. 18A will be described with reference to FIG. The film forming chamber 80 includes a target 87, a deposition preventing plate 88, and a substrate stage 90. Here, a glass substrate 89 is installed on the substrate stage 90. Although not shown, the substrate stage 90 may include a substrate holding mechanism for holding the glass substrate 89, a back heater for heating the glass substrate 89 from the back surface, and the like. Further, the deposition preventing plate 88 can suppress accumulation of particles sputtered from the target 87 in an unnecessary region.

19A is connected to a transfer chamber 83 via a gate valve, and the transfer chamber 83 is connected to a load / unload lock chamber 82 via a gate valve. Yes. A substrate transfer robot 86 is provided in the transfer chamber 83, and the glass substrate can be transferred between the film forming chamber 80b and the load / unload lock chamber 82. The load / unload lock chamber 82 is divided into upper and lower portions in one vacuum chamber, and either one can be used as a load chamber and the other can be used as an unload chamber. Such a structure is preferable because the installation area of the sputtering apparatus can be reduced.

Further, the film formation chamber 80 b shown in FIG. 19A is connected to the purifier 94 through the mass flow controller 97. In addition, although the refiner 94 and the mass flow controller 97 are provided by the number of gas types, only one is shown for simplicity. A gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower is used as the gas used for the film formation chamber 80 or the like. By using an oxygen gas, a rare gas (such as argon gas), or the like having a low dew point, moisture mixed during film formation can be reduced.

19A is connected to a cryopump 95a through a valve, and the transfer chamber 83 is connected to the cryopump 95b through a gate valve, and a load / unload lock chamber 82 is connected. Is connected to a vacuum pump 96 through a gate valve. The load / unload lock chamber 82 may be connected to the vacuum pump independently of the load lock chamber and the unload lock chamber. The film forming chamber 80b and the transfer chamber 83 are each connected to a vacuum pump 96 through gate valves.

The vacuum pump 96 may be, for example, a dry pump and a mechanical booster pump connected in series. With such a configuration, the film formation chamber 80b and the transfer chamber 83 are evacuated from the atmospheric pressure to low vacuum (about 0.1 Pa to 10 Pa) using the vacuum pump 96, and the valves are switched to start from the low vacuum. Up to high vacuum (1 × 10 ⁻⁴ Pa to 1 × 10 ⁻⁷ Pa) is exhausted using the cryopump 95a or the cryopump 95b.

Next, an example of the deposition chamber illustrated in FIG. 18B will be described with reference to FIG.

The film formation chamber 80 shown in FIG. 19B is connected to the transfer chamber 83 via a gate valve, and the transfer chamber 83 is connected to the load / unload lock chamber 82 via a gate valve.

A film formation chamber 80 b shown in FIG. 19B is connected to a mass flow controller 97 through a gas heating mechanism 98, and the gas heating mechanism 98 is connected to a purifier 94 through the mass flow controller 97. The gas used in the film formation chamber 80 can be heated to 40 ° C. or higher and 400 ° C. or lower, or 50 ° C. or higher and 200 ° C. or lower by the gas heating mechanism 98. In addition, although the gas heating mechanism 98, the refiner | purifier 94, and the mass flow controller 97 are provided by the number of gas types, only one is shown for simplicity.

A film formation chamber 80b shown in FIG. 19B is connected to a turbo molecular pump 95c and a vacuum pump 96b through valves. The turbo molecular pump 95c is provided with a vacuum pump 96a via a valve as an auxiliary pump. The vacuum pump 96a and the vacuum pump 96b may have the same configuration as the vacuum pump 96.

In addition, a deposition chamber 80b illustrated in FIG. 19B is provided with a cryotrap 99.

It is known that the turbo molecular pump 95c stably evacuates large-sized molecules (atoms) and has a low maintenance frequency. Therefore, the turbo molecular pump 95c is excellent in productivity, but has a low exhaust capability of hydrogen or water. Therefore, a cryotrap 99 having a high exhaust capability for molecules (atoms) having a relatively high melting point such as water is connected to the film forming chamber 80. The temperature of the refrigerator of the cryotrap 99 is 100K or less, preferably 80K or less. In addition, when the cryotrap 99 includes a plurality of refrigerators, it is preferable to change the temperature for each refrigerator because exhaust can be efficiently performed. For example, the temperature of the first stage refrigerator may be 100K or less, and the temperature of the second stage refrigerator may be 20K or less.

Further, the transfer chamber 83 shown in FIG. 19B is connected to the vacuum pump 96b, the cryopump 95d, and the cryopump 95e through valves. If there is only one cryopump, it cannot be exhausted while the cryopump is being regenerated, but by connecting two or more cryopumps in parallel, the remaining cryopumps can be used even if one is being regenerated. It becomes possible to exhaust using. Note that cryopump regeneration refers to a process of releasing molecules (atoms) trapped in the cryopump. The cryopump is periodically regenerated because the exhaust capacity is reduced if molecules (atoms) are accumulated too much.

Further, the load / unload lock chamber 82 shown in FIG. 19B is connected to the cryopump 95f and the vacuum pump 96c through valves. The vacuum pump 96c may have the same configuration as the vacuum pump 96.

A target-facing sputtering apparatus may be applied to the film formation chamber 80b.

Note that a parallel plate sputtering apparatus or an ion beam sputtering apparatus may be applied to the film formation chamber 80b.

Next, exhaust of an example of the substrate heating chamber illustrated in FIG. 18B will be described with reference to FIG.

The substrate heating chamber 85 shown in FIG. 20 is connected to the transfer chamber 83 through a gate valve. The transfer chamber 83 is connected to the load / unload lock chamber 82 via a gate valve. The configuration of the load / unload lock chamber 82 is the same as the configuration of FIG. 19A or 19B.

The substrate heating chamber 85 shown in FIG. 20 is connected to the refiner 94 via the mass flow controller 97. In addition, although the refiner 94 and the mass flow controller 97 are provided by the number of gas types, only one is shown for simplicity. The substrate heating chamber 85 is connected to the vacuum pump 96b via a valve.

The substrate heating chamber 85 has a substrate stage 92. The substrate stage 92 only needs to be able to install at least one substrate, and may be a substrate stage on which a plurality of substrates can be installed. The substrate heating chamber 85 has a heating mechanism 93. The heating mechanism 93 may be a heating mechanism that heats using a resistance heating element, for example. Alternatively, a heating mechanism that heats by heat conduction or heat radiation from a medium such as a heated gas may be used. For example, RTA (Rapid Thermal Anneal) such as GRTA (Gas Rapid Thermal Anneal) and LRTA (Lamp Rapid Thermal Anneal) can be used. LRTA heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas.

Note that the back pressure of the film forming chamber 80b and the substrate heating chamber 85 is 1 × 10 ⁻⁴ Pa or less, preferably 3 × 10 ⁻⁵ Pa or less, and more preferably 1 × 10 ⁻⁵ Pa or less.

In the film formation chamber 80b and the substrate heating chamber 85, the partial pressure of gas molecules (atoms) having an m / z of 18 is 3 × 10 ⁻⁵ Pa or less, preferably 1 × 10 ⁻⁵ Pa or less, more preferably 3 × 10 ⁻⁶ Pa or less.

In the film formation chamber 80b and the substrate heating chamber 85, the partial pressure of gas molecules (atoms) having an m / z of 28 is 3 × 10 ⁻⁵ Pa or less, preferably 1 × 10 ⁻⁵ Pa or less, more preferably 3 × 10 ⁻⁶ Pa or less.

In the film formation chamber 80b and the substrate heating chamber 85, the partial pressure of gas molecules (atoms) having an m / z of 44 is 3 × 10 ⁻⁵ Pa or less, preferably 1 × 10 ⁻⁵ Pa or less, more preferably 3 × 10 ⁻⁶ Pa or less.

Note that the film formation chamber 80b and the substrate heating chamber 85 have a leak rate of 3 × 10 ⁻⁶ Pa · m ³ / s or less, preferably 1 × 10 ⁻⁶ Pa · m ³ / s or less.

In the film formation chamber 80b and the substrate heating chamber 85, the leak rate of gas molecules (atoms) whose m / z is 18 is 1 × 10 ⁻⁷ Pa · m ³ / s or less, preferably 3 × 10 ⁻⁸ Pa. · ^m is 3 / s or less.

In the film formation chamber 80b and the substrate heating chamber 85, the leak rate of gas molecules (atoms) having an m / z of 28 is 1 × 10 ⁻⁵ Pa · m ³ / s or less, preferably 1 × 10 ⁻⁶ Pa. · ^m is 3 / s or less.

In the film formation chamber 80b and the substrate heating chamber 85, the leak rate of gas molecules (atoms) having an m / z of 44 is 3 × 10 ⁻⁶ Pa · m ³ / s or less, preferably 1 × 10 ⁻⁶ Pa. · ^m is 3 / s or less.

Note that the total pressure and partial pressure in a vacuum chamber such as a film formation chamber, a substrate heating chamber, or a transfer chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also referred to as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used. The leak rate may be derived from the total pressure and partial pressure measured using the mass spectrometer described above.

The leak rate depends on the external leak and the internal leak. An external leak is a gas flowing from outside the vacuum system due to a minute hole or a seal failure. The internal leak is caused by leakage from a partition such as a valve in the vacuum system or gas released from an internal member. In order to make the leak rate below the above-mentioned numerical value, it is necessary to take measures from both the external leak and the internal leak.

For example, the open / close portion of the film formation chamber may be sealed with a metal gasket. The metal gasket is preferably a metal covered with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. In addition, by using the passivation of a metal covered with iron fluoride, aluminum oxide, chromium oxide, or the like, emission gas containing impurities released from the metal gasket can be suppressed, and internal leakage can be reduced.

As a member constituting the film formation apparatus, aluminum, chromium, titanium, zirconium, nickel, or vanadium that emits less impurities and contains less gas is used. Further, the above-described member may be used by being coated with an alloy containing iron, chromium, nickel and the like. Alloys containing iron, chromium, nickel, etc. are rigid, heat resistant and suitable for processing. Here, if the surface irregularities of the member are reduced by polishing or the like in order to reduce the surface area, the emitted gas can be reduced.

Alternatively, the member of the above-described film formation apparatus may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like.

It is preferable that the members of the film forming apparatus be made of only metal as much as possible. For example, when a viewing window made of quartz or the like is installed, the surface is made of iron fluoride, aluminum oxide, or oxide in order to suppress the released gas. It is good to coat thinly with chrome.

Note that in the case where a purifier is provided immediately before the film formation gas flows, the length of the pipe from the purifier to the film formation chamber is 10 m or less, preferably 5 m or less, and more preferably 1 m or less. By setting the length of the pipe to 10 m or less, 5 m or less, or 1 m or less, the influence of the gas released from the pipe can be reduced according to the length.

Further, a metal pipe whose inside is covered with iron fluoride, aluminum oxide, chromium oxide, or the like may be used for the film forming gas pipe. The above-described piping has a smaller amount of gas containing impurities compared to, for example, SUS316L-EP piping, and can reduce the entry of impurities into the deposition gas. Moreover, it is good to use a high performance ultra-small metal gasket joint (UPG joint) for the joint of piping. In addition, it is preferable that the pipes are all made of metal, because the influence of the generated released gas and external leakage can be reduced as compared with the case where resin or the like is used.

The adsorbate present in the film forming chamber does not affect the pressure in the film forming chamber because it is adsorbed on the inner wall or the like, but causes gas emission when the film forming chamber is exhausted. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to desorb the adsorbate present in the film formation chamber as much as possible and exhaust it in advance using a pump having a high exhaust capability. Note that the deposition chamber may be baked to promote desorption of the adsorbate. Baking can increase the desorption rate of the adsorbate by about 10 times. Baking may be performed at 100 ° C to 450 ° C. At this time, if the adsorbate is removed while flowing an inert gas into the film formation chamber, the desorption rate of water or the like that is difficult to desorb by simply exhausting can be further increased. Note that the desorption rate of the adsorbate can be further increased by heating the inert gas to the same temperature as the baking temperature. Here, it is preferable to use a rare gas as the inert gas. Further, depending on the type of film to be formed, oxygen or the like may be used instead of the inert gas. For example, in the case where an oxide semiconductor layer is formed, it may be preferable to use oxygen which is a main component.

Alternatively, it is preferable to increase the pressure in the deposition chamber by flowing an inert gas such as a heated rare gas or oxygen, and exhaust the deposition chamber again after a predetermined time has elapsed. By flowing the heated gas, the adsorbate in the deposition chamber can be desorbed, and impurities present in the deposition chamber can be reduced. In addition, it is effective when this treatment is repeated 2 times or more and 30 times or less, preferably 5 times or more and 15 times or less. Specifically, by flowing an inert gas or oxygen having a temperature of 40 ° C. or higher and 400 ° C. or lower, or 50 ° C. or higher and 200 ° C. or lower, the pressure in the deposition chamber is 0.1 Pa or higher and 10 kPa or lower, preferably 1 Pa or higher. 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, and the pressure maintaining period may be 1 minute or more and 300 minutes or less, preferably 5 minutes or more and 120 minutes or less. After that, the film formation chamber is evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

Further, the desorption rate of the adsorbate can be further increased by performing dummy film formation. Dummy film formation is performed by depositing a film on the dummy substrate by sputtering or the like, thereby depositing a film on the dummy substrate and the inner wall of the film forming chamber, and depositing impurities on the film forming chamber and adsorbed material on the inner wall of the film forming film. It means confining inside. The dummy substrate is preferably a substrate with a small amount of released gas. For example, a substrate similar to the substrate 100 described later may be used. By performing dummy film formation, the impurity concentration in a film to be formed later can be reduced. The dummy film formation may be performed simultaneously with baking.

By forming an oxide semiconductor layer using the above deposition apparatus, entry of impurities into the oxide semiconductor layer can be suppressed. Further, by using the above deposition apparatus to form a film in contact with the oxide semiconductor layer, entry of impurities from the film in contact with the oxide semiconductor layer to the oxide semiconductor layer can be suppressed.

Next, the oxide layer 136a to be the oxide layer 106a, the oxide semiconductor layer 136b to be the oxide semiconductor layer 106b, and the oxide layer 136c to be the oxide layer 106c are formed using the film formation apparatus described above. A method will be described.

Next, an oxide layer 136a is formed. The oxide layer 136a is formed in an oxygen gas atmosphere at a substrate heating temperature of room temperature (25 ° C.) to 600 ° C., preferably 70 ° C. to 550 ° C., more preferably 100 ° C. to 500 ° C. The higher the heating temperature during film formation, the lower the impurity concentration of the oxide layer 136a. Further, migration of sputtered particles easily occurs on the deposition surface, so that the atomic arrangement is aligned and the density is increased, and the crystallinity of the oxide layer 136a is increased. Further, by forming the film in an oxygen gas atmosphere, plasma damage is reduced and extra atoms such as a rare gas are not included, so that the oxide layer 136a with high crystallinity is formed. However, a mixed atmosphere of oxygen gas and rare gas may be used. In that case, the ratio of oxygen gas is 30% by volume or more, preferably 50% by volume or more, and more preferably 80% by volume or more. In order to stabilize the pressure, the oxide layer 136a is made not less than 10 seconds and not more than 1000 seconds in order to flow the deposition gas after flowing the substrate into the deposition chamber and set the deposition pressure to 0.8 Pa or less, preferably 0.4 Pa or less. Hereinafter, preferably, the film is formed after holding for 15 seconds or more and 720 seconds or less. By maintaining the above time for stabilizing the pressure, the amount of impurities mixed when the oxide layer 136a is formed can be reduced. However, since the oxide layer 136a may be amorphous, the oxide layer 136a may be intentionally formed at a low temperature of less than 70 ° C. and a ratio of oxygen gas of less than 30% by volume.

Next, the oxide semiconductor layer 136b is formed. The target has a surface temperature of 100 ° C. or lower, preferably 50 ° C. or lower, more preferably about room temperature (typically 20 ° C. or 25 ° C.). In a sputtering apparatus corresponding to a large area substrate, a large area target is often used. However, it is difficult to seamlessly produce a target having a size corresponding to a large area. In reality, a large number of targets are arranged side by side with as little gap as possible, but a slight gap is inevitably generated. From such a small gap, Zn or the like volatilizes as the surface temperature of the target increases, and the gap may gradually widen. When the gap widens, the backing plate and the metal used for bonding may be sputtered, which becomes a factor for increasing the impurity concentration. Therefore, it is preferable that the target is sufficiently cooled.

Specifically, a metal (specifically Cu) having high conductivity and high heat dissipation is used as the backing plate. Moreover, a target can be efficiently cooled by forming a water channel in the backing plate and flowing a sufficient amount of cooling water through the water channel. Here, although a sufficient amount of cooling water depends on the size of the target, for example, in the case of a regular circular target having a diameter of 300 mm, it should be 3 L / min or more, 5 L / min or more, or 10 L / min or more. Good.

The oxide semiconductor layer 136b is formed in an oxygen gas atmosphere at a substrate heating temperature of 100 ° C to 600 ° C, preferably 150 ° C to 550 ° C, more preferably 200 ° C to 500 ° C. The higher the heating temperature at the time of film formation, the lower the impurity concentration of the oxide semiconductor layer 136b. Further, migration of sputtered particles easily occurs on the deposition surface, so that the atomic arrangement is aligned and the density is increased, and the crystallinity of the oxide semiconductor layer 136b is increased. Further, by forming the film in an oxygen gas atmosphere, plasma damage is reduced and extra atoms such as a rare gas are not included; thus, the oxide semiconductor layer 136b with high crystallinity is formed. However, a mixed atmosphere of oxygen gas and rare gas may be used. In that case, the ratio of oxygen gas is 30% by volume or more, preferably 50% by volume or more, and more preferably 80% by volume or more.

Note that in the case where the target contains Zn, the oxide semiconductor layer 136b in which plasma damage is reduced and Zn is less likely to volatilize can be obtained by forming the film in an oxygen gas atmosphere.

In order to stabilize the pressure, the oxide semiconductor layer 136b is made to flow for 10 seconds or more in order to flow the deposition gas after the substrate is transferred to the deposition chamber and to set the deposition pressure to 0.8 Pa or less, preferably 0.4 Pa or less. The film is formed after holding for 15 seconds or less, preferably 15 seconds or more and 720 seconds or less. By maintaining the above time for stabilizing the pressure, the amount of impurities mixed when the oxide semiconductor layer 136b is formed can be reduced. At this time, the distance between the target and the substrate is set to 40 mm or less, preferably 25 mm or less. When the oxide semiconductor layer 136b is formed under such conditions, the frequency with which the sputtered particles collide with other sputtered particles, gas molecules, or ions can be reduced. That is, the impurity concentration taken into the film can be reduced by making the distance between the target and the substrate smaller than the mean free path of the sputtered particles, gas molecules or ions in accordance with the film forming pressure.

For example, the mean free path at a pressure of 0.4 Pa and a temperature of 25 ° C. (absolute temperature of 298 K) is as follows: hydrogen molecule (H ₂ ) is 48.7 mm, helium atom (He) is 57.9 mm, and water molecule (H ₂ O) is 31.3 mm, ethane molecule (CH ₄ ) is 13.2 mm, neon atom (Ne) is 42.3 mm, nitrogen molecule (N ₂ ) is 23.2 mm, and carbon monoxide molecule (CO) is 16.0 mm. Oxygen molecule (O ₂ ) 26.4 mm, argon atom (Ar) 28.3 mm, carbon dioxide molecule (CO ₂ ) 10.9 mm, krypton atom (Kr) 13.4 mm, xenon atom (Xe) It is 9.6 mm. When the pressure is doubled, the mean free path is halved, and when the absolute temperature is doubled, the mean free path is doubled.

The mean free path is determined from pressure, temperature and the diameter of the molecule (atom). When the pressure and temperature are constant, the mean free path becomes shorter as the diameter of the molecule (atom) increases. In addition, the diameter of each molecule (atom) is 0.218 nm for H ₂ , 0.200 nm for He, 0.272 nm for H ₂ O, 0.419 nm for CH ₄ , 0.234 nm for Ne, and 0.2 for N ₂ . 316 nm, CO is 0.380 nm, O ₂ is 0.296 nm, Ar is 0.286 nm, CO ₂ is 0.460 nm, Kr is 0.415 nm, and Xe is 0.491 nm.

Accordingly, the larger the diameter of the molecule (atom), the shorter the mean free path, and when taken into the film, the crystallinity is lowered because the diameter of the molecule (atom) is large. Therefore, for example, it can be said that a molecule (atom) having a diameter equal to or larger than Ar is likely to be an impurity that reduces crystallinity.

Next, an oxide layer 136c is formed. The oxide layer 136c is formed in an oxygen gas atmosphere at a substrate heating temperature of room temperature (25 ° C.) to 600 ° C., preferably 70 ° C. to 550 ° C., more preferably 100 ° C. to 500 ° C. The higher the heating temperature during film formation, the lower the impurity concentration of the oxide layer 136c. Further, since migration of sputtered particles easily occurs on the deposition surface, the atomic arrangement is aligned, the density is increased, and the crystallinity of the oxide layer 136c is increased. Further, by forming the film in an oxygen gas atmosphere, plasma damage is reduced and extra atoms such as a rare gas are not included, so that the oxide layer 136c with high crystallinity is formed. However, a mixed atmosphere of oxygen gas and rare gas may be used. In that case, the ratio of oxygen gas is 30% by volume or more, preferably 50% by volume or more, and more preferably 80% by volume or more. For the oxide layer 136c, after the substrate is transferred to the film formation chamber, a film formation gas is flowed, and the film formation pressure is set to 0.8 Pa or less, preferably 0.4 Pa or less. Hereinafter, preferably, the film is formed after holding for 15 seconds or more and 720 seconds or less. By maintaining the above time for stabilizing the pressure, the amount of impurities mixed when the oxide layer 136c is formed can be reduced.

Next, heat treatment is performed. The heat treatment is performed under reduced pressure in an inert atmosphere or an oxidizing atmosphere. By the heat treatment, the impurity concentration in the oxide semiconductor layer 136b can be reduced.

The heat treatment is preferably performed after the heat treatment is performed under reduced pressure or in an inert atmosphere, and then the heat treatment is performed by switching to an oxidizing atmosphere while maintaining the temperature. This is because when the heat treatment is performed under reduced pressure or in an inert atmosphere, the impurity concentration in the oxide semiconductor layer 136b can be reduced, but oxygen vacancies are generated at the same time. Defects can be reduced by heat treatment in an oxidizing atmosphere.

The oxide semiconductor layer 136b can be subjected to heat treatment in addition to substrate heating at the time of film formation, whereby the impurity concentration in the film can be reduced.

Specifically, the hydrogen concentration in the oxide semiconductor layer 136b is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ^{3 in} SIMS. cm ³ or less, more preferably 5 × 10 ¹⁸ atoms / cm ³ or less.

The nitrogen concentration in the oxide semiconductor layer 136b is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less in SIMS. More preferably, it can be 5 × 10 ¹⁷ atoms / cm ³ or less.

The carbon concentration in the oxide semiconductor layer 136b is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 2 × 10 ¹⁸ atoms / cm ^{3 in} SIMS. In the following, it can be more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, the oxide semiconductor layer 136b has a gas molecule (atom) in which m / z is 2 (hydrogen molecule or the like) according to a temperature desorption gas spectroscopy (TDS) analysis, and m / z is 18. gas molecule (atom), the released amount of gas molecules (atoms) m / z is a gas molecule (atom) and m / z is 28 is 44, respectively 1 × ^{10 19} / cm ³ or less, preferably 1 × 10 ¹⁸ pieces / cm ³ or less.

For the method of measuring the release amount by TDS analysis, refer to the description of the method for measuring the release amount of oxygen atoms described later.

As described above, by forming the oxide semiconductor layer 136b and the oxide layer 136c, the crystallinity of the oxide semiconductor layer 136b can be increased, and the oxide semiconductor layer 136b, the oxide layer 136c, and the oxide The impurity concentration at the interface between the semiconductor layer 136b and the oxide layer 136c can be reduced.

2. Hereinafter, a transistor including a multilayer film 106 in which a channel is formed in the oxide semiconductor layer 106b is described.

2-1. Transistor structure (1)
In this section, a top-gate transistor will be described.

2-1-1. Transistor structure (1-1)
Here, a top-gate top-contact (TGTC) transistor, which is a kind of top-gate transistor, is described with reference to FIGS.

FIG. 21 shows a top view and a cross-sectional view of a transistor having a TGTC structure. FIG. 21A illustrates a top view of a transistor. In FIG. 21A, a cross-sectional view corresponding to the dashed-dotted line A1-A2 is illustrated in FIG. Note that FIG. 21D is an enlarged view of the vicinity of the source electrode 116a and the multilayer film 106 in FIG. FIG. 21C is a cross-sectional view corresponding to the dashed-dotted line A3-A4 in FIG.

A transistor illustrated in FIG. 21B includes a base insulating film 102 provided over the substrate 100, an oxide layer 106a provided over the base insulating film 102, and an oxide semiconductor layer provided over the oxide layer 106a. 106b, a multilayer film 106 including an oxide layer 106c provided over the oxide semiconductor layer 106b, and an oxide layer 106d provided in contact with at least a side surface of the oxide semiconductor layer 106b; a base insulating film 102 and a multilayer film; The source electrode 116a and the drain electrode 116b provided on the gate 106, the gate insulating film 112 provided on the multilayer film 106, the gate electrode 104 provided on the gate insulating film 112, the multilayer film 106, and the source electrode 116a. , The drain electrode 116b, the gate insulating film 112, and the gate electrode 104, and the source electrode 116a and the drain electrode 116b. A protective insulating film 118 having an opening reaching the in-electrode 116b; a wiring 122a and a wiring 122b which are provided over the protective insulating film 118 and are in contact with the source electrode 116a and the drain electrode 116b through the opening of the protective insulating film 118; Have Note that the gate electrode 104 of the transistor has a structure which does not overlap with the source electrode 116a and the drain electrode 116b. Note that the transistor does not need to have the base insulating film 102.

Note that depending on the type of the conductive film used for the source electrode 116 a and the drain electrode 116 b, oxygen is removed from part of the multilayer film 106, or a mixed layer (a metal element which is a main component of the conductive film enters the multilayer film 106. A source region and a drain region may be formed in the multilayer film 106 between the channel and the source electrode 116a and the drain electrode 116b. In FIG. 21B, the source region and the drain region are denoted by n layers and indicated by dotted lines.

In the transistor illustrated in FIG. 21, the channel formation region is a multilayer film 106 that is sandwiched between the source electrode 116 a and the drain electrode 116 b and overlaps with the gate electrode 104. Here, a main path of a current flowing through the oxide semiconductor layer 106b is referred to as a channel.

As illustrated in FIG. 21C, the oxide semiconductor layer 106b forming the channel of the transistor has a structure in which an oxide layer 106d is provided on a side surface. The side surface of the oxide semiconductor layer 106b is a region where oxygen vacancies or the like are easily generated and the impurity concentration is easily increased in the absence of a protective film. If a large amount of oxygen vacancies or impurities exist on the side surface, it may behave as if a second transistor having a different threshold voltage is formed on the side surface, and the electrical characteristics of the transistor vary. In the transistor illustrated in FIG. 21, the oxide layer 106d protects the side surface of the oxide semiconductor layer 106b, so that oxygen vacancies are not generated in the side surface and the impurity concentration is not increased. Therefore, a transistor having stable electric characteristics is obtained.

In FIG. 21C, the base insulating film 102 includes three regions having different thicknesses. Specifically, the first region in contact with the oxide layer 106a has the largest thickness and is the same as the outer periphery of the oxide layer 106d (see FIG. 21A) or outside the outer periphery of the oxide layer 106d. The second region located next to the second region has the next largest thickness, and the third region further outside the second region has the smallest thickness.

For the multilayer film 106, refer to the description of the multilayer film 106 shown in the previous section. The transistor illustrated in FIG. 21 is a transistor in which a channel is formed in the oxide semiconductor layer 106 b included in the multilayer film 106. Since the oxide semiconductor layer 106b has a wide band gap and is substantially intrinsic, a leakage current (also referred to as off-state current) when the transistor is off is extremely small. Specifically, in a transistor having a channel length of 3 μm and a channel width of 10 μm, the off-state current is less than 1 × 10 ⁻²⁰ A, preferably less than 1 × 10 ⁻²² A, more preferably less than 1 × 10 ⁻²⁴ A. can do. That is, the on / off ratio can be 15 to 50 digits, preferably 20 to 50 digits, and more preferably 20 to 150 digits.

The transistor illustrated in FIGS. 21A and 21B includes an oxide layer 106d having a curved surface as a part of the multilayer film 106 and the base insulating film 102 having three regions with different thicknesses; The step coverage of the film to be increased is increased, and the generation of cracks and voids in the film is suppressed. Therefore, impurities are not introduced from the outside due to film cracks or voids, and the transistor has stable electrical characteristics.

There is no major limitation on the substrate 100. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 100. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI (Silicon On Insulator) substrate, or the like can be applied, and a semiconductor element is formed on these substrates. A substrate provided with may be used as the substrate 100.

Further, as the substrate 100, the fifth generation (1000 mm × 1200 mm or 1300 mm × 1500 mm), the sixth generation (1500 mm × 1800 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2500 mm), the ninth generation ( When a large glass substrate such as 2400 mm × 2800 mm) or 10th generation (2880 × 3130 mm) is used, fine processing may be difficult due to shrinkage of the substrate 100 caused by heat treatment in a manufacturing process of a semiconductor device. Therefore, in the case where a large glass substrate as described above is used as the substrate 100, it is preferable to use a substrate with small shrinkage due to heat treatment. For example, the substrate 100 has a large shrinkage amount of 10 ppm or less, preferably 5 ppm or less, more preferably 3 ppm or less after heat treatment at 400 ° C., preferably 450 ° C., more preferably 500 ° C. for 1 hour. A glass substrate may be used.

Further, a flexible substrate may be used as the substrate 100. Note that as a method for providing a transistor over a flexible substrate, there is a method in which after a transistor is manufactured over a non-flexible substrate, the transistor is peeled off and transferred to the substrate 100 which is a flexible substrate. In that case, a separation layer is preferably provided between the non-flexible substrate and the transistor.

The base insulating film 102 is formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. One or more insulating films including one or more layers may be used as a single layer or stacked layers.

For example, the base insulating film 102 may be a multilayer film in which a first layer is a silicon nitride layer and a second layer is a silicon oxide layer. In this case, the silicon oxide layer may be a silicon oxynitride layer. The silicon nitride layer may be a silicon nitride oxide layer. As the silicon oxide layer, a silicon oxide layer with a low defect density is preferably used. Specifically, a silicon oxide layer in which the spin density of a spin derived from a signal having a g value of 2.001 by ESR is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less. Is used. As the silicon oxide layer, a silicon oxide layer containing excess oxygen is used. As the silicon nitride layer, a silicon nitride layer that releases less hydrogen and ammonia is used. The release amount of hydrogen and ammonia may be measured by TDS analysis. As the silicon nitride layer, a silicon nitride layer that does not transmit or hardly transmits oxygen is used.

Excess oxygen refers to oxygen that can move in an oxide layer, an oxide semiconductor layer, a silicon oxide layer, a silicon oxynitride layer, or the like by heat treatment, or in excess of oxygen that has a stoichiometric composition. Oxygen or oxygen having a function of entering oxygen deficiency and reducing oxygen deficiency.

A silicon oxide layer containing excess oxygen refers to a silicon oxide layer from which oxygen can be released by heat treatment or the like. The insulating film containing excess oxygen is an insulating film having a function of releasing oxygen by heat treatment.

Here, oxygen is released by heat treatment means that oxygen released by TDS analysis is converted into oxygen atoms in an amount of 1 × 10 ¹⁸ atoms / cm ³ or more, 1 × 10 ¹⁹ atoms / cm ³ or more, or 1 × 10. ^It means ²⁰ atoms / cm ³ or more.

Here, a method of measuring the amount of released oxygen using TDS analysis will be described below.

The total amount of gas released when the measurement sample is subjected to TDS analysis is proportional to the integrated value of the ionic strength of the released gas. The total amount of gas released can be calculated by comparison with a standard sample.

For example, from the TDS analysis result of a silicon wafer containing hydrogen of a predetermined density as a standard sample, and the TDS analysis result of the measurement sample, the amount of released oxygen molecules (N _O2 ) of the measurement sample is obtained by Equation (2). Can do. Here, it is assumed that all the gases detected by the mass number 32 obtained by the TDS analysis are derived from oxygen molecules. There is CH ₃ OH in addition to those having a mass number of 32, but these are not considered here because they are unlikely to exist. In addition, oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18 which are isotopes of oxygen atoms are not considered because the existence ratio in nature is extremely small.

N _H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. _SH2 is an integral value of ion intensity when the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is N _H2 / SH ₂ . S _O2 is an integrated value of ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ionic strength in the TDS analysis. For details of Equation (2), refer to Japanese Patent Laid-Open No. Hei 6-275697. The oxygen release amount is determined by using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd., and using a silicon wafer containing 1 × 10 ¹⁶ atoms / cm ² of hydrogen atoms as a standard sample. It was measured.

In TDS analysis, part of oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can be estimated by evaluating the amount of released oxygen molecules.

Note that N _{2 O 2} is the amount of released oxygen molecules. The amount of release when converted to oxygen atoms is twice the amount of release of oxygen molecules.

Alternatively, releasing oxygen by heat treatment means containing a peroxide radical. Specifically, it means that the spin density resulting from the peroxide radical is 5 × 10 ¹⁷ spins / cm ³ or more. Note that including a peroxide radical means that an ESR has an asymmetric signal with a g value near 2.01.

Alternatively, the insulating film containing excess oxygen may be oxygen-excess silicon oxide (SiO _X (X> 2)). Oxygen-excess silicon oxide (SiO _X (X> 2)) contains oxygen atoms more than twice the number of silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are values measured by RBS.

The source electrode 116a and the drain electrode 116b are each formed using a single layer or a stack of conductive films containing one or more of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten. That's fine. Note that the source electrode 116a and the drain electrode 116b may have the same composition or different compositions.

The gate insulating film 112 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. One or more insulating films including one or more layers may be used as a single layer or stacked layers.

For example, the gate insulating film 112 may be a multilayer film in which a first layer is a silicon nitride layer and a second layer is a silicon oxide layer. In this case, the silicon oxide layer may be a silicon oxynitride layer. The silicon nitride layer may be a silicon nitride oxide layer. As the silicon oxide layer, a silicon oxide layer with a low defect density is preferably used. Specifically, the spin density of a spin derived from a signal having a g value of 2.001 by electron spin resonance (ESR) is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins. A silicon oxide layer of / cm ³ or less is used. As the silicon oxide layer, a silicon oxide layer containing excess oxygen is preferably used. As the silicon nitride layer, a silicon nitride layer that releases less hydrogen and ammonia is used. The release amount of hydrogen and ammonia may be measured by TDS analysis.

The thickness of the gate insulating film 112 has an optimum value depending on the shapes of the oxide layer 106 a and the base insulating film 102. Here, the thickness of the oxide layer 106a is H _S1 , the difference between the thickness of the second region and the thickness of the third region of the base insulating film 102 is H _O1, and the first region and the second region are The difference in thickness is H _{2 O 2} . At this time, the thickness of the gate insulating film 112 is H _S1 or more, preferably (H _S1 + H _O2 ) or more, and more preferably (H _S1 + H _O2 + H _O1 ) or more. The thickness of the gate insulating film 112 is 100 nm or less, preferably 50 nm or less, more preferably 30 nm or less, and more preferably 20 nm or less. By setting the thickness of the gate insulating film 112 to the above range, an electric field from the gate electrode 104 can be applied to the oxide semiconductor layer 106b through the oxide layer 106d; thus, the transistor can be quickly turned on and off. Thus, the transistor can be operated at high speed.

The gate electrode 104 may be formed using a single layer or a stack of conductive films containing one or more of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten.

Note that as illustrated in FIG. 21A, the multilayer film 106 is not limited to be provided outside the gate electrode 104, and the multilayer film 106 may be provided inside the gate electrode 104. Thus, carriers can be prevented from being generated by light in the multilayer film 106 when light is incident from the substrate 100 side.

Note that in FIG. 21A, the multilayer film 106 is formed to the outside of the gate electrode 104; however, in order to suppress the generation of carriers by light in the multilayer film 106, the inside of the gate electrode 104 is formed. Alternatively, the multilayer film 106 may be formed.

The protective insulating film 118 is formed using aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. One or more insulating films including one or more layers may be used as a single layer or stacked layers.

For example, the protective insulating film 118 may be a multilayer film in which a first layer is a silicon oxide layer and a second layer is a silicon nitride layer. In this case, the silicon oxide layer may be a silicon oxynitride layer. The silicon nitride layer may be a silicon nitride oxide layer. As the silicon oxide layer, a silicon oxide layer with a low defect density is preferably used. Specifically, a silicon oxide layer in which the spin density of a spin derived from a signal having a g value of 2.001 by ESR is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less. Is used. As the silicon nitride layer, a silicon nitride layer that releases less hydrogen and ammonia is used. The release amount of hydrogen and ammonia may be measured by TDS analysis. As the silicon nitride layer, a silicon nitride layer that does not transmit or hardly transmits oxygen is used.

Alternatively, the protective insulating film 118 may be a multilayer film in which a first layer is a first silicon oxide layer, a second layer is a second silicon oxide layer, and a third layer is a silicon nitride layer, for example. In this case, the first silicon oxide layer and / or the second silicon oxide layer may be a silicon oxynitride layer. The silicon nitride layer may be a silicon nitride oxide layer. As the first silicon oxide layer, a silicon oxide layer with a low defect density is preferably used. Specifically, a silicon oxide layer in which the spin density of a spin derived from a signal having a g value of 2.001 by ESR is 3 × 10 ¹⁷ spins / cm ³ or less, preferably 5 × 10 ¹⁶ spins / cm ³ or less. Is used. As the second silicon oxide layer, a silicon oxide layer containing excess oxygen is used. As the silicon nitride layer, a silicon nitride layer that releases less hydrogen and ammonia is used. As the silicon nitride layer, a silicon nitride layer that does not transmit or hardly transmits oxygen is used.

Alternatively, the protective insulating film 118 may be a multilayer film in which a first layer is a silicon nitride layer and a second layer is a silicon oxide layer, for example. In this case, the silicon oxide layer may be a silicon oxynitride layer. The silicon nitride layer may be a silicon nitride oxide layer. As the silicon nitride layer, a silicon nitride layer that releases a large amount of hydrogen and nitrogen is used. The amount of hydrogen and nitrogen released may be measured by TDS analysis. Specifically, the amount of hydrogen released by TDS analysis is 1 × 10 ²⁰ pieces / cm ³ or more, preferably 5 × 10 ²⁰ pieces / cm ³ or more, more preferably 1 × 10 ²¹ pieces / cm ³ or more. A silicon layer is used. Further, a silicon nitride layer having a nitrogen release amount by TDS analysis of 1 × 10 ¹⁹ atoms / cm ³ or more, preferably 5 × 10 ¹⁹ atoms / cm ³ or more, more preferably 1 × 10 ²⁰ atoms / cm ³ or more. Use. As the silicon nitride layer, a silicon nitride layer that does not transmit or hardly transmits oxygen is used. By using a silicon nitride layer as the first layer of the protective insulating film 118, the carrier density on the top surface of the multilayer film 106 can be increased by hydrogen, nitrogen, or the like released from the silicon nitride layer, and the source electrode 116a and the drain electrode Since the resistance between the transistors 116b is reduced, the field-effect mobility of the transistor can be increased.

The wiring 122a and the wiring 122b may be formed using a single layer or a stack of conductive films containing one or more of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten. . Note that the wiring 122a and the wiring 122b may have the same composition or different compositions.

In the case where at least one of the base insulating film 102, the gate insulating film 112, and the protective insulating film 118 includes an insulating film containing excess oxygen, oxygen vacancies in the oxide semiconductor layer 106b can be reduced by the excess oxygen.

The transistor having the above structure has stable electric characteristics and high field-effect mobility when a channel is formed in the oxide semiconductor layer 106b of the multilayer film 106. In addition, since the oxide layer 106d having a curved surface is provided as a part of the multilayer film 106 and includes the base insulating film 102 having three regions having different thicknesses, the step coverage of the upper layer is high, and A transistor having stable electrical characteristics is obtained.

2-1-2. Method for Manufacturing Transistor Structure (1-1) A method for manufacturing the transistor illustrated in FIGS. 21A to 21C is described with reference to FIGS.

First, the substrate 100 is prepared.

Next, an insulating film to be the base insulating film 102 is formed.

Here, the case where the insulating film to be the base insulating film 102 has a three-layer structure is described. First, a silicon nitride layer is formed. Next, a first silicon oxide layer is formed. Next, treatment for adding oxygen ions to the silicon oxide layer may be performed. For the treatment for adding oxygen ions, an ion doping apparatus or a plasma treatment apparatus may be used. An ion doping apparatus having a mass separation function may be used as the ion doping apparatus. As a raw material for oxygen ions, oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas, or ozone gas may be used. Next, an insulating film to be the base insulating film 102 may be formed by forming a second silicon oxide layer.

The silicon nitride layer is preferably formed by a plasma CVD method. Specifically, the substrate temperature is set to 180 ° C. or more and 400 ° C. or less, preferably 200 ° C. or more and 370 ° C. or less, and a pressure of 20 Pa or more and 250 Pa or less, preferably 40 Pa or more using a deposition gas containing nitrogen, nitrogen gas and ammonia gas. The film thickness may be set to 200 Pa or less by supplying high frequency power.

Nitrogen gas is 5 to 50 times, preferably 10 to 50 times the flow rate of ammonia gas. Note that by using ammonia gas, it is possible to promote the decomposition of the deposition gas containing nitrogen and nitrogen gas. This is because the energy generated by the dissociation of ammonia gas by the plasma energy and the thermal energy is the silicon. This is to contribute to the decomposition of the bonding of the deposition gas containing nitrogen and the bonding of the nitrogen gas.

Therefore, a silicon nitride layer with a small release amount of hydrogen gas and ammonia gas can be formed by the above-described method. Further, since the content of hydrogen is small, the silicon nitride layer can be formed dense and hardly or hardly transmit hydrogen, water, and oxygen.

The first silicon oxide layer is preferably formed by a plasma CVD method. Specifically, the substrate temperature is set to 160 ° C. to 350 ° C., preferably 180 ° C. to 260 ° C., and a pressure of 100 Pa to 250 Pa, preferably 100 Pa to 200 Pa using a deposition gas and an oxidizing gas containing silicon. as the electrode to 0.17 W / cm ² or more 0.5 W / cm ² or less, preferably it may be film by supplying high-frequency power of 0.25 W / cm ² or more 0.35 W / cm ² or less.

By the above-described method, the efficiency of gas decomposition in plasma is increased, oxygen radicals are increased, and gas oxidation proceeds. Therefore, the first silicon oxide layer containing excess oxygen can be formed.

The second silicon oxide layer is preferably formed by a plasma CVD method which is a kind of CVD method. Specifically, the substrate temperature is set to 180 ° C. or higher and 400 ° C. or lower, preferably 200 ° C. or higher and 370 ° C. or lower, and a pressure of 20 Pa or higher and 250 Pa or lower, preferably 40 Pa or higher and 200 Pa or lower, using a deposition gas and an oxidizing gas containing silicon. Then, film formation may be performed by supplying high-frequency power to the electrodes. Note that typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

Note that when the flow rate of the oxidizing gas with respect to the deposition gas containing silicon is 100 times or more, the hydrogen content in the second silicon oxide layer can be reduced and dangling bonds can be reduced.

As described above, the second silicon oxide layer having a low defect density is formed. That is, in the second silicon oxide layer, the density of spins derived from a signal having a g value of 2.001 in ESR is 3 × 10 ¹⁷ spins / cm ³ or less, or 5 × 10 ¹⁶ spins / cm ³ or less. be able to.

Next, the oxide layer 106a, the oxide semiconductor layer 106b provided over the oxide layer 106a, the oxide layer 106c provided over the oxide semiconductor layer 106b, and at least a side surface of the oxide semiconductor layer 106b A multilayer film 106 including the oxide layer 106d provided in contact therewith is formed. At this time, part of the insulating film to be the base insulating film 102 is etched to be the base insulating film 133 (see FIG. 22A). For the formation method of the base insulating film 133 and the multilayer film 106, the description of FIGS.

Next, a conductive film to be the source electrode 116a and the drain electrode 116b is formed. As the conductive film to be the source electrode 116a and the drain electrode 116b, the conductive film shown as the source electrode 116a and the drain electrode 116b is formed by a sputtering method, a chemical vapor deposition (CVD) method, or a molecular beam epitaxy (MBE). The film formation may be performed by using an epitaxy (ALD) method, an atomic layer deposition (ALD) method, or a pulse laser deposition (PLD) method.

Next, part of the conductive film to be the source electrode 116a and the drain electrode 116b is etched to form the source electrode 116a and the drain electrode 116b, and part of the base insulating film 133 is etched to form the base insulating film 102. (See FIG. 22B.) The base insulating film 102 has three regions having different thicknesses by being partially etched twice.

Next, a gate insulating film 142 is formed (see FIG. 22C). The gate insulating film 142 may be formed using the insulating film shown as the gate insulating film 112 by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Next, a conductive film to be the gate electrode 104 is formed. The conductive film to be the gate electrode 104 may be formed using the conductive film shown as the gate electrode 104 by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Next, part of the conductive film to be the gate electrode 104 is etched to form the gate electrode 104. Further, the gate insulating film 142 is etched to have a top shape similar to that of the gate electrode 104, so that the gate insulating film 112 is formed (see FIG. 23A).

Next, a protective insulating film 118 is formed (see FIG. 23B). As the protective insulating film 118, the insulating film shown as the protective insulating film 118 may be formed by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method. The protective insulating film 118 is provided with an oxide layer 106d having a curved surface as a part of the multilayer film 106. The base insulating film 102 has three regions having different thicknesses, so that the step coverage is high. , Shape defects are less likely to occur.

Here, the case where the protective insulating film 118 has a three-layer structure is described. First, a first silicon oxide layer is formed. Next, a second silicon oxide layer is formed. Next, treatment for adding oxygen ions to the second silicon oxide layer is preferably performed. For the treatment for adding oxygen ions, an ion doping apparatus or a plasma treatment apparatus may be used. An ion doping apparatus having a mass separation function may be used as the ion doping apparatus. As a raw material for oxygen ions, oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas, or ozone gas may be used. Next, the protective insulating film 118 may be formed by forming a silicon nitride layer.

The first silicon oxide layer is preferably formed by a plasma CVD method which is a kind of CVD method. Specifically, the substrate temperature is set to 180 ° C. or higher and 400 ° C. or lower, preferably 200 ° C. or higher and 370 ° C. or lower, and a pressure of 20 Pa or higher and 250 Pa or lower, preferably 40 Pa or higher and 200 Pa or lower, using a deposition gas and an oxidizing gas containing silicon. Then, film formation may be performed by supplying high-frequency power to the electrodes. Note that typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

Note that when the flow rate of the oxidizing gas with respect to the deposition gas containing silicon is 100 times or more, the hydrogen content in the first silicon oxide layer can be reduced and dangling bonds can be reduced.

As described above, the first silicon oxide layer having a low defect density is formed. That is, in the first silicon oxide layer 118a, the density of the spin derived from the signal having the g value of 2.001 in ESR is 3 × 10 ¹⁷ spins / cm ³ or less, or 5 × 10 ¹⁶ spins / cm ³ or less. can do.

The second silicon oxide layer is preferably formed by a plasma CVD method. Specifically, the substrate temperature is set to 160 ° C. to 350 ° C., preferably 180 ° C. to 260 ° C., and a pressure of 100 Pa to 250 Pa, preferably 100 Pa to 200 Pa using a deposition gas and an oxidizing gas containing silicon. as the electrode to 0.17 W / cm ² or more 0.5 W / cm ² or less, preferably it may be film by supplying high-frequency power of 0.25 W / cm ² or more 0.35 W / cm ² or less.

By the above-described method, the efficiency of gas decomposition in plasma increases, oxygen radicals increase, and gas oxidation proceeds, so that the second silicon oxide layer containing excess oxygen can be formed.

The silicon nitride layer is preferably formed by a plasma CVD method. Specifically, the substrate temperature is set to 180 ° C. or more and 400 ° C. or less, preferably 200 ° C. or more and 370 ° C. or less, and a pressure of 20 Pa or more and 250 Pa or less, preferably 40 Pa or more using a deposition gas containing nitrogen, nitrogen gas and ammonia gas. The film thickness may be set to 200 Pa or less by supplying high frequency power.

Nitrogen gas is 5 to 50 times, preferably 10 to 50 times the flow rate of ammonia gas. Note that by using ammonia gas, it is possible to promote the decomposition of the deposition gas containing nitrogen and nitrogen gas. This is because the energy generated by the dissociation of ammonia gas by the plasma energy and the thermal energy is the silicon. This is to contribute to the decomposition of the bonding of the deposition gas containing nitrogen and the bonding of the nitrogen gas.

Therefore, a silicon nitride layer with a small release amount of hydrogen and ammonia can be formed by the above-described method. Further, since the content of hydrogen is small, the silicon nitride layer can be formed dense and hardly or hardly transmit hydrogen, water, and oxygen.

A case where the protective insulating film 118 has a two-layer structure is described. First, a silicon nitride layer is formed. Next, a silicon oxide layer is formed.

The silicon nitride layer is preferably formed by a plasma CVD method. Specifically, the substrate temperature is set to 180 ° C. or higher and 400 ° C. or lower, preferably 200 ° C. or higher and 370 ° C. or lower, and a pressure of 10 Pa or higher and 100 Pa or lower, preferably 20 Pa or higher, using a deposition gas containing silicon, ammonia gas and argon gas. The film may be formed by supplying high-frequency power at 50 Pa or less.

Note that the ammonia gas is 30 times to 1000 times, preferably 50 times to 500 times the flow rate of the deposition gas containing silicon. With such a condition, a silicon nitride layer with a large release amount of hydrogen and nitrogen can be formed.

By releasing hydrogen and ammonia from the silicon nitride layer, a region having a high carrier density can be formed on the upper surface of the multilayer film 106. Accordingly, resistance between the source electrode 116a and the drain electrode 116b is reduced, so that the field-effect mobility of the transistor can be increased.

Note that before forming the protective insulating film 118, an impurity for reducing the resistance of the multilayer film 106 may be added to the multilayer film 106 using the gate electrode 104 and the gate insulating film 112 as a mask. As the impurity, one or more selected from hydrogen, helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony, and xenon may be added. Note that this method may be performed by an ion implantation method or an ion doping method. An ion implantation method is preferably used.

Next, heat treatment is preferably performed. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C. The atmosphere for the heat treatment is an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more, or a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. . By the heat treatment, excess oxygen is released from at least one of the base insulating film 102, the gate insulating film 112, and the protective insulating film 118, so that oxygen vacancies in the multilayer film 106 can be reduced. Note that in the multilayer film 106, oxygen vacancies apparently move by capturing adjacent oxygen atoms. Accordingly, excess oxygen can reach the oxide semiconductor layer 106b through the oxide layer 106a, the oxide layer 106c, the oxide layer 106d, and the like.

Next, openings reaching the source electrode 116 a and the drain electrode 116 b are formed in the protective insulating film 118.

Next, a conductive film to be the wiring 122a and the wiring 122b is formed. The conductive film to be the wiring 122a and the wiring 122b may be formed using the conductive film shown as the wiring 122a and the wiring 122b by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Next, part of the conductive film to be the wirings 122a and 122b is etched, so that the wirings 122a and 122b are formed (see FIG. 23C).

As described above, a transistor can be manufactured.

The transistor has stable electric characteristics because oxygen vacancies in the oxide semiconductor layer 106b in the multilayer film 106 are reduced. In addition, an oxide layer 106d having a curved surface is provided as a part of the multilayer film 106, and the base insulating film 102 includes three regions having different thicknesses, so that the step coverage of the protective insulating film 118 and the like can be increased. Is high and it is difficult for shape defects to occur, so that productivity can be improved.

2-2. Transistor structure (2)
In this section, a top gate transistor having a structure different from that of the previous section will be described.

2-2-1. Transistor structure (2-1)
Here, a transistor which is a kind of top-gate transistor is described with reference to FIGS.

FIG. 24 shows a top view and a cross-sectional view of the transistor. FIG. 24A illustrates a top view of a transistor. In FIG. 24A, a cross-sectional view corresponding to the dashed-dotted line B1-B2 is illustrated in FIG. FIG. 24C illustrates a cross-sectional view corresponding to the dashed-dotted line B3-B4 in FIG.

A transistor illustrated in FIG. 24B includes a base insulating film 202 provided over a substrate 200, an oxide layer 206a provided over the base insulating film 202, and an oxide semiconductor layer provided over the oxide layer 206a. 206b, a multilayer film 206 including an oxide layer 206c provided over the oxide semiconductor layer 206b, and an oxide layer 206d provided in contact with at least a side surface of the oxide semiconductor layer 206b; and a multilayer film 206 provided over the multilayer film 206. Gate insulating film 212, gate electrode 204 provided on gate insulating film 212, sidewall insulating film 210 provided in contact with the side surface of gate electrode 204, multilayer film 206, gate insulating film 212, and gate electrode 204. A protective insulating film 218 having an opening reaching the multilayer film 206, and a protective insulating film 218 provided on the protective insulating film 218; It has a wiring 222a and a wiring 222b in contact with the multilayer film 206, the through part. Note that the transistor may not include the base insulating film 202 and / or the sidewall insulating film 210. FIG. 24B illustrates a structure in which the lower surface of the sidewall insulating film 210 is provided in contact with the upper surface of the gate insulating film 212; however, the present invention is not limited to this. For example, a structure in which the lower surface of the sidewall insulating film 210 is provided in contact with the upper surface of the multilayer film 206 may be employed.

As illustrated in FIG. 24C, the oxide semiconductor layer 206b forming the channel of the transistor has a structure in which an oxide layer 206d is provided on a side surface. The side surface of the oxide semiconductor layer 206b is a region where oxygen vacancies or the like are easily generated and the impurity concentration is easily increased when there is no protective film. If a large amount of oxygen vacancies or impurities exist on the side surface, it may behave as if a second transistor having a different threshold voltage is formed on the side surface, and the electrical characteristics of the transistor vary. In the transistor illustrated in FIG. 24, since the oxide layer 206d protects the side surface of the oxide semiconductor layer 206b, oxygen vacancies are not generated in the side surface and the impurity concentration is not increased. Therefore, a transistor having stable electric characteristics is obtained.

In FIG. 24C, the base insulating film 202 has three regions with different thicknesses. Specifically, the first region in contact with the oxide layer 206a has the largest thickness and is the same as the outer periphery of the oxide layer 206d (see FIG. 24A) or outside the outer periphery of the oxide layer 206d. The second region located next to the second region has the next largest thickness, and the third region further outside the second region has the smallest thickness.

The sidewall insulating film 210 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. One or more insulating films including one or more layers may be used as a single layer or stacked layers.

For the multilayer film 206, the description of the multilayer film 106 is referred to. Specifically, the oxide layer 206a is the oxide layer 106a, the oxide semiconductor layer 206b is the oxide semiconductor layer 106b, the oxide layer 206c is the oxide layer 106c, and the oxide layer 206d is the oxide layer 106d. Each corresponds. The transistor illustrated in FIG. 24 is a transistor in which a channel is formed in the oxide semiconductor layer 206b included in the multilayer film 206. Since the oxide semiconductor layer 206b has a wide band gap and is substantially intrinsic, a leakage current (also referred to as off-state current) when the transistor is off is extremely small. Specifically, in a transistor having a channel length of 3 μm and a channel width of 10 μm, the off-state current is less than 1 × 10 ⁻²⁰ A, preferably less than 1 × 10 ⁻²² A, more preferably less than 1 × 10 ⁻²⁴ A. can do. That is, the on / off ratio can be 20 digits or more and 150 digits or less.

For the substrate 200, the description of the substrate 100 is referred to. For the gate insulating film 212, the description of the gate insulating film 112 is referred to. For the gate electrode 204, the description of the gate electrode 104 is referred to. For the protective insulating film 218, the description of the protective insulating film 118 is referred to. For the wiring 222a and the wiring 222b, the description of the wiring 122a and the wiring 122b is referred to.

The transistor illustrated in FIG. 24 includes an oxide layer 206d having a curved surface as a part of the multilayer film 206, and the base insulating film 202 having three regions with different thicknesses; The step coverage of the film to be increased is increased, and the generation of cracks and voids in the film is suppressed. Therefore, impurities are not introduced from the outside due to film cracks or voids, and the transistor has stable electrical characteristics.

2-2-2. Method for Manufacturing Transistor Structure (2-1) Here, a method for manufacturing a transistor is described with reference to FIGS.

First, the substrate 200 is prepared.

Next, the base insulating film 202 and the multilayer film 206 are formed (see FIG. 25A). For the formation method of the base insulating film 202 and the multilayer film 206, the description of FIGS. 6 and 7 is referred to.

Next, a gate insulating film 242 is formed (see FIG. 25B). For the gate insulating film 242, refer to the description of the gate insulating film 142.

Next, a conductive film to be the gate electrode 204 is formed. For the method for forming the conductive film to be the gate electrode 204, the description of the method for forming the conductive film to be the gate electrode 104 is referred to.

Next, part of the conductive film to be the gate electrode 204 is etched to form the gate electrode 204 (see FIG. 23A).

Next, an insulating film to be the sidewall insulating film 210 is formed. As a method for forming the insulating film to be the sidewall insulating film 210, the insulating film shown as the sidewall insulating film 210 may be formed by a sputtering method, a CVD method, an MBE method, an ALD method, or a PLD method.

Next, the sidewall insulating film 210 is formed in a self-aligned manner by performing highly anisotropic etching on the insulating film to be the sidewall insulating film 210. For example, a dry etching method may be used as the highly anisotropic etching. In addition, the gate insulating film 242 is etched to have the same top shape as that of the gate electrode 204 and the sidewall insulating film 210 in combination, so that the gate insulating film 212 is formed (see FIG. 26A).

Next, a protective insulating film 218 is formed (see FIG. 26B). For the deposition method of the protective insulating film 218, the description of the deposition method of the protective insulating film 118 is referred to. The protective insulating film 218 is provided with an oxide layer 206d having a curved surface as a part of the multilayer film 206. The base insulating film 202 has three regions having different thicknesses, so that the step coverage is high. , Shape defects are less likely to occur.

Note that before forming the protective insulating film 218, an impurity for reducing the resistance of the multilayer film 206 may be added to the multilayer film 206 using the gate electrode 204, the sidewall insulating film 210, and the gate insulating film 212 as a mask. As the impurity, one or more selected from hydrogen, helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony, and xenon may be added. Note that this method may be performed by an ion implantation method or an ion doping method. An ion implantation method is preferably used.

Next, heat treatment is preferably performed. The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C. The atmosphere for the heat treatment is an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more, or a reduced pressure state. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. . By the heat treatment, excess oxygen is released from at least one of the base insulating film 202, the gate insulating film 212, and the protective insulating film 218, so that oxygen vacancies in the multilayer film 206 can be reduced. Note that in the multilayer film 206, oxygen vacancies apparently move by capturing adjacent oxygen atoms. Accordingly, excess oxygen can reach the oxide semiconductor layer 206b through the oxide layer 206a, the oxide layer 206c, the oxide layer 206d, and the like.

Next, an opening reaching the multilayer film 206 is formed in the protective insulating film 218.

Next, a conductive film to be the wiring 222a and the wiring 222b is formed. For the conductive film to be the wiring 222a and the wiring 222b, the description of the film formation method for the conductive film to be the wiring 122a and the wiring 122b is referred to.

Next, part of the conductive film to be the wiring 222a and the wiring 222b is etched to form the wiring 222a and the wiring 222b (see FIG. 26C).

As described above, a transistor can be manufactured.

The transistor has stable electric characteristics because oxygen vacancies in the oxide semiconductor layer 206b of the multilayer film 206 are reduced. Further, an oxide layer 206d having a curved surface is provided as a part of the multilayer film 206, and the base insulating film 202 includes three regions having different thicknesses, so that the step coverage of the protective insulating film 218 and the like can be increased. Is high and it is difficult for shape defects to occur, so that productivity can be improved.

3. In this section, an example of a semiconductor device according to one embodiment of the present invention is described.

In the following, each layer of the multilayer film of the transistor may be omitted. In addition, steps (regions having different thicknesses) of a film (such as a base insulating film) which is a base generated when forming a multilayer film may be omitted.

3-1. Microcomputer The above-described transistor can be applied to a microcomputer mounted on various electronic devices.

Hereinafter, the configuration and operation of a fire alarm will be described with reference to FIGS. 27, 28, 29, and 30A as an example of an electronic device equipped with a microcomputer.

In addition, in this specification, a fire alarm means a general device that promptly reports the occurrence of a fire. For example, it is used for a residential fire alarm, an automatic fire alarm facility, or the automatic fire alarm facility. Fire alarms, etc., to be included in fire alarms.

The alarm device illustrated in FIG. 27 includes at least a microcomputer 500. Here, the microcomputer 500 is provided inside the alarm device. The microcomputer 500 includes a power gate controller 503 electrically connected to the high-potential power line VDD, a power gate 504 electrically connected to the high-potential power line VDD and the power gate controller 503, and the power gate 504 and the power gate 504. A central processing unit (CPU) 505 and a detection unit 509 electrically connected to the power gate 504 and the CPU 505 are provided. The CPU 505 includes a volatile storage unit 506 and a nonvolatile storage unit 507.

The CPU 505 is electrically connected to the bus line 502 via the interface 508. The interface 508 is also electrically connected to the power gate 504 in the same manner as the CPU 505. As the bus standard of the interface 508, for example, an I ² C bus or the like can be used. In addition, the alarm device is provided with a light emitting element 530 that is electrically connected to the power gate 504 via the interface 508.

The light emitting element 530 preferably emits light having strong directivity. For example, an organic EL element, an inorganic EL element, an LED, or the like can be used.

The power gate controller 503 has a timer and controls the power gate 504 according to the timer. The power gate 504 supplies or cuts off the power supplied from the high-potential power line VDD to the CPU 505, the detection unit 509, and the interface 508 according to the control of the power gate controller 503. Here, as the power gate 504, for example, a switching element such as a transistor can be used.

By using the power gate controller 503 and the power gate 504, power is supplied to the detection unit 509, the CPU 505, and the interface 508 during the period of measuring the light amount, and the detection unit 509, the CPU 505, and the interface are provided between the measurement periods. The power supply to 508 can be cut off. By operating the alarm device in this way, it is possible to reduce power consumption compared to the case where power is constantly supplied to each of the above components.

In the case where a transistor is used as the power gate 504, it is preferable to use a transistor with a very low off-state current used for the nonvolatile memory portion 507, for example, a transistor including a multilayer film including the above-described oxide semiconductor layer. By using such a transistor, leakage current can be reduced and power consumption can be reduced when the power gate 504 shuts off the power supply.

A DC power supply 501 may be provided in the alarm device, and power may be supplied from the DC power supply 501 to the high potential power supply line VDD. The high potential side electrode of the DC power supply 501 is electrically connected to the high potential power supply line VDD, and the low potential side electrode of the DC power supply 501 is electrically connected to the low potential power supply line VSS. The low potential power line VSS is electrically connected to the microcomputer 500. Here, a high potential H is applied to the high potential power supply line VDD. The low potential power supply line VSS is supplied with a low potential L such as a ground potential (GND).

In the case where a battery is used as the DC power supply 501, for example, an electrode electrically connected to the high potential power supply line VDD, an electrode electrically connected to the low potential power supply line VSS, and the battery can be held. A battery case having a housing may be provided in the housing. Note that the alarm device does not necessarily need to be provided with the DC power source 501, and may be configured to supply power via a wiring from an AC power source provided outside the alarm device, for example.

In addition, a secondary battery such as a lithium ion secondary battery (also referred to as a lithium ion storage battery, a lithium ion battery, or a lithium ion battery) can be used as the battery. In addition, a solar battery is preferably provided so that the secondary battery can be charged.

The detection unit 509 measures a physical quantity related to the abnormality and transmits the measurement value to the CPU 505. The physical quantity relating to the abnormality varies depending on the use of the alarm device, and the alarm device functioning as a fire alarm measures the physical quantity relating to the fire. Therefore, the detection unit 509 measures the amount of light as a physical quantity related to a fire and senses the presence of smoke.

The detection unit 509 includes an optical sensor 511 that is electrically connected to the power gate 504, an amplifier 512 that is electrically connected to the power gate 504, and an AD converter 513 that is electrically connected to the power gate 504 and the CPU 505. Have. The light emitting element 530, the optical sensor 511, the amplifier 512, and the AD converter 513 operate when the power gate 504 supplies power to the detection unit 509.

FIG. 28 shows a part of a cross section of the alarm device. A p-type semiconductor substrate 101 has an element isolation region 103, and has a gate insulating film 107 and a gate electrode 109, an n-type impurity region 111 a, an n-type impurity region 111 b, an insulating film 115 and an insulating film 117. A transistor 519 is formed. The n-type transistor 519 is formed using a semiconductor such as single crystal silicon and can operate at high speed. Therefore, it is possible to form a volatile storage unit of the CPU that can be accessed at high speed.

In addition, contact plugs 119a and 119b are formed in openings in which a part of the insulating film 115 and the insulating film 117 is selectively etched, and an insulating film having a groove over the insulating film 117, the contact plug 119a, and the contact plug 119b. 121 is provided. In addition, a wiring 123 a and a wiring 123 b are formed in the groove portion of the insulating film 121. Further, the insulating film 120 is formed over the insulating film 121, the wiring 123a, and the wiring 123b by a sputtering method, a CVD method, or the like, and the insulating film 122 having a groove is formed over the insulating film 120. An electrode 124 is formed in the groove portion of the insulating film 122. The electrode 124 is an electrode that functions as a back gate electrode of the second transistor 517. By providing such an electrode 124, the threshold voltage of the second transistor 517 can be controlled.

An insulating film 125 is provided over the insulating film 122 and the electrode 124 by a sputtering method, a CVD method, or the like.

A second transistor 517 and a photoelectric conversion element 514 are provided over the insulating film 125. The second transistor 517 includes a multilayer film 106, a source electrode 116 a and a drain electrode 116 b that are in contact with the multilayer film 106, a gate insulating film 112, a gate electrode 104, and a protective insulating film 118. An insulating film 145 that covers the photoelectric conversion element 514 and the second transistor 517 is provided, and a wiring 149 is provided over the insulating film 145 in contact with the drain electrode 116b. For the wiring 149, the description of the wiring 122b is referred to. Note that the wiring 149 functions as a node that electrically connects the drain electrode of the second transistor 517 and the gate electrode 109 of the n-type transistor 519.

The optical sensor 511 includes a photoelectric conversion element 514, a capacitor, a first transistor, a second transistor 517, a third transistor, and an n-type transistor 519. Here, as the photoelectric conversion element 514, for example, a photodiode or the like can be used.

One terminal of the photoelectric conversion element 514 is electrically connected to the low-potential power supply line VSS, and the other terminal is electrically connected to one of the source electrode and the drain electrode of the second transistor 517. The gate electrode of the second transistor 517 is supplied with the charge accumulation control signal Tx, and the other of the source electrode and the drain electrode is one of the pair of electrodes of the capacitor and one of the source electrode and the drain electrode of the first transistor. Are electrically connected to the gate electrode of the n-type transistor 519 (hereinafter, the node may be referred to as a node FD). The other of the pair of electrodes of the capacitor is electrically connected to the low potential power supply line VSS. A reset signal Res is supplied to the gate electrode of the first transistor, and the other of the source electrode and the drain electrode is electrically connected to the high potential power supply line VDD. One of a source electrode and a drain electrode of the n-type transistor 519 is electrically connected to the amplifier 512 and one of the source electrode and the drain electrode of the third transistor. The other of the source electrode and the drain electrode of the n-type transistor 519 is electrically connected to the high potential power supply line VDD. A bias signal Bias is supplied to the gate electrode of the third transistor, and the other of the source electrode and the drain electrode is electrically connected to the low potential power supply line VSS.

Note that the capacitor is not necessarily provided. For example, when the parasitic capacitance of the n-type transistor 519 or the like is sufficiently large, the capacitor may not be provided.

In addition, it is preferable to use transistors with extremely low off-state current for the first transistor and the second transistor 517. As the transistor with extremely low off-state current, a transistor including a multilayer film including the above-described oxide semiconductor layer is preferably used. With such a structure, the potential of the node FD can be held for a long time.

In the structure illustrated in FIG. 28, the photoelectric conversion element 514 is provided over the insulating film 125 so as to be electrically connected to the second transistor 517.

The photoelectric conversion element 514 includes a semiconductor film 160 provided over the insulating film 125, and a source electrode 116 a and an electrode 116 c provided in contact with the semiconductor film 160. The source electrode 116 a is an electrode functioning as a source electrode or a drain electrode of the second transistor 517 and electrically connects the photoelectric conversion element 514 and the second transistor 517.

A gate insulating film 112, a protective insulating film 118, and an insulating film 145 are provided over the semiconductor film 160, the source electrode 116a, and the electrode 116c. A wiring 156 is provided over the insulating film 145 and is in contact with the electrode 116 c through an opening provided in the gate insulating film 112, the protective insulating film 118, and the insulating film 145.

The electrode 116 c can be formed in the same process as the wiring 149, and the source electrode 116 a and the drain electrode 116 b and the wiring 156 can be formed.

As the semiconductor film 160, a semiconductor film that can perform photoelectric conversion may be provided. For example, silicon, germanium, or the like can be used. When silicon is used for the semiconductor film 160, it functions as an optical sensor that detects visible light. In addition, since the wavelength of electromagnetic waves that can be absorbed is different between silicon and germanium, a structure in which germanium is used for the semiconductor film 160 can be used as a sensor that detects infrared rays.

As described above, since the microcomputer 500 can be provided with the detection portion 509 including the optical sensor 511, the number of components can be reduced and the housing of the alarm device can be reduced.

The fire alarm including the above-described IC chip uses a CPU 505 in which a plurality of circuits using the above-described transistors are combined and mounted on one IC chip.

3-1-1. CPU
FIG. 29 is a block diagram illustrating a specific configuration of a CPU using at least part of the above-described transistors.

29A includes an ALU 1191 (ALU: Arithmetic logic unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, and a register controller 1197. , A bus interface 1198 (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 29A is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the internal clock signal CLK2 to the various circuits.

In the CPU illustrated in FIG. 29A, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the above-described transistor can be used.

In the CPU illustrated in FIG. 29A, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

The power supply is stopped by providing a switching element between the memory cell group and the node to which the power supply potential VDD or the power supply potential VSS is applied, as shown in FIG. 29B or 29C. Can do. The circuits in FIGS. 29B and 29C will be described below.

FIGS. 29B and 29C illustrate a memory device in which the above-described transistor is used as a switching element that controls supply of a power supply potential to a memory cell.

A memory device illustrated in FIG. 29B includes a switching element 1141 and a memory cell group 1143 including a plurality of memory cells 1142. Specifically, the above-described transistor can be used for each memory cell 1142. A high-level power supply potential VDD is supplied to each memory cell 1142 included in the memory cell group 1143 through the switching element 1141. Further, each memory cell 1142 included in the memory cell group 1143 is supplied with the potential of the signal IN and the low-level power supply potential VSS.

In FIG. 29B, the above-described transistor is used as the switching element 1141, and switching of the transistor is controlled by a signal SigA applied to the gate electrode thereof.

Note that FIG. 29B illustrates a structure in which the switching element 1141 includes only one transistor; however, there is no particular limitation, and a plurality of transistors may be included. In the case where the switching element 1141 includes a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be combined in series and parallel. May be connected.

In FIG. 29B, the switching element 1141 controls the supply of the high-level power supply potential VDD to each memory cell 1142 included in the memory cell group 1143, but the switching element 1141 controls the low-level power supply potential VDD. The supply of the power supply potential VSS may be controlled.

FIG. 29C illustrates an example of a memory device in which a low-level power supply potential VSS is supplied to each memory cell 1142 included in the memory cell group 1143 through the switching element 1141. The switching element 1141 can control supply of the low-level power supply potential VSS to each memory cell 1142 included in the memory cell group 1143.

A switching element is provided between the memory cell group and a node to which the power supply potential VDD or the power supply potential VSS is applied to temporarily stop the operation of the CPU and retain data even when the supply of the power supply voltage is stopped. It is possible to reduce power consumption. Specifically, for example, the operation of the CPU can be stopped while the user of the personal computer stops inputting information to an input device such as a keyboard, thereby reducing power consumption. it can.

Here, the CPU has been described as an example, but the present invention can also be applied to LSIs such as a DSP (Digital Signal Processor), a custom LSI, and an FPGA (Field Programmable Gate Array).

3-1-2. Installation Example In FIG. 30A, an alarm device 8100 is a residential fire alarm, and includes a detection unit and a microcomputer 8101. The microcomputer 8101 includes a CPU using the above-described transistor.

In FIG. 30A, an air conditioner including an indoor unit 8200 and an outdoor unit 8204 includes a CPU using the above-described transistor. Specifically, the indoor unit 8200 includes a housing 8201, an air outlet 8202, a CPU 8203, and the like. FIG. 30A illustrates the case where the CPU 8203 is provided in the indoor unit 8200; however, the CPU 8203 may be provided in the outdoor unit 8204. Alternatively, the CPU 8203 may be provided in both the indoor unit 8200 and the outdoor unit 8204. By including the CPU using the above-described transistor, it is possible to save power in the air conditioner.

In FIG. 30A, an electric refrigerator-freezer 8300 includes a CPU using the above-described transistor. Specifically, the electric refrigerator-freezer 8300 includes a housing 8301, a refrigerator door 8302, a freezer door 8303, a CPU 8304, and the like. In FIG. 30A, the CPU 8304 is provided inside the housing 8301. By including the CPU using the above-described transistor, the electric refrigerator-freezer 8300 can save power.

FIG. 30B illustrates an example of an electric vehicle. An electric vehicle 9700 is equipped with a secondary battery 9701. The output of the power of the secondary battery 9701 is adjusted by the control circuit 9702 and supplied to the driving device 9703. The control circuit 9702 is controlled by a processing device 9704 having a ROM, a RAM, a CPU, etc. (not shown). By including the CPU using the above-described transistor, the electric vehicle 9700 can save power.

Drive device 9703 is configured by a DC motor or an AC motor alone, or a combination of an electric motor and an internal combustion engine. The processing device 9704 is based on input information such as operation information (acceleration, deceleration, stop, etc.) of the driver of the electric vehicle 9700 and information at the time of travel (information such as uphill and downhill, load information on the drive wheels, etc.). The control signal is output to the control circuit 9702. The control circuit 9702 controls the output of the driving device 9703 by adjusting the electric energy supplied from the secondary battery 9701 according to the control signal of the processing device 9704. When an AC motor is mounted, an inverter that converts direct current to alternating current is also built in, although not shown.

70 atmosphere side substrate supply chamber 70a film formation chamber 70b film formation chamber 71 atmosphere side substrate supply chamber 72a load lock chamber 72b unload lock chamber 73 transfer chamber 73a transfer chamber 73b transfer chamber 74 cassette port 75 substrate heating chamber 76 substrate transfer robot 80 Deposition chamber 80a Deposition chamber 80b Deposition chamber 80c Deposition chamber 80d Deposition chamber 81 Air side substrate supply chamber 82 Load / unload lock chamber 83 Transfer chamber 84 Cassette port 85 Substrate heating chamber 86 Substrate transfer robot 87 Target 88 Prevention Substrate 89 Glass substrate 90 Substrate stage 92 Substrate stage 93 Heating mechanism 94 Purifier 95a Cryo pump 95b Cryo pump 95c Turbo molecular pump 95d Cryo pump 95e Cryo pump 95f Cryo pump 96 Vacuum pump 96a Vacuum pump 96b Vacuum pump 96c Vacuum pump 97 Mass flow controller 98 Gas heating mechanism 99 Cryo trap 100 Substrate 101 Semiconductor substrate 102 Base insulating film 103 Element isolation region 104 Gate electrode 105 Oxide layer 106 Multilayer film 106a Oxide layer 106b Oxide semiconductor layer 106c Oxide layer 106d Oxide layer 107 Gate insulating film 109 Gate electrode 111a Impurity region 111b Impurity region 112 Gate insulating film 115 Insulating film 116a Source electrode 116b Drain electrode 116c Electrode 117 Insulating film 118 Protective insulating film 118a Silicon oxide layer 119a Contact plug 119b Contact plug 120 Insulating film 121 Insulating Film 122 Insulating film 122a Wiring 122b Wiring 123a Wiring 123b Wiring 124 Electrode 125 Insulating film 132 Underlying insulating film 133 Underlying insulating film 136a Oxide layer 13 6b Oxide semiconductor layer 136c Oxide layer 137d Oxide layer 140 Resist mask 142 Gate insulating film 145 Insulating film 149 Wiring 150 Plasma 152 Underlying insulating film 156 Wiring 156a Oxide layer 156b Oxide semiconductor layer 156c Oxide semiconductor layer 160 Semiconductor film 200 Substrate 202 Base insulating film 204 Gate electrode 206 Multilayer film 206a Oxide layer 206b Oxide semiconductor layer 206c Oxide layer 206d Oxide layer 210 Side wall insulating film 212 Gate insulating film 218 Protective insulating film 222a Wiring 222b Wiring 242 Gate insulating film 500 Micro Computer 501 DC power supply 502 Bus line 503 Power gate controller 504 Power gate 505 CPU
506 Volatile storage unit 507 Nonvolatile storage unit 508 Interface 509 Detection unit 511 Optical sensor 512 Amplifier 513 AD converter 514 Photoelectric conversion element 517 Transistor 519 Transistor 530 Light emitting element 1000 Target 1001 Ion 1002 Sputtered particle 1003 Oxide semiconductor layer 1004 Amorphous Film 1005 Plasma 1141 Switching element 1142 Memory cell 1143 Memory cell group 1189 ROM interface 1190 Substrate 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
8100 Alarm device 8101 Microcomputer 8200 Indoor unit 8201 Housing 8202 Air outlet 8203 CPU
8204 Outdoor unit 8300 Electric refrigerator-freezer 8301 Housing 8302 Refrigeration room door 8303 Freezing room door 8304 CPU
9700 Electric vehicle 9701 Secondary battery 9702 Control circuit 9703 Driving device 9704 Processing device

Claims (14)

A multilayer film including an oxide semiconductor layer and an oxide layer surrounding the oxide semiconductor layer;
A source electrode and a drain electrode in contact with the multilayer film;
A stack of a gate insulating film and a gate electrode sandwiched between the source electrode and the drain electrode on the multilayer film;
A protective insulating film in contact with the source electrode, the drain electrode, the gate insulating film, the gate electrode and the multilayer film;
The semiconductor device according to claim 1, wherein an end portion has a curvature in one cross section of the multilayer film. In claim 1,
The oxide semiconductor layer and the oxide layer include at least indium, and the content ratio of indium in the oxide semiconductor layer is higher than the content ratio of indium in the oxide layer.   3. The semiconductor device according to claim 1, wherein the oxide layer has an energy gap larger than that of the oxide semiconductor layer. 4. The oxide layer and the oxide semiconductor layer according to claim 1, wherein the oxide layer and the oxide semiconductor layer include indium, zinc, and an element M.
The element M is aluminum, titanium, silicon, gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium or hafnium,
The oxide layer is a semiconductor device in which the content ratio of the element M is higher than that of the oxide semiconductor layer.   5. The semiconductor device according to claim 1, wherein a lower end portion of the multilayer film has a curved surface.   The oxide layer according to any one of claims 1 to 5, wherein the oxide layer includes a first oxide layer under the oxide semiconductor layer, a second oxide layer over the oxide semiconductor layer, A semiconductor device including a third oxide layer covering a side surface of the oxide semiconductor layer.   7. The distance between the interface between the oxide semiconductor layer and the oxide layer and the side surface of the oxide layer is the interface between the oxide semiconductor layer and the oxide layer according to claim 1. And a gap between the upper surface of the oxide layer and the upper surface of the oxide layer.   8. The semiconductor device according to claim 1, wherein the thickness of the multilayer film is not less than 1/50 and not more than 50 times the curvature radius of the side surface of the multilayer film. In any 1 item | term of Claim 1 thru | or 8, It has a base insulating film under the said multilayer film,
2. A semiconductor device according to claim 1, wherein a thickness of a region of the base insulating film overlapping with the multilayer film is larger than that of other regions. The base insulating film according to claim 9, wherein the base insulating film includes a first region overlapping with the multilayer film, a second region surrounding the first region, and a third region surrounding the second region. Including
The film thickness of the second region is smaller than that of the first region,
A semiconductor device in which the film thickness of the third region is smaller than that of the second region.   11. The semiconductor device according to claim 1, wherein the protective insulating film includes a silicon nitride layer or a silicon nitride oxide layer that emits at least one of hydrogen and nitrogen.   12. The semiconductor device according to claim 11, wherein a region of the multilayer film in contact with the silicon nitride layer or the silicon nitride oxide layer has lower resistance than other regions. A first oxide film, an oxide semiconductor film, and a second oxide film are sequentially stacked;
Forming a resist mask on the second oxide film;
By performing first etching on the second oxide film and the oxide semiconductor film using the resist mask, an island-shaped second oxide layer and oxide semiconductor layer are formed,
By performing the second etching on the first oxide film, an island-shaped first oxide layer is formed, and a reaction product at the time of the second etching is formed on a side surface of the oxide semiconductor layer. To form a third oxide layer covering the oxide semiconductor layer,
Removing the resist mask;
Forming a gate insulating film and a gate electrode on the second oxide layer;
Forming a source electrode and a drain electrode on the second oxide layer and the third oxide layer;
A method for manufacturing a semiconductor device, wherein a protective insulating film is formed on and in contact with the second oxide layer, the source electrode, the drain electrode, the gate insulating film, and the gate electrode.   14. The method for manufacturing a semiconductor device according to claim 13, wherein after the resist mask is removed, heat treatment is performed in an oxidizing gas atmosphere.