JP2014096521A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of good quality.SOLUTION: A semiconductor device comprises: a semiconductor chip; and a wiring board on which the semiconductor chip is mounted. The semiconductor chip includes: a first internal circuit; a first power supply pad electrically connected with the first internal circuit; a first ground pad electrically connected with the first internal circuit; a second internal circuit; a second power supply pad electrically connected with the second internal circuit; a second ground pad electrically connected with the second internal circuit; a first ESD protection element electrically connected with the first power supply pad and the first ground pad; and a second ESD protection element connected between the second power supply pad and the second ground pad. The wiring board includes first common ground wiring for electrically connecting the first ground pad and the second ground pad. The first ground pad and the second ground pad are electrically independent in the semiconductor chip.

Description

  The present invention relates to a semiconductor device, for example, a technique for discharging a surge current.

  A wireless communication terminal that transmits and receives a signal includes an RFIC (Radio Frequency Integrated Circuit) that performs frequency conversion of the signal. For example, Patent Document 1 discloses a technique related to improvement of ESD withstand voltage applied to RFIC. Patent Document 2 discloses a technique relating to prevention of destruction of internal elements due to static electricity or surge voltage in a semiconductor integrated circuit.

JP 2010-21357 A International Publication No. 2007/013145

The inventors have found various problems in developing a semiconductor device used for a wireless communication terminal or the like. Each embodiment disclosed in the present application provides a semiconductor device suitable for a wireless communication terminal, for example.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  The semiconductor device according to one embodiment has a common ground wiring on the wiring board for connecting each of the ground pads.

  According to one embodiment, a high-quality semiconductor device can be provided that is suitable for a wireless communication terminal or the like, for example.

It is a figure which shows the structural example of the semiconductor chip of RFIC which concerns on a comparative example. It is a figure which shows the structural example of the package substrate of RFIC which concerns on a comparative example. It is a figure which shows the circuit structural example of the semiconductor chip which concerns on a comparative example. It is a figure which shows the problem of RFIC which concerns on a comparative example. 2 is an external view showing a configuration example of a wireless communication terminal according to Embodiment 1. FIG. 2 is an external view showing a configuration example of a wireless communication terminal according to Embodiment 1. FIG. 2 is a block diagram illustrating a configuration example of a wireless communication terminal according to Embodiment 1. FIG. 3 is a cross-sectional view illustrating a configuration example of an RFIC according to Embodiment 1. FIG. 1 is a diagram illustrating a configuration example of an RFIC semiconductor chip according to a first embodiment. 3 is a diagram illustrating a configuration example of an RFIC semiconductor chip and a package substrate according to the first embodiment. FIG. 3 is a surface view of the RFIC according to Embodiment 1. FIG. FIG. 3 is an inner layer wiring diagram of the package substrate PCB according to the first embodiment. FIG. 3 is a rear view of the package substrate PCB according to the first embodiment. 1 is a diagram illustrating a circuit configuration example of a semiconductor chip according to a first embodiment. 2 is a diagram illustrating a configuration example of an internal circuit according to the first embodiment. FIG. It is a figure which shows the surge current discharge path | route to the ground at the time of application of the positive surge voltage concerning static electricity. It is a figure which shows the surge current discharge path | route to the ground at the time of the application of the negative surge voltage concerning static electricity. It is a figure which shows the surge current discharge path | route to the power supply at the time of the application of the positive surge voltage concerning static electricity. It is a figure which shows the surge current discharge path | route to the power supply at the time of the application of the negative surge voltage concerning static electricity. 6 is a diagram illustrating a configuration example of an RFIC semiconductor chip according to a second embodiment. FIG. 6 is a diagram illustrating a configuration example of an RFIC semiconductor chip and a package substrate according to a second embodiment. FIG. It is a figure which shows the structural example of the semiconductor chip and package substrate of RFIC which concern on a modification. It is an inner layer wiring diagram of a package substrate PCB according to a modification. It is an inner layer wiring diagram of a package substrate PCB according to a modification.

  Hereinafter, preferred embodiments will be described in detail with reference to the drawings. That is, it is not necessarily limited to the following embodiment. Further, for clarity of explanation, illustration and description of elements not directly related to the present embodiment are omitted as appropriate.

<Configuration of Semiconductor Device According to Comparative Example>
First, the configuration of an RFIC that is a semiconductor device according to a comparative example studied by the inventors will be described with reference to FIGS. FIG. 1 is a diagram illustrating a configuration example of an RFIC semiconductor chip CP according to a comparative example. FIG. 2 is a diagram illustrating a configuration example of an RFIC package substrate PCB (Printed Circuit Board) according to a comparative example. The RFIC shown in FIGS. 1 and 2 is used for a wireless communication terminal such as a mobile phone.

  First, the configuration of the semiconductor chip CP will be described with reference to FIG. The semiconductor chip CP includes a plurality of processing circuits PC1 to 6, a plurality of signal input pads CPD_RFIN1 to 6, a plurality of signal output pads CPD_RFOUT1 to 6, a plurality of power supply pads CPD_VDD1 to 6, a plurality of ground (ground) pads CPD_GND1 to 6, It has a common ground (common ground) pad CPD_CMN0 and a power supply network NW.

  The processing circuits PC1 to PC6 are connected to the signal input pads CPD_RFIN1 to 6, the signal output pads CPD_RFOUT1 to 6, the power supply pads CPD_VDD1 to 6, and the ground pads CPD_GND1 to 6, respectively. Each of the processing circuits PC1 to PC6 is connected to the power supply network NW. The power supply network NW is connected to the common ground pad CPD_CMN0.

  Each of the processing circuits PC1 to PC6 receives an audio signal and a data signal from each of the signal input pads CPD_RFIN1 to 6. Each of the processing circuits PC1 to PC6 generates an RF signal from the input audio signal and outputs the RF signal to each of the signal output pads CPD_RFOUT1 to 6. Each of the processing circuits PC1 to PC6 operates based on a power supply voltage supplied from each of the power supply pads CPD_VDD1 to 6 and a ground voltage (ground voltage) supplied from each of the ground pads CPD_GND1 to 6.

  The power supply network NW serves as an ESD (Electro-Static Discharge) discharge path. The power supply network NW is composed of a circumferential wiring (annular wiring, ring-shaped wiring) that goes around the entire semiconductor chip CP, and wiring that connects the circumferential wiring and each of the processing circuits PC1 to PC6.

  In addition, each of the processing circuits PC1 to PC6 generates a surge current generated by applying a surge voltage related to static electricity to each of the signal input pads CPD_RFIN1 to 6 or each of the signal output pads CPD_RFOUT1 to 6. Then, all the ground pads CPD_GND1 to 6 and all the power pads CPD_VDD1 to 6 are discharged through the power supply network NW.

  Next, the configuration of the package substrate PCB will be described with reference to FIG. The package substrate PCB includes a plurality of signal input pads PPD_RFIN1 to 6, a plurality of signal output pads PPD_RFOUT1 to 6, a plurality of power supply pads PPD_VDD1 to 6, a plurality of ground (ground) pads PPD_GND1 to 6, a common ground (common ground) pad PPD_CMN0. , And a plurality of lands LND.

  Each of the signal input pads PPD_RFIN1 to 6 is connected to each of the signal input pads CPD_RFIN1 to 6 through a bonding wire BW. Each of the signal output pads PPD_RFOUT1 to 6 is connected to each of the signal output pads CPD_RFOUT1 to 6 through a bonding wire BW. Each of the power supply pads PPD_VDD1 to 6 is connected to each of the power supply pads CPD_VDD1 to 6 through a bonding wire BW. Each of the ground pads PPD_GND1 to 6 is connected to each of the ground pads CPD_GND1 to 6 through a bonding wire BW. The common ground pad PPD_CMN0 is connected to the common ground pad CPD_CMN0 via the bondin wire BW.

  Further, each of the signal input pads PPD_RFIN 1 to 6 is connected to a land LND in which a signal input pin for inputting an audio signal is formed. Each of the signal output pads PPD_RFOUT1 to 6 is connected to a land LND in which a signal output pin for outputting an RF signal is formed. Each of the power supply pads PPD_VDD1 to 6 is connected to a land LND in which a power supply pin to which a power supply voltage is supplied is formed. Each of the ground pads PPD_GND1 to 6 is connected to a land LND having a ground (ground) pin to which a ground voltage is supplied. The common ground pad PPD_CMN0 is connected to a land LND having a ground pin to which a ground voltage is supplied. That is, each of the ground pads PPD_GND1 to 6 and the common ground pad PPD_CMN0 is connected to the ground of the wireless communication terminal 100 via the ground pin.

  With the configuration described above, for example, when a surge voltage related to static electricity is applied to the processing circuit PC1 via the signal input pad CPD_RFIN or the signal output pad CPD_RFOUT, the processing circuit PC1 generates a surge current generated by the processing circuit PC1. Output from the internal circuit to the power supply network NW. The surge current flows to each of the other processing circuits PC2 to PC6 through the power supply network NW. The surge current is discharged to the ground and the power supply via the ground pads CPD_GND2 to 6 and the power supply pads CPD_VDD2 to 6 of the other processing circuits PC2 to PC6. Accordingly, the surge current is discharged by all the ground pads PPD_GND1 to 6 and all the power supply pads CPD_VDD1 to 6, and the internal circuit of the processing circuit PC to which the surge voltage related to static electricity is applied can be prevented from being damaged by static electricity. it can. Similarly, when a surge voltage related to static electricity is applied in any of the other processing circuits PC2 to PC6, it is possible to discharge static electricity via the power supply network NW in the same manner.

<Circuit Configuration of Semiconductor Chip According to Comparative Example>
With reference to FIG. 3, the circuit configuration of the semiconductor chip CP according to the comparative example will be described. FIG. 3 is a diagram illustrating a circuit configuration example of the semiconductor chip CP according to the comparative example. FIG. 3 shows the semiconductor chip CP shown in FIGS. 1 and 2.

  In FIG. 3, the components from the processing circuits PC1 to PC3 to the processing circuits PC1 to PC6 of the semiconductor chip CP illustrated in FIG. 1 are illustrated, and the processing circuits PC4 to PC6 are not illustrated. Yes. Further, the signal output pads CPD_RFOUT1 to 3 are not shown.

  The processing circuit PC1 includes an internal circuit INT1, an ESD protection element PD1, a first diode DIOA1, a second diode DIOB1, a third diode DIOC1, and a bidirectional diode DDIO1. The processing circuit 2 includes an internal circuit INT2, an ESD protection element PD2, a first diode DIOA2, a second diode DIOB2, a third diode DIOC2, and a bidirectional diode DDIO2. The processing circuit 3 includes an internal circuit INT3, an ESD protection element PD3, a first diode DIOA3, a second diode DIOB3, a third diode DIOC3, and a bidirectional diode DDIO3.

  The internal circuit INT1 is connected to the signal input pad CPD_RFIN1 via a wiring (signal line SL1). The internal circuit INT1 generates an RF signal from the audio signal input from the signal input pad CPD_RFIN1. The internal circuit INT1 is connected to the power supply pad CPD_VDD1 via a wiring (power supply line PL1). The internal circuit INT1 is connected to the ground pad CPD_GND1 via a wiring (ground line GL1). The internal circuit INT1 operates based on a current generated by a potential difference between voltages supplied from the power supply pad CPD_VDD1 and the ground pad CPD_GND1.

  One end of the ESD protection element PD1 is connected to the power supply line PL1, and the other end is connected to the ground line GL1. In response to the occurrence of a large potential difference due to static electricity between one end (power supply line PL1) and the other end (ground line GL1), the ESD protection element PD1 causes a surge current generated thereby to flow from the power supply line PL1 to the ground line GL1. Thus, it operates to keep the potential difference between them constant. The ESD protection element PD1 is, for example, a GCNMOS (Gate Coupled Ntype Metal Oxide Semiconductor).

  The first diode DIOA1 has one end (anode) connected to the signal line SL1 and the other end (cathode) connected to the power supply line PL1. When a positive surge voltage related to static electricity (a voltage higher than that supplied from the power supply pad CPD_VDD1) is applied to the signal input pad CPD_RFIN1, the first diode DIOA1 transmits a surge current generated thereby to the signal line SL1. To the power line PL1.

  The second diode DIOB1 has one end (anode) connected to the ground line GL1 and the other end (cathode) connected to the signal line SL1. When a negative surge voltage related to static electricity (a voltage lower than that supplied from the ground pad CPD_GND1) is applied to the signal input pad CPD_RFIN1, the second diode DIOB1 transmits a surge current generated thereby to the ground line GL1. To the signal line SL1.

  The third diode DIOC1 has one end (anode) connected to the ground line GL1 and the other end (cathode) connected to the power supply line PL1. The third diode DIOC1 grounds a surge current generated when a positive surge voltage is applied to one end (ground line GL1) due to a surge voltage discharge from any of the other processing circuits 2 to 6. Flow from the line GL1 to the power supply line PL1.

  The bidirectional diode DDIO1 has one end connected to the common ground pad CPD_CMN1 via a wiring, and the other end connected to the ground line GL1. In response to the occurrence of a large potential difference due to static electricity between one end (power supply network NW) and the other end (ground line GL1), the bidirectional diode DDIO1 transmits a surge current generated from the power supply network NW to the ground line GL1, Alternatively, static electricity is discharged by flowing from the ground line GL1 to the power supply network NW.

  Note that the processing circuits PC2 and PC3 have the same configuration as the processing circuit PC1 described above, and thus the description thereof is omitted. The processing circuits PC4 to PC6 are not shown in the figure, but have the same configuration as the processing circuit PC1.

  Further, the semiconductor chip CP includes a power supply pad CPD_VDDL, a ground pad CPD_GNDL, an ESP protection element PDL, a diode DIOL, and a bidirectional diode DDIOL for supplying logic power.

  One end of the ESD protection element PDL is connected to a wiring (power supply line PLL) connected to the power supply pad CPD_VDDL, and the other end is connected to a wiring (grounding line GLL) connected to the ground pad CPD_GNDL. In response to the occurrence of a large potential difference due to static electricity between one end (power supply line PLL) and the other end (ground line GLL), the ESD protection element PDL causes a surge current generated thereby to flow from the power supply line PLL to the ground line GLL. Thus, it operates to keep the potential difference between them constant. The ESD protection element PDL is, for example, a GCNMOS.

  The diode DIOL has one end (anode) connected to the ground line GLL and the other end (cathode) connected to the power supply line PLL. When a positive surge voltage is applied to one end (the ground line GLL) due to the discharge of the surge voltage from any of the other processing circuits 2 to 6, the diode DIOL transmits a surge current generated thereby from the ground line GLL. Flow through power line PLL.

  The bidirectional diode DDIOL has one end connected to the common ground pad CPD_CMNL via a wiring, and the other end connected to the ground line GLL. The bidirectional diode DDIOL causes a surge current generated by static electricity between one end (power supply network NW) and the other end (ground line GLL) to be generated from the power supply network NW to the ground line GLL, Alternatively, static electricity is discharged by flowing from the ground line GLL to the power supply network NW.

  Thus, in the semiconductor device according to the comparative example, the processing circuits PC1 to PC6 are connected to each other via the power supply network NW in the semiconductor chip. Accordingly, when a surge voltage related to static electricity is applied to a certain signal input pad CPD_RFIN, all the ground pads CPD_GNDL, 1 to 6 and all the power pads CPD_VDDL, 1 to 6 are connected via the power supply network NW. Therefore, it is possible to discharge a surge voltage related to static electricity. Similarly, when a surge voltage related to static electricity is applied to the signal output pad CPD_RFOUT, a surge voltage related to static electricity is similarly applied from all the ground pads CPD_GNDL, 1-6 and all the power supply pads CPD_VDDL, 1-6. It is possible to discharge.

<Problems of the semiconductor device according to the comparative example>
With reference to FIG. 4, a problem of RFIC which is a semiconductor device according to a comparative example will be described. FIG. 4 is a diagram illustrating problems of the RFIC that is a semiconductor device according to a comparative example.

  As described above, in the semiconductor device according to the comparative example, the peripheral wiring of the power supply network NW serving as an ESD discharge path is formed in the semiconductor chip CP. For this reason, an intersection or a parallel portion (coupling path CP) is formed between the peripheral wiring of the power supply network NW, the signal line SL, and the power supply line PL. As a result, the noise NZ from the pin serving as a noise source propagates through the circuit wiring, and noise propagates from the coupling path to the signal line SL or the power supply line PL, which adversely affects the operation of the RFIC. As pins that become noise sources, for example, input / output pins for inputting / outputting signals from the oscillation circuit, clock pins for inputting clock signals, logic power supply pins for supplying power supply voltage for logic power, and There is a logic ground pin to which a ground voltage for a logic power supply is supplied.

(Embodiment 1)
<Overview of wireless communication terminal>
First, an outline of a wireless communication terminal suitable as an electronic device to which the semiconductor device according to the present embodiment is applied will be described with reference to FIGS. 5A and 5B. 5A and 5B are external views showing a configuration example of the wireless communication terminal 1. FIG.

  5A and 5B show a case where the wireless communication terminal 1 is a smartphone. However, the wireless communication terminal 1 may be another wireless communication terminal such as a feature phone (for example, a foldable mobile phone terminal), a mobile game terminal, a tablet PC (Personal Computer), or a notebook PC. As a matter of course, the semiconductor device according to this embodiment can also be applied to devices other than wireless communication terminals.

  FIG. 5A shows one main surface (front surface) of the housing 11 that forms the wireless communication terminal 1. A display device 12, a touch panel 13, some operation buttons 14, and a camera device 15 are disposed on the front surface of the housing 11. On the other hand, FIG. 5B shows the other main surface (back surface) of the housing 11. A camera device 16 is disposed on the back surface of the housing 11.

  The display device 12 is a display device such as a liquid crystal display (LCD) or an organic EL display (OLED: Organic Light-Emitting Diode). The display device 12 is arranged so that the display surface is positioned on the front surface of the housing 11.

  The touch panel 13 is disposed so as to cover the display surface of the display device 12, or is disposed on the back side of the display device 12, and detects a contact position on the display surface by the user. That is, the user can intuitively operate the wireless communication terminal 1 by touching the display surface of the display device 12 with a finger or a dedicated pen (generally called a stylus).

  The operation button 14 is used for an auxiliary operation on the wireless communication terminal 1. Note that such operation buttons may not be provided depending on the wireless communication terminal.

  The camera device 15 is a sub camera arranged so that its lens unit is located on the front surface of the housing 11. Depending on the wireless communication terminal, such a sub camera may not be provided.

  The camera device 16 is a main camera arranged so that its lens unit is located on the back surface of the housing 11.

<Configuration of wireless communication device>
With reference to FIG. 6, the configuration of radio communication terminal 100 on which the semiconductor device according to the present embodiment is mounted will be described. FIG. 6 is a block diagram showing a configuration example of radio communication terminal 100 according to Embodiment 1.

  FIG. 6 shows an internal configuration of the wireless communication terminal 1 shown in FIGS. 5A and 5B. As shown in FIG. 6, the wireless communication terminal 100 includes an application processor (host IC) 101, a baseband processor 102, an RFIC 103, a main memory 104, a battery 105, a power management IC (PMIC: Power Management Integrated Circuit) 106, and a display unit. 107, a camera unit 108, an operation input unit 109, an audio IC 110, a microphone 111, and a speaker 112.

  The application processor (host IC) 101 is a semiconductor integrated circuit that reads a program stored in the main memory 104 and performs processing for realizing various functions of the wireless communication terminal 100. For example, the application processor 101 reads an OS (Operating System) program from the main memory 104 and executes it, and also executes an application program based on the OS program.

  The baseband processor 102 performs baseband processing including encoding (for example, error correction encoding such as convolutional code and turbo code) processing or decoding processing on a signal transmitted and received by the wireless communication terminal 100.

  In particular, for the audio signal, the baseband processor 102 receives the transmission audio signal from the audio IC 110, performs an encoding process on the received transmission audio signal, and transmits it to the RFIC 103. More specifically, the baseband processor 102 encodes PCM data, which is a transmission voice signal received from the audio IC 110, and converts it into AMR data that can be received by the RFIC 103.

  On the other hand, the baseband processor 102 receives the received audio signal from the RFIC 103, performs a decoding process on the received received audio signal, and transmits it to the audio IC 110. More specifically, the baseband processor 102 decodes AMR data, which is a received audio signal demodulated by the RFIC 103, and converts it into PCM data. AMR data is compressed data, and PCM data is uncompressed data.

  The RFIC 103 performs analog RF signal processing. Analog RF signal processing includes frequency up-conversion, frequency down-conversion, amplification and the like. Particularly for the audio signal, the RFIC 103 generates a transmission RF signal from the transmission audio signal modulated by the baseband processor 102, and wirelessly transmits the transmission RF signal via the antenna (Up Link). On the other hand, the RFIC 103 wirelessly receives the received RF signal via the antenna, generates a received audio signal from the received RF signal, and transmits this received audio signal to the baseband processor 102 (Down Link).

  A main memory (external memory) 104 stores programs and data used by the application processor 101. The main memory 104 stores a program used for vocoder processing by the audio IC 110, that is, a codec. As the main memory 104, a DRAM (Dynamic Random Access Memory), which is a volatile memory in which stored data is cleared when the power is turned off, is often used. Of course, the main memory 104 may be a non-volatile memory that retains stored data even when the power is turned off.

  The battery 105 is a battery and is used when the wireless communication apparatus 100 operates without depending on an external power source. Note that the wireless communication device 100 may use the power source of the battery 105 even when an external power source is connected. As the battery 105, a secondary battery is preferably used.

  The power management IC 106 generates an internal power supply from the battery 105 or an external power supply. This internal power supply is given to each block of the wireless communication apparatus 100. At this time, the power management IC 106 controls the voltage of the internal power supply for each block that receives the supply of the internal power supply. The power management IC 106 performs voltage control of the internal power supply based on an instruction from the application processor 101. Furthermore, the power management IC 106 can also control supply and interruption of the internal power for each block. The power management IC 106 also controls charging of the battery 105 when external power is supplied.

  The display unit 107 corresponds to the display device 102 in FIGS. 5A and 5B, and is a display device such as a liquid crystal display (LCD) or an organic EL display (OLED: Organic Light-Emitting Diode). . The display unit 107 displays various images according to processing in the application processor 101. The image displayed on the display unit 607 includes a user interface image, a camera image, a moving image, and the like that the user gives an operation instruction to the wireless communication apparatus 100.

  The camera unit 108 acquires an image in accordance with an instruction from the application processor 101. The camera unit 108 corresponds to the camera devices 105 and 106 in FIGS. 5A and 5B.

  The operation input unit 109 is a user interface that is operated by a user to give an operation instruction to the wireless communication apparatus 100. The operation input unit 109 corresponds to the touch panel 103 and the operation button 104 in FIGS. 5A and 5B.

  The audio IC 110 converts the received audio signal that is a digital signal received from the baseband processor 102 into an analog signal, and drives the speaker 112. As a result, sound is output from the speaker 112. On the other hand, the audio IC 110 performs analog / digital (A / D) conversion on the audio, which is an analog signal detected by the microphone 111, and outputs it to the baseband processor 102. More specifically, the audio IC 110 generates PCM data that is a digital signal from voice that is an analog signal. The audio IC 110 outputs the generated PCM data to the baseband processor 102 as a transmission audio signal.

<Outline Configuration of Semiconductor Device According to First Embodiment>
With reference to FIG. 7, a schematic configuration of RFIC 103 which is a semiconductor device according to the present embodiment will be described. FIG. 7 is a cross-sectional view illustrating a configuration example of the RFIC 103 according to the first embodiment. FIG. 7 is a cross-sectional view of the RFIC 103 shown in FIG. Here, a BGA (Ball Grid Array) type package will be described as an example.

  The RFIC 103 includes a semiconductor chip CP and a package substrate PCB. The semiconductor chip CP has a plurality of pads CPD. The package substrate PCB has a plurality of pads PPD on the upper surface, a plurality of lands LND on the lower surface, and solder balls BL (pins PN) formed on the lands LND. The pad CPD on the semiconductor chip CP side is connected to a predetermined pad PPD on the package substrate PCB side via a bonding wire BW. The pad PPD is electrically connected to the land LND via the via. Thereby, the pad PPD is electrically connected to the predetermined pin PN via the internal wiring of the package substrate PCB. The package substrate PCB is electrically connected to the baseband processor 102 or the antenna via a pin PN. The semiconductor chip CP and the bonding wire BW are sealed with a resin RES.

  The semiconductor chip CP receives a transmission audio signal from the baseband processor 102 via the pin PN, the package substrate PCB, the pad PPD, the bonding wire BW, and the pad PPD. The semiconductor chip CP generates a transmission RF signal from the input transmission voice signal. The semiconductor chip CP outputs the generated transmission RF signal to the antenna via the pad PPD, the bonding wire BW, the pad PPD, the package substrate PCB, and the pin PN.

  Further, the semiconductor chip CP receives an input of a reception RF signal from the antenna via the pin PN, the package substrate PCB, the pad PPD, the bonding wire BW, and the pad PPD. The semiconductor chip CP generates a reception voice signal from the input reception RF signal. The semiconductor chip CP outputs the generated received audio signal to the baseband processor 102 via the pad PPD, the bonding wire BW, the pad PPD, the package substrate PCB, and the pin PN.

<Configuration of Semiconductor Device According to First Embodiment>
With reference to FIG. 8 to FIG. 12, the configuration of the RFIC 103 which is a semiconductor device according to the present embodiment will be described. FIG. 8 is a diagram illustrating a configuration example of the semiconductor chip CP of the RFIC 103 according to the first embodiment. FIG. 9 is a diagram illustrating a configuration example of the semiconductor chip CP and the package substrate PCB of the RFIC 103 according to the first embodiment. FIG. 8 shows the semiconductor chip CP of the RFIC 103 shown in FIGS. FIG. 9 shows the semiconductor chip CP and the package substrate PCB of the RFIC 103 shown in FIGS. FIG. 10 is a surface view of the RFIC 103 according to the first embodiment. FIG. 10 shows the surface (upper surface, upper layer) of the RFIC 103 shown in FIGS. 6 and 7. FIG. 11 is an inner layer wiring diagram of the package substrate PCB according to the first embodiment. FIG. 11 shows an inner layer of the package substrate PCB shown in FIGS. 6 and 7. FIG. 12 is a rear view of the package substrate PCB according to the first embodiment. FIG. 12 shows the back surface (lower surface, lower layer) of the package substrate PCB shown in FIGS. 6 and 7.

  First, the configuration of the semiconductor chip CP will be described with reference to FIG. The semiconductor chip CP includes a plurality of processing circuits PC1 to 6, a plurality of signal input pads CPD_RFIN1 to 6, a plurality of signal output pads CPD_RFOUT1 to 6, a plurality of power supply pads CPD_VDD1 to 6 for supplying a power supply voltage, a ground voltage (reference voltage, A plurality of ground (ground) pads CPD_GND 1 to 6 for supplying a ground voltage) and a plurality of common ground (common ground) pads CPD_CMN 1 to 6 are provided.

  The processing circuits PC1 to PC6 are electrically connected to the signal input pads CPD_RFIN1 to 6, the signal output pads CPD_RFOUT1 to 6, the power supply pads CPD_VDD1 to 6, the ground pads CPD_GND1 to 6, and the common ground pads CPD_CMN1 to 6, respectively. ing.

  Each of the processing circuits PC1 to PC6 receives a transmission audio signal or a reception audio signal from each of the signal input pads CPD_RFIN1 to 6. Each of the processing circuits PC1 to PC6 generates a transmission RF signal or a reception RF signal from the input transmission audio signal or reception audio signal, and outputs it to the signal output pads CPD_RFOUT1 to CPD6. Strictly speaking, each of the signal input pads CPD_RFIN1 to 6 receives a voltage to be a transmission audio signal or a reception audio signal, and each of the signal output pads CPD_RFOUT1 to 6 transmits a transmission RF signal or a reception RF signal. Is output. Each of the processing circuits PC1 to PC6 operates based on a power supply voltage supplied from each of the power supply pads CPD_VDD1 to 6 and a ground voltage (ground voltage) supplied from each of the ground pads CPD_GND1 to 6.

  Each of the processing circuits PC1 to PC6 shares a common surge current generated by applying a surge voltage related to static electricity to each of the signal input pads CPD_RFIN1 to 6 or each of the signal output pads CPD_RFOUT1 to 6. Discharge occurs through each of the ground pads CPD_CMN1-6.

  That is, each of the ground pads CPD_GND1 to 6 is not connected to each other in the semiconductor chip CP and is electrically independent. Each of the ground pads CPD_GND1 to 6 is electrically connected in the package substrate PCB by a common ground wiring CG in the package substrate PCB described later.

  Here, the case where the semiconductor chip CP has one signal input pad CPD_RFIN and one signal output pad CPD_RFOUT so as to correspond to each of the processing circuits CP1 to CP6 is illustrated, but the present invention is not limited to this. For example, the semiconductor chip CP is a signal input / output pad in which the input / output of the signal is shared instead of the signal input pad CPD_RFIN and the signal output pad CPD_RFOUT as a signal pad for inputting / outputting the signal to / from the processing circuit CP. CPD_RFIN / OUT may be included. That is, the signal input / output pad receives a transmission audio signal or a reception audio signal and outputs a transmission RF signal or a reception RF signal.

  Next, the configuration of the package substrate PCB will be described with reference to FIG. The package substrate PCB includes a plurality of signal input pads PPD_RFIN1 to 6, a plurality of signal output pads PPD_RFOUT1 to 6, a plurality of power supply pads PPD_VDD1 to 6, a plurality of ground (ground) pads PPD_GND1 to 6, a plurality of common grounds (common ground). Pads PPD_CMN1 to 6 and common ground wiring CG are included.

  Each of the signal input pads PPD_RFIN1 to 6 is electrically connected to each of the signal input pads CPD_RFIN1 to 6 via a bonding wire BW. Each of the signal output pads PPD_RFOUT1 to 6 is electrically connected to each of the signal output pads CPD_RFOUT1 to 6 via a bonding wire BW. Each of the power supply pads PPD_VDD1 to 6 is electrically connected to each of the power supply pads CPD_VDD1 to 6 through a bonding wire BW. Each of the ground pads PPD_GND1 to 6 is electrically connected to each of the ground pads CPD_GND1 to 6 through a bonding wire BW. Each of the common ground pads PPD_CMN1 to 6 is electrically connected to each of the common ground pads CPD_CMN1 to 6 via a bonding wire BW.

  Further, each of the signal input pads PPD_RFIN1 to 6 is electrically connected to a land LND in which a signal input pin PN to which a transmission audio signal or a reception audio signal is input from the baseband processor 102 or an antenna is formed. Each of the signal output pads PPD_RFOUT1 to 6 is electrically connected to a land LND in which a signal output pin PN for outputting a transmission RF signal or a reception RF signal to the baseband processor 102 or the antenna is formed. Each of the power supply pads PPD_VDD1 to 6 is electrically connected to a land LND in which a power supply pin PN to which a power supply voltage is supplied from the PMIC 106 is formed. Each of the ground pads PPD_GND1 to 6 is electrically connected to a land LND having a ground (ground) pin PN to which a ground voltage (ground voltage) is supplied. The common ground line CG is electrically connected to a land LND in which a ground pin PN to which a ground voltage is supplied is formed. That is, each of the ground pads PPD_GND1 to 6 and the common ground wiring CG is connected to the ground of the wireless communication terminal 100 via the ground pin PN. The LND in which the ground PN is formed will be described in detail later with reference to FIGS.

  The common ground wiring CG serves as an ESD discharge path. The common ground wiring CG includes a wiring L_CMN0 that electrically connects the circumferential wiring (annular wiring, ring-shaped wiring) CL and the land LND on which the pin PN is formed. The common ground wiring CG includes a circumferential wiring CL and a plurality of wirings L_CMN1 to 6 that electrically connect the circumferential wiring CL and each of the plurality of common ground pads PPD_CMN1 to 6. Here, each of the plurality of wirings L_CMN0 to 6 is electrically connected via the circumferential wiring CL and is not directly connected.

  Next, with reference to FIGS. 10 to 12, the arrangement positions of the components will be described. As shown in FIG. 10, the above-described signal input pads CPD_RFIN1 to 6, signal output pads signal output pads CPD_RFOUT1 to 6, power supply pads CPD_VDD1 to 6, ground pads CPD_GND1 to 6, common ground pads CPD_CMN1 to 6, signal input pads PPD_RFIN1 to PPD_RFIN1 6, signal output pads PPD_RFOUT1 to 6, power supply pads PPD_VDD1 to 6, ground pads PPD_GND1 to 6, common ground pads PPD_CMN1 to 6, and processing circuits PC1 to PC6 are provided on the surface of the RFIC 103.

  As shown in FIG. 11, the common ground wiring CG is provided in the inner layer of the package substrate PCB. The common ground wiring CG is electrically connected to each of the lands LND_CMN0 to 6 with the ground pin PN formed via vias Via_CMN0 to 6, respectively. More specifically, each of the vias Via_CMN1 to 6 is electrically connected to each of the wirings L_CMN1 to 6 electrically connecting the peripheral wiring CL and each of the common ground pads PPD_CMN1 to 6 in the common ground wiring CG described above. Connected. The via Via_CMN0 is electrically connected to the wiring L_CMN0.

  Further, as shown in FIG. 12, the plurality of LNDs are provided on the back surface of the package substrate PCB. The plurality of LNDs include lands LND_CMN0 to 6 that are electrically connected to the vias Via_CMN0 to 6, respectively.

  With the configuration described above, for example, when a surge voltage related to static electricity is applied to the processing circuit PC1 through the signal input pad CPD_RFIN or the signal output pad CPD_RFOUT, the processing circuit PC1 generates a surge current generated in the processing circuit PC1. By bypassing the circuit, the current flows to the ground pad CPD_GND1 and the power supply pad CPD_VDD1, and flows to the common ground wiring CG via the common ground pad CPD_CMN1 and the common ground pad PPD_CMN1. The surge current flows to each of the other processing circuits PC2 to 6 through the other common ground pads PPD_CMNL, 2-6 and the common ground pads CPD_CMNL, 2-6 via the common ground line CG. The surge current is discharged from the ground pads CPD_GNDL, 2-6 and the power supply pads CPD_VDDL, 2-6 of the other processing circuits PC2-6. As a result, the surge current is discharged from all the ground pads PPD_GNDL, 1-6 and the power supply pads PPD_VDDL, 2-6, and the internal circuit of the processing circuit PC1 to which the surge voltage related to static electricity is applied is prevented from being damaged by static electricity. be able to. Similarly, when a surge voltage related to static electricity is applied in any of the other processing circuits PC2 to PC6, it is possible to similarly discharge static electricity through the common ground wiring CG.

  When the semiconductor chip CP has a signal input / output pad CPD_RFIN / OUT as a signal pad for inputting / outputting the above-described signal to / from the processing circuit PC, the package substrate PCB is also replaced with the signal input pad PPD_RFIN and the signal output pad PPD_RFOUT. The signal input / output pad PPD_RFIN / OUT is electrically connected to the signal input / output pad CPD_RFIN / OUT. In this case, the signal input / output pad PPD_RFIN / OUT is electrically connected to a signal input / output pin for inputting / outputting the aforementioned signal to / from the baseband processor 102 or the antenna.

<Circuit Configuration of Semiconductor Chip According to First Embodiment>
A circuit configuration of the semiconductor chip CP according to the present embodiment will be described with reference to FIG. FIG. 13 is a diagram illustrating a circuit configuration example of the semiconductor chip CP according to the first embodiment. FIG. 13 shows the semiconductor chip CP shown in FIGS.

  In FIG. 13, components of the processing circuits PC1 to PC3 to the processing circuits PC1 to PC6 of the semiconductor chip CP illustrated in FIG. 8 are illustrated, and the processing circuits PC4 to PC6 are not illustrated. Has been. Further, the signal output pads CPD_RFOUT1 to 3 are not shown.

  The processing circuit PC1 includes an internal circuit INT1, an ESD protection element PD1, a first diode DIOA1, a second diode DIOB1, a third diode DIOC1, and a bidirectional diode DDIO1. The processing circuit 2 includes an internal circuit INT2, an ESD protection element PD2, a first diode DIOA2, a second diode DIOB2, a third diode DIOC2, and a bidirectional diode DDIO2. The processing circuit 3 includes an internal circuit INT3, an ESD protection element PD3, a first diode DIOA3, a second diode DIOB3, a third diode DIOC3, and a bidirectional diode DDIO3.

  The internal circuit INT1 is electrically connected to the signal input pad CPD_RFIN1 via a wiring (signal line SL1). The internal circuit INT1 generates a transmission RF signal or a reception RF signal from the transmission audio signal or the reception audio signal input from the signal input pad CPD_RFIN1. The internal circuit INT1 is electrically connected to the power supply pad CPD_VDD1 via a wiring (power supply line PL1). The internal circuit INT1 is electrically connected to the ground pad CPD_GND1 via a wiring (ground line GL1).

  One end of the ESD protection element PD1 is electrically connected to the power supply line PL1, and the other end is electrically connected to the ground line GL1. In response to the occurrence of a large potential difference due to static electricity between one end (power supply line PL1) and the other end (ground line GL1), the ESD protection element PD1 causes a surge current generated thereby to flow from the power supply line PL1 to the ground line GL1. Thus, it operates to keep the potential difference between them constant. Thereby, the surge current can be bypassed from the internal circuit INT1. The ESD protection element PD1 is, for example, a GCNMOS.

  One end (anode) of the first diode DIOA1 is electrically connected to the signal line SL1, and the other end (cathode) is electrically connected to the power supply line PL1. When a positive surge voltage related to static electricity (a voltage higher than that supplied from the power supply pad CPD_VDD1) is applied to the signal input pad CPD_RFIN1, the first diode DIOA1 transmits a surge current generated thereby to the signal line SL1. To the power line PL1.

  The second diode DIOB1 has one end (anode) electrically connected to the ground line 1 and the other end (cathode) electrically connected to the signal line SL1. When a negative surge voltage related to static electricity (a voltage lower than that supplied from the ground pad CPD_GND1) is applied to the signal input pad CPD_RFIN1, the second diode DIOB1 transmits a surge current generated thereby to the ground line GL1. To the signal line SL1.

  The third diode DIOC1 has one end (anode) electrically connected to the ground line GL1, and the other end (cathode) electrically connected to the power supply line PL1. The third diode DIOC1 grounds a surge current generated when a positive surge voltage is applied to one end (ground line GL1) due to a surge voltage discharge from any of the other processing circuits 2 to 6. Flow from the line GL1 to the power supply line PL1.

  One end of the bidirectional diode DDIO1 is electrically connected to the common ground pad CPD_CMN1 via a wiring, and the other end is electrically connected to the ground line GL1. The bidirectional diode DDIO1 generates a surge current generated from the common ground pad CPD_CMN1 in response to the occurrence of a large potential difference due to static electricity between one end (common ground pad CPD_CMN1) and the other end (ground line GL1). Static electricity is discharged by flowing from GL1 or the ground line GL1 to the common ground pad CPD_CMN1.

  Note that the processing circuits PC2 and PC3 have the same configuration as the processing circuit PC1 described above, and thus the description thereof is omitted. The processing circuits PC4 to PC6 are not shown in the figure, but have the same configuration as the processing circuit PC1.

  Further, the semiconductor chip CP has a power supply pad CPD_VDDL, a ground pad CPD_GNDL, a common ground pad CPD_CMNL, an ESP protection element PDL, a diode DIOL, and a bidirectional diode DDIOL for supplying logic power.

  One end of the ESD protection element PDL is electrically connected to a wiring (power supply line PLL) electrically connected to the power supply pad CPD_VDDL, and the other end is electrically connected to a ground pad CPD_GNDL (grounding line). GLL). In response to the occurrence of a large potential difference due to static electricity between one end (power supply line PLL) and the other end (ground line GLL), the ESD protection element PDL causes a surge current generated thereby to flow from the power supply line PLL to the ground line GLL. Thus, it operates to keep the potential difference between them constant. The ESD protection element PDL is, for example, a GCNMOS.

  One end (anode) of the diode DIOL is electrically connected to the ground line GLL, and the other end (cathode) is electrically connected to the power supply line PLL. When a positive surge voltage is applied to one end (the ground line GLL) due to the discharge of the surge voltage from any of the other processing circuits 1 to 6, the diode DIOL transmits a surge current generated thereby from the ground line GLL. Flow through power line PLL.

  The bidirectional diode DDIOL has one end electrically connected to the common ground pad CPD_CMNL via a wiring, and the other end electrically connected to the ground line GLL. The bidirectional diode DDIOL generates a surge current generated from the common ground pad CPD_CMNL from the common ground pad CPD_CMNL in response to the occurrence of a large potential difference due to static electricity between one end (the common ground pad CPD_CMNL) and the other end (the ground line GLL). Static electricity is discharged by flowing from the GLL or the ground line GLL to the common ground pad CPD_CMNL.

  As described above, in the first embodiment, the common ground pads CPD_CMNL, 1 to 6 are connected to each other through the common ground wiring CG in the package substrate PCB. Accordingly, when a surge voltage related to static electricity is applied to a certain signal input pad CPD_RFIN, all the ground pads CPD_GNDL, 1 to 6 and all the power supply pads CPD_VDDL, 1 to 6 are connected via the common ground wiring CG. 6 makes it possible to discharge a surge voltage related to static electricity. Similarly, when a surge voltage related to static electricity is applied to the signal output pad CPD_RFOUT, a surge voltage related to static electricity is similarly applied from all the ground pads CPD_GNDL, 1-6 and all the power supply pads CPD_VDDL, 1-6. It is possible to discharge.

<Circuit Configuration of Internal Circuit According to Embodiment 1>
The circuit configuration of the internal circuit INT according to the present embodiment will be described with reference to FIG. FIG. 14 is a diagram illustrating a configuration example of the internal circuit INT of the processing circuit PC according to the first embodiment. FIG. 14 shows each of the internal circuits INT1 to INT6 shown in FIG.

  The internal circuit INT includes a capacitor CAP, a MOS transistor (MOSFET: Metal Oxide Semiconductor Field Effect Transistor), a switch element SW, a first resistor IND_L, and a second resistor IND_S.

  One end of the capacitor CAP is electrically connected to the signal input pad CPP_RFIN via the signal line SL, and the other end is connected to the gate of the MOS transistor MF. The capacitor CAP changes the voltage at the other end in response to a change in the voltage at one end (signal line SL) due to the input of a voltage that becomes a transmission audio signal or a reception audio signal to the signal input pad CPP_RFIN. As an example, the capacitor CAP is configured by a MiM (Metal Insulator Metal) type capacitor or a MOS capacitor.

  One end of the first resistor IND_L is electrically connected to the power supply line PL, and the other end is electrically connected to the drain of the MOS transistor MF. One end of the second resistor IND_S is electrically connected to the source of the MOS transistor MF, and the other end is electrically connected to the ground line GL. The resistance values of the first resistor IND_L and the second resistor IND_S are determined in advance based on the characteristics of the generated transmission RF signal or the reception RF signal.

  The MOS transistor MF causes a current to flow between the drain and the source in accordance with a change in the gate voltage. Thereby, for example, a voltage that changes between the first resistor IND_L and the MOS transistor MF is extracted as a transmission RF signal or a reception RF signal after frequency conversion, and is output from a signal output pad CPP_RFOUT (not shown). be able to.

  The switch element SW switches between conduction and interruption between the first resistor IND_L and the MOS transistor MF. For example, when the output of the transmission RF signal or the reception RF signal is stopped, the switch element SW interrupts the connection between the first resistor IND_L and the MOS transistor MF.

  As the gate oxide film of a MOS transistor becomes thinner (for example, 10 nm or less as the processing process becomes finer), electrostatic breakdown of the gate oxide film is likely to occur, so that an ESD countermeasure is particularly necessary.

<Operation of Semiconductor Device According to First Embodiment>
With reference to FIGS. 15 to 18, the surge current discharging operation of RFIC 103 which is the semiconductor device according to the present embodiment will be described. FIG. 15 is a diagram illustrating a surge current discharge path to the ground when a positive surge voltage related to static electricity is applied. FIG. 16 is a diagram illustrating a surge current discharge path to the ground when a negative surge voltage related to static electricity is applied. FIG. 17 is a diagram showing a surge current discharge path to the power supply when a positive surge voltage related to static electricity is applied. FIG. 18 is a diagram showing a surge current discharge path to the power supply when a negative surge voltage related to static electricity is applied. 15 to 18 show the surge current discharging operation of the semiconductor chip CP shown in FIG.

  Hereinafter, in order to clarify the surge current discharge operation of the RFIC 103, a description will be given by dividing into a case where the discharge is discharged to the ground and a case where the surge current is discharged to the power source. That is, in reality, a surge current may be discharged to both the ground and the power supply. 15 and 16 show a discharge path in the case where the discharge is discharged to the ground by a surge current. 17 and 18 show a discharge path when the discharge is discharged to the power source by a surge current.

  First, a surge current discharging operation to the ground pads CPD_GNDL, 1 to 6 when a positive surge voltage related to static electricity is applied will be described with reference to FIG. When a positive surge voltage related to static electricity is applied to the signal line SL2 via the signal input pad CPD_RFIN2, the first diode DIOA2 causes a surge current generated thereby to flow from the signal line SL2 to the power supply line PL2. The ESD protection element PD2 causes a surge current to flow from the power supply line PL2 to the ground line GL2 in accordance with the voltage rise of the power supply line PL2 due to this. As a result, the surge current flows to the ground pad CPD_GND2 and also flows to the bidirectional diode DDIO2.

  The bidirectional diode DDIO2 causes a surge current to flow from the ground line GL2 to the common ground pad CPD_CMN2 in response to the voltage rise of the ground line GL2. As a result, the surge current flows through the common ground wiring CG via the common ground pad CPD_GND2. In addition, this surge current flows through the common ground line CG and to the other bidirectional diodes DDIOL, 1, 3-6 through the other common ground pads CPD_CMNL, 1, 3-6. Each of the bi-directional diodes DDIOL, 1, 3-6 causes surge currents to be applied to the common ground pads CPD_CMNL, 1, 3-6 in response to the respective voltage rises of the common ground pads CPD_CMNL, 1, 3-6. To the ground lines GLL, 1, 3 to 6 respectively. This surge current flows from the ground line GLL, 1, 3-6 to the ground pad CPD_GNDL, 1, 3-6. Thereby, in addition to the ground pad CPD_GND1, a surge current can also flow from the other ground pads CPD_GNDL, 1, 3 to 6 to the ground. That is, a surge voltage related to static electricity can be discharged to the ground.

  Next, a surge current discharging operation to the ground pads CPD_GNDL, 1 to 6 when a negative surge voltage related to static electricity is applied will be described with reference to FIG. When a negative surge voltage related to static electricity is applied to the signal line SL2 via the signal input pad CPD_RFIN2, the second diode DIOB2 causes a surge current generated thereby to flow from the ground line GL2 to the signal line SL2. As a result, a surge current flows from the ground pad CPD_GND2 and the bidirectional diode DDIO2 to the second diode DIOB2.

  The bidirectional diode DDIO2 causes a surge current to flow from the common ground pad CPP_CMN2 to the ground line GL2 according to the voltage drop of the ground line GL2 due to this. As a result, the surge current flows from the common ground line CG to the bidirectional diode DDIO2 via the common ground pad CPD_CMN2. The surge current flows from the other common ground pad CPD_GNDL, 1, 3 to 6 to the common ground pad CPD_GND2 via the common ground line CG. Each of the other bidirectional diodes DDIOL, 1, 3 to 6 sends a surge current to the ground lines GLL, 1, 3 to 6 in accordance with the respective voltage drops of the common ground pad CPD_GNDL, 1 to 3-6. To each of the common ground pads CPD_GNDL, 1, 3-6. This surge current flows from the other ground pads CPD_GNDL, 1, 3-6 to the ground lines GLL, 1, 3-6. As a result, in addition to the ground pad CPD_GND2, a surge current can also flow from the ground from the other ground pads CPD_GNDL, 1, 3-6. That is, a surge voltage related to static electricity can be discharged to the ground.

  First, the surge current discharging operation to the power supply pads CPD_VDDL and 1 to 6 to the power supply pads CPD_VDDL and 1 to 6 when a positive surge voltage related to static electricity is applied will be described with reference to FIG. When a positive surge voltage related to static electricity is applied to the signal line SL2 via the signal input pad CPD_RFIN2, the first diode DIOA2 causes a surge current generated thereby to flow from the signal line SL2 to the power supply line PL2. As a result, a surge current flows to the power supply pad CPD_VDD2 and the ESD protection element PD2. The ESD protection element PD2 causes a surge current to flow from the power supply line PL2 to the ground line GL2 in accordance with the voltage rise of the power supply line PL2 due to this. As a result, a surge current flows through the bidirectional diode DDIO2.

  The bidirectional diode DDIO2 causes a surge current to flow from the ground line GL2 to the common ground pad CPD_CMN2 in response to the voltage rise of the ground line GL2. As a result, the surge current flows through the common ground wiring CG via the common ground pad CPD_GND2. In addition, this surge current flows through the common ground line CG and to the other bidirectional diodes DDIOL, 1, 3-6 through the other common ground pads CPD_CMNL, 1, 3-6. Each of the bi-directional diodes DDIOL, 1, 3-6 causes surge currents to be applied to the common ground pads CPD_CMNL, 1, 3-6 in response to the respective voltage rises of the common ground pads CPD_CMNL, 1, 3-6. To the ground lines GLL, 1, 3 to 6 respectively. Each of the third diodes DIOCL, 1, 3-6 sends a surge current to each of the power supply lines PLL, 1, 3-6 in response to the respective voltage rises of the ground lines GLL, 1, 3-6. Shed. This surge current flows from the power supply line PLL, 1, 3-6 to the power supply pad CPD_VDDL, 1, 3-6. Thereby, in addition to the power supply pad CPD_VDD2, a surge current can be supplied to the power supply from the other ground pads CPD_VDDL, 1 and 3-6. That is, a surge voltage related to static electricity can be discharged to the power source.

  Next, a surge current discharging operation to the power supply pads CPD_VDDL, 1 to 6 when a negative surge voltage related to static electricity is applied will be described with reference to FIG. When a negative surge voltage related to static electricity is applied to the signal line SL2 via the signal input pad CPD_RFIN2, the second diode DIOB2 causes a surge current generated thereby to flow from the ground line GL2 to the signal line SL2. As a result, a surge current flows from the ESD protection element PD2 and the bidirectional diode DDIO2 to the second diode DIOB2.

  The ESD protection element PD2 causes a surge current to flow from the power supply line PL2 to the ground line GL2 in accordance with the voltage drop of the ground line GL2 due to this. Thereby, a surge current flows from the power supply pad CPD_VDD2 to the ESD protection element PD2.

  Further, the bidirectional diode DDIO2 causes a surge current to flow from the common ground pad CPP_CMN2 to the ground line GL2 in accordance with the voltage drop of the ground line GL2 described above. As a result, the surge current flows from the common ground line CG to the bidirectional diode DDIO2 via the common ground pad CPD_CMN2. The surge current flows from the other common ground pad CPD_GNDL, 1, 3 to 6 to the common ground pad CPD_GND2 via the common ground line CG. Each of the other bidirectional diodes DDIOL, 1, 3 to 6 sends a surge current to the ground lines GLL, 1, 3 to 6 in accordance with the respective voltage drops of the common ground pad CPD_GNDL, 1 to 3-6. To each of the common ground pads CPD_GNDL, 1, 3-6. Each of the ESD protection elements PDL, 1, 3 to 6 grounds a surge current from each of the power supply lines PLL, 1, 3-6 according to the respective voltage drops of the ground lines GNDL, 1, 3-6. It flows in each of the lines GNDL, 1, 3-6. This surge current flows from the other power supply pads CPD_VDDL, 1, 3-6 to the ground lines GLL, 1, 3-6. As a result, in addition to the power supply pad CPD_VDD2, a surge current can be supplied from the power supply from the other power supply pads CPD_VDDL, 1, 3-6. That is, a surge voltage related to static electricity can be discharged to the power source.

  By the operation described above, it is possible to prevent the internal circuit INT1 from being destroyed due to the application of a positive or negative surge voltage related to static electricity to the internal circuit INT1. For example, it is possible to prevent the capacitor CAP from being destroyed by applying a high voltage to the capacitor CAP of the internal circuit INT shown in FIG. In a circuit configuration in which a surge voltage can be applied to the gate electrode of the MOS transistor, it is possible to prevent the gate insulating film of the MOS transistor from being broken.

<Contrast of operation with comparative example>
Here, in the semiconductor device according to the comparative example shown in FIGS. 1 to 3, as described with reference to FIG. 4, the peripheral wiring of the power supply network NW serving as an ESD discharge path is formed in the semiconductor chip CP. I have to. Therefore, an intersection (coupling path CP) is formed between the peripheral wiring of the power supply network NW, the signal line SL, and the power supply line PL. As a result, there is a problem that noise NZ from a pin serving as a noise source propagates through the circuit wiring, and noise propagates from the coupling path to the signal line SL or the power supply line PL to adversely affect the operation of the RFIC 103.

  On the other hand, in the semiconductor device according to the first embodiment, as shown in FIG. 9 and FIG. 13, the circumferential wiring CL in the common ground wiring CG is formed in the package substrate PCB. There is no need to form a circular wiring inside. This eliminates the propagation of noise through the peripheral wiring in the semiconductor chip CP.

  In particular, a semiconductor device employing WPP (Wafer Process Package), IPD (Intelligent Power Device), etc., has pads arranged inside the semiconductor chip, so the wiring in the semiconductor chip is complicated, and the influence of noise is reduced. Easy to receive. Therefore, it is particularly effective for such a semiconductor device.

(Embodiment 2)
In the first embodiment, the case where the common ground wiring CG is formed only in the package substrate PCB is illustrated, but the present invention is not limited to this. For example, the common ground wiring CG may be formed in the semiconductor chip CP in a section that is not affected by the pin PN that is a noise source.

<Configuration of Semiconductor Device According to Second Embodiment>
With reference to FIGS. 19 and 20, the configuration of the RFIC 103 which is a semiconductor device according to the second embodiment will be described. FIG. 19 is a diagram illustrating a configuration example of the semiconductor chip CP of the RFIC 103 according to the second embodiment. FIG. 20 is a diagram illustrating a configuration example of the semiconductor chip CP and the package substrate PCB of the RFIC 103 according to the second embodiment. FIG. 19 shows the semiconductor chip CP shown in FIGS. 6 and 7. FIG. 20 shows the semiconductor chip CP and the package substrate PCB shown in FIGS. 6 and 7. Note that the same contents as those in the first embodiment are omitted as appropriate.

  First, the configuration of the semiconductor chip CP will be described with reference to FIG. In the second embodiment, the semiconductor chip CP has a common ground pad CPD_CMN0 and a common ground wiring CG1 on the semiconductor chip CP side. Each of the processing circuits PC5 and PC6 is electrically connected through a common ground wiring CG1. The common ground line CG1 is electrically connected to the common ground pad CPD_CMN0. That is, the bidirectional diodes DDIO5, 6 included in the processing circuits PC5, 6 are electrically connected at one end via the common ground wiring CG1 and electrically connected at the other end to the ground line GL1. Accordingly, the semiconductor chip CP does not have the common ground pads CPD_CMN5 and 6 corresponding to the processing circuits PC5 and PC6, respectively.

  Here, the common ground wiring CG1 is formed so as not to be affected by the noise NZ from the pin serving as the noise source. For example, the common ground line CG1 is formed such that a pin that is predetermined as a noise source is not disposed within a predetermined range from the common ground line CG1. As described above, the common ground pads CPD_CMN and PPD_CMN corresponding to the processing circuit PC are provided for the processing circuit PC that cannot be connected by the common ground wiring CG1, and the common ground wiring CG2 on the package substrate PCB side is thus installed. It is only necessary to be electrically connected to.

  Here, as the above-mentioned predetermined range, if there is no noise source within the range, a range that is considered not to be affected by noise may be defined. Further, as a pin PN used as a noise source, an arbitrary pin among pins that can be a noise source such as an input / output pin, a clock pin, a logic power supply pin, and a logic ground pin may be defined.

  Next, the configuration of the package substrate PCB will be described with reference to FIG. In the second embodiment, the package substrate PCB has a common ground pad PPD_CMN0. The common ground pad CPD_CMN0 is electrically connected to the common ground pad PPD_CMN0 via the bondin wire BW. Further, the package substrate PCB does not have the common ground pads PPD_CMN5 and 6 corresponding to the common ground pads CPD_CMN5 and 6, respectively. The common ground line CG2 on the package substrate PCB side is electrically connected to the common ground pad PPD_CMN0 by a line L_CMN0 that electrically connects the peripheral line CL and the land LND_CMN0.

  That is, each of the ground pads CPD_GND1 to 4 is not connected to the other ground pads CPD_GND in the semiconductor chip CP, and is electrically independent. However, the ground pad CPD_GND5 and the ground pad CPD_GND6 are electrically connected in the semiconductor chip CP. That is, each of the ground pads CPD_GND1 to 6 is electrically connected in the package substrate PCB by the common ground wiring CG2 in the package substrate PCB.

  With the configuration described above, for example, when a surge voltage related to static electricity is applied to the processing circuit PC6 via the signal input pad CPD_RFIN or the signal output pad CPD_RFOUT, the processing circuit PC6 generates a surge current generated in the processing circuit PC. Bypassing from the circuit INT, it flows to the ground pad CPD_GND6 and the power supply pad CPD_VDD6, and also flows to the common ground wiring CG1. The surge current flows to the processing circuit PC5 via the common ground wiring CG1, and also flows to the common ground wiring CG2 via the common ground pad CPD_CMN0 and the common ground pad PPD_CMN0. The surge current flows from the common ground line CG2 to each of the other processing circuits PC1 to PC4 via the other common ground pads PPD_CMN1 to 4 and the common ground pads CPD_CMN1 to 4, respectively. The surge current is discharged to the ground and the power supply via the ground pads CPD_GND1 to 5 and the power supply pads CPD_VDD1 to 5 of the other processing circuits PC1 to PC5. Thus, the surge current is discharged by all the ground pads PPD_GND1 to 6 and CPD_VDD1 to 6, and the internal circuit INT of the processing circuit PC to which the surge voltage related to static electricity is applied can be prevented from being damaged by static electricity. Similarly, when a surge voltage related to static electricity is applied in any of the other processing circuits PC1 to PC5, the static electricity can be discharged through the common ground wiring CG1 and the common ground wiring CG2.

  As described above, in the second embodiment, the plurality of processing circuits PC5 and PC6 are electrically connected to each other by the common ground wiring CG1 on the semiconductor chip CP side within a range not affected by noise. Then, an ESD discharge path is formed by electrically connecting the common ground wiring CG1 on the semiconductor chip CP side and the common ground wiring CG2 on the package substrate PCB side. According to this, it is not necessary to provide the common ground pad PPD_CMN and the common ground pad CPD_CMN so as to correspond to each of the processing circuits PC, so that the number of pads can be reduced. For example, for the processing circuit PC electrically connected to the common ground line CG1, as illustrated in FIG. 20, the common ground pad PPD_CMN0 and the common ground pad CPD_CMN0 that connect the common ground line CG1 and the common ground line CG2 are provided. It is sufficient to provide at least one. Therefore, the number of pads can be reduced, the scale of the RCIC 103 can be reduced, and the cost can be reduced.

<Modifications>
Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  For example, as an example of a modification, the shape of the common ground wiring CG2 can be changed as shown in FIG. That is, the shape of the peripheral wiring CL of the common ground wiring CG2 of the package substrate PCB may be non-annular instead of annular. For example, as shown in FIG. 19, the common ground wiring CG2 is a wiring CL that connects each of the common ground pads PPD_CMN0 to 4, and the common ground pad PPD_CMN0 and the common ground pad PPD_CMN4 are connected to the other common ground pads PPD_CMN1-3. A non-circular wiring (arc-shaped wiring) connected via a connection point with each of them. According to this, in the common ground wiring CG2, it is possible to reduce the wiring of the portion that connects the common ground pad CPD_CMN0 and the common ground pad CPD_CMN4 in the shortest time.

  In this case, the common ground wiring CG2 is, for example, a wiring of a portion that connects the common ground pads PPD_CMN3 and 4 corresponding to the processing circuits PC3 and 4 at the shortest (a connection point between the wiring L_CMN3 in the circumferential wiring CL and a wiring A non-circular wiring having a reduced number of wirings to the connection point with L_CMN4 may be used. However, preferably, as shown in FIG. 21, the portion of the common ground pad PPD_CMN0 of the common ground wiring CG1 in which the plurality of processing circuits PC5 and 6 are connected together and the other common ground pad PPD_CMN4 are connected at the shortest. A non-annular wiring in which wiring (wiring between a connection point with the wiring L_CMN0 and a connection point with the wiring L_CMN4) in the circumferential wiring CL is reduced is preferable. According to this, since the distance between the common ground pads PPD_CMN0 and 4 becomes long, the amount of wiring that can be reduced can be reduced.

  However, from the viewpoint of discharging static electricity more stably, the common ground wiring CG2 may be a ring wiring as in the above-described embodiment. For example, in the case shown in FIG. 21, when a surge voltage related to static electricity is applied to the processing circuit PC4, the surge current is discharged only to one path on the processing circuit PC3 side via the common ground wiring CG2. Can not do it. On the other hand, in the case shown in FIG. 20, when a surge voltage related to static electricity is applied to the processing circuit PC4, the path on the processing circuit PC3 side and the processing circuit PC5 side via the common ground wiring CG2. A surge current can be discharged to two paths. Therefore, the common ground wiring CG2 can be discharged more stably by using an annular wiring. Note that the common ground wiring CG described in the first embodiment may also be a non-annular wiring as described above.

  As an example of another modification, as shown in FIG. 22, the shape of the peripheral wiring CL of the common ground wiring CG may be a flat wiring. Although FIG. 22 illustrates the case where the common ground wiring CG is rectangular, other shapes such as a circle may be used. Here, each of the plurality of wirings L_CMN0 to 5 is electrically connected via the flat wiring CL and is not directly connected. In this way, as shown in FIG. 11, as compared to the case where the common ground wiring CG is annular, the common ground pad CPD_CMN of the processing circuit PC to which the surge voltage is applied is connected to another common ground. With respect to any of the pads CPD_CMN, a surge current can be directly propagated and discharged instead of a detour path. Therefore, the surge voltage can be discharged more stably and efficiently.

  As an example of another modification, as shown in FIG. 23, the shape of the peripheral wiring CL of the common ground wiring CG is a flat plate shape, and a hole portion HL that forms a hole for preventing peeling of the solder resist is provided. It is good also as a structure provided. That is, the package substrate PCB in this modification has holes (including through-holes) extending in advance from the upper surface or the lower surface of the package substrate PCB to at least the inner layer in which the circumferential wiring CL is provided. A resist is applied. The flat wiring CL of the common ground wiring CG also has a hole HL for forming this hole. According to this, the surge voltage can be discharged stably and efficiently, and the adhesion area of the solder resist can be increased to prevent the peeling of the solder resist.

  23 illustrates the case where the shape of the hole HL in the flat wiring CL is circular, the shape of the hole HL may be an arbitrary shape. Also, the number of holes HL may be an arbitrary number. That is, the shape and number of holes for preventing peeling of the solder resist formed on the package substrate PCB can be any shape and number.

DESCRIPTION OF SYMBOLS 1 Wireless communication terminal 11 Case 12 Display device 13 Touch panel 14 Operation buttons 15 and 16 Camera device 101 Application processor (host IC)
102 Baseband processor 103 RFIC
104 Main memory 105 Battery 106 PMIC
107 Display Unit 108 Camera Unit 109 Operation Input Unit 110 Audio IC
111 microphone 112 speaker CP semiconductor chip PCB package substrate CPD, PPD pad BW bonding wire LND land PN pin BL solder ball NW power supply network PC processing circuit CPD_RFIN, PPD_RFIN signal input pad CPD_RFOUT, PPD_RFOUT signal output pad CPD_VDD, PPD_VDD power supply pad CPD_GND, PPD_GND Ground pad CPD_CMN, PPD_CMN Common ground pad CG Common ground line CL Circumferential line L_CMN Line Via_CMN Via SL Signal line PL Power line GL Ground line INT Internal circuit PD ESD protection element DIOA, DIOB Diode DDIO Bidirectional diode CP Coupling path NZ Noise CAP Capacitor MF MOS type Transistor SW Switch element IND_L, IND_S Resistance

Claims (9)

Semiconductor devices including:
(A) a semiconductor chip;
Here, the semiconductor chip includes:
A first internal circuit;
A first power pad electrically connected to the first internal circuit for supplying a power supply voltage to the first internal circuit;
A first ground pad electrically connected to the first internal circuit and for supplying a ground voltage;
A second internal circuit;
A second power supply pad electrically connected to the second internal circuit and for supplying a power supply voltage to the second internal circuit;
A second ground pad electrically connected to the second internal circuit and for supplying a ground voltage;
A first ESD protection element electrically connected to the first power supply pad and the first ground pad; and a second electrically connected to the second power supply pad and the second ground pad. ESD protection element,
(B) A wiring board on which the semiconductor chip is mounted, including:
A first common ground wiring that electrically connects the first ground pad and the second ground pad;
Here, the first ground pad and the second ground pad are electrically independent within the semiconductor chip. The first ESD protection element can divert surge current from the first internal circuit to the first ground pad;
The second ESD protection element can divert surge current from the second internal circuit to the second ground pad.
The semiconductor device according to claim 1. The semiconductor chip further includes:
A third internal circuit;
A third power supply pad electrically connected to the third internal circuit and for supplying a power supply voltage to the third internal circuit;
A third ground pad electrically connected to the third internal circuit and for supplying a ground voltage;
A fourth internal circuit;
A fourth power supply pad electrically connected to the fourth internal circuit and for supplying a power supply voltage to the fourth internal circuit;
A fourth ground pad electrically connected to the fourth internal circuit and for supplying a ground voltage;
A third ESD protection element electrically connected between the third power supply pad and the third ground pad;
A fourth ESD protection element electrically connected between the fourth power supply pad and the fourth ground pad; and a second connecting the third ground pad and the fourth ground pad respectively. Common ground wiring,
Here, the second common ground wiring is connected to the first common ground wiring, and a predetermined pin as a noise source is not disposed within a predetermined range.
The semiconductor device according to claim 1. The semiconductor chip further includes:
A third internal circuit;
A third power supply pad electrically connected to the third internal circuit and supplying a power supply voltage to the third internal circuit;
A third ground pad electrically connected to the third internal circuit and for supplying a ground voltage; and electrically connected between the third power supply pad and the third ground pad. A third ESD protection element;
Here, the first common ground wiring electrically connects each of the first to third ground pads via an annular wiring,
The first to third ground pads are electrically independent in the semiconductor chip.
The semiconductor device according to claim 1. The semiconductor chip further includes:
A third internal circuit;
A third power supply pad electrically connected to the third internal circuit and supplying a power supply voltage to the third internal circuit;
A third ground pad electrically connected to the third internal circuit and for supplying a ground voltage; and electrically connected between the third power supply pad and the third ground pad. A third ESD protection element;
Here, the first common ground wiring electrically connects each of the first to third ground pads via a non-annular wiring,
The first to third ground pads are electrically independent in the semiconductor chip.
The semiconductor device according to claim 1. The semiconductor chip further includes:
A third internal circuit;
A third power supply pad electrically connected to the third internal circuit and supplying a power supply voltage to the third internal circuit;
A third ground pad electrically connected to the third internal circuit and for supplying a ground voltage; and electrically connected between the third power supply pad and the third ground pad. A third ESD protection circuit;
Here, the first common ground wiring electrically connects each of the first to third ground pads via a flat wiring,
The first to third ground pads are electrically independent in the semiconductor chip.
The semiconductor device according to claim 1. The first common ground wiring has a hole portion for forming a hole extending from at least one of an upper surface and a lower surface of the wiring board to an inner layer provided with the first common ground wiring.
The semiconductor device according to claim 6. The semiconductor chip further includes:
A first signal input pad for supplying a voltage to be processed by the first internal circuit;
A second signal input pad for supplying a voltage as a signal to be processed by the second internal circuit;
A first signal-to-power diode, which is electrically connected to the first signal input pad and the first power supply pad, and allows a surge current to flow from the first signal input pad side to the first power supply pad side;
A first ground signal-to-ground diode that is electrically connected to the first ground pad and the first signal input pad, and allows a surge current to flow from the first ground pad side to the first signal input pad side;
A second signal-to-power diode, which is electrically connected to the second signal input pad and the second power supply pad, and allows a surge current to flow from the second signal input pad side to the second power supply pad side; And a second ground signal inter-diode that is electrically connected to the second ground pad and the second signal input pad and allows a surge current to flow from the second ground pad side to the second signal input pad side. ,
The semiconductor device according to claim 1. The semiconductor device is an RFIC (Radio Frequency Integrated Circuit).
The semiconductor device according to claim 1.

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