JP2014096477A - Method for manufacturing mask pattern, method for manufacturing semiconductor device, and program for manufacturing mask pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a low-cost semiconductor device that can be miniaturized.SOLUTION: A method of manufacturing a semiconductor device comprises the steps of: forming a first photoresist pattern on a first film; curing the first photoresist pattern; forming a second photoresist pattern on the first film so as to partially overlap with the first photoresist pattern in a planar view; and etching the first film using the first and second photoresist patterns as a mask.

Description

  The present invention relates to a mask pattern creation method, a semiconductor device manufacturing method, and a mask pattern creation program.

  In a lithography process for forming a wiring layer or the like, a line-and-space-shaped photoresist pattern partially including a large-width line portion is used. However, in recent years, since miniaturization of semiconductor devices has progressed, a sufficient depth of focus for forming a photoresist pattern cannot be obtained, resulting in a decrease in yield.

  FIG. 1 is a diagram for explaining this state. FIGS. 1A and 1B are diagrams illustrating an ideal state, and FIGS. 1C and 1D are diagrams illustrating a state of defocusing. 1A and 1C are plan views, and FIGS. 1B and 1D are cross-sectional views in the A-A ′ direction of FIGS. 1A and 1C, respectively.

  As shown in FIGS. 1A and 1B, in an ideal state, a line-and-space-shaped photoresist pattern 6 including a line portion 6a having a large width is formed on the film 12 to be processed. However, as shown in FIGS. 1C and 1D, the photoresist portion 6b that is to form a large-width line portion is actually deformed by a focus shift (defocus) at the time of exposure, so that a desired photoresist pattern is formed. Could not be obtained.

  Therefore, a double patterning method has been proposed as a method for forming a desired photoresist pattern during the manufacture of a semiconductor device that has been miniaturized. The double patterning method is a method of dividing a desired photoresist pattern into two patterns and performing exposure twice. Main double patterning methods include a litho-etch litho-etch (LELE) method and a litho-process litho-etch (LPLE) method. In the LELE method, after a first photoresist pattern is formed, a film to be processed is etched using the first photoresist pattern, and after a second photoresist pattern is formed, a second photoresist pattern is formed. This is a method of etching a film to be processed by using the method. The LPLE method is a method in which a first photoresist pattern is formed, a second photoresist pattern is formed, and a film to be processed is etched using the first and second photoresist patterns.

  Patent Document 1 (Japanese Unexamined Patent Application Publication No. 2009-53605) discloses a double patterning method in which a line and space pattern (L / S pattern) is divided into two patterns.

JP 2009-53605 A

  However, in the method described in Patent Document 1, since alignment of two photoresist patterns is essential, a desired L / S pattern may not be finally obtained. That is, when manufacturing a semiconductor device in which miniaturization has progressed, the method of Patent Document 1 has a problem that the margin of misalignment between two photoresist patterns becomes small and the yield deteriorates.

One embodiment is:
Forming a first photoresist pattern on the first film;
Curing the first photoresist pattern;
Forming a second photoresist pattern on the first film so as to at least partially overlap the first photoresist pattern in plan view;
Etching the first film using the first and second photoresist patterns as a mask;
The present invention relates to a method for manufacturing a semiconductor device having

Other embodiments are:
A step of setting exposure conditions, layout patterns, division location detection conditions, and division conditions;
Detecting the division location of the layout pattern using the exposure condition and the division location detection condition;
Dividing the layout pattern into a first mask pattern and a second mask pattern using the division condition so that the division portion is divided;
The present invention relates to a mask pattern creation program having

Other embodiments are:
A step of setting exposure conditions, layout patterns, division location detection conditions, and division conditions;
Using the exposure condition and the division location detection condition to detect a division location of the layout pattern;
Dividing the layout pattern into a first mask pattern and a second mask pattern using the division condition so that the division portion is divided;
The present invention relates to a mask pattern creation method having

  A semiconductor device that can be miniaturized can be provided at low cost. In addition, a mask pattern corresponding to miniaturization can be created.

It is a figure showing the conventional lithography process. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a figure showing the manufacturing method of the semiconductor device of 1st Example. It is a flowchart explaining the processing content of a mask pattern creation program. It is a top view showing a layout pattern. It is a figure showing the manufacturing method of the semiconductor device of 2nd Example. It is a figure showing the manufacturing method of the semiconductor device of 2nd Example.

  In an example of the method for manufacturing a semiconductor device of the present invention, after forming a first photoresist pattern on the first film, the first photoresist pattern is cured and fixed. Next, a second photoresist pattern is formed on the first film so as to at least partially overlap the first photoresist pattern in plan view. Thereafter, the first film is etched using the first and second photoresist patterns as a mask.

  In the above method, the first and second photoresist patterns are formed by the litho process litho etch (LPLE) method. Therefore, the number of steps can be reduced and the manufacturing cost can be reduced as compared with the case of using the litho-etch litho-etch (LELE) method. The second photoresist pattern is formed so that at least a part of the second photoresist pattern overlaps the first photoresist pattern in plan view. For this reason, in the region where the first and second photoresist patterns overlap, even if the first photoresist pattern does not become a desired pattern due to defocusing or the like, the second photoresist pattern is further formed thereon. By forming, a desired photoresist pattern can be obtained. Furthermore, since two patterns are provided in the region where the first and second photoresist patterns overlap, a margin for misalignment of the second photoresist pattern can be increased. As a result, it is possible to manufacture a semiconductor device that can sufficiently cope with miniaturization (for example, miniaturization near the limit resolution at the time of exposure).

  Preferably, the first photoresist pattern is a line-and-space pattern (L / S pattern) including a line portion and a space portion between the line portions having the first width, and the second photoresist pattern is formed. The pattern may be a pattern in which a region overlapping the first photoresist pattern has a second width larger than the first width in plan view. Here, the “first width” represents the width in the direction perpendicular to the extending direction of the line portion and parallel to the first film, and the “second width” is the width in the same direction as the first width. Represents. The line-and-space pattern is a pattern in which the line portions are arranged with a certain interval (first width), so that a margin in the lithography process can be increased and it can sufficiently cope with miniaturization. be able to. In addition, since the second photoresist pattern also has a pattern having a second width larger than the first width, a margin in the lithography process can be increased and sufficient miniaturization can be handled. it can. Therefore, this is a case of manufacturing a semiconductor device that has been miniaturized so that the width of the line portion constituting the first photoresist pattern is (λ / NA) / 4 to (λ / NA) / 2 nm. However, the method of the present invention can be applied. Here, λ represents the wavelength of the exposure light source, and NA represents the numerical aperture of the exposure machine.

  The second photoresist pattern only has to overlap at least part of the second photoresist pattern with the first photoresist pattern in plan view. That is, the entire second photoresist pattern may overlap with the first photoresist pattern, or a part of the second photoresist pattern may overlap with the first photoresist pattern.

  The first film is not particularly limited and may be any film as long as it can be applied to a lithography process such as a semiconductor film (semiconductor substrate) such as silicon, a conductive film, and an insulating film. In addition, the method of the present invention may be applied simultaneously with a plurality of films as the first film.

  In the step of curing the first photoresist pattern, the first photoresist pattern can be cured by a process such as ion implantation, deep ultraviolet (DUV) exposure, chemical curing, or the like.

  A method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied will be described below with reference to the drawings. This embodiment is a specific example shown for a deeper understanding of the present invention, and the present invention is not limited to this specific example. Moreover, the same code | symbol is attached | subjected to the same member and description is abbreviate | omitted or simplified. Further, the same members will be appropriately omitted. The drawings used in the following description are schematic, and the ratios of length, width, and thickness in each drawing are not necessarily the same as the actual ones, and the length, width, and thickness in each drawing are not the same. The ratios may not match each other. In the following examples, the concretely shown conditions such as materials and dimensions are merely examples.

(First embodiment)
The present embodiment relates to a semiconductor device in which a wiring layer and a connection portion are formed using the method of the present invention. Hereinafter, with reference to FIGS. 2 to 10, a method of manufacturing the semiconductor device of this embodiment will be described. 4A, 5A, 5B, and 8A are plan views. 2, 3, 4B, 5C, 6 and 7 represent cross-sectional views corresponding to the direction AA ′ of FIG. 8A. FIG. 8B shows a cross-sectional view in the AA ′ direction of FIG. 8A. FIG. 9 is a flowchart showing the processing contents of the mask pattern creation program used to determine the first and second photoresist patterns. FIG. 10 is a plan view showing a layout pattern.

  As shown in FIG. 2, a trench for an element isolation region is formed on the silicon semiconductor substrate 1 by using a lithography technique and a dry etching technique. A silicon oxide film, a silicon nitride film, or a laminated film of these films is buried in this trench by CVD, and then planarized by CMP or etch back to form an element isolation region 2. Next, an insulating film for a gate insulating film is formed by thermal oxidation or CVD, and a polysilicon film and a silicon nitride film containing impurities are formed thereon. Thereafter, a hard mask 8a made of a silicon nitride film is formed using a lithography technique and a dry etching technique. Using the hard mask 8a as a mask, the gate insulating film 3 and the gate electrode 4 are formed by patterning the gate insulating film and the polysilicon film thereon. Next, LDD regions 9 are formed by implanting impurities into the silicon semiconductor substrate 1 on both sides of the gate electrode 4. A silicon nitride film is formed on the entire surface of the silicon semiconductor substrate 1 and then etched back to form sidewall films 8b on both side surfaces of the gate electrode facing each other. Source and drain regions 10 are formed by implanting impurities into the silicon semiconductor substrate 1 on both sides of the gate electrode 4 using the hard mask 8a and the sidewall film 8b as a mask. Thereby, a planar type transistor composed of the gate insulating film 3, the gate electrode 4, the LDD region 9, the source and drain region 10, and the silicon semiconductor substrate 1 is completed.

  As shown in FIG. 3, a first interlayer insulating film 11 made of silicon oxide is formed on the entire surface of the silicon semiconductor substrate 1. Contact holes are formed in the first interlayer insulating film 11 so as to expose the source and drain regions 10. Next, the first contact plug 13 is formed by filling the contact hole with a conductive material.

  As shown in FIG. 4, a conductive film 15 such as tungsten is formed on the first interlayer insulating film 11.

  Next, the first and second mask patterns corresponding to the first and second photoresist patterns are determined using the mask pattern forming program, respectively. Hereinafter, the processing content of the mask pattern forming program will be described with reference to the flowchart shown in FIG. 9 and the layout pattern shown in FIG.

First, a layout pattern, an exposure condition, a division location detection condition, and a division condition of a wiring layout composed of a first connection portion 18a and a first wiring layer 18b formed in the process of FIG. 6 to be described later are set (S1). This setting process is performed by reading a layout pattern, exposure conditions, division location detection conditions, and division conditions stored in advance in the computer. Examples of exposure conditions include a focus value, an exposure amount, an illumination shape (effective light source distribution) and illumination intensity of an exposure apparatus, a numerical aperture (NA), a wavelength of a light source, a degree of polarization, and an aberration amount. The division location detection condition of the present embodiment is a condition for detecting a portion in which the width in a specific direction in the layout pattern is a certain value or less after a litho simulation described later. Further, the division conditions of this embodiment are the following conditions (1) and (2).
(1) The first mask pattern is a line-and-space pattern including a line portion and a space portion having a first width located between the line portions.
(2) The second mask pattern has a second width in which the region overlapping the first mask pattern is larger than the first width in plan view.

Next, an OPC (Optical Proximity Correction) process is performed on the layout pattern to correct pattern distortion (S2).
Next, with respect to the layout pattern after the OPC process, the division part is detected using the exposure condition and the division part detection condition set in the process of S1. Specifically, first, a litho simulation of the layout pattern is performed using the exposure conditions (S3). Next, with respect to the layout pattern, a part where the width in a specific direction is equal to or smaller than a certain value is detected using the division location detection condition (S4). FIG. 10 is a plan view showing a layout pattern. In the present embodiment, in the layout pattern of FIG. 10, the divided portion 14 in which the width in the direction 7 becomes equal to or smaller than a certain value after the lithography simulation is detected. The divided portion 14 is a portion having a small margin at the time of exposure, and corresponds to a partial region of the first connection portion 18a and the first wiring layer 18b formed in a process described later.

  Next, the layout pattern is divided into the first mask pattern and the second mask pattern using the division condition so that the division part 14 detected in the process of S4 is divided (S5). In this embodiment, since the division conditions (1) and (2) are set in advance, the first mask pattern is located between the line part and the line part including the space part having the first width. The layout pattern is divided so that the second mask pattern has a second width larger than the first width in an area overlapping the first mask pattern in plan view. That is, a region where the first and second mask patterns are overlapped is a partial region of the first connection portion 18a and the first wiring layer 18b (the divided portion 14 detected in S4).

  Next, OPC processing is performed on each of the divided first and second mask patterns to correct pattern distortion (S6, S7).

  The first and second mask patterns are finally determined through the above process (S8, S9).

Next, as shown in FIG. 4, after a positive photoresist film is formed on the entire surface of the conductive film 15, a photomask (reticle) corresponding to the first mask pattern determined according to the process of FIG. 9 is prepared. The photoresist film is exposed and developed using this photomask. As a result, the first mask pattern is transferred to the photoresist film to form the first photoresist pattern 16. The first photoresist pattern 16, the line sections 16a and 16c has a width W ₁ is disposed with a first width W _2, and has a line-and-space pattern. That is, the first photoresist pattern 16 has a line section 16a and 16c has a width W _1, line section 16a, the space portion 16b of the W ₂ having a first width located between the 16c. The first photoresist pattern 16 has a pattern 16c corresponding to the first connection portion formed on the first contact plug 13 and a pattern 16a corresponding to the first wiring layer. Next, the first photoresist pattern 16 is cured by processes such as ion implantation, deep ultraviolet (DUV) exposure, and chemical curing.

As shown in FIG. 5, after forming a positive photoresist film on the entire surface of the conductive film 15, a photomask (reticle) corresponding to the second mask pattern determined according to the process of FIG. 9 is prepared. An exposure / development process is performed on the photoresist film using a photomask. Thereby, the second mask pattern is transferred to the photoresist film to form the second photoresist pattern 17. At this time, the first photoresist pattern 16 formed in the step of FIG. 4 is already subjected to the curing process and is not affected by the exposure process. FIG. 5A is a plan view showing only the second photoresist pattern 17, and FIG. 5B is a plan view showing the first and second photoresist patterns 16 and 17. As shown in FIG. 5A, the second photoresist pattern 17 is larger than the first width W ₂ of the space portion of the first photoresist pattern 16, and considering the misalignment (W ₁ + W ₂ ) It is desirable to have a second width W ₃ of the order. Further, as shown in FIG. 5, the region where the second photoresist pattern 17 and the first photoresist patterns 16a and 16c are combined corresponds to the first connection portion and the first wiring layer in a later step. It becomes a pattern.

  As shown in FIG. 6, the conductive film 15 is etched using the first and second photoresist patterns 16 and 17 (not shown) as a mask. As a result, the first connection portion 18a and the first wiring layer 18b electrically connected to the first contact plug 13 are formed.

  As shown in FIG. 7, a second interlayer insulating film 20 made of silicon oxide is formed on the first interlayer insulating film 11. A contact hole is formed so as to penetrate through the second interlayer insulating film 20 and expose the first connection portion 18a. By embedding a conductive material in the contact hole, the second contact plug 21 electrically connected to the first connection portion 18a is formed.

  As shown in FIG. 8, the second connection portion 22 a and the second wiring layer 22 b are formed so as to be electrically connected to the second contact plug 21. The second connection portion 22a and the second wiring layer 22b are formed in the same manner as the step of forming the first connection portion 18a and the first wiring layer 18b (see FIGS. 4 to 6 and 9).

In this embodiment, the first photoresist pattern 16 is formed in the step of forming the first connection portion 18a and the first wiring layer 18b and the step of forming the second connection portion a and the second wiring layer 22b. Since the line-and-space pattern is used, a large margin in the lithography process can be obtained, and it is possible to sufficiently cope with miniaturization. Further, since the second photoresist pattern 17 also has a pattern having a second width W ₃ that is larger than the first width W ₁ , a large margin can be secured in the lithography process, which is sufficient for miniaturization. Can respond. That is, a mask pattern sufficiently corresponding to miniaturization can be created by the mask pattern creation program (mask pattern creation method) having the processing contents shown in FIG.

  In the above embodiment, positive photoresists are used for the first and second photoresist patterns 16 and 17. However, the first and second photoresist patterns 16 and 17 are not limited to positive photoresists, and negative photoresists may be used. In this case, in this embodiment, the first and second photoresist patterns 16 and 17 may be formed in such a manner that the photoresist portion and the space portion are reversed from those in the case where a positive photoresist is used. Instead of the photoresist, a hard mask material such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, an amorphous carbon film, or an antireflection film (BARC film) may be used.

  In the present embodiment, the first and second photoresists are formed in the step of forming the first connection portion 18a and the first wiring layer 18b and the step of forming the second connection portion 22a and the second wiring layer 22b. The method of the present invention using patterns 16 and 17 was applied. However, the method of the present invention may be further applied when a wiring layer or the like is formed on the second interlayer insulating film 20 or in other regions.

(Second embodiment)
In the first embodiment, the first photoresist pattern is a line and space pattern. On the other hand, the present embodiment is different in that the same pattern as the layout pattern is used as the first photoresist pattern. In the present embodiment, the second photoresist pattern is provided so that the entire second photoresist pattern overlaps the first photoresist pattern in plan view. For this reason, even if the first photoresist pattern is deformed by defocusing, the second photoresist pattern supplements the pattern, so that a large margin can be secured in the lithography process, which is sufficient for miniaturization. It can correspond to.

  The semiconductor device of this embodiment can be manufactured using the same process as that of the first embodiment, except that the first photoresist pattern has a different shape in plan view. Hereinafter, with reference to FIGS. 11 and 12, a method of manufacturing the semiconductor device of this embodiment will be described. In this embodiment, a layout pattern having the same wiring layout as that of the first embodiment shown in FIG. 10 is formed.

  First, a planar type transistor or the like is formed by the steps of FIGS. 2 and 3 of the first embodiment.

  Next, as shown in FIG. 11, a conductive film 15 such as tungsten is formed on the first interlayer insulating film 11. 11A is a plan view, and FIG. 11B is a cross-sectional view in the A-A ′ direction of FIG. 11A.

Next, the first and second mask patterns corresponding to the first and second photoresist patterns are determined using the mask pattern forming program, respectively. Specifically, the layout pattern of the wiring layout, the exposure condition, the division location detection condition, and the division condition are set (S1 in FIG. 9). At this time, the division location detection conditions are the same as in the first embodiment. The division conditions are the following conditions (1) and (2).
(1) The first mask pattern is the same pattern as the layout pattern of the wiring layout shown in FIG.
(2) The second mask pattern is located in a divided portion, which will be described later, in a plan view, and the second mask pattern entirely overlaps the first mask pattern.

  Next, after performing the OPC process of the layout pattern (S2 in FIG. 9), the litho simulation of the layout pattern (S3 in FIG. 9), the division part is detected (S4 in FIG. 9). In the present embodiment, the same division location detection condition as that in the first embodiment is used, so the same location as that in the first embodiment is detected as a division location.

  Next, the layout pattern is divided into a first mask pattern and a second mask pattern using the division condition (S5 in FIG. 9). In this embodiment, since the division conditions (1) and (2) are set in advance, the first mask pattern becomes the same pattern as the layout pattern of the wiring layout, and the second mask pattern is positioned at the division location in plan view. Then, pattern division is performed so that the entire second mask pattern overlaps the first mask pattern. Note that the shape and size of the second mask pattern in plan view are not particularly limited as long as it is located at the divided portion in plan view and the second mask pattern does not protrude from the first mask pattern. That is, pattern division is performed so that the entire second mask pattern is positioned on the first mask pattern.

Next, OPC processing is performed on each of the divided first and second mask patterns (S6 and S7 in FIG. 9), and the first and second mask patterns are determined (S8 and S9 in FIG. 9). .
Next, as shown in FIG. 11, a first photoresist pattern 16 is formed on the conductive film 15 in the same manner as in the first embodiment. Thereafter, the first photoresist pattern 16 is cured.

  Next, as shown in FIG. 12, a second photoresist pattern 17 is formed on the first photoresist pattern 16 in the same manner as in the first embodiment. FIG. 12A is a plan view showing the case where only the second photoresist pattern 17 is formed on the conductive film 15, and the first photoresist pattern 16 is omitted. FIG. 12B is a plan view showing a case where the first and second photoresist patterns 16 and 17 are formed on the conductive film 15. FIG. 12C shows a cross-sectional view in the A-A ′ direction of FIG. 12B. Similar to the first embodiment, the region where the second photoresist pattern 17 and the first photoresist patterns 16a and 16c are combined corresponds to the first connection portion and the first wiring layer to be formed in a later step. To do.

  Next, by carrying out the steps of FIGS. 6 to 8 of the first embodiment, the semiconductor device of this embodiment is completed.

DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Element isolation region 3 Gate insulating film 4 Gate electrode 6 Photoresist pattern 6a Line part 8a Hard mask 8b Side wall film 9 LDD region 10 Source and drain region 11 First interlayer insulating film 12 Processed film 13 1 contact plug 14 division 15 conductive film 16 first photoresist pattern 17 second photoresist pattern 18a first connection portion 18b first wiring layer 20 second interlayer insulating film 21 second contact plug 22a 2nd connection part 22b 2nd wiring layer W ₁ line width W ₂ 1st width W ₃ 2nd width

Claims (19)

Forming a first photoresist pattern on the first film;
Curing the first photoresist pattern;
Forming a second photoresist pattern on the first film so as to at least partially overlap the first photoresist pattern in plan view;
Etching the first film using the first and second photoresist patterns as a mask;
A method for manufacturing a semiconductor device comprising:   2. The semiconductor device manufacturing method according to claim 1, wherein the first photoresist pattern is a line-and-space pattern including a line portion and a space portion having a first width located between the line portions. Method.   The width of the line portion is (λ / NA) / 4 to (λ / NA) / 2 (λ is the wavelength of the exposure light source, and NA is the numerical aperture of the exposure device) nm. A method for manufacturing a semiconductor device. In the step of forming the second photoresist pattern,
The second photoresist pattern is formed in such a manner that a region overlapping the first photoresist pattern has a second width larger than the first width in plan view. A method for manufacturing a semiconductor device according to claim 2. In the step of forming the second photoresist pattern,
The said 2nd photoresist pattern is formed in any one of Claims 1-4 so that all or a part of said 2nd photoresist pattern may overlap with a said 1st photoresist pattern by planar view. The manufacturing method of the semiconductor device as described in any one of Claims 1-3. The first film is a conductive film;
In the step of etching the first film,
The method for manufacturing a semiconductor device according to claim 1, wherein a wiring layer is formed under the first and second photoresist patterns by etching the conductive film. Prior to the step of forming the first photoresist pattern,
Forming a planar transistor on a semiconductor substrate;
Forming an interlayer insulating film on the semiconductor substrate;
Forming a contact plug penetrating the interlayer insulating film and connected to a source and drain region of the planar transistor;
Forming the first film on the interlayer insulating film;
Have
In the step of forming the first photoresist pattern,
Forming a positive type first photoresist pattern;
In the step of forming the second photoresist pattern,
Forming the positive type second photoresist pattern so that the region where the first and second photoresist patterns overlap is at least located on the contact plug;
In the step of etching the first film,
The method for manufacturing a semiconductor device according to claim 6, wherein the connection portion connected to the contact plug and the wiring layer are formed by etching the first film. A step of setting exposure conditions, layout patterns, division location detection conditions, and division conditions;
Detecting the division location of the layout pattern using the exposure condition and the division location detection condition;
Dividing the layout pattern into a first mask pattern and a second mask pattern using the division condition so that the division portion is divided;
A mask pattern creating program. Furthermore,
The mask pattern creation program according to claim 8, further comprising a step of performing optical proximity effect correction processing of the first and second mask patterns using the exposure conditions.   The division condition is a condition in which the first mask pattern is a line-and-space pattern including a line portion and a space portion having a first width located between the line portions. 9. The mask pattern creation program according to 9.   The width of the line portion is (λ / NA) / 4 to (λ / NA) / 2 (λ is the wavelength of the exposure light source, and NA is the numerical aperture of the exposure device) nm. Mask pattern creation program.   The division condition is a condition in which the second mask pattern has a second width larger than the first width in a region where the second mask pattern overlaps the first mask pattern in plan view. The mask pattern creation program described.   The mask pattern creation program according to any one of claims 8 to 12, wherein the division condition is a condition in which all or a part of the second mask pattern overlaps the first mask pattern in a plan view. . A step of setting exposure conditions, layout patterns, division location detection conditions, and division conditions;
Using the exposure condition and the division location detection condition to detect a division location of the layout pattern;
Dividing the layout pattern into a first mask pattern and a second mask pattern using the division condition so that the division portion is divided;
A mask pattern forming method having: Furthermore,
The mask pattern creation method according to claim 14, further comprising a step of performing optical proximity effect correction processing of the first and second mask patterns using the exposure conditions.   The division condition is a condition in which the first mask pattern is a line-and-space pattern including a line portion and a space portion having a first width located between the line portions. 15. The method for creating a mask pattern according to 15.   The width of the line portion is (λ / NA) / 4 to (λ / NA) / 2 (λ is the wavelength of the exposure light source, and NA is the numerical aperture of the exposure device) nm. Mask pattern creation method.   The division condition is a condition in which the second mask pattern has a second width larger than the first width in a region where the second mask pattern overlaps the first mask pattern in plan view. The mask pattern creation method as described.   19. The mask pattern creation method according to claim 14, wherein the division condition is a condition in which all or part of the second mask pattern overlaps the first mask pattern in plan view. .

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