JP2014095955A - Design device and design method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly and easily obtain an RTL circuit having an optimum cell delay in an FPGA, in the design of a semiconductor integrated circuit using high-level synthesis.SOLUTION: After high-level synthesis (S1), logic synthesis (S2), and the implementation to an FPGA (S3), it is determined whether or not the implementation has succeeded (S4). If the implementation has not succeeded (S4: NO), wiring delay information and the like 6 which are obtained by the implementation are fed back to parts which are not compatible with the processing performance indicated by a high-level synthesis constraint 2 to update the high-level synthesis constraint 2; and a new high-level synthesis constraint is created (S5). S1 to S4 are performed for the second time by using the updated high-level synthesis constraint. Since the implementation to the FPGA is facilitated by the improved processing performance of the updated high-level synthesis constraint 2, the implementation for the second time surely succeeds.

Description

  The present invention relates to a design apparatus and a design method for a semiconductor integrated circuit suitable for use in designing a field programmable gate array (FPGA).

  Although the degree of integration of LSI (Large Scale Integration) is increasing exponentially year by year, there is a limit to the ability of each designer, and there is a situation where the design ability cannot catch up with the increase in design scale. One effective approach for overcoming this design productivity crisis is to increase the level of design abstraction, and EDA (Electronic Design Automation) tools for this purpose are known.

  For example, when designing hardware to execute a certain process, from the "operation description" in which the algorithm of the target process is described at the operation level, to the "register There is a high-level synthesis tool having a “high-level synthesis” (also referred to as “behavioral synthesis” or “functional synthesis”) function for automatically synthesizing a “transfer level description” (hereinafter referred to as “RTL description”).

  Here, “operation description” is a description of circuit operation as sequential processing using a programming language such as C language, and “RTL description” is a hardware description language (Hardware Description) such as Verilog-HDL. (Language: HDL).

  In high-level synthesis, transformation, so as to satisfy the high-level synthesis constraints such as the operating frequency that determines the delay between registers and registers, between input and output terminals and registers, and the type and number of hardware resources such as arithmetic units and registers Performs scheduling, allocation, and binding to convert the behavior level description into an RTL description.

  Here, in the transformation, the behavioral description is analyzed, adaptation processing for hardware implementation such as reduction of the number of operations and stages, loop expansion, etc. is performed, and the resulting data flow and processing for that data Are converted into a CDFG (Control Data Flow Graph) represented by an arrow indicating the direction of data flow and each processing portion.

  In scheduling, each processing portion in the CDFG is assigned to each clock cycle on the time axis, and the execution timing of each processing is determined. In the allocation, a type of hardware resource corresponding to each type of processing is allocated to each processing part from a library storing hardware resources (calculators).

  In binding, the final connection relationship of hardware resources is determined. At this time, if the hardware resources allocated in the allocation are connected as they are, the circuit area becomes enormous, so the hardware resources that can be shared are shared, and the system is simplified as much as possible.

  The RTL description synthesized in this way is converted into a “net list description” (also referred to as “gate level description”) having delay information such as between registers and between input / output terminals and registers by a logic synthesis tool. Converted.

  At the stage of this logic synthesis, timing analysis is performed, and the delay information of the netlist description circuit is checked to confirm whether the netlist description circuit satisfies the design condition relating to the delay time. If not satisfied, the RTL circuit is corrected and the logic synthesis is performed again. At this time, without modifying the RTL circuit directly, for example, by changing the high-level synthesis constraint, the high-level synthesis is repeated until an RTL circuit that converges the timing in the circuit of the netlist description that is logically synthesized is obtained.

  As a technique for improving the design efficiency of such a semiconductor integrated circuit, there is a method for designing a semiconductor integrated circuit device described in Patent Document 1. In this method, as an ASIC (Application Specific Integrated Circuit) development flow, an optimum RTL circuit can be obtained by feeding back placement and routing information after logic synthesis to high-level synthesis.

  However, the design method of the semiconductor integrated circuit device described in Patent Document 1 does not take into account logic cells having a configuration peculiar to the FPGA, so that there is a problem that mapping to the FPGA cannot be performed smoothly. Hereinafter, this point will be described.

  An FPGA is a collection of logic cells composed of a look-up table (LUT) and flip-flops (FF). In the case of FPGA design, after logic synthesis, a circuit described in a netlist is converted into a logic cell in the FPGA. Perform the mapping implementation.

  At this time, even if it is possible to obtain an RTL circuit capable of logical synthesis by high-level synthesis (no problem in timing), a problem arises in timing by mapping the logically synthesized netlist description circuit to the logic cell. Sometimes.

  That is, in ASIC, logic is configured by freely using AND circuits or OR circuits, etc., and functions are realized. In FPGA, functions are realized by using many logic cells. As a result, the accumulation of wiring delays increases stepwise.

  Since the design method of the semiconductor integrated circuit device described in Patent Document 1 does not consider such a stepwise increasing delay, mapping to the FPGA cannot be performed smoothly. For this reason, it is necessary to adjust the delay by repeating the following operations.

  In other words, mapping is performed manually, and work such as placing a data path with severe wiring delay in a nearby location is performed by mapping. If this is not possible, the logic synthesis is re-established with strict logic synthesis constraints in order to regenerate the RTL description corresponding to the input RTL circuit. If implementation is still not possible, high-level synthesis constraints are tightened, and logic synthesis constraints are tightened to reduce the number of stages of logic circuits stored between registers (flip-flops) in the netlist description. The synthesis is repeated so as to reduce the delay and facilitate the implementation.

  Each work is basically done until it can be done, but if it can not be solved by all means, it will move to the upstream work, and if the timing of whether to solve each work is mistaken, it will accumulate unnecessary man-hours. .

  The present invention has been made to solve such a problem, and an object of the present invention is to quickly and easily obtain an RTL circuit having an optimum cell delay for an FPGA in the design of a semiconductor integrated circuit using high-level synthesis. Is to be able to.

  A semiconductor integrated circuit design apparatus according to the present invention includes a high-level synthesis means for converting an operation description into an RTL description, a logic synthesis means for converting the RTL description converted by the high-level synthesis means into a netlist description, and the logic synthesis. Implementation means for implementing the netlist description converted by the means in the FPGA, determination means for determining whether the implementation means has been implemented, and implementation by the determination means is not possible And a constraint updating unit that updates a high-level synthesis constraint in the high-level synthesis unit.

  According to the present invention, in designing a semiconductor integrated circuit using high-level synthesis, an RTL circuit having an optimum cell delay for an FPGA can be obtained quickly and easily.

It is a block diagram which shows the hardware constitutions of the design apparatus of the semiconductor integrated circuit which concerns on embodiment of this invention. 3 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus according to the embodiment of the present invention. It is a figure for demonstrating the operation | movement description in FIG. FIG. 3 is a diagram for explaining a high-level synthesis constraint in FIG. 2.

<Configuration of semiconductor integrated circuit design equipment>
FIG. 1 is a block diagram showing a hardware configuration of a semiconductor integrated circuit design apparatus according to an embodiment of the present invention.

  This semiconductor integrated circuit design apparatus is constituted by a computer system. The computer system 110 includes a CPU (Central Processing Unit) 111, a ROM (Read Only Memory) 112, a RAM (Random Access Memory) 113, an HDD (Hard Disk) 114, a display device 115, a keyboard 116, a mouse 117, and a CD-ROM device. 118 is provided.

  The CPU 111 performs processing while inputting / outputting data to / from the display device 115, keyboard 116, mouse 117, CD-ROM device 118, network device (not shown), ROM 112, RAM 113 or HDD 114.

  The semiconductor integrated circuit design program recorded on the CD-ROM is temporarily stored in the HDD 114 by the CPU 111 via the CD-ROM device 118. The CPU 111 loads the semiconductor integrated circuit design program from the HDD 114 to the RAM 113 and executes it to design the FPGA.

  Here, the semiconductor integrated circuit design program includes a high-level synthesis tool, a logic synthesis tool, an implementation tool, a constraint update tool, and the like. Means realized by the functions of these tools correspond to high-level synthesis means, logic synthesis means, implementation means, constraint update means, and the like in the present invention.

<Operation of semiconductor integrated circuit design equipment>
FIG. 2 is a flowchart showing the operation of the semiconductor integrated circuit design apparatus according to the embodiment of the present invention. In this figure, solid arrows indicate work transitions, and broken arrows indicate input information necessary for processing and output information generated by the processing. The flow starts when high-level synthesis with the highest level of abstraction is performed in the processing by the design device.

  In step S1, high-level synthesis is performed by inputting the behavior description 1 and the high-level synthesis constraint 2 to the high-level synthesis tool, and the RTL description 4 is generated. The behavioral description 1 is a description written in the behavioral description that is the basis for generating a high-level synthesis circuit, and the high-level synthesis constraint 2 is a description that indicates what processing performance is to be generated in the high-level synthesis. . The generated RTL description 4 is scheduled by high-level synthesis and satisfies the processing performance according to the high-level synthesis constraint.

  In step S2, logic synthesis is performed by inputting the RTL description 4 and the logic synthesis constraint 3 to the logic synthesis tool, and a netlist description 5 is generated. The logic synthesis constraint 3 is a description that instructs the logic synthesis tool about the processing performance of the RTL circuit in order to achieve the same processing performance as the high-level synthesis constraint 2. By using a logic synthesis tool for FPGA, logic synthesis suitable for the characteristics of the FPGA can be performed.

  When the logic synthesis is completed, the netlist description 5 of the output information is input to the implementation tool for implementation (conversion, map, placement and routing) (step S3). Next, it is determined whether or not the implementation has been completed (step S4).

  When it is determined that the implementation has been completed (step S4: YES), the flow of this figure ends. If it is determined that the implementation has failed (step S4: NO), the process proceeds to step S5 to update the constraints.

  Here, when it is determined that the implementation could not be performed, it is also determined whether or not it is the first implementation, that is, whether or not the high-level synthesis constraint 2 has been updated by the feedback information of the implementation result. . As a result of the determination, if it is the first implementation, the process proceeds to step S5.

  In step S5, with reference to the wiring delay information 6 obtained in the implementation (step S3), the high-level synthesis constraint 2 is fed back by feeding back a portion that does not match the processing performance specified by the high-level synthesis constraint 2. Update and create new high-level synthesis constraints.

  Here, the information referred to when updating the high-level synthesis constraint 2 in step S5 includes register correspondence information (information indicating the correspondence between RTL description registers and netlist description registers) and wiring delay information (FPGA). Information indicating delay between FFs). This register correspondence information is obtained as a result of high-level synthesis and a result of logic synthesis. Further, the wiring delay information is obtained as a result of implementation.

  The operation description 1, high-level synthesis constraint 2, logic synthesis constraint 3, RTL description 4, netlist description 5, and wiring delay information 6 in this figure are stored in the HDD 114 in FIG.

  Next, using the updated high-level synthesis constraints, high-level synthesis (step S1) is performed in the same manner as the first time, and further logic synthesis (step S2) and implementation in FPGA (step S3) are performed. It is determined whether or not the application has been completed (step S4).

  The updated high-level synthesis constraint has improved processing performance that becomes a bottleneck in logic synthesis (step S2) as compared to the high-level synthesis constraint before being updated. This improved processing performance facilitates implementation in FPGAs. For this reason, it is determined that the second implementation has been implemented and it has been successfully implemented (step S4: YES), and the flow of FIG.

  As described above, according to the present embodiment, the register correspondence information obtained from the result of high-level synthesis and the result of logic synthesis and the wiring delay information obtained from the result of implementation are added as inputs at the time of high-level synthesis. Then, for a high-level synthesis output, a data path having a strict timing is specified based on a delay between registers, and scheduling is performed again. Thereby, it is possible to smoothly obtain an RTL description having an optimum cell delay for the FPGA without implementing it in the FPGA many times.

<Example of behavioral description>
FIG. 3 is a diagram for explaining the operation description 1 in FIG. This figure is an operation description that describes only the operation of the process, and any language that can describe the operation description may be used. Here, mod1.h and mod1.cc in FIGS. 3A and 3B are sample code of a circuit described in the SystemC language.

  Data is input from in1 and in2 on the 7th and 8th lines (not including blank lines) of mod1.cc, and assigned to tmp_in1 and tmp_in2, respectively. 8-bit tmp_in1 and tmp_in2 are arguments of calc () of the function that processes data.

  Process tmp_in1 and tmp_in2 with calc () function and store the processed result in tmp_out. The stored 8-bit data of tmp_out is output to out. The transition of each state is due to the rise of the clk (clock) signal input to mod1. As shown in while (1) on the fifth line of mod1.cc, data input, processing, and data output are repeated with the clk signal.

<Example of high-level synthesis constraints>
FIG. 4 is a diagram for explaining the high-level synthesis constraint 2 in FIG. Here, FIG. 4A is an example of a high-level synthesis constraint prepared when performing high-level synthesis at the very beginning (first time), and FIGS. 4B, 4C, and 4D are high-level synthesis constraints updated according to the constraint transformation (step S5). It is an example.

  In the high-level synthesis constraint, the signal name of the clock signal, the signal name of the reset signal, the clock cycle, and options at the time of synthesis are written. The option indicates how to behave at the time of synthesis, and in FIG. 4A, it is instructed to perform with minimum effort when performing synthesis.

  In FIG. 4B, the operating clock is more restrictive than in FIG. 4A (5000 ps → 4500 ps). Since the clock cycle restriction is effective for the entire circuit, it is suitable for cases where there are many places that are likely to cause problems.

  In FIG. 4C, the behavioral synthesis option is instructed to be performed with the maximum effort, and the purpose is to obtain an effect on the entire circuit as in FIG. 4B. In FIG. 4D, the high-level synthesis is optimized by designating a high-level synthesis range (inline module = calc) for the function used in the behavioral description of the circuit of FIG.

  As described above, the implementation of the second high-level synthesis and logic synthesis is performed by adding various high-level synthesis constraints depending on the case, thereby facilitating the implementation in the FPGA and ensuring the implementation. it can.

  DESCRIPTION OF SYMBOLS 1 ... Action description, 2 ... High-level synthesis constraint, 3 ... Logic synthesis constraint, 4 ... RTL description, 5 ... Netlist description, 6 ... Wiring delay information, etc. 110 ... Computer system, 111 ... CPU, 112 ... ROM, 113 ... RAM, S1 ... high-level synthesis step, S2 ... logic synthesis step, S3 ... implementation step, S4 ... determination step, S5 ... constraint update step.

JP 2001-142922 A

Claims (6)

High-level synthesis means for converting the behavior description into the RTL description;
Logic synthesis means for converting the RTL description converted by the high-level synthesis means into a netlist description;
Implementation means for implementing in the FPGA the netlist description converted by the logic synthesis means;
Determination means for determining whether or not the implementation has been implemented by the implementation means;
When it is determined by the determination means that the implementation could not be performed, a constraint update means for updating a high-level synthesis constraint in the high-level synthesis means;
A device for designing a semiconductor integrated circuit. In the design apparatus of the semiconductor integrated circuit according to claim 1,
When the implementation is impossible, the determination unit also determines whether or not the implementation is the first time, and outputs the determination that the implementation was not possible only when the first time. Circuit design equipment. In the design apparatus of the semiconductor integrated circuit according to claim 1,
The constraint update means is a semiconductor integrated circuit design device for updating a clock cycle necessary for scheduling. In the design apparatus of the semiconductor integrated circuit according to claim 1,
The constraint updating means is a semiconductor integrated circuit design apparatus for updating an option for instructing how to synthesize. In the design apparatus of the semiconductor integrated circuit according to claim 1,
The constraint update means is a semiconductor integrated circuit design apparatus for adding information indicating a range of a portion requiring optimization. A high-level synthesis step that converts the behavioral description into an RTL description;
A logic synthesis step for converting the RTL description converted by the high-level synthesis step into a netlist description;
An implementation step of implementing in the FPGA the netlist description converted by the logic synthesis step;
A determination step for determining whether or not the implementation step has been implemented;
A constraint update step for updating a high-level synthesis constraint in the high-level synthesis step when it is determined that the implementation is not possible in the determination step;
A method for designing a semiconductor integrated circuit.

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