JP2014093674A - Switch circuit of satellite broadcast converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a chip area still smaller when integrating circuit components.SOLUTION: Provided is a switch circuit 10 of a satellite broadcast converter 1 for switching between two local oscillators 34, 35 having different oscillation frequencies which are built into the satellite broadcast converter 1 depending on whether a band-switching pulse signal of prescribed frequency is superposed on a power supply voltage sent out from a satellite broadcast tuner. The switch circuit 10 comprises: a charge/discharge unit 11 for charging or discharging according to the respective logic level of a two-level signal corresponding to the band-switching pulse signal superposed on the power supply voltage; a comparison unit 12 for comparing the output level of the charge/discharge unit changing with charging and discharging with a prescribed threshold; a determination unit 13 for determining, on the basis of the result of comparison by the comparison unit 12, whether one period of one logical level of the two-level signal is within a prescribed range; and a drive circuit 14 for driving either of the two local oscillators 34, 35 in accordance with the result of determination by the determination unit.

Description

  The present invention relates to a switch circuit for a satellite broadcast converter, and, for example, to a switch circuit for a satellite broadcast converter (BS (broadcasting satellite) converter) that selects a reception signal band of satellite broadcast.

  BS broadcasting is used in a wider band with digitization and an increase in the number of channels. For example, at a reception frequency of 10.7 GHz to 12.75 GHz, a low band of 10.7 GHz to 11.7 GHz and a high band are used. 11.7 GHz to 12.75 GHz band. In this case, as a receiver configuration on the receiving side, it is necessary to provide two sets of antennas and BS converters independently of each other for reception in each frequency band.

  On the other hand, in order to receive the BS broadcast with the frequency band divided by one antenna and the BS converter, the oscillation frequency of the local oscillator for frequency conversion incorporated in the BS converter is switched. For example, a BS converter configured to include a switching circuit that switches by a 22 KHz band switching pulse signal superimposed on a power supply voltage from a BS tuner connected to the BS converter is known (see Patent Document 1).

  As a related technique, Patent Document 2 discloses a switch circuit for a satellite broadcast converter that counts the frequency of a 22 KHz band switching pulse signal by a frequency counter.

Japanese Patent No. 3863538 Japanese Patent No. 3942608

  The analysis of related technology is given below.

  Incidentally, the switch circuit of the satellite broadcast converter described in Patent Document 1 requires a monostable circuit, an integration circuit, a delay circuit, and the like in order to determine the period of the 22 KHz band switching pulse signal. Each of these monostable circuit, integrating circuit, and delay circuit includes a capacitive element in order to create timing in the time direction. In particular, a delay circuit corresponding to a time window in the window comparator function requires a capacitive element having a large capacitance value in order to increase the delay time. Therefore, when integrating the switch circuit, the chip area is increased by these capacitive elements.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the switch circuit of the satellite broadcast converter includes two local oscillators having different oscillation frequencies built in the satellite broadcast converter, and the power supply voltage sent from the satellite broadcast tuner has a predetermined frequency. A switch circuit for a satellite broadcasting converter that switches according to whether or not a band switching pulse signal is superimposed, and at each logic level of a binary signal corresponding to the band switching pulse signal superimposed on the power supply voltage. 1 of the binary signal based on the comparison result of the charging / discharging unit that performs charging / discharging, the comparison unit that compares the output level of the charging / discharging unit that varies with charging / discharging with a predetermined threshold, A determination unit that determines whether or not one period of the logic level is within a predetermined range, and a drive circuit that drives one of the two local oscillators according to the determination result of the determination unit And, equipped with a.

  According to one embodiment, the chip area can be reduced.

It is a block diagram which shows the structure which comprises the switch circuit of BS converter of this Embodiment. 2 is a circuit diagram of a switch circuit according to Embodiment 1. FIG. It is a figure which shows the modification of the circuit in a comparison part and a determination part. It is a figure which shows the signal waveform of each part of a switch circuit. 6 is a circuit diagram of a switch circuit according to Embodiment 2. FIG. It is a figure which shows the insertion position of a 1/2 frequency dividing circuit.

  Hereinafter, the form for implementing is outlined. Note that the reference numerals of the drawings attached to the following outline are only examples for facilitating understanding, and are not intended to be limited to the illustrated embodiments.

  The switch circuit (10 in FIG. 1) of the satellite broadcast converter (1 in FIG. 1) according to one preferred embodiment includes two local oscillators (34, FIG. 1) having different oscillation frequencies built in the satellite broadcast converter. 35) is a switch circuit for a satellite broadcast converter that switches according to whether or not a band switching pulse signal of a predetermined frequency is superimposed on the power supply voltage sent from the satellite broadcast tuner (2 in FIG. 1). A charging / discharging unit (11 in FIG. 1) that performs charging / discharging according to each logic level of the binary signal corresponding to the band switching pulse signal superimposed on the power supply voltage, and charging / discharging that varies with charging / discharging One period of one logical level of the binary signal is within a predetermined range based on the comparison result (12 in FIG. 1) that compares the output level of the unit with a predetermined threshold and the comparison result of the comparison unit Whether or not Comprises determining unit that the constant a (13 in FIG. 1), a drive circuit for driving one of the two local oscillators in accordance with the determination result of the determination unit (14 in FIG. 1), the.

  According to the switch circuit of the satellite broadcasting converter as described above, the capacitance value of the capacitive element related to charging / discharging is configured to be small enough to charge or discharge in one period of 1 logic level of the binary signal. be able to. Therefore, the chip area when integrating the switch circuit can be further reduced.

  In the switch circuit, the charging / discharging unit includes first and second charging / discharging circuits (MN1, C1, I1, and MN2 in FIG. 2) having first and second time constants related to charging or discharging in one period, respectively. , C2, I2), and the comparison section includes first and second comparison circuits (CMP1, CMP2 in FIG. 2) for comparing the output levels of the first and second charge / discharge circuits with predetermined threshold values, respectively. The determination unit determines whether one period is within a predetermined range based on a logical operation result of the comparison outputs of the first and second comparison circuits at the end of one period. May be.

  In the switch circuit, the charging / discharging unit includes a charging / discharging circuit (MN1, C1, I1 in FIG. 5) having a predetermined time constant related to charging or discharging in one period, and the comparing unit outputs the output of the charging / discharging circuit. First and second comparison circuits (CMP1 and CMP2 in FIG. 5) for comparing the level with the first and second thresholds, respectively, and the determination unit performs the first and second comparisons at the end of one period. Based on the logical operation result of the comparison output of the circuit, it may be determined whether or not one period is within a predetermined range.

  In the switch circuit, the determination unit indicates that one period is within a predetermined range when only one comparison output of the first and second comparison circuits has exceeded a corresponding threshold value in one period. May be determined.

  In the switch circuit, the determination unit determines that one period is within a predetermined range when the logical values of the comparison outputs of the first and second comparison circuits are different at the end of one period. Also good.

  In the switch circuit, the first and second charge / discharge circuits include a current source (I1 and I2 in FIG. 2), a capacitor element (C1 and C2 in FIG. 2) having one end connected to the current source, Switch elements (MN1 and MN2 in FIG. 2) connected to both ends, both switch elements are opened in one period, and one end of each capacitor element is connected to the first and second charge / discharge terminals, respectively. The output of the circuit may be used.

  In the switch circuit, the charge / discharge circuit includes a current source (I1 in FIG. 5), a capacitor element (C1 in FIG. 5) that connects the current source to one end, and a switch element (in FIG. 5) that is connected to both ends of the capacitor element. MN1), and the switch element may be open during one period, and one end of the capacitor element may be used as the output of the charge / discharge circuit.

  In the switch circuit, the charging / discharging unit includes a frequency divider (DIV in FIG. 6) that divides the band switching pulse signal into two and then divides the pulse signal into two, and outputs the frequency divider as a binary signal. You may do it.

  Hereinafter, it will be described in detail with reference to the drawings in accordance with a more specific embodiment.

[Embodiment 1]
The satellite broadcasting receiving system converts a signal received by a parabolic antenna into an intermediate frequency signal by a low noise down converter block (LNB) satellite broadcasting converter (hereinafter referred to as “BS converter”) provided on the antenna, and Set Top It is configured to transmit to a Box (LNB, hereinafter referred to as “BS tuner”) via a cable. The BS tuner has a configuration in which a power supply for generating a negative bias such as a high frequency FET (GaAs-FET) built in the LNB and a control signal are supplied to the BS converter via a cable.

  The control signal includes a switching DC voltage based on two types of power supply voltage levels (13V / 18V) and a 22 KHz signal (tone signal) superimposed thereon. The switching of the reception polarization of the BS converter and the local oscillation frequency for frequency conversion is controlled by switching the DC voltage of the control signal and the presence or absence of a 22 KHz tone signal, respectively. In general, the BS converter uses a three-terminal regulator that outputs a stabilized voltage (8 V) from a DC voltage. Hereinafter, an embodiment of a satellite broadcast converter according to the present invention will be described in detail with reference to the drawings.

(Description of configuration)
FIG. 1 is a block diagram showing a configuration including a switch circuit of a BS converter according to the present embodiment. It is composed of a BS converter 1 provided in an outdoor parabolic antenna and an indoor BS tuner 2 connected to the BS converter 1 by a coaxial cable (cable).

  The BS signal (12 GHz band microwave signal) transmitted from the satellite is reflected by the parabolic antenna and received through the feed horn of the BS converter 1. The BS converter 1 converts the received BS signal into a 1 GHz intermediate frequency BS signal (hereinafter referred to as a “BS-IF (intermediate frequency) signal”) that can be transmitted by a cable, and then converts the BS-IF signal indoors. To the BS tuner 2

  The power supply voltage for operation of the BS converter 1 is supplied from the BS tuner 2 as either a high voltage value (18V) or a low voltage value (13V) via a cable. Further, a signal of 22 ± 4 KHz for band switching control (referred to as “band switching pulse signal”) is superimposed on the power supply voltage when the BS tuner 1 selects a high band (11.7 GHz to 12.75 GHz). . Here, 22 ± 4 KHz of the band switching pulse signal is a setting frequency that is very low with respect to the frequency of the BS-IF signal (950 MHz to 2150 MHz) and does not affect the BS-IF signal.

  The internal circuit of the BS converter 1 shown in FIG. 1 includes a reception system circuit A that amplifies a received signal and converts the frequency, and a control system circuit B that switches a frequency conversion operation and the like. The reception system circuit A includes a first-stage amplifier that amplifies a circularly polarized wave or a vertically-polarized BS signal reflected and received by a parabolic antenna, and a second-stage amplifier that amplifies the output of one of the first-stage amplifiers. A low-noise high-frequency amplifier 31 composed of a high electron mobility transistor (HEMT) or the like, a frequency converter (mixer) 32 that converts the output of the second-stage amplifier into a BS-IF signal, and a BS-IF An intermediate frequency amplifier 33 that amplifies the signal, and two local oscillators 34 and 35 that output a local signal having a frequency corresponding to the divided frequency to the frequency converter 32.

  The control system circuit B includes a BS converter switch circuit 10 and an antenna switching circuit 20. The switch circuit 10 includes a charge / discharge unit 11, a comparison unit 12, a determination unit 13, and a drive circuit 14. The charging / discharging unit 11 performs charging / discharging according to each logic level of the binary signal corresponding to the band switching pulse signal superimposed on the power supply voltage supplied from the BS tuner 2. The comparison unit 12 compares the output level of the charge / discharge unit 11 that varies with charge / discharge with a predetermined threshold. The determination unit 13 determines whether one period of the 1 logic level of the binary signal is within a predetermined range based on the comparison result of the comparison unit 12. That is, by determining the cycle of the binary signal, a determination result as to whether or not the frequency of the binary signal is within, for example, 22 ± 4 KHz is output. The drive circuit 14 supplies an operating bias to one of the two local oscillators 34 and 35 according to the determination result of the determination unit 13 to drive the oscillation.

  The antenna switching circuit 20 is controlled according to whether the power supply voltage supplied from the BS tuner 2 is the high voltage value (18V) or the low voltage value (13V) described above, and performs a switching operation according to the voltage, so that the amplifier 31 This is a switch that switches the bias so that the high electron mobility transistor of either of the two first-stage amplifiers is operated, and selects reception of either a circularly polarized wave or a vertically polarized BS signal. A more detailed description of the antenna switching circuit 20 is omitted.

  In the present embodiment, the local oscillator 35 for high band (11.7 GHz to 12.75 GHz) is controlled to oscillate only when the presence of the band switching pulse signal is detected, and the low band (10.7 GHz to 11). .7 GHz) local oscillator 34 is controlled to a non-oscillating state. If the presence of the band switching pulse signal is not detected, the low-band local oscillator 34 is controlled to be in an oscillating state and the high-band local oscillator 35 is controlled to be in a non-oscillating state. In either case, the frequency-converted signal output from the frequency converter 32 is output to the tuner 2 via the intermediate frequency amplifier 33 and the cable as a BS-IF signal having a specified intermediate frequency.

  Next, details of the switch circuit 10 will be described. FIG. 2 is a circuit diagram of the switch circuit according to the first embodiment.

  The charge / discharge unit 11 includes capacitive elements C0, C1, C2, resistance elements R1, R2, an amplifier (op-amp) AMP, a Schmitt trigger circuit ST, NMOS transistors MN1, MN2, and current sources I1, I2.

  The amplifier AMP inputs the band switching pulse signal S1 to the inverting input terminal (−) via the series circuit of the capacitive element C0 and the resistance element R1, and the resistance element R2 is connected between the inverting input terminal (−) and the output terminal. And a bias voltage Vb is applied to the non-inverting terminal (+). The amplifier AMP cuts off the power supply voltage superimposed on the band switching pulse signal S1, inverts and amplifies the band switching pulse signal S1, and supplies it to the Schmitt trigger circuit ST.

  The Schmitt trigger circuit ST is a circuit that binarizes the output signal of the amplifier AMP with a threshold value near the bias voltage Vb, and generates a binary signal corresponding to the band switching pulse signal S1 as a signal CLK.

  The NMOS transistor MN1 receives the signal CLK at its gate, connects its drain to one end of the current source I1 and one end of the capacitive element C1, and grounds its source. The other end of the capacitive element C1 is grounded. The NMOS transistor MN1 is turned on when the signal CLK is at the H level, and rapidly discharges the charge stored in the capacitor C1. When the signal CLK is at the L level, it is turned off and the capacitor C1 is charged by the current of the current source I1. Here, a signal at one end of the capacitive element C1 that repeats charging and discharging according to the signal CLK is Vcd1.

  The NMOS transistor MN2 receives the signal CLK at its gate, connects its drain to one end of the current source I2 and one end of the capacitive element C2, and grounds its source. The other end of the capacitive element C2 is grounded. The NMOS transistor MN2 is turned on when the signal CLK is at the H level, and rapidly discharges the charge stored in the capacitor C2. When the signal CLK is at the L level, it is turned off and the capacitor C2 is charged by the current of the current source I2. Here, a signal at one end of the capacitive element C2 that repeats charging and discharging according to the signal CLK is Vcd2.

  Note that, here, charging is a rise in the potential of one end of each of the capacitive elements C1 and C2 and discharge is a fall in the negative direction. It may be interpreted as charging.

  The comparison unit 12 includes comparison circuits CMP1 and CMP2. The comparison circuits CMP1 and CMP2 receive the signals Vcd1 and Vcd2 at the non-inverting terminal (+), respectively, and apply the threshold voltage Vt to the inverting input terminal (−) in common. The comparison circuits CMP1 and CMP2 output an H level when the signals Vcd1 and Vcd2 exceed (exceed) the threshold voltage Vt, respectively, and output an L level when the signals Vcd1 and Vcd2 are below the threshold voltage Vt.

  The determination unit 13 includes a 2-input AND circuit AND1 and a D-type flip-flop circuit DFF1. The AND circuit AND1 has one input terminal connected to the output of the comparison circuit CMP1, the other input terminal connected to the logically inverted output of the comparison circuit CMP2, and the output terminal connected to the D terminal of the flip-flop circuit DFF1. The flip-flop circuit DFF1 receives the signal CLK at its clock terminal and connects its output to the drive circuit 14. The flip-flop circuit DFF1 latches the H level at the rising edge of the signal CLK and outputs it to the drive circuit 14 when the output of the comparison circuit CMP1 is at the H level and the output of the comparison circuit CMP2 is at the L level. That is, when Vcd1> Vt and Vcd2 <Vt, the flip-flop circuit DFF1 latches the H level at the rising edge of the signal CLK and outputs it to the drive circuit 14. If the non-inverting terminal (+) and the inverting input terminal (−) in the comparison circuit CMP2 are switched, the AND circuit AND1 directly inputs the output of the comparison circuit CMP2 to the other input terminal without logically inverting it. Is possible.

  The drive circuit 14 drives the local oscillator 35 when the output of the flip-flop circuit DFF1 is at the H level, and drives the local oscillator 34 when the output of the flip-flop circuit DFF1 is at the L level.

  Next, modified examples of the circuits of the comparison unit 12 and the determination unit 13 will be described.

  In FIG. 3A, the comparison unit 12a includes Schmitt trigger circuits ST1 and ST2, respectively, instead of the comparison circuits CMP1 and CMP2 in FIG. Here, the Schmitt trigger circuits ST1 and ST2 are circuits that output an H level if the levels of the signals Vcd1 and Vcd2 exceed (exceed) the level corresponding to the threshold voltage Vt in FIG. The comparison unit 12a having such a configuration functions in the same manner as the comparison unit 12 of FIG.

  3A, the determination unit 13a includes an exclusive OR circuit EXOR1 instead of the AND circuit AND1 in FIG. The exclusive OR circuit EXOR1 outputs the H level when only one of the outputs of the Schmitt trigger circuits ST1 and ST2 is at the H level and the other is at the L level. The determination unit 13a having such a configuration functions in the same manner as the determination unit 13 of FIG.

  Further, in FIG. 3B, the determination unit 13b includes D-type flip-flop circuits DFF2 and DFF3, and an exclusive OR circuit EXOR2. The D-type flip-flop circuits DFF2 and DFF3 connect the outputs of the Schmitt trigger circuits ST1 and ST2 to the D terminals (input the signals D1 and D2), receive the signal CLK at the clock terminals, and exclusive the output terminals, respectively. Connected to one and the other input terminals of the OR circuit EXOR2 (outputs signals Q1 and Q2). The exclusive OR circuit EXOR2 connects the output terminal to the drive circuit 14. The determination unit 13b having such a configuration functions in the same manner as the determination unit 13 of FIG.

  Next, the operation of the switch circuit 10 having the above configuration will be described.

  Here, T is a period during which the signal CLK is at the L level. In the period T, if the capacitive element C1 is charged by the current source I1 and the level of the signal Vcd1 reaches Vt, T = C1 · Vt / I1 holds. In the period T, if the capacitive element C2 is charged by the current source I2 and the level of the signal Vcd2 reaches Vt, T = C2 · Vt / I2. If the duty ratio of the signal CLK is 50%, the frequency f of the band switching pulse signal S1 is 1 / 2T.

Since the switch circuit 10 determines whether or not the frequency f of the band switching pulse signal S1 is in the range of fl to fh (fh> fl), the constant of the charge / discharge circuit is determined as follows. That's fine.
fh = I1 / (2 · C1 · Vt)
fl = I2 / (2 · C2 · Vt)

  FIG. 4 shows signal waveforms at various parts of the switch circuit 10 configured as described above. Here, a case where the modification of FIG. 3B is applied will be described. In FIG. 4, the signal waveforms of the respective parts in the case of (1) f <fl, (2) fl <f <fh, and (3) f> fh are as follows.

  In the case of (1), T> C2 · Vt / I2> C1 · Vt / I1, and at the end of the period T (rising of the signal CLK), Vcd1> Vt, Vcd2> Vt, and the Schmitt trigger circuit ST1, The respective outputs D1 and D2 of ST2 are at the H level. Therefore, the outputs Q1 and Q2 of the flip-flop circuits DFF2 and DFF3 latched at the rising edge of the signal CLK are both at the H level. As a result, the output OUT of the exclusive OR circuit EXOR2 becomes L level.

  In the case of (2), C2 · Vt / I2> T> C1 · Vt / I1, and at the end of the period T (rising of the signal CLK), Vcd1> Vt, Vcd2 <Vt, and the Schmitt trigger circuit ST1. , ST2 outputs D1 and D2 are H level and L level, respectively. Accordingly, the outputs Q1 and Q2 of the flip-flop circuits DFF2 and DFF3 latched at the rising edge of the signal CLK become the H level and the L level, respectively. As a result, the output OUT of the exclusive OR circuit EXOR2 becomes H level.

  In the case of (3), C2 · Vt / I2> C1 · Vt / I1> T, and Vcd1 <Vt and Vcd2 <Vt at the end of the period T (rising of the signal CLK), and the Schmitt trigger circuit ST1 , ST2 outputs D1 and D2 are at L level. Therefore, the outputs Q1 and Q2 of the flip-flop circuits DFF2 and DFF3 latched at the rising edge of the signal CLK are both at the L level. As a result, the output OUT of the exclusive OR circuit EXOR2 becomes L level.

  The switch circuit 10 operating as described above is in the case of (2) (C2 · Vt / I2> T> C1 · Vt / I1) by determining whether the level of the output OUT is H level or L level. It can be determined whether or not. That is, it can be determined whether or not the frequency f of the band switching pulse signal S1 is in the range of fl to fh. In this case, since the capacitance elements C1 and C2 have a capacitance value small enough to be charged in the period T, the switch circuit 10 can further reduce the chip area when integrated.

[Embodiment 2]
FIG. 5 is a circuit diagram of a switch circuit according to the second embodiment. 5, the same reference numerals as those in FIG. 2 represent the same items, and the description thereof is omitted.

  The charging / discharging unit 11a is different from the charging / discharging unit 11 shown in FIG. 2 in that the capacitive element C2, the NMOS transistor MN2, and the current source I2 are omitted to form a single charging / discharging circuit. Here, a signal at one end of the capacitive element C1 that repeats charging and discharging is Vcd.

  In the comparison unit 12c, the comparison circuit CMP1 provides the threshold voltage Vt1 to the non-inverting terminal (+) and the signal Vcd to the inverting input terminal (−). Further, the comparison circuit CMP2 receives the signal Vcd at the non-inverting terminal (+) and applies the threshold voltage Vt2 (Vt2 <Vt1) to the inverting input terminal (−). The comparison circuits CMP1 and CMP2 both output an H level when the signal Vcd is between the threshold voltages Vt1 and Vt2, respectively, and output an L level and an H level when the signal Vcd is equal to or higher than the threshold voltage Vt1, respectively. Are output at H level and L level, respectively.

  In the determination unit 13c, the two-input AND circuit AND2 connects the outputs of the comparison circuits CMP1 and CMP2 to one and the other input terminals, respectively, and connects the output terminal to the D terminal of the flip-flop circuit DFF1.

  The charging / discharging unit 11a as described above functions in the same manner as the charging / discharging unit 11 of FIG. However, since the charging / discharging unit 11a includes a single charging / discharging circuit, the charging / discharging circuit has one capacitive element and can further reduce the chip area.

  In the switch circuits of the first and second embodiments as described above, the duty ratio of the signal CLK that is a binary signal is assumed to be 50%. However, the duty ratio of the signal CLK may deviate from 50% when the band switching pulse signal S1 includes odd harmonics or due to fluctuations in the threshold in the Schmitt trigger circuit ST. In such a case, the frequency f = 1 / 2T of the band switching pulse signal S1 is not satisfied, and the frequency determination range (fl to fh) of the band switching pulse signal S1 is relatively shifted.

  When the duty ratio of the signal CLK deviates from 50%, the duty ratio of the signal CLK may be correctly set to 50% by inserting a ½ frequency divider DIV after the Schmitt trigger circuit ST as shown in FIG. it can. In this case, since the period of the signal CLK is double that when the ½ divider circuit DIV is not inserted, the time constant of the charge / discharge circuit in the charge / discharge units 11 and 11a is also doubled. It is necessary to set the current value of the current source and the capacitance value of the capacitive element.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  It should be noted that the disclosures of the aforementioned patent documents are incorporated herein by reference. Within the scope of the entire disclosure (including claims) of the present invention, the embodiments and examples can be changed and adjusted based on the basic technical concept. Further, various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. It is. That is, the present invention of course includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the technical idea.

DESCRIPTION OF SYMBOLS 1 BS converter 2 BS tuner 10 Switch circuit 11, 11a Charging / discharging part 12, 12a, 12c Comparison part 13, 13a, 13b, 13c Determination part 14 Drive circuit 20 Antenna switching circuit 31 High frequency amplifier 32 Frequency converter 33 Intermediate frequency amplifier 34 , 35 Local oscillator AMP Amplifier AND1, AND2 AND circuits C0, C1, C2 Capacitance elements CMP1, CMP2 Comparison circuits DFF1, DFF2, DFF3 Flip-flop circuit DIV 1/2 divider circuit EXOR1, EXOR2 Exclusive OR circuit I1, I2 Current Sources MN1, MN2 NMOS transistors R1, R2 Resistive elements ST, ST1, ST2 Schmitt trigger circuit

Claims (8)

A satellite that switches two local oscillators having different oscillation frequencies built in a satellite broadcast converter according to whether or not a band switching pulse signal of a predetermined frequency is superimposed on a power supply voltage transmitted from a satellite broadcast tuner. A switch circuit for a broadcast converter,
A charge / discharge unit that performs charge / discharge according to each logic level of the binary signal corresponding to the pulse signal for band switching superimposed on the power supply voltage;
A comparison unit that compares the output level of the charging / discharging unit that varies with charging / discharging with a predetermined threshold;
A determination unit that determines whether one period of one logical level of the binary signal is within a predetermined range based on a comparison result of the comparison unit;
A drive circuit for driving one of the two local oscillators according to a determination result of the determination unit;
Switch circuit for a satellite broadcast converter comprising: The charging / discharging unit includes first and second charging / discharging circuits respectively having first and second time constants related to charging or discharging in the one period,
The comparison unit includes first and second comparison circuits that compare output levels of the first and second charge / discharge circuits with predetermined threshold values, respectively.
The determination unit determines whether the one period is within the predetermined range based on a logical operation result of comparison outputs of the first and second comparison circuits at the end of the one period. The switch circuit for the satellite broadcast converter according to claim 1. The charging / discharging unit includes a charging / discharging circuit having a predetermined time constant related to charging or discharging in the one period,
The comparison unit includes first and second comparison circuits that compare the output level of the charge / discharge circuit with first and second threshold values, respectively.
The determination unit determines whether the one period is within the predetermined range based on a logical operation result of comparison outputs of the first and second comparison circuits at the end of the one period. The switch circuit for the satellite broadcast converter according to claim 1.   When the determination unit indicates that only one comparison output of the first and second comparison circuits has exceeded a corresponding threshold value in the one period, the one period is within the predetermined range. 4. The switch circuit for a satellite broadcast converter according to claim 2, wherein the switch circuit is determined to be present.   The determination unit determines that the one period is within the predetermined range when logical values of comparison outputs of the first and second comparison circuits at the end of the one period are different. The switch circuit of the converter for satellite broadcasting according to 2 or 3.   The first and second charge / discharge circuits each include a current source, a capacitor element having one end connected to the current source, and a switch element connected to both ends of the capacitor element. 3. The switch circuit for a satellite broadcasting converter according to claim 2, wherein the switch element is in an open state, and one end of each of the capacitive elements is used as an output of each of the first and second charge / discharge circuits.   The charge / discharge circuit includes a current source, a capacitive element that connects the current source to one end, and a switch element that is connected to both ends of the capacitive element, and the switch element is open during the one period, and the capacitor 4. The switch circuit for a satellite broadcast converter according to claim 3, wherein one end of the element is an output of the charge / discharge circuit.   The said charging / discharging part is provided with the frequency divider which frequency-divides to 1/2 after binarizing the said pulse signal for band switching, The output of the said frequency divider is made into the said binary signal. Switch circuit for converter for satellite broadcasting.

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