JP2014092860A - Task execution order diagnosis device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a task execution order diagnosis device capable of diagnosing the execution order of a plurality of tasks including tasks in hierarchies for performing divided processing in the same processing level.SOLUTION: A task execution order diagnosis circuit 2 for diagnosing the execution order of a plurality of tasks T1 to T372 including tasks T21 to T372 in hierarchies H2 and H3 for performing divided processing includes: a current number register 24 for storing a current task code; a previous number register 25 for storing the previous task code; a number management table 26 for managing the final task code of each of hierarchies H1 to H3; a diagnosis circuit 27 for diagnosing whether or not the current task code is valid on the basis of the previous task code; and a comparator circuit 28 for comparing the current task code with the final task code of the number management table 26. The task code of the previous number register 25 is updated on the basis of the comparison result of the comparator circuit 28.

Description

  The present invention relates to an apparatus for diagnosing the order of tasks executed by a computer.

  In general, task execution order diagnosis is known as a method for monitoring normal operation of firmware. The task execution order diagnosis is performed by checking the validity of the task to be executed last time and the task to be executed this time.

  For example, it is disclosed that the execution order is diagnosed by setting identification information including information for identifying the task and information for identifying the task to be executed before the task itself in the monitoring unit at the time of activation (for example, , See Patent Document 1).

  Further, it is disclosed that the execution order is diagnosed by an operation inspection circuit in which a circuit for simulating a program executed by a microprocessor is mounted in advance (see, for example, Patent Document 2).

JP 2010-9296 A Japanese Patent No. 4359632

  However, when the processing within a task is divided and executed multiple times, the task execution order is diagnosed for each processing level of the hierarchy to which the divided tasks belong, and all tasks are diagnosed at the same processing level. Not known about what to do. When diagnosing the task execution order for each processing level, the diagnosis method becomes complicated and the diagnosis time becomes longer. Also, if the task execution order changes due to firmware changes or the like, there is a possibility that the diagnostic device cannot be easily changed.

  Accordingly, an object of the present invention is to provide a task execution order diagnosis apparatus capable of diagnosing the execution order of a plurality of tasks including tasks in a hierarchy for performing divided processing at the same processing level.

  A task execution order diagnosis apparatus according to an aspect of the present invention is a diagnosis apparatus for diagnosing the execution order of a plurality of tasks including tasks in a hierarchy that performs divided processing, and stores a task code indicating a task to be diagnosed First task code storage means, second task code storage means for storing a task code for diagnosing the task to be diagnosed, and a final task code indicating a task to be executed last for each hierarchy The task code indicating the diagnosis target task stored in the first task code storage unit based on the task code stored in the second task code storage unit and the final task code storage unit to store A diagnostic means for diagnosing whether or not is appropriate, and before the task code indicating the task to be diagnosed is stored in the final task code storage means The task code stored in the second task code storage unit is updated based on a determination result by the final task code determination unit and a final task code determination unit that determines whether the task code is a final task code. Updating means.

  ADVANTAGE OF THE INVENTION According to this invention, the task execution order diagnostic apparatus which can diagnose the execution order of several tasks containing the task which divides | segments the process in a task into multiple times and can be diagnosed at the same process level can be provided.

The block diagram which shows the structure of the microcomputer to which the task execution order diagnostic circuit which concerns on embodiment of this invention was applied. The conceptual diagram showing the structure of the task of the firmware which concerns on this embodiment. The figure which shows the execution order of the task of the firmware which concerns on this embodiment. FIG. 3 is a structural diagram showing a structure of a storage area of a current number register according to the present embodiment. FIG. 3 is a structural diagram showing the structure of a storage area of a previous number register according to the present embodiment. FIG. 3 is a structural diagram showing the structure of a storage area of a number management table according to the present embodiment. The data change figure showing the update state of the data of the last number register which concerns on this embodiment. The data structure figure which shows the structure of the data showing the task code which concerns on this embodiment. The data structure figure which shows the structure of the extended data showing the task code which concerns on this embodiment. The timing chart showing the 1st operation of the execution order diagnostic circuit concerning this embodiment. The timing chart showing the 2nd operation of the execution order diagnostic circuit concerning this embodiment. The timing chart showing the 3rd operation of the execution order diagnostic circuit concerning this embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment)
FIG. 1 is a configuration diagram showing a configuration of a microcomputer (hereinafter referred to as “microcomputer”) 10 to which a task execution order diagnosis circuit 2 according to an embodiment of the present invention is applied. In addition, the same code | symbol is attached | subjected to the same part in drawing, the detailed description is abbreviate | omitted, and a different part is mainly described.

  The microcomputer 10 includes a microprocessor 1, an execution order diagnosis circuit 2, a firmware storage unit 3, a work memory 4, and a memory mapped I / O 5. Each component constituting the microcomputer 10 is connected by an address bus AB and a data bus DB. Thereby, communication between each component part is performed.

  The microprocessor 1 is an arithmetic processing unit that executes a program. The microprocessor 1 outputs the address of the target device in the memory bus cycle by the address bus AB. Thereby, the microprocessor 1 designates a target device to be read or written. The microprocessor 1 transmits data to and from the target device in a memory bus cycle using the data bus DB. The microprocessor 1 outputs a command in a memory bus cycle to instruct data reading or writing and its timing.

  The execution order diagnosis circuit 2 is a circuit for diagnosing the execution order of firmware (program) tasks executed by the microprocessor 1. The execution order diagnosis circuit 2 is configured by a computer. The execution order diagnosis circuit 2 completes the diagnosis within a cycle in which the microprocessor 1 writes a task code to the execution order diagnosis circuit 2. The task code is a unique code indicating a task assigned to each task.

  The firmware storage unit 3 is a memory in which firmware is stored. The firmware storage unit 3 is, for example, a FROM (flash read only memory).

  The work memory 4 is a memory for temporarily storing data used by the microprocessor 1 for arithmetic processing. The work memory 4 is, for example, a RAM (random access memory).

  The memory mapped I / O 5 is a circuit having an interface function for transmission with an external circuit.

  Next, the configuration of the execution order diagnosis circuit 2 will be described.

  The execution order diagnosis circuit 2 compares the address decode circuit 21, the R / W control circuit 22, the timing circuit 23, the current number register 24, the previous number register 25, the number management table 26, and the diagnosis circuit 27. Circuit 28.

  The address decoding circuit 21 decodes the address received from the address bus AB. The address decoding circuit 21 outputs the address decoding result to the R / W control circuit 22. The address decode circuit 21 functions as a bus interface for the microcomputer 10.

  The R / W control circuit 22 reads and writes data to and from the register or table in the execution order diagnosis circuit 2 based on the command received from the microprocessor 1 and the decoding result of the address received from the address decoding circuit 21. To control.

  The timing circuit 23 determines the timing at which the diagnosis circuit 27 and the comparison circuit 28 start processing. The timing circuit 23 outputs a signal for causing the diagnosis circuit 27 and the comparison circuit 28 to process at the determined timing.

  In the current number register 24, a current task code executed by the microprocessor 1 is written. The task indicated by the task code written in the current number register 24 becomes a diagnosis target by the execution order diagnosis circuit 2.

  In the previous number register 25, the previous task code before diagnosis by the diagnosis circuit 27 is written. The task code written in the previous number register 25 is a task code for diagnosing a task to be diagnosed. Therefore, the previous number register 25 does not necessarily hold the previous task code as it is, and may be corrected as necessary for diagnosis.

  In the number management table 26, the final task code of each layer is set by the microprocessor 1 as management information at the time of initialization. The final task code is a task code indicating a task to be executed last in each layer.

  The diagnosis circuit 27 refers to the current task code held in the current number register 24 and the previous task code held in the previous number register 25 at the timing TA output from the timing circuit 23, and updates the firmware. Diagnose the validity of the task execution order. After diagnosis, the diagnostic circuit 27 outputs a transfer command for writing the current task code held in the current number register 24 to the previous number register 25. As a result, the current task code is written in the previous number register 25.

  The comparison circuit 28 refers to the management information in the number management table 26 at the timing TB output from the timing circuit 23 and refers to the current task code (current number register 24) that has been stored in the previous number register 25 and has been diagnosed. Is the same as the task code held in (1). If the comparison circuit 28 determines that the task is the final task, it initializes the task code held in the previous number register 25 for the next diagnosis.

  Next, the operation of the execution order diagnostic circuit 2 will be described. FIG. 2 is a conceptual diagram showing a configuration of firmware tasks T1 to T728 according to the present embodiment. Here, the description will be given mainly using the configuration of tasks T1 to T728 shown in FIG. 2, but the configuration is the same for any configuration of tasks.

  First, the configuration of tasks T1 to T728 will be described.

  The microprocessor 1 repeatedly executes the tasks T1 to T9 in the first hierarchy H1 of the highest hierarchy in order.

  The tasks T2, T4, T6, and T7 are divided into a plurality of processes. The task T2 is divided into five tasks T21 to T25 in the second hierarchy H2. The task T4 is divided into three tasks T41 to T43 in the second hierarchy H2. The task T6 is divided into four tasks T61 to T64 in the second hierarchy H2. The task T7 is divided into two tasks T71 and T72 in the second hierarchy H2.

  The two tasks T41 and T43 in the second hierarchy H2 of the task T4 and the two tasks T71 and T72 in the second hierarchy H2 of the task T7 are further divided into a plurality of times. The task T41 of the second hierarchy H2 is divided into three tasks T411 to T413 in the third hierarchy H3. The task T43 in the second hierarchy H2 is divided into six tasks T431 to T436 in the third hierarchy H3. The task T71 of the second hierarchy H2 is divided into three tasks T711 to T713 in the third hierarchy H3. The task T72 of the second hierarchy H2 is divided into eight tasks T721 to T728 in the third hierarchy H3.

  FIG. 3 is a diagram showing the execution order of tasks T1 to T728 executed by the microprocessor 1. The sequence order indicates the order in which the tasks T1 to T9 of the first hierarchy H1 are executed.

  The microprocessor 1 executes task T1 to task T9 sequentially.

  First, the first scan (first round) will be described.

  Since the task T1 is not divided, the task T2 is executed after the task T1 is executed.

  The task T2 executes the task T21 of the second hierarchy H2 in the first scan. Since the task T21 is not divided, the task T3 is executed after the task T21 is executed.

  Since the task T3 is not divided, the task T4 is executed after the task T3 is executed.

  The task T4 executes the task T41 of the second hierarchy H2 in the first scan. Here, the task T41 is further divided in the third hierarchy H3. Accordingly, the task T41 executes the task T411 of the third hierarchy H3. After execution of task T411, task T5 is executed.

  Since the task T5 is not divided, the task T6 is executed after the task T5 is executed.

  The task T6 executes the task T61 of the second hierarchy H2 in the first scan. Since task T61 is not divided, task T7 is executed after execution of task T61.

  The task T7 executes the task T71 of the second hierarchy H2 in the first scan. Here, the task T71 is further divided in the third hierarchy H3. Therefore, the task T71 executes the task T711 of the third hierarchy H3. After execution of task T711, task T8 is executed.

  Since the task T8 is not divided, the task T9 is executed after the execution of the task T8.

  Since task T9 is not divided, task T1 is executed as the second scan after execution of task T9.

  Next, the second scan will be described.

  After execution of task T1, task T2 is executed. The task T2 executes the task T22 of the second hierarchy H2 in the second scan. After execution of task T22, task T3 is executed. After execution of task T3, task T4 is executed.

  In the second scan, the task T4 executes the same task T41 as that in the first scan of the second hierarchy H2. This is because the execution of all the tasks T411 to T413 divided in the third hierarchy H3 located below the second hierarchy H2 is not completed. Task T41 executes task T412 in the second scan. After execution of task T412, task T5 is executed. After execution of task T5, task T6 is executed.

  The task T6 executes the task T62 of the second hierarchy H2 in the second scan. After execution of task T62, task T7 is executed.

  The task T7 executes the same task T71 as the first scan of the second hierarchy H2 in the second scan. Task T71 executes task T712 in the second scan. After execution of task T712, task T8 is executed. After execution of task T8, task T9 is executed. After the execution of task T9, task T1 is executed as the third scan.

  As in the first and second scans, tasks T1 to T728 are also executed after the third scan, as shown in FIG.

  FIG. 4 is a structural diagram showing the structure of the storage area of the current number register 24 according to the present embodiment.

  Three storage areas RP1, RP2, and RP3 corresponding to the three hierarchies H1 to H3 are allocated to the current number register 24, respectively. The storage area RP1 stores the task number of the first hierarchy H1. The storage area RP2 stores the task number of the second hierarchy H2. The storage area RP3 stores the task number of the third hierarchy H3.

  Here, it is assumed that the task number is determined as follows.

  For tasks with the second hierarchy H2 and the third hierarchy H3, the task numbers of the hierarchies H1 to H3 are the numbers in the order of execution in each hierarchy. Further, the task number of the non-existing layers H2 and H3 is “1”. For example, in the task T431, the task number of the first hierarchy H1 is “4”, the task number of the second hierarchy H2 is “3”, and the task number of the third hierarchy H3 is “1”. Further, the second hierarchy H2 and the third hierarchy H3 of the task 5 are “1”. The task number is not limited to a numerical value but may be represented by a bit arrangement or may be represented by other methods.

  Next, a case where the current number register 24 has a 32-bit storage area will be described.

  The 1st to 15th bits are allocated to the storage area RP3, the 16th to 23rd bits are allocated to the storage area RP2, and the 24th to 31st bits are allocated to the storage area RP1, respectively. When the current task code is the task T411 of the third hierarchy H3, “4” is written in the storage area RP1, “1” is written in the storage area RP2, and “1” is written in the storage area RP3.

  FIG. 5 is a structural diagram showing the structure of the storage area of the previous number register 25 according to this embodiment.

  The previous number register 25 includes a storage area RN1 for storing the task number of the first hierarchy H1, and the second hierarchy H2 and the third hierarchy H3 corresponding to the number of tasks T1 to T9 in the first hierarchy H1. Are assigned storage areas RN12 to RN93.

  When the task code is transferred from the current number register 24, the previous number register 25 writes the task numbers of the tasks T1 to T728 indicated by the task code in the corresponding storage areas RN12 to RN93. For example, when the task code indicating the task T724 is transferred, “7” is written in the storage area RN1 of the first hierarchy H1, and “2” is written in the storage area RN72 of the second hierarchy H2 of the task T7. Accordingly, “4” is written in the storage area RN73 of the third hierarchy H3 of the task T7.

  FIG. 6 is a structural diagram showing the structure of the storage area of the number management table 26 according to the present embodiment.

  The number management table 26 includes a storage area RT1 that stores the final task number of the first hierarchy H1, storage areas RT12 to RT92 that store the final task number of the second hierarchy H2, and a final area of the third hierarchy H3. Storage areas RT131 to RT931 for storing task numbers are allocated. For example, a task number “9” indicating the ninth task T9 executed last in the first hierarchy H1 is set in the storage area RT1. In the storage area RT42, a task number “3” indicating the third task T43 to be executed last in the second hierarchy H2 of the task T4 in the first hierarchy H1 is set. Also, “1” is set in the hierarchy where there is no task to be executed. For example, in the task T5 of the first hierarchy H1, there is no task to be executed in the second hierarchy H2, so “1” is set in the storage area RT52.

  Next, update of data in the previous number register 25 will be described. Here, a case where the execution order of tasks T1 to T728 is all normal (valid) will be described.

  FIG. 7 is a data change diagram showing a data update state of the previous number register 25 according to the present embodiment.

  In the previous number register 25, '0' is written in all the storage areas RN1 to RN93 in the initial state.

  When it is determined that the task code of the task T1 written in the current number register 24 is normal, the task code of the task T1 is written in the previous number register 25. As a result, '1' is written to the storage area RN1 of the first hierarchy H1, the storage area RN12 of the second hierarchy H2 of the task T1, and the storage area RN13 of the third hierarchy H3 of the task T1. If it is determined by comparison with the number management table 26 that the second hierarchy H2 and the third hierarchy H3 of the task T1 are the final task numbers, the storage area RN12 and the third hierarchy H3 of the second hierarchy H2 Storage area RN13 is initialized to '0'.

  Since the task T21 is executed after the execution of the task T1 of the first scan, the task code of the task T21 is written in the current number register 24.

  When it is determined that the task code of the task T21 written in the current number register 24 is normal, the task code of the task T21 is written in the previous number register 25. As a result, “2” is written to the storage area RN1 of the first hierarchy H1, and “1” is written to the storage area RN22 of the second hierarchy H2 of the task T2 and the storage area RN23 of the third hierarchy H3 of the task T2. Is written. If it is determined by comparison with the number management table 26 that the third hierarchy H3 of the task T2 is the final task number, the storage area RN23 of the hierarchy H3 is initialized to “0”.

  Since the task T3 is executed after the execution of the task T21 in the first scan, the task code of the task T3 is written in the current number register 24.

  When it is determined that the task code of the task T3 written in the current number register 24 is normal, the task code of the task T3 is written in the previous number register 25. As a result, “3” is written to the storage area RN1 of the first hierarchy H1, and “1” is written to the storage area RN32 of the second hierarchy H2 of the task T3 and the storage area RN33 of the third hierarchy H3 of the task T3. Is written. If it is determined by comparison with the number management table 26 that the second hierarchy H2 and the third hierarchy H3 of the task T3 are the final task numbers, the storage area RN22 and the third hierarchy H3 of the second hierarchy H2 Storage area RN23 is initialized to '0'.

  In this way, the data in the previous number register 25 is sequentially updated.

  FIG. 8 is a data structure diagram showing a structure of data DT representing a task code transmitted through the data bus DB according to the present embodiment. Here, the capacity of the data DT will be described with 32 bits, but the capacity of the data DT may be any number.

  Data DT includes areas D1 to D3 representing task numbers of the respective hierarchies H1 to H3 and an extension flag FL. A region D1 from 24 bits to 31 bits represents the task number of the first hierarchy H1. A region D2 from 16 bits to 23 bits represents the task number of the second hierarchy H2. A region D3 from 1 bit to 15 bits represents the task number of the third hierarchy H3.

  As shown in FIG. 8, the task numbers of the areas D1 to D3 of the data DT are changed according to the sequence order.

  The extension flag FL is an area located at 0 bit. The extension flag FL is “1” when there is data that extends the data DT, and is “0” when there is no data that extends the data DT. The extension flag FL becomes “1” when there is a lower hierarchy than the third hierarchy H3. Therefore, in the configuration of the execution order of the tasks T1 to T728 shown in FIG. 2, since there is no hierarchy lower than the third hierarchy H3, the expansion flag FL is always “0”.

  FIG. 9 is a data structure diagram showing the structure of the expanded data DT1 to DT3. With reference to FIG. 9, a case will be described in which task codes in the first hierarchy H1 to the eighth hierarchy H8 are divided into three data DT1 to DT3. Note that the capacities of the areas D1 to D8 representing the task numbers of the hierarchies H1 to H8 may be allocated to the three data DT1 to DT3 in any way.

  The first data DT1 is the same as the structure of the data DT shown in FIG. 8 except that the extension flag FL is “1”. Accordingly, the first data DT1 includes areas D1 to D3 representing task numbers from the first hierarchy H1 to the third hierarchy H3. Since the extension flag FL is “1”, the processing unit that has received the first data DT1 waits for the reception of the second data DT2.

  The second data DT2 includes areas D4 and D5 representing the task numbers of the fourth hierarchy H4 and the fifth hierarchy H5, and an extension flag FL. Since the extension flag FL is “1”, the processing unit that has received the second data DT2 waits for reception of the third data DT3.

  The third data DT3 includes areas D6 to D8 representing task numbers of the sixth hierarchy H6 and the eighth hierarchy H8, and an extension flag FL. Since the extension flag FL is “0”, the processing unit that has received the third data DT3 ends the process of receiving data representing the task code.

  FIG. 10 is a timing chart illustrating a first operation of the execution order diagnosis circuit 2 according to the present embodiment. The first operation is an operation when the task execution order is normal and the task to be diagnosed is not the final task. The shaded portion in the figure indicates that the operating state is indeterminate.

  The microprocessor 1 initializes the execution order diagnosis circuit 2 before making a diagnosis by the execution order diagnosis circuit 2. Specifically, the microprocessor 1 writes management information in the number management table 26 and writes “0” in the previous number register 25. The management information in the number management table 26 may be initialized by firmware when the microcomputer 10 is initialized.

  When executing the tasks T1 to T728, the microprocessor 1 writes the unique task codes of the tasks T1 to T728 to be executed in the current number register 24.

  Specifically, the microprocessor 1 outputs the address of the current number register 24 to the address decoding circuit 21 when executing the tasks T1 to T728, and performs a R / W control on a command for writing data to the execution order diagnosis circuit 2. It outputs to the circuit 22 and outputs the unique task code of the tasks T1 to T728 to be executed to the current number register 24.

  The address decoding circuit 21 decodes the received address and outputs the decoded address to the R / W control circuit 22. The R / W control circuit 22 outputs a write command to the current number register 24 based on the received address and command. As a result, the task code output from the microprocessor 1 is written in the current number register 24.

  When the task code is written in the current number register 24, the R / W control circuit 22 outputs a WAIT signal to the microprocessor 1. As a result, the bus cycle of the microprocessor 1 enters a standby state. Further, the R / W control circuit 22 outputs a diagnosis start command for diagnosing the execution order to the timing circuit 23.

  When the timing circuit 23 receives the diagnosis start command, the timing circuit 23 controls the sequence of the execution order diagnosis.

  First, the timing circuit 23 outputs the timing TA to the diagnosis circuit 27 when receiving the diagnosis start command. When receiving the timing TA, the diagnostic circuit 27 refers to the task code stored in the current number register 24 and the task code stored in the previous execution order diagnosis stored in the previous number register 25, and the execution order is valid. Diagnose whether it is normal.

  Here, a diagnosis method by the diagnosis circuit 27 will be described.

  The diagnosis circuit 27 performs diagnosis by comparing the task numbers indicated by the current number register 24 and the previous number register 25 in order from the upper layer to the lower layer.

  First, the diagnostic circuit 27 performs the diagnosis of the first hierarchy H1 as follows.

  The diagnosis circuit 27 adds 1 to the task number of the first hierarchy H1 (highest hierarchy) of the task indicated by the current number register 24 and the task number of the first hierarchy H1 of the task indicated by the previous number register 25. It is determined whether (incremented value) is the same. If they are not the same, the diagnostic circuit 27 determines that the execution order is abnormal.

  When the diagnosis circuit 27 determines that the first hierarchy H1 is normal, the diagnosis circuit 27 performs the diagnosis of the second hierarchy H2 as follows.

  When the third hierarchy H3 of the task indicated by the previous number register 25 is “0”, the diagnosis circuit 27 indicates the task number of the second hierarchy H2 of the task indicated by the current number register 24 and the previous number register 25. It is determined whether or not the value obtained by adding 1 to the task number of the second hierarchy H2 of the task is the same. If they are not the same, the diagnostic circuit 27 determines that the execution order is abnormal.

  When the third hierarchy H3 of the task indicated by the previous number register 25 is not “0”, the diagnostic circuit 27 determines the task number of the second hierarchy H2 of the task indicated by the current number register 24 and the task indicated by the previous number register 25. It is determined whether the task numbers of the second hierarchy H2 are the same. If they are not the same, the diagnostic circuit 27 determines that the execution order is abnormal.

  When the diagnosis circuit 27 determines that the second hierarchy H2 is normal, the diagnosis circuit 27 diagnoses the third hierarchy H3 as follows.

  Whether the diagnosis circuit 27 has the same value as the task number of the third hierarchy H3 of the task indicated by the current number register 24 and the task number of the third hierarchy H3 of the task indicated by the previous number register 25 plus 1. Judge whether or not. If they are not the same, the diagnostic circuit 27 determines that the execution order is abnormal.

  The diagnosis circuit 27 determines that the execution order is appropriate (normal) when none of the hierarchies H1 to H3 is determined to be abnormal.

  When the diagnosis circuit 27 diagnoses that the execution order is valid, the diagnosis circuit 27 outputs a diagnosis result to the timing circuit 23 and outputs a transfer command for transferring the task code stored in the current number register 24 to the previous number register 25. . As a result, the task code stored in the previous number register 25 is updated to the task code stored in the current number register 24.

  The timing circuit 23 outputs the timing TB to the comparison circuit 28 when receiving the diagnosis result that the execution order is valid.

  When the comparison circuit 28 receives the timing TB, the comparison circuit 28 refers to the management information in the number management table 26 to determine whether or not the task code for which the diagnosis stored in the previous number register 25 has been completed is the final task. If the comparison circuit 28 determines that the task code stored in the previous number register 25 is not the final task (mismatch with the management information), the comparison circuit 28 does not initialize the previous number register 25. When the comparison is completed, the comparison circuit 28 outputs a comparison completion notification to the timing circuit 23.

  When receiving the comparison completion notification, the timing circuit 23 outputs a diagnosis completion notification to the R / W control circuit 22. When the R / W control circuit 22 receives the diagnosis completion notification, the R / W control circuit 22 cancels the standby state of the bus cycle of the microprocessor 1.

  FIG. 11 is a timing chart showing a second operation of the execution order diagnosis circuit 2 according to the present embodiment. The second operation is an operation when the task execution order is normal and the task to be diagnosed is the final task. The shaded portion in the figure indicates that the operating state is indeterminate. Here, the difference from the first operation shown in FIG. 10 will be mainly described.

  Until the processing by the comparison circuit 28 is started, it is the same as the first operation described above.

  When the comparison circuit 28 determines that the task code stored in the previous number register 25 is the final task (matches the management information), the comparison circuit 28 initializes the previous number register 25. When the comparison is completed, the comparison circuit 28 outputs a comparison completion notification to the timing circuit 23.

  Regarding other operations, the second operation is the same as the first operation shown in FIG.

  FIG. 12 is a timing chart showing a third operation of the execution order diagnostic circuit 2 according to the present embodiment. The third operation is an operation when the task execution order is abnormal. The shaded portion in the figure indicates that the operating state is indeterminate. Here, the difference from the first operation shown in FIG. 10 will be mainly described.

  Until the diagnosis by the diagnosis circuit 27 is started, the first operation is the same as that described above.

  When the diagnosis circuit 27 diagnoses that the execution order is abnormal, the diagnosis circuit 27 outputs a diagnosis result indicating the abnormality to the timing circuit 23 and does not update the previous number register 25.

  When the timing circuit 23 receives the diagnosis result indicating the abnormality, the timing circuit 23 outputs an execution order abnormality notification to the microprocessor 1 and outputs a diagnosis completion notification to the R / W control circuit 22. When the R / W control circuit 22 receives the diagnosis completion notification, the R / W control circuit 22 releases the standby state of the microprocessor 1 in the bus cycle.

  The microprocessor 1 can obtain the diagnosis result by receiving the execution order abnormality notification. By starting the interrupt process of the microprocessor 1 by the execution order abnormality notification, the microprocessor 1 can detect an abnormality in the execution order.

  According to the present embodiment, the final task codes of the respective hierarchies H1 to H3 are centrally managed as management information by the number management table 26, thereby including the tasks T21 to T728 of the hierarchies H2 and H3 that perform divided processing. The execution order of the plurality of tasks T1 to T728 can be diagnosed at the same processing level without being separated by the hierarchies H1 to H3.

  Further, by setting the number management table 26 by firmware at the time of initialization of the microcomputer 10, it is possible to easily make a diagnosis corresponding to the firmware whose task execution order has been changed.

  Further, the execution order diagnosis circuit 2 waits for the diagnosis by the execution order diagnosis circuit 2 by completing the diagnosis within the cycle in which the microprocessor 1 writes the task code to the execution order diagnosis circuit 2. Time to be in the state can be minimized.

  In addition, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Microprocessor, 2 ... Execution order diagnostic circuit, 3 ... Firmware memory | storage part, 4 ... Work memory, 5 ... Memory mapped I / O, 6 ... External circuit, 10 ... Microcomputer, 21 ... Address decoding circuit, 22 ... R / W control circuit, 23 ... timing circuit, 24 ... current number register, 25 ... previous number register, 26 ... number management table, 27 ... diagnostic circuit, 28 ... comparison circuit.

Claims (8)

A diagnostic device for diagnosing the execution order of a plurality of tasks including tasks of a hierarchy that performs divided processing,
First task code storage means for storing a task code indicating a task to be diagnosed;
Second task code storage means for storing a task code for diagnosing the task to be diagnosed;
Final task code storage means for storing a final task code indicating a task to be executed last for each hierarchy;
Based on the task code stored in the second task code storage means, a diagnosis is made as to whether or not the task code indicating the diagnosis target task stored in the first task code storage means is valid. Diagnostic means to
Final task code determining means for determining, for each layer, whether or not the task code indicating the task to be diagnosed is the final task code stored in the final task code storage means;
A task execution order diagnosis apparatus comprising: an update unit that updates the task code stored in the second task code storage unit based on a determination result by the final task code determination unit. 2. The task execution order diagnosis apparatus according to claim 1, wherein the final task code storage unit is set with the final task code by firmware that executes the task. The first task code storage means is written with the task code indicating the task to be diagnosed by a processor that executes the task,
The task execution order diagnosis apparatus according to claim 1, wherein the diagnosis unit completes the diagnosis within a write cycle of the task code by the processor. A task code transfer means for transferring the task code stored in the first task code storage means to the second task code storage means when the diagnosis result by the diagnosis means is valid;
The update means initializes the task code transferred to the second task code storage means when the final task code is determined by the final task code determination means. The task execution order diagnosis apparatus according to claim 3. A diagnostic method for diagnosing the execution order of a plurality of tasks including a task of a hierarchy that performs divided processing by a diagnostic device,
The diagnostic device stores a task code indicating a task to be diagnosed,
The diagnostic device stores a task code for diagnosing the task to be diagnosed,
The diagnostic device stores a final task code indicating a task to be executed last for each hierarchy,
The diagnosis device diagnoses whether or not the task code indicating the stored task to be diagnosed is valid based on the stored task code for diagnosing the task to be diagnosed.
The diagnostic device determines, for each hierarchy, whether or not the task code indicating the task to be diagnosed is the final task code,
The diagnostic apparatus includes a task execution order diagnostic method, comprising: updating a task code for diagnosing the diagnosis target task based on a determination result of whether or not the final task code. 6. The task execution order diagnosis method according to claim 5, wherein the final task code is set by firmware that executes the task. The task code indicating the task to be diagnosed is written by a processor that executes the task,
6. The task execution order diagnosis method according to claim 5, wherein the task code diagnosis is completed within a write cycle of the task code by the processor. When the diagnosis result of the task code is valid, the diagnostic device stores the diagnosed task code as the task code for diagnosing the task to be diagnosed,
6. The diagnosis device according to claim 5, wherein when the diagnosed task code is determined as the final task code, the diagnostic device initializes the stored task code for diagnosing the task to be diagnosed. Task execution order diagnosis method.

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