JP2014085473A - Video processing apparatus and video processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a memory capacity required for generation of one video signal resulting from mixture of data of two video sources in a video display system capable of simultaneously displaying images of two video sources.SOLUTION: A signal separation circuit 111 separates a video signal V1 into a television video signal Vtv and synchronizing signals (a horizontal synchronizing signal HS1 and a vertical synchronizing signal VS1). Data of the television video signal Vtv is written in a 1H memory circuit 112. A horizontal synchronizing signal delay circuit 113 delays the horizontal synchronizing signal HS1, and a vertical synchronizing signal delay circuit 114 delays the vertical synchronizing signal VS1. A DSP 120 outputs a net video signal Vnet on the basis of delayed horizontal synchronizing signal HS2 and vertical synchronizing signal VS2. Data of the net video signal Vnet is written in the 1H memory circuit 112. A signal superposition circuit 115 reads out data written in the 1H memory circuit 112 and gives the data to a display device as a video signal V2.

Description

  The present invention relates to a display device that can simultaneously display images (two images) based on two video sources, a video processing device that generates the video signal, and a video processing method.

  In recent years, video display systems capable of simultaneously displaying images (two images) based on two video sources are becoming popular. In a television apparatus which is a component of such a video display system, a SoC (System on) which is an integrated circuit in which a series of required functions (systems) are integrated on a single chip as a video processing circuit for broadcasting. (Chip) 900 is provided (see FIG. 14). The SoC 900 has a built-in CPU, and the SoC can generate a net video (a video generated based on data acquired by the Internet) using the built-in CPU. However, when TV broadcast processing is performed in the SoC 900, the external memory 901 of the SoC 900 is used for processing TV images. For this reason, when TV broadcast processing is being performed in the SoC 900, it is not possible to generate a net image that can be sufficiently satisfied by the user using the built-in CPU. In view of this, a DSP (Digital Signal Processor) 920 dedicated to a net image for displaying a sufficient net image on the display device together with the TV image is often used.

  The following prior art documents are known in relation to the present invention. Japanese Patent Laid-Open No. 2009-290395 discloses a wireless communication system that aims to allow TV broadcasts and Web contents to be viewed in parallel on appropriate display devices and display areas, respectively. Japanese Patent Application Laid-Open No. 2007-300382 and Japanese Patent Application Laid-Open No. 2004-272371 also disclose an invention related to an apparatus that displays a TV image and an image other than the TV image.

JP 2009-290395 A JP 2007-300382 A JP 2004-272371 A

  As described above, in a configuration in which a DSP 920 dedicated to net images is used, television images are generated by the SoC 900, and net images are generated by the DSP 920. In this regard, in the SoC 900, a television image is generated at the timing of a synchronization signal sent from a broadcasting station, but the DSP 920 operates at a unique synchronization timing. For this reason, a timing lag occurs between the generation of the television image and the generation of the net image. Therefore, in a system that takes in data from two video sources and provides one video signal to a timing controller (referred to as “TCON”) 930 of the display device, the data from the two video sources are mixed to create one A mixing circuit (hereinafter referred to as “MIX circuit”) 910 that generates a video signal is provided with a memory (frame memory) for one frame. Then, after each data is written to the memory area allocated for each video source, the data is read from the memory at one synchronization timing. By the way, in the case of FHD (Full High Definition) television images, the memory capacity for one frame is about 62 Mbit (= 1080 (vertical) × 1920 (horizontal) × 3 (RGB) × 10 bits). When a memory having such a capacity is mounted on the MIX circuit 910, the cost becomes high. Therefore, a configuration in which the MIX circuit 910 uses an external memory 911 as shown in FIG. However, even in this configuration, the cost of the external memory itself, the circuit cost for controlling the external memory, and the like are necessary, and the cost is relatively high. Therefore, cost reduction is required.

  Therefore, the present invention is necessary for generating one video signal by mixing data of two video sources in a video display system capable of simultaneously displaying images (two images) based on two video sources. The object is to reduce the memory capacity.

According to a first aspect of the present invention, there is provided the display for providing to the display device such that an image composed of a main image and a sub-image is displayed in a display device configured to display an image based on only one display signal. A video processing device for generating a signal,
A signal separation unit that separates an input video signal into a first video signal and a synchronization signal corresponding to the main video and outputs them;
A synchronization signal delay unit that delays the synchronization signal output from the signal separation unit;
A second video signal output unit that outputs a second video signal corresponding to the sub-video based on the delayed synchronization signal;
A first storage unit for storing data of the first video signal output from the signal separation unit and data of the second video signal output from the second video signal output unit;
And a display signal output unit that reads out data stored in the first storage unit and outputs the data as the display signal.

According to a second invention, in the first invention,
The synchronization signal consists of a horizontal synchronization signal and a vertical synchronization signal,
The synchronization signal delay unit is
Using a dot clock signal to delay the horizontal synchronization signal by a period within one horizontal scanning period;
The vertical synchronization signal is delayed using a delayed horizontal synchronization signal.

According to a third invention, in the first invention,
The second video signal output unit includes:
A second storage unit for storing data of the second video signal for one frame;
Receiving the second video signal from the outside and storing it in the second storage unit;
Based on the delayed synchronization signal, the data stored in the second storage unit is read and output as the second video signal,
The sub-picture has a resolution lower than that of the main picture.

According to a fourth invention, in the first invention,
The display signal output from the display signal output unit includes a synchronization signal.

According to a fifth aspect of the present invention, there is provided the display for providing to the display device such that an image composed of a main image and a sub-image is displayed in a display device configured to display an image based on only one display signal. A video processing method for generating a signal, comprising:
A signal separation step of separating an input video signal into a first video signal and a synchronization signal corresponding to the main video and outputting them;
A synchronization signal delay step for delaying the synchronization signal output in the signal separation step;
A second video signal output step for outputting the second video signal corresponding to the sub-video based on the delayed synchronization signal;
The first video signal data output in the signal separation step and the second video signal data output in the second video signal output step are stored in a first storage unit provided in advance. A first storing step,
A display signal output step of reading out data stored in the first storage unit and outputting the data as the display signal.

  According to the first aspect of the invention, in the video display system having the display device capable of simultaneously displaying the main video and the sub video, the display signal (the main video data and the sub video data are combined into one). In a video processing apparatus that generates a combined signal), a synchronization signal is extracted from an input video signal including a first video signal corresponding to a main video by a signal separation unit, and a synchronization signal is delayed by a synchronization signal delay unit Is done. Then, the second video signal output unit outputs a second video signal corresponding to the sub-video based on the delayed synchronization signal. For this reason, it is possible to prevent a timing shift from occurring between the output of the first video signal from the signal separation unit and the output of the second video signal from the second video signal output unit. As described above, in a video display system capable of simultaneously displaying images based on two video sources (two images), the memory capacity required to generate one display signal that is a mixture of data from the two video sources is reduced. It becomes possible to make it smaller than before.

  According to the second aspect of the invention, it is possible to delay the horizontal synchronizing signal and the vertical synchronizing signal only by providing a memory having a relatively small capacity.

  According to the third aspect of the invention, a memory provided in the second video signal output unit for generating a display signal (a composite signal in which main video data and sub-video data are combined into one). Data for one frame of the sub-picture is held in the (second storage unit). On the other hand, according to the conventional configuration, data for at least one frame of the main video is held in the video processing device in order to generate a display signal. Here, according to the third aspect, since the resolution of the sub-picture is lower than that of the main picture, the necessary memory capacity is reduced as compared with the conventional art.

  According to the fourth aspect of the present invention, in the video display system having the display device capable of simultaneously displaying the main video and the sub-video and operating based on the display signal including the synchronization signal, the first video The same effect as the invention can be obtained.

  According to the fifth aspect, the same effect as that of the first aspect can be achieved in the video display method.

It is a block diagram which shows the structure of the principal part of the video display system which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the whole structure of the video display system in the said 1st Embodiment. FIG. 3 is a block diagram illustrating a configuration example of a liquid crystal display in the first embodiment. FIG. 6 is a diagram for explaining a delay of a horizontal synchronization signal in a horizontal synchronization signal delay circuit and a delay of a vertical synchronization signal in a vertical synchronization signal delay circuit in the first embodiment. In the said 1st Embodiment, it is a figure for demonstrating the delay of the horizontal synchronizing signal and vertical synchronizing signal in DSP. In the said 1st Embodiment, it is a figure for demonstrating adjustment of the delay time of a synchronizing signal. 6 is a timing chart for explaining adjustment of a delay time of a synchronization signal in the horizontal synchronization signal delay circuit and the vertical synchronization signal delay circuit in the first embodiment. It is a figure for demonstrating the effect in the said 1st Embodiment. It is a figure for demonstrating the effect in the said 1st Embodiment. It is a block diagram which shows the whole structure of the video display system which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the principal part of the video display system which concerns on the said 2nd Embodiment. It is a figure for demonstrating the effect in the said 2nd Embodiment. It is a block diagram which shows the whole structure of the video display system in a modification. It is a block diagram which shows the whole structure of the video display system in a prior art example.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

<1. First Embodiment>
<1.1 Overall configuration and operation overview>
FIG. 2 is a block diagram showing the overall configuration of the video display system according to the first embodiment of the present invention. This video display system includes a liquid crystal television 10, an STB (set top box) 20, and a remote controller 30. The video display system can wirelessly exchange data with a portable information terminal (typically, a mobile phone called a “smart phone”) 40. The STB 20 has a function as a tuner. The STB 20 receives a broadcast signal such as cable television broadcast, terrestrial television broadcast, and sanitary broadcast and can process the broadcast signal with the liquid crystal television 10 (for example, , CVBS (Composite Video, Blanking, and Sync) signal, HDMI (High-definition Multimedia Interface) signal). The remote controller 30 controls the operation of the liquid crystal television 10. The liquid crystal television 10 displays an image on the liquid crystal display 140 in accordance with an operation by the remote controller 30. The liquid crystal display 140 displays an image based on one video source, but the liquid crystal television 10 can display two images based on two video sources. In the present embodiment, a television video is displayed as a main video, and a net video is displayed as a sub video.

  The liquid crystal television 10 includes an SoC 100, an external memory 101 of the SoC 100, a MIX circuit 110, a DSP 120, a timing controller 130, and a liquid crystal display 140. The SoC 100 receives a signal (CVBS signal, HDMI signal, etc.) sent from the STB 20 and generates a television image using the external memory 101. A video signal V1 including a television video signal, a horizontal synchronization signal, a vertical synchronization signal, and a dot clock is sent from the SoC 100 to the MIX circuit 110. Typically, LVDS (Low Voltage differential signaling) is adopted as the transmission method of the video signal V1. The MIX circuit 110 delays a synchronization signal (horizontal synchronization signal and vertical synchronization signal) included in the video signal (input video signal) V1, and provides the delayed synchronization signal SS1 to the DSP 120. Then, the MIX circuit 110 receives the net video signal Vnet and the synchronization signal SS2 given from the DSP 120, and a signal (hereinafter referred to as a “composite signal”) that combines the television video signal and the net video signal into one. Is supplied to the timing controller 130. At that time, the MIX circuit 110 sets the display position / display size of the television image and the display position / display size of the net image in accordance with an instruction from the remote controller 30. As a transmission method of the video signal V2, LVDS or V-by-One signal standard is typically adopted. The DSP 120 accesses the Internet via the portable information terminal 40 in accordance with an instruction from the remote controller 30 and acquires desired data. Then, the DSP 120 generates a net image based on the synchronization signal SS1 provided from the MIX circuit 110, and provides the net image signal Vnet and the synchronization signal SS2 to the MIX circuit 110. The timing controller (TCON) 130 receives the video signal V2 supplied from the MIX circuit 110, and generates a digital video signal DV and a control signal Sctl for controlling the operation of the driving circuit of the liquid crystal display 140. Then, the timing controller 130 gives the digital video signal DV and the control signal Sctl to the liquid crystal display 140. A detailed description of the operation of the MIX circuit 110 and the operation of the DSP 120 will be given later.

  FIG. 3 is a block diagram illustrating a configuration example of the liquid crystal display 140. The liquid crystal display 140 includes a display unit 141, a source driver (video signal line driving circuit) 142, and a gate driver (scanning signal line driving circuit) 143. In the liquid crystal display 140, as a control signal Sctl, a source start pulse signal SSP, a source clock signal SCK, and a latch strobe signal LS for controlling the operation of the source driver 142, and an operation of the gate driver 143 are controlled. A gate start pulse signal GSP and a gate clock signal GCK are supplied.

  3, the display unit 141 includes a plurality of source bus lines (video signal lines) SL and a plurality of gate bus lines (scanning signal lines) GL. A pixel forming portion for forming a pixel is provided corresponding to each intersection of the source bus line SL and the gate bus line GL. In other words, the display unit 141 includes a plurality of pixel formation units. The plurality of pixel forming portions are arranged in a matrix to form a pixel array. In each pixel forming portion, a TFT 80 which is a switching element having a gate terminal connected to a gate bus line GL passing through a corresponding intersection and a source terminal connected to a source bus line SL passing through the intersection, and the TFT 80 A liquid crystal capacitor formed by the pixel electrode 81 connected to the drain terminal, the common electrode 84 and the auxiliary capacitance electrode 85 commonly provided in the plurality of pixel formation portions, and the pixel electrode 81 and the common electrode 84. 82, and an auxiliary capacitance 83 formed by the pixel electrode 81 and the auxiliary capacitance electrode 85. The liquid crystal capacitor 82 and the auxiliary capacitor 83 constitute a pixel capacitor. Note that only the components corresponding to one pixel formation portion are shown in the display portion 141 in FIG.

  The source driver 142 receives the digital video signal DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS sent from the timing controller 130, and applies a driving video signal to each source bus line SL. At this time, the source driver 142 sequentially holds the digital video signal DV indicating the voltage to be applied to each source bus line SL at the timing when the pulse of the source clock signal SCK is generated. The held digital video signal DV is converted into an analog voltage at the timing when the pulse of the latch strobe signal LS is generated. The converted analog voltage is simultaneously applied to all the source bus lines SL as a driving video signal. Based on the gate start pulse signal GSP and the gate clock signal GCK sent from the timing controller 130, the gate driver 143 repeats application of the active scanning signal to each gate bus line GL with a period of one vertical scanning period.

  As described above, the driving video signal is applied to each source bus line SL, and the scanning signal is applied to each gate bus line GL, whereby an image based on the digital video signal DV is displayed on the display unit 141. .

<1.2 Configuration of main parts>
FIG. 1 is a block diagram showing a configuration of a main part of the video display system according to the present embodiment. 1 is used to display a video composed of a main video (“TV video” in the present embodiment) and a sub-video (“net video” in the present embodiment). A video processing device that generates a display signal (“video signal V2” in the present embodiment) to be supplied to the device (“liquid crystal display 140” in the present embodiment) is realized.

  As shown in FIG. 1, the MIX circuit 110 includes a signal separation circuit 111, a 1H memory circuit 112, a horizontal synchronization signal delay circuit 113, a vertical synchronization signal delay circuit 114, and a signal superimposing circuit 115. The signal separation circuit 111 receives the video signal V1 and separates it into a television video signal Vtv and a synchronization signal (horizontal synchronization signal HS1 and vertical synchronization signal VS1). Then, the signal separation circuit 111 writes data based on the television video signal Vtv into the television video memory area of the 1H memory circuit 112, supplies the horizontal synchronization signal HS1 to the horizontal synchronization signal delay circuit 113, and applies the vertical synchronization signal VS1 to the vertical. The signal is supplied to the synchronization signal delay circuit 114.

  The horizontal synchronization signal delay circuit 113 delays the horizontal synchronization signal HS1 provided from the signal separation circuit 111 using the dot clock CLK. The delayed horizontal synchronizing signal is represented by reference symbol HS2. The delay time is a time within one horizontal scanning period. More specifically, the delay time is adjusted so that data based on the net video signal Vnet generated by the DSP 120 is written to the 1H memory circuit 112 at a suitable timing. In the example shown in FIG. 4, the horizontal synchronization signal HS2 is delayed by a time t1 with respect to the horizontal synchronization signal HS1. The delayed horizontal synchronization signal HS2 is applied to the vertical synchronization signal delay circuit 114 and the DSP 120.

  The vertical synchronization signal delay circuit 114 delays the vertical synchronization signal VS1 provided from the signal separation circuit 111 using the horizontal synchronization signal HS2. Note that the delayed vertical synchronizing signal is denoted by reference numeral VS2. The delay time is adjusted such that a vertical synchronization signal VS3 (vertical synchronization signal output from the DSP 120), which will be described later, is delayed from the vertical synchronization signal VS1 by a time within one horizontal scanning period. A detailed description thereof will be described later. In the example shown in FIG. 4, the vertical synchronization signal VS2 is delayed by a time t2 with respect to the vertical synchronization signal VS1. The delayed vertical synchronization signal VS2 is given to the DSP 120.

  Based on the horizontal synchronization signal HS2 and the vertical synchronization signal VS2, the DSP 120 generates a net image based on data (data acquired by the portable information terminal 40 via the Internet) Dnet sent from the portable information terminal 40. At that time, according to the performance of the DSP 120 and the contents of the program executed by the DSP 120, for example, as shown in FIG. 5, a delay occurs in the synchronization signals (the horizontal synchronization signal HS2 and the vertical synchronization signal VS2). The delayed horizontal synchronizing signal and vertical synchronizing signal are represented by symbols HS3 and VS3, respectively. The DSP 120 writes data based on the net video signal Vnet to the net video memory area of the 1H memory circuit 112 and supplies the data to the horizontal synchronizing signal HS3 and the vertical synchronizing signal VS3 signal superimposing circuit 115. The frame frequency and the number of vertical lines in the DSP 120 are set to be equal to the frame frequency and the number of vertical lines in the SoC 100.

  The signal superimposing circuit 115 receives the horizontal synchronizing signal HS1 and the vertical synchronizing signal VS1 sent from the signal separating circuit 111 and the horizontal synchronizing signal HS3 and the vertical synchronizing signal VS3 sent from the DSP 120, and sends the timing control signal St to the 1H memory circuit 112. As a result, each pixel data constituting a composite video (a video in which a television video and a net video are represented by one frame) is read from the 1H memory circuit 112. Then, the signal superimposing circuit 115 provides the timing controller 130 with the video signal V2 including the synthesized signal and the synchronization signal based on the data read from the 1H memory circuit 112.

  The synchronization signal SS1 described above is composed of a horizontal synchronization signal HS2 and a vertical synchronization signal VS2, and the synchronization signal SS2 described above is composed of a horizontal synchronization signal HS3 and a vertical synchronization signal VS3 (see FIG. 2). In this embodiment, a signal separation unit is realized by the signal separation circuit 111, a synchronization signal delay unit is realized by the horizontal synchronization signal delay circuit 113 and the vertical synchronization signal delay circuit 114, and the second video signal is obtained by the DSP 120. An output unit is realized, a first storage unit is realized by the 1H memory circuit 112, a display signal output unit is realized by the signal superimposing circuit 115, a first video signal is realized by the TV video signal Vtv, and a net video A second video signal is realized by the signal Vnet.

  By the way, in the case of a general HDTV (high definition television), the number of pixels is “1080 (vertical) × 1920 (horizontal)”. Including the period for synchronization, one horizontal scanning period corresponds to 2200 dots, and one vertical scanning period corresponds to 1125 × 2200 dots. Here, the horizontal synchronizing signal is binary, and the delay time of the horizontal synchronizing signal in the horizontal synchronizing signal delay circuit 113 is set to a time within one horizontal scanning period as described above. Therefore, the capacity of the memory (horizontal synchronization signal delay circuit 113) necessary for delaying the horizontal synchronization signal HS1 using the dot clock CLK is 2200 bits at the maximum. Further, if a configuration in which the vertical synchronization signal VS1 is delayed by using the dot clock CLK is employed, the vertical synchronization signal is binary, and therefore a memory (vertical synchronization signal delay circuit 114) required to delay the vertical synchronization signal VS1. ) Is 1125 × 2200 bits. In contrast, in the present embodiment, a configuration is employed in which the vertical synchronization signal VS1 is delayed using the horizontal synchronization signal HS2. Therefore, the capacity of the memory (vertical synchronization signal delay circuit 114) necessary for delaying the vertical synchronization signal VS1 is 1125 bits at the maximum.

<1.3 Adjustment of delay time of synchronization signal>
Next, how the delay time of the synchronization signal is adjusted in the present embodiment will be described. Here, for convenience of explanation, regarding the display unit 141 of the liquid crystal display 140, “there are 16 pixels in the horizontal direction, the pixels from the first pixel to the twelfth pixel are TV video pixels, and the thirteenth pixel. To the 16th pixel are assumed to be pixels for the net image ”(see FIG. 6).

  FIG. 7 is a timing chart for explaining the adjustment of the delay time of the synchronization signal in the horizontal synchronization signal delay circuit 113 and the vertical synchronization signal delay circuit 114. In FIG. 7, HS1 represents the waveform of the horizontal synchronization signal output from the signal separation circuit 111, VS1 represents the waveform of the vertical synchronization signal output from the signal separation circuit 111, and Vtv represents each pixel based on the TV video signal. The timing at which data is written to the 1H memory circuit 112 is represented, HS3 represents the waveform of the horizontal synchronizing signal output from the DSP 120, VS3 represents the waveform of the vertical synchronizing signal output from the DSP 120, and Vnet is based on the net video signal. Each pixel data represents a timing at which the DSP 120 generates, and Vmix represents a timing at which each pixel data of the composite video is read from the 1H memory circuit 112.

  In order to normally display the TV image and the net image on the display unit 141 based on the combined signal obtained by combining the TV image signal Vtv and the net image signal Vnet, as shown by Vmix in FIG. The TV video data of the line and the net video data of each line must be read from the 1H memory circuit 112 as a series of video data. In order to realize this, in the example shown in FIG. 7, the data of the first pixel of the net image is written to the 1H memory circuit 112 until the data of the thirteenth pixel of the composite image is read from the 1H memory circuit 112. Must be finished. In addition, before the 16th pixel data of the composite video is read from the 1H memory circuit 112, the writing of the fourth pixel data of the net video to the 1H memory circuit 112 must be completed. Here, if the difference between the synchronization timing based on the vertical synchronization signal HS1 and the synchronization timing based on the vertical synchronization signal HS3 is within one horizontal scanning period, the timing at which the TV image data can be written to the 1H memory circuit 112 and the net image The difference from the timing at which data can be written to the 1H memory circuit 112 is within one horizontal scanning period. Then, as indicated by Vmix in FIG. 7, it is possible to read out the television video data and the net video data from the 1H memory circuit 112 as a series of video data, and give it to the timing controller 130. In the present embodiment, the horizontal synchronization signal delay circuit 113 performs the horizontal synchronization signal HS1 to the horizontal synchronization signal HS1 so that the television image data and the net image data can be read from the 1H memory circuit 112 as a series of image data. The delay time to the synchronization signal HS2 is adjusted, and the delay time from the vertical synchronization signal VS1 to the vertical synchronization signal VS2 is adjusted in the vertical synchronization signal delay circuit 114.

  By the way, as described above, the magnitude of the delay time from the horizontal synchronizing signal HS2 to the horizontal synchronizing signal HS3 and the magnitude of the delay time from the vertical synchronizing signal VS2 to the vertical synchronizing signal VS3 are executed by the performance of the DSP 120 and the DSP 120. Depends on program content. Therefore, adjustment of the delay time in the horizontal synchronizing signal delay circuit 113 and the vertical synchronizing signal delay circuit 114 is performed for each model.

  For example, in a certain model, it is assumed that the delay time (the delay time from the vertical synchronization signal VS2 to the vertical synchronization signal VS3) in the DSP 120 for the vertical synchronization signal is 10H (10 horizontal scanning periods). At this time, if one vertical scanning period is 1125H, when the vertical synchronization signal VS2 is delayed by (1125-10) H with respect to the vertical synchronization signal VS1, the synchronization timing by the vertical synchronization signal VS1 and the synchronization timing by the vertical synchronization signal VS3 Is within one horizontal scanning period. That is, when one vertical scanning period is mH (m is a natural number) and the delay time of the vertical synchronization signal in the DSP 120 is nH (n is a natural number), the vertical synchronization signal VS2 is Adjustment is performed so as to be delayed by (mn) H with respect to the vertical synchronization signal VS1.

  In the horizontal synchronizing signal delay circuit 113, data based on the net video signal Vnet is obtained at a desired timing in consideration of a delay time (delay time from the horizontal synchronizing signal HS2 to the horizontal synchronizing signal HS3) in the DSP 120 for the horizontal synchronizing signal. The delay time from the horizontal synchronization signal HS1 to the horizontal synchronization signal HS2 is adjusted so as to be written in the 1H memory circuit 112.

  As described above, the horizontal synchronization signal delay circuit 113 adjusts the delay time from the horizontal synchronization signal HS1 to the horizontal synchronization signal HS2, and the vertical synchronization signal delay circuit 114 delays from the vertical synchronization signal VS1 to the vertical synchronization signal VS2. Time adjustments are made.

<1.4 Effect>
According to the present embodiment, in the liquid crystal television 10 capable of simultaneously displaying a television image and a net image, the MIX circuit 110 that generates a composite signal of the television image signal Vtv and the net image signal Vnet has the television image. Processing for extracting a synchronization signal (horizontal synchronization signal HS1 and vertical synchronization signal VS1) from an input video signal including the signal Vtv and delaying the synchronization signal by a delay circuit (horizontal synchronization signal delay circuit 113 and vertical synchronization signal delay circuit 114) Done. Then, a net video signal Vnet is generated based on the delayed synchronization signals (horizontal synchronization signal HS2 and vertical synchronization signal VS2). At this time, the synchronization timing shift between the television video signal Vtv and the net video signal Vnet is within one horizontal scanning period. For this reason, it is possible to generate a composite signal in which the TV video signal Vtv and the net video signal Vnet are combined into one video signal by using only the line memory (1H memory circuit 112) without using a frame memory. On the other hand, according to the conventional configuration, it is necessary to mount at least a memory having a capacity capable of holding TV video data in the MIX circuit. As described above, according to the present embodiment, in the liquid crystal television 10 capable of simultaneously displaying TV images and net images, it is possible to reduce the memory capacity required to be installed in the MIX circuit as compared with the conventional case. It becomes. As a result, cost is reduced.

  Further, for example, when an SD (Standard Definition) broadcast video with an aspect ratio of “4: 3” is enlarged and displayed on an HDTV display device with an aspect ratio of “16: 9”, the aspect ratio of the video display portion Becomes “12: 9”. At this time, as shown in FIG. 8, black display portions are generated in the left and right areas of the display unit. Therefore, as shown in FIG. 9, if the configuration is such that the net image can be displayed in the area of the aspect ratio “4: 9”, the net image can be displayed without hindering the display of the TV image. In the present embodiment, it is possible to realize a video display system including a liquid crystal display having such a configuration with a smaller memory capacity than in the past.

<2. Second Embodiment>
<2.1 Overall configuration and operation overview>
FIG. 10 is a block diagram showing the overall configuration of a video display system according to the second embodiment of the present invention. Also in the present embodiment, the liquid crystal display 140 displays an image based on one video source, but the liquid crystal television 10 can simultaneously display two images based on two video sources, as a main video. TV image is displayed, and net image is displayed as sub-image. Note that the resolution of the sub-picture is set lower than that of the main picture.

  Only differences from the first embodiment (see FIG. 2) will be described below. In the present embodiment, unlike the first embodiment, the SoC 100 is provided outside the liquid crystal television 10. The video signal V1 generated by the SoC 100 is sent from the TX circuit (transmission circuit) 102 in the SoC 100 to the RX circuit (reception circuit) 150 in the liquid crystal television 10. The video signal V1 is sent from the RX circuit 150 to the MIX circuit 110.

  In the present embodiment, the net information signal Vnet supplied to the MIX circuit 110 is generated by the portable information terminal 40. That is, the RX circuit 121 in the DSP 120 receives the net video signal Vnet sent from the portable information terminal 40, and the DSP 120 gives the net video signal Vnet and the synchronization signal SS2 to the MIX circuit 110. The portable information terminal 40 is controlled by the controller 50.

<2.2 Configuration of main parts>
FIG. 11 is a block diagram illustrating a configuration of a main part of the video display system according to the present embodiment. The MIX circuit 110 has the same configuration as that of the first embodiment. In the present embodiment, the DSP 120 includes an RX circuit 121, a processor 122, and a memory 123. Note that a second storage unit is realized by the memory 123.

  The RX circuit 121 receives the net video signal Vnet sent from the portable information terminal 40 and transfers it to the processor 122. The processor 122 temporarily stores data based on the net video signal Vnet received from the RX circuit 121 in the memory 123. Then, the processor 122 reads out data stored in the memory 123 based on the horizontal synchronizing signal HS2 and the vertical synchronizing signal VS2, and supplies it to the 1H memory circuit 112 as a net video signal Vnet. Data based on the net video signal Vnet is written in the net video memory area of the 1H memory circuit 112. Further, the processor 122 supplies the horizontal synchronization signal HS3 and the vertical synchronization signal VS3 to the signal superimposing circuit 115.

<2.3 Adjustment of delay time of synchronization signal>
In the present embodiment, as in the first embodiment, the horizontal synchronization signal delay circuit 113 adjusts the delay time from the horizontal synchronization signal HS1 to the horizontal synchronization signal HS2, and the vertical synchronization signal delay circuit 114 The delay time from the vertical synchronization signal VS1 to the vertical synchronization signal VS2 is adjusted.

<2.4 Effect>
FIG. 12 is a diagram showing a memory capacity necessary to hold data for one frame for each panel type. In the present embodiment, the resolution of the sub video is set lower than that of the main video. Therefore, for example, “FHD, color” television video is displayed as the main video, and “VGA, color” net video is displayed as the sub video. In this case, the memory 123 in the DSP 120 needs to store data for one frame of “VGA, color”. That is, the required capacity of the memory 123 provided in the DSP 120 is about 7.4 Mbit. By the way, according to the conventional configuration, when displaying “FHD, color” television video as the main video, it is necessary to provide the MIX circuit with a memory having a capacity of about 62 Mbit in order to hold the television video data. As described above, according to the present embodiment, in the liquid crystal television 10 capable of simultaneously displaying a TV image and a net image, the memory capacity required for generating a composite image is reduced as compared with the conventional case. It becomes possible. As a result, cost is reduced.

<3. Modification>
In the first embodiment and the second embodiment, access to the Internet from the liquid crystal television 10 is performed wirelessly. However, the present invention is not limited to this. The liquid crystal television 10 and the portable information terminal 40 may be connected to each other via a USB connection to access the Internet, or may be accessed via a LAN connection via the router 60 (see FIG. 13). .

<4. Addendum>
As the video processing apparatus and video processing method according to the present invention, the following configurations are conceivable.

(Appendix 1)
Video processing for generating the display signal to be given to the display device so that the video composed of the main video and the sub-video is displayed on the display device configured to display video based on only one display signal. A device,
A signal separation unit that separates an input video signal into a first video signal and a synchronization signal corresponding to the main video and outputs them;
A synchronization signal delay unit that delays the synchronization signal output from the signal separation unit;
A second video signal output unit that outputs a second video signal corresponding to the sub-video based on the delayed synchronization signal;
A first storage unit for storing data of the first video signal output from the signal separation unit and data of the second video signal output from the second video signal output unit;
An image processing apparatus comprising: a display signal output unit that reads out data stored in the first storage unit and outputs the data as the display signal.

  According to such a configuration, in a video display system having a display device capable of simultaneously displaying a main video and a sub video, display signals (main video data and sub video data are combined into one. In the video processing device that generates the synthesized signal), the signal separation unit extracts the synchronization signal from the input video signal including the first video signal corresponding to the main video, and the synchronization signal delay unit delays the synchronization signal. Done. Then, the second video signal output unit outputs a second video signal corresponding to the sub-video based on the delayed synchronization signal. For this reason, it is possible to prevent a timing shift from occurring between the output of the first video signal from the signal separation unit and the output of the second video signal from the second video signal output unit. As described above, in a video display system capable of simultaneously displaying images based on two video sources (two images), the memory capacity required to generate one display signal that is a mixture of data from the two video sources is reduced. It becomes possible to make it smaller than before.

(Appendix 2)
The video processing apparatus according to appendix 1, wherein the first storage unit includes a storage area that can store data for only one line in the display device.

  According to such a configuration, the capacity of the memory provided in the video processing apparatus for generating the display signal (the synthesized signal in which the main video data and the sub video data are combined into one) is conventionally increased. Is significantly reduced compared to

(Appendix 3)
The synchronization signal consists of a horizontal synchronization signal and a vertical synchronization signal,
The synchronization signal delay unit is
Using a dot clock signal to delay the horizontal synchronization signal by a period within one horizontal scanning period;
The video processing apparatus according to appendix 1, wherein the vertical synchronizing signal is delayed using a delayed horizontal synchronizing signal.

  According to such a configuration, it is possible to delay the horizontal synchronizing signal and the vertical synchronizing signal only by providing a memory having a relatively small capacity.

(Appendix 4)
The synchronizing signal delay unit is configured such that one vertical scanning period is m horizontal scanning periods (m is a natural number) and the vertical synchronizing signal is delayed by n horizontal scanning periods in the second video signal output unit (n is a natural number). The video processing apparatus according to appendix 3, wherein the vertical synchronization signal output from the signal separation unit is delayed by (mn) horizontal scanning periods.

  According to such a configuration, the synchronization signal delay unit delays the vertical synchronization signal in accordance with the delay time of the vertical synchronization signal in the second video signal output unit. Accordingly, the synchronization timing shift between the output of the first video signal from the signal separation unit and the output of the second video signal from the second video signal output unit is within one horizontal scanning period. For this reason, display signals (main video data and sub-video data are combined into one by simply using line memory (memory for one line) without using frame memory (memory for one frame). (Combined signal) can be generated. As described above, in a video display system capable of simultaneously displaying images based on two video sources (two images), the memory capacity required to generate one display signal that is a mixture of data from the two video sources. It is greatly reduced than before.

(Appendix 5)
The second video signal output unit includes:
A second storage unit for storing data of the second video signal for one frame;
Receiving the second video signal from the outside and storing it in the second storage unit;
Based on the delayed synchronization signal, the data stored in the second storage unit is read and output as the second video signal,
The video processing apparatus according to appendix 1, wherein a resolution of the sub-video is lower than a resolution of the main video.

  According to such a configuration, in order to generate a display signal (a composite signal in which main video data and sub-video data are combined into one), a memory ( Data for one frame of the sub-picture is held in the second storage unit). On the other hand, according to the conventional configuration, data for at least one frame of the main video is held in the video processing device in order to generate a display signal. Here, according to the third aspect, since the resolution of the sub-picture is lower than that of the main picture, the necessary memory capacity is reduced as compared with the conventional art.

(Appendix 6)
The video processing apparatus according to appendix 1, wherein the display signal output from the display signal output unit includes a synchronization signal.

  According to such a configuration, in the video display system having the display device that can display the main video and the sub video at the same time and operates based on the display signal including the synchronization signal, The same effect as the configuration can be obtained.

(Appendix 7)
The main video is a TV broadcast video,
The video processing apparatus according to appendix 1, wherein the sub-video is a video based on data acquired via the Internet.

  According to such a configuration, in the video display system having the display device capable of simultaneously displaying the TV video and the net video (video generated based on data acquired through the Internet), the video display system according to appendix 1 The effect obtained by the configuration is particularly obtained.

(Appendix 8)
Video processing for generating the display signal to be given to the display device so that the video composed of the main video and the sub-video is displayed on the display device configured to display video based on only one display signal. A method,
A signal separation step of separating an input video signal into a first video signal and a synchronization signal corresponding to the main video and outputting them;
A synchronization signal delay step for delaying the synchronization signal output in the signal separation step;
A second video signal output step for outputting the second video signal corresponding to the sub-video based on the delayed synchronization signal;
The first video signal data output in the signal separation step and the second video signal data output in the second video signal output step are stored in a first storage unit provided in advance. A first storing step,
A video signal processing method comprising: a display signal output step of reading out data stored in the first storage unit and outputting the data as the display signal.

  According to such a configuration, the same effect as the configuration described in Appendix 1 can be achieved in the video display method.

10 ... LCD television 20 ... STB (Set Top Box)
30 ... Remote control 40 ... Portable information terminal 100 ... SoC (System on Chip)
DESCRIPTION OF SYMBOLS 110 ... MIX circuit 111 ... Signal separation circuit 112 ... 1H memory circuit 113 ... Horizontal synchronizing signal delay circuit 114 ... Vertical synchronizing signal delay circuit 115 ... Signal superimposing circuit 120 ... DSP (Digital Signal Processor)
130 ... Timing controller 140 ... Liquid crystal display HS1, HS2, HS3 ... Horizontal sync signal VS1, VS2, VS3 ... Vertical sync signal V1, V2 ... Video signal Vtv ... TV video signal Vnet ... Net video signal

Claims (5)

Video processing for generating the display signal to be given to the display device so that the video composed of the main video and the sub-video is displayed on the display device configured to display video based on only one display signal. A device,
A signal separation unit that separates an input video signal into a first video signal and a synchronization signal corresponding to the main video and outputs them;
A synchronization signal delay unit that delays the synchronization signal output from the signal separation unit;
A second video signal output unit that outputs a second video signal corresponding to the sub-video based on the delayed synchronization signal;
A first storage unit for storing data of the first video signal output from the signal separation unit and data of the second video signal output from the second video signal output unit;
An image processing apparatus comprising: a display signal output unit that reads out data stored in the first storage unit and outputs the data as the display signal. The synchronization signal consists of a horizontal synchronization signal and a vertical synchronization signal,
The synchronization signal delay unit is
Using a dot clock signal to delay the horizontal synchronization signal by a period within one horizontal scanning period;
The video processing apparatus according to claim 1, wherein the vertical synchronization signal is delayed using a delayed horizontal synchronization signal. The second video signal output unit includes:
A second storage unit for storing data of the second video signal for one frame;
Receiving the second video signal from the outside and storing it in the second storage unit;
Based on the delayed synchronization signal, the data stored in the second storage unit is read and output as the second video signal,
The video processing apparatus according to claim 1, wherein a resolution of the sub-video is lower than a resolution of the main video.   The video processing apparatus according to claim 1, wherein the display signal output from the display signal output unit includes a synchronization signal. Video processing for generating the display signal to be given to the display device so that the video composed of the main video and the sub-video is displayed on the display device configured to display video based on only one display signal. A method,
A signal separation step of separating an input video signal into a first video signal and a synchronization signal corresponding to the main video and outputting them;
A synchronization signal delay step for delaying the synchronization signal output in the signal separation step;
A second video signal output step for outputting the second video signal corresponding to the sub-video based on the delayed synchronization signal;
The first video signal data output in the signal separation step and the second video signal data output in the second video signal output step are stored in a first storage unit provided in advance. A first storing step,
A video signal processing method comprising: a display signal output step of reading out data stored in the first storage unit and outputting the data as the display signal.

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