JP2014081865A - Cache memory, cache memory fault control method, and information processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache memory of which the degradation can be quickly and appropriately determined by the execution of diagnosis based on a detected error.SOLUTION: A cache memory 30 comprising an address array 33 and a data array 34 includes at least: an error detection unit 35 which detects and corrects an error of data read from a way of an entry in the data array 34; and an error diagnosis control unit 36 which is started in response to detection of an error in the error detection unit 35 to control the execution of diagnosis for the way of the entry where the error has been detected. When a diagnosis result of the error diagnosis control unit 36 shows that the error is determined to be caused by an intermittent fault, the way of the entry where the error has been detected is allowed to be continuously used. When the error is determined to be caused by a fixed fault, the way of the entry where the error has been detected is degraded and is set to an unavailable state.

Description

  The present invention relates to a cache memory, a cache memory failure control method, and an information processing system, and more particularly, to a cache memory having a failure diagnosis control function in a cache memory provided in the information processing system, a cache memory failure control method, and an information processing system. Therefore, the present invention can be suitably applied to an information processing system including a multi-way set associative cache memory.

  An error in a cache memory provided in the information processing system includes an intermittent failure due to a soft error or the like and a fixed failure due to a hardware error or the like. In the case of a cache memory consisting of a multi-way set associative address array and data array, even if some of the ways of the cache memory become unusable, the system operation will continue on the remaining ways. Therefore, it is possible to continue using the cache memory by degrading the way in which the failure has occurred and setting it to a state where it is not used.

  However, there is a risk that degradation will cause performance degradation. In other words, as described above, since there is an intermittent failure due to a soft error in the cache memory failure, a cache that can continue to use the way is normally used like a way in which an intermittent failure has occurred. Regarding the memory, it is undesirable in terms of performance to immediately degrade the way by detecting an error once. On the other hand, if you continue to use the cache memory even if a fixed failure occurs, the control by accessing the fixed failure way increases, which may lead to a decrease in performance and reliability. .

  As prior arts for preventing degradation due to intermittent failure, there are techniques described in Japanese Patent Laid-Open No. 04-124747 “Cache Memory” of Patent Document 1 and Japanese Patent Laid-Open No. 03-250345 “Cache Memory Control Circuit” of Patent Document 2. As a prior art for setting a degradation by diagnosis, there is a technique described in Japanese Patent No. 3199378 “Integrated Memory, Management Method and Information System Obtained from the Method” of Patent Document 3.

  The technique described in Patent Document 1 treats the first error as a miss hit and rewrites it in order to save performance degradation due to excessive degradation due to intermittent failure, and an error occurs continuously for the second time. Sometimes it is a technique to perform degradation, but the second error is unknown until the normal transaction reads the cache memory, and it is quick to determine whether an intermittent failure or a fixed failure has occurred. Cannot be judged.

  The technique described in Patent Document 2 is a technique in which the number of errors is held and degradation is performed when the number of errors defined in advance as a system is reached in order to save performance degradation due to excessive degradation due to intermittent failures. However, as in the case of Patent Document 1, the error determination is not known until the next normal transaction for reading the cache memory occurs.

  The technique described in Patent Document 3 is a technique of detecting and degrading an unusable part by performing a diagnosis, but the diagnosis is performed through a processor and due to an error during operation. Since the diagnosis is not performed, there is a possibility that performance is deteriorated and an error that occurs during operation cannot be accurately detected.

JP 04-124747 A (page 2-3) Japanese Patent Laid-Open No. 03-250345 (page 2-3) Japanese Patent No. 3199378 (pages 3-6)

  In an information processing system equipped with a multi-way set associative cache memory, as described above, when an error is detected in the cache memory data, the way of the entry in which the error is detected is degraded and operated. Can continue. In this case, if the error that occurred is due to an intermittent failure, it is important to prevent unnecessary performance degradation due to degradation, and to ensure that errors due to fixed failures are detected and degraded. is important.

  However, as described above, in the conventional techniques as described in Patent Document 1 and Patent Document 2 for preventing degradation due to intermittent failure, it takes time to determine whether the error is due to intermittent failure. In the conventional technique as described in Patent Document 3 for detecting a fixed fault with certainty, it is necessary to devote the capacity of the processor for diagnosis, and it has actually occurred. Since the diagnosis is not based on an error, there is a possibility that it may not be a detection of an effective fixed fault.

(Object of the present invention)
The present invention has been made in view of such circumstances, and a cache memory, a cache memory failure control method, and information capable of quickly and appropriately determining a degradation by immediate execution of a diagnosis based on a detected error. Its purpose is to provide a processing system.

  In order to solve the above-described problems, the cache memory, the cache memory failure control method, and the information processing system according to the present invention mainly adopt the following characteristic configuration.

  (1) A cache memory according to the present invention detects an error in data read from a way of any entry of the data array in a cache memory composed of a multiple way set associative address array and a data array. An error detection unit that performs and corrects, and an error diagnosis control unit that is activated when an error is detected by the error detection unit and controls the execution of the diagnosis of the way of the entry in which the error is detected When the detected error is determined to be an error due to an intermittent failure as a result of diagnosis by the error diagnosis control unit, the way of the entry in which the error is detected can be used continuously and detected. If the error is determined to be an error due to a fixed fault, the error is detected. By degrading the way of the entry, and sets the unusable.

  (2) A cache memory failure control method according to the present invention is a cache memory failure control method for controlling a failure of a cache memory composed of a multi-way set associative address array and a data array. An error detection step for detecting and correcting an error in data read from any entry way, and an entry way that is activated when an error is detected by the error detection step and that is detected by the error detection step An error diagnosis control step for controlling execution of diagnosis, and when the detected error is determined to be an error due to an intermittent failure as a diagnosis result of the error diagnosis control step, the entry in which the error is detected Allows you to continue using your way And, if the detected error is judged as an error by the fixed fault, by degrading the way of the entry in which the error is detected, and sets the unusable.

  (3) An information processing system according to the present invention is an information processing system including at least a cache memory for absorbing a performance difference between a processor and a memory, wherein the cache memory is at least from the cache memory according to (1). It is characterized by becoming.

  According to the cache memory, the cache memory failure control method, and the information processing system of the present invention, the following effects can be obtained.

  In other words, when a cache memory error is detected, an error diagnosis control unit (or error diagnosis control step) is provided as a function for immediately diagnosing the part where the error has occurred (that is, the entry way), so Because it enables quick and accurate judgment, cache memory performance degradation due to unnecessary degradation at the time of intermittent failure is minimized, while the fixed failure occurrence site is used carelessly at the time of fixed failure It is possible to prevent such a situation, and thus the reliability of the cache memory can be maintained.

It is a system configuration figure showing an example of an internal configuration of an information processing system by the present invention. FIG. 2 is an explanatory diagram for explaining a configuration example of an address array and a data array when the address array and the data array of the information processing system shown in FIG. 1 are configured as a multi-way set associative cache memory. 3 is a flowchart illustrating an example of the operation of the information processing system illustrated in FIGS. 1 and 2. 3 is a flowchart for explaining an example of the operation of the information processing system shown in FIGS. 1 and 2 different from FIG. 5 is a flowchart for explaining an example different from FIGS. 3 and 4 of the operation of the information processing system shown in FIGS. 1 and 2. 3 is a flowchart for supplementary explanation of the operation of the information processing system shown in FIGS. 1 and 2.

  Preferred embodiments of a cache memory, a cache memory failure control method, and an information processing system according to the present invention will be described below with reference to the accompanying drawings. In the following description, the cache memory, the cache memory failure control method, and the information processing system according to the present invention will be described. However, in some cases, the cache memory failure control method is executed as a cache memory failure control program that can be executed by a computer. Needless to say, the cache memory failure control program may be recorded on a computer-readable recording medium.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, an outline of the features of the present invention will be described first. In the cache memory, the cache memory failure control method, and the information processing system according to the present invention, the target information processing system includes a cache memory including a plurality of ways of associative address arrays and data arrays. It is.

  In the cache memory configuration like this, when an error occurs in the cache memory data during system operation, by adding a function to immediately diagnose the way of the cache memory entry where the error occurred, Determine whether the error that occurred is due to an intermittent failure or a fixed failure.If the error is due to an intermittent failure, allow continuous use of the way of the entry in which the error has occurred. The main feature is that the way is degraded and set to an unusable state. Therefore, as a countermeasure against a cache memory error, it is possible to quickly determine whether it is due to an intermittent failure or a fixed failure, and to prevent unnecessary degradation, thereby suppressing performance degradation. In addition, inadvertent continuous use of the fixed failure site can be prevented, and the reliability of the cache memory can be maintained.

(Configuration example of embodiment)
Next, configuration examples of embodiments of a cache memory failure control circuit, a cache memory failure control method, and an information processing system according to the present invention will be described. First, a configuration example of an information processing system according to the present invention will be described with reference to the system configuration diagram of FIG. FIG. 1 is a system configuration diagram showing an example of an internal configuration of an information processing system according to the present invention. The configuration of an information processing system including a cache memory including a multi-way set associative address array and a data array An example is shown.

  The information processing system 11 illustrated in FIG. 1 includes a processor 21, a memory 22, a transaction control unit 25, and a cache memory 30. The cache memory 30 includes at least a cache control unit 32, an address array 33, a data array 34, an error detection unit 35, and an error diagnosis control unit 36.

  The transaction control unit 25 performs transmission / reception of transactions with the processor 21 and the memory 22 and transmission / reception of transactions with the cache control unit 32. The address array 33 and the data array 34 are multi-way set associative cache memories. The cache control unit 32 is a part that controls the address array 33 and the data array 34. The error detector 35 is a part that detects and corrects errors in data read from the data array 34. Further, the error diagnosis control unit 36 is a part provided as one of the additional functions characterizing the present invention. Upon receiving an error notification from the error detection part 35, the error diagnosis control part 36 is activated immediately and a part where an error is detected (that is, an entry). Control of the diagnosis of the portion of the detected error is performed based on the diagnosis result based on the diagnosis result. In this part, a setting instruction for degradation is given to the cache control unit 32.

  Further, as will be described later with reference to FIG. 2, the address array 33 indicates that the in-diagnosis flag indicating that the way of the entry in which the error is detected and the entry way are invalid data. A failure flag is provided. The cache control unit 32 checks the in-diagnosis flag of the address array 33. When the address specified by the normal transaction matches the address of the way of the entry under diagnosis, the cache control unit 32 gives priority to the execution of the diagnosis. It has a function of controlling the data being diagnosed not to be used for the normal transaction by waiting for the processing of the normal transaction. When the cache control unit 32 receives a diagnosis instruction from the error diagnosis control unit 36, the cache control unit 32 has a function of performing cache access control to the address array 33 and the data array 34 in accordance with the diagnosis instruction in preference to the normal transaction. doing. When the error detection unit 35 detects an error in the data read from the data array 34 by the functions of the error diagnosis control unit 36 and the cache control unit 32, the diagnosis of the entry in which the error is detected to the way is performed. Can be executed by interrupting the normal transaction, and the degradation determination can be performed promptly and appropriately.

  FIG. 2 shows a configuration example of the address array 33 and the data array 34 when the address array 33 and the data array 34 of the information processing system 11 shown in FIG. 1 are configured as a multi-way set associative cache memory. FIG. 2A illustrates an address array 33 including a plurality of ways, and FIG. 2B illustrates a data array 34 including a plurality of ways.

  As shown in FIG. 2A, the address array 33 is composed of a plurality of ways for holding information for each cache line size, and a set address 42 which is a part of an address (for example, a lower address) is stored. , Used as an entry in the address array 33. Each entry is composed of a key address 41, a status 43, and a flag 44. Here, the key address 41 is a remaining address (for example, a higher-order address) excluding the set address 42 among the addresses.

  The status 43 indicates the caching status of the address (entry way) indicated by the set address 42 and the key address 41. In the present embodiment, the status 43 includes, for example, three states in the MSI (Modified, Shared, Invalid) cache protocol used in the write-back method, that is, 'Invalid' (the cache memory entry way is not used). State), 'Shared' (state where the same data exists in the cache memory entry way and the corresponding address in the memory 22), 'Modified' (state where data exists only in the cache memory entry way) In addition to the above three states, a state called “Degrade” indicating that the entry way is in an unusable degraded state is added to hold any of the four states in total. In the degraded state, one bit may be additionally arranged as a flag separately from the status 43, but in the present embodiment, it is added to the status 43 for convenience of explanation.

  The flag 44 is one of the functions added in the present embodiment, and the diagnosis flag 51 indicating that the way of the corresponding entry is being diagnosed and the data of the address registered in the way of the corresponding entry are displayed. There are two types of flags, a failure flag 52 indicating fraud. The in-diagnosis flag 51 is used to wait for a normal transaction so that the normal transaction does not use data at an address in a state under diagnosis. On the other hand, the failure flag 52 indicates that the data at the same address is invalid and there is no data in the memory 22, and is a flag for coherency control.

  In addition, the data array 34 shown in FIG. 2B has a one-to-one relationship in which the entries and ways have the same configuration as the address array 33, and each entry is composed of cache data 45. . The cache data 45 is data of the cache line size and is accompanied by error detection and correction bits such as ECC (Error Correcting Code).

(Description of operation of embodiment)
Next, an example of the operation of the information processing system 11 shown in FIGS. 1 and 2 will be described using the flowcharts of FIGS. 3, 4, and 5. FIG. 3 is a flowchart for explaining an example of the operation of the information processing system 11 shown in FIGS. 1 and 2. When the cache data 45 of the data array 34 is read from the processor 21, the error detection unit 35 does not correct the error. An example of a diagnostic control operation after detecting a possible error is described. FIG. 4 is a flowchart for explaining an example of the operation of the information processing system 11 shown in FIGS. 1 and 2 that is different from that in FIG. 3. After the diagnosis in the flowchart of FIG. An example of the operation when referring to the way of the entry that has been described will be described. FIG. 5 is a flowchart for explaining an example of the operation of the information processing system 11 shown in FIGS. 1 and 2 different from those in FIGS. 3 and 4. In the state under diagnosis in the flowchart of FIG. Describes an example of the operation when referring to the way of the entry to be diagnosed.

  First, an example of an operation when an uncorrectable error is detected and diagnosis is performed will be described using the flowchart of FIG. When an error that cannot be corrected is detected by the error detection unit 35 when data in the data array 34 is read in response to a normal transaction request from the processor 21, the fact is reported to the error diagnosis control unit 36. When the error diagnosis control unit 36 receives the error detection report from the error detection unit 35, the error diagnosis control unit 36 receives information on the entry and way at the time of error detection from the cache control unit 32, and immediately starts diagnosis control. First, the error diagnosis control unit 36 designates information related to the received entry and way when an error is detected (hereinafter abbreviated as “the entry way”) to the cache control unit 32 and starts diagnosis. When the instruction is given, the flowchart of FIG. 3 is activated.

  When an error occurs and the flowchart of FIG. 3 is started, the cache control unit 32 that has received the diagnosis start instruction from the error diagnosis control unit 36 prioritizes the transaction processing from the transaction control unit 25 and performs the diagnosis. In response to the start instruction, the diagnostic flag 51 is set in the entry way of the address array 33 (step S101). Subsequently, as an initial diagnosis, the error diagnosis control unit 36 performs reread (reread) from the entry way to check whether or not an error is detected, to the cache control unit 32, A lead (reading) diagnosis instruction designating the entry way is performed (step S102).

  In the cache control unit 32 that has received the read (read) diagnosis instruction from the error diagnosis control unit 36, after indexing the diagnostic flag 51 of the entry way of the address array 33 and confirming that the diagnosis is being performed, The data of the entry way of the data array 34 is read (read). The error detection unit 35 checks whether there is an error in the read operation, and sends the check result to the error diagnosis control unit 36.

  In the error diagnosis control unit 36 that has received the check result from the error detection unit 35, when no error is detected as the entry way read (read) diagnosis result (in the case of “No” in step S 103), Judging that it is an intermittent failure at the time of reading (reading) the entryway, it is assumed that the read (read) data and the entryway can be used as they are, In step S109, the cache control unit 32 is instructed to cancel diagnosis by canceling the setting of the diagnostic flag 51 of the entry way. The cache control unit 32 that has received the diagnosis cancellation instruction from the error diagnosis control unit 36 cancels the setting of the diagnostic flag 51 of the entry way in the address array 33 (step S109). Thereafter, the error diagnosis control unit 36 ends the diagnosis process.

  On the other hand, as the result of reading (reading) diagnosis of the entry way performed as the first diagnosis, an uncorrectable error, that is, correction of data by an error detection correction bit such as ECC attached to the read data is impossible. If an error is detected (in the case of “Yes” in step S103), in order to confirm the possibility of a fixed failure at the time of reading (reading) the entry way, the process proceeds to step S104, where the data array 34 The entry way data write (write) & read (read) diagnosis is performed (step S104). Here, in the write & read diagnosis, all the bits including the error detection and correction bits such as ECC are set to both the “1” value and the “0” value so that it is possible to surely determine whether or not the failure is a fixed failure. It must be set, and at least two write and read operations are required. Here, the first round uses data with a value of “1”, and the second round uses data with a value of “0” for all bits. An example will be described.

  First, the error diagnosis control unit 36 sends to the cache control unit 32 a write (write) diagnosis instruction for data in which all bits of the entry way are “1” values. In the cache control unit 32 that has received a write (write) diagnosis instruction for data in which all bits from the error diagnosis control unit 36 are “1” values, the diagnostic flag 51 of the entry way in the address array 33 is indexed, After confirming that the diagnosis is in progress, a value “1” is written in all the bits of the line data of the data array 34 as the cache data 45. When the writing is completed, the error diagnosis control unit 36 is notified of this.

  The error diagnosis control unit 36 that has received the write (write) operation end notification of the “1” value from the cache control unit 32 then sends a read diagnosis instruction after writing to the cache control unit 32. In the cache control unit 32 that has received the read diagnosis instruction after writing from the error diagnosis control unit 36, after indexing the diagnostic flag 51 of the entry way of the address array 33 and confirming that the diagnosis is being performed, Data of the entry way (cache data 45) of the data array 34 is read (read). The error detection unit 35 checks whether there is an error in the read data, and sends the check result to the error diagnosis control unit 36.

  In the case of read diagnosis after writing, it is necessary to check the content of the data that has been read (read), and the data content cannot be checked by a check using an error correction circuit such as ECC. For this reason, the error detection unit 35 is notified from the cache control unit 32 that the data is checked by the read diagnosis after the write for diagnosis, and is not a check using an error correction circuit such as a normal ECC. It is checked whether all the bits of the read (read) data match the expected value of “1”.

  The error diagnosis control unit 36 that has received the check result from the error detection unit 35 next sends a write (write) diagnosis instruction for data in which all the bits of the entry way have a value of “0” to the cache control unit 32. The same control as in the case of the write & read diagnosis in which all bits are “1” values is performed, and the check result in the write & read diagnosis in which all bits are “0” values is acquired from the error detection unit 35.

  In the error diagnosis control unit 36 that acquired the check result of the two write & read operations in which all the bits are “1” value and all the bits are “0” value, the check result is read twice after writing without error. If the read (read) data matches the expected values of all bits having a value of “1” and all bits having a value of “0” (“NO” in step S105), the entry way Therefore, the entry way is considered to be in a state where it can be used continuously.

  However, in this case, unlike the case of step S103 in which only the read operation is performed, since the write and read operations are performed twice, the entry way is in a state where it can be used as it is. Itself cannot be used. Therefore, the error diagnosis control unit 36 sends to the cache control unit 32 a data unusable instruction indicating that the entryway can be continuously used but the data is unusable.

  The cache control unit 32 that has received the data unusable instruction from the error diagnosis control unit 36 checks the status 43 of the entry way in the address array 33 (step S110). If the status 43 is “Shared” (in the case of “Shared” in step S110), the same data exists in the memory 22, and the data of the entry way in the cache memory cannot be used. Since there is no problem, the status 43 of the entry way in the address array 33 is set to “Invalid” indicating that the cache memory is not used (step S112). The error diagnosis control unit 36 is notified.

  The error diagnosis control unit 36 that has received the notification of the completion of the setting of the status 43 from the cache control unit 32 proceeds to step S109 and sets the entry way diagnostic flag 51 to the cache control unit 32. Instructs the diagnosis to be released. The cache control unit 32 that has received the diagnosis cancellation instruction from the error diagnosis control unit 36 cancels the setting of the diagnostic flag 51 of the entry way in the address array 33 (step S109). Thereafter, the error diagnosis control unit 36 ends the diagnosis process.

  On the other hand, if the status 43 is 'Modified' in step S110 (in the case of "Modified" in step S110), this is a case where valid data exists only in the entry way and is left as it is. Since the process cannot be terminated, a failure flag 52 indicating that the data is invalid data and cannot be used is set in the entry way of the address array 33 (step S111). Is notified to the error diagnosis control unit 36.

  The error diagnosis control unit 36 that has received the notification of the completion of the setting of the failure flag 52 from the cache control unit 32 shifts to step S109 to notify the cache control unit 32 of the diagnostic flag 51 of the entryway. Instructs diagnosis cancellation to cancel the setting. The cache control unit 32 that has received the diagnosis cancellation instruction from the error diagnosis control unit 36 cancels the setting of the diagnostic flag 51 of the entry way in the address array 33 (step S109). Thereafter, the error diagnosis control unit 36 ends the diagnosis process.

  In step S105, the error diagnosis control unit 36 that acquired the check result of the two write & read operations in which all the bits have the value “1” and all the bits have the value “0”, the check result is Or both have errors, and the data read (read) after writing did not match one or both of the expected values of all bits having a value of '1' and all bits having a value of '0' In this case (in the case of “Yes” in step S105), it is determined that the entry way is a fixed failure at the time of reading (reading), and the entry way cannot be used as it is. Consider what needs to be done. Therefore, the error diagnosis control unit 36 sends a degradation instruction to the cache control unit 32 in order to perform a degradation that sets the entry way so that it cannot be used continuously.

  The cache control unit 32 that has received the degradation instruction from the error diagnosis control unit 36 checks the status 43 of the entry way in the address array 33 (step S106). If the status 43 is “Shared” (in the case of “Shared” in step S106), the same data exists in the memory 22, and the data of the entry way in the cache memory cannot be used. Since there is no problem, the process proceeds to step S108, and the status 43 of the entry way in the address array 33 is rewritten and set to “Degrade” indicating an unusable state (step S108). This is notified to the error diagnosis control unit 36.

  The error diagnosis control unit 36 that has received the notification of the completion of the setting of the status 43 from the cache control unit 32 proceeds to step S109 and sets the entry way diagnostic flag 51 to the cache control unit 32. Instructs the diagnosis to be released. The cache control unit 32 that has received the diagnosis cancellation instruction from the error diagnosis control unit 36 cancels the setting of the diagnostic flag 51 of the entry way in the address array 33 (step S109). Thereafter, the error diagnosis control unit 36 ends the diagnosis process.

  On the other hand, when the status 43 is “Modified” in step S106 (in the case of “Modified” in step S106), this is a case where valid data exists only in the entry way, and is left as it is. Since the process cannot be terminated, a failure flag 52 indicating that the data is invalid and cannot be used is set in the entry way of the address array 33 (step S107). Is notified to the error diagnosis control unit 36.

  The error diagnosis control unit 36 that has received the notification of the completion of the setting of the failure flag 52 from the cache control unit 32 proceeds to step S108, and notifies the cache control unit 32 of the status of the entry way of the address array 33. Degrade instruction to rewrite 43 to “Degrade” indicating an unusable state is performed. In the cache control unit 32 that has received the degradation instruction from the error diagnosis control unit 36, the status 43 of the entry way in the address array 33 is rewritten and set to “Degrade” indicating an unusable state (step S108). The error diagnosis control unit 36 is notified that the setting of the status 43 has been completed.

  The error diagnosis control unit 36 that has received the notification of the completion of the setting of the status 43 from the cache control unit 32 proceeds to step S109 and sets the entry way diagnostic flag 51 to the cache control unit 32. Instructs the diagnosis to be released. The cache control unit 32 that has received the diagnosis cancellation instruction from the error diagnosis control unit 36 cancels the setting of the diagnostic flag 51 of the entry way in the address array 33 (step S109). Thereafter, the error diagnosis control unit 36 ends the diagnosis process.

  As shown in the flowchart of FIG. 3 above, when an uncorrectable error occurs, a diagnosis is immediately executed based on the information about the generated error to determine whether it is an intermittent failure or a fixed failure. If it is determined that there is a failure, the entry way data in which the error has occurred cannot be used, but the entry way is set to a state where it can be used continuously. Performance degradation can be prevented. On the other hand, if it is determined that the failure is a fixed failure, the status 43 of the entry way in which the error has occurred is rewritten to “Degrade” indicating an unusable state (degraded state), and the entry way is continuously used. By prohibiting the cache memory, it is possible to prevent a decrease in the reliability of the cache memory due to inadvertent continuous use.

  Next, referring to the flowchart of FIG. 4, after the diagnosis in the flowchart of FIG. 3 is completed, the way of the entry for which the normal transaction is the diagnosis target (hereinafter referred to as “the entry way”) is referred to. An example of the operation will be described. Prior to the description of the flowchart of FIG. 4, first, the combination of the failure flag 52 and the status 43 of the entryway that has been a diagnosis target after completion of the diagnosis will be further described.

  When the failure flag 52 is set and is in a valid state, the status 43 is set to either 'Modified' or 'Degrade' as described in the flowchart of FIG. If the failure flag 52 is in a valid state and the status 43 is set to “Modified”, the data stored in the data array 34 cannot be used, but the entry way itself continues. It is possible to use it. On the other hand, when the failure flag 52 is in a valid state and the status 43 is set to “Degrade”, the entry way itself cannot be used, and the stored data cannot be used. It is shown that. If neither the diagnostic flag 51 nor the failure flag 52 is set and is in an invalid state, the status 43 is set to 'Degrade' as described in the flowchart of FIG. In other words, it indicates that the normal processing can be performed. However, if neither the in-diagnosis flag 51 nor the failure flag 52 is set and is in an invalid state and the status 43 is set to 'Degrade', the entry This indicates that the way cannot be used, the entry way is not registered, and the entry way cannot be newly registered.

  In the flowchart of FIG. 4, when a normal transaction from the processor 21 that performs normal processing occurs after the diagnosis is completed, the transaction control unit 25 receives the normal transaction, and the cache control unit 32 receives the normal transaction from the transaction control unit 25. The address array 33 is indexed based on the address information specified by the transaction (step S201). As a result of the indexing, it is confirmed whether or not the same address is registered as an entry way in the address array 33 and the failure flag 52 of the entry way is set to a valid state as a diagnosis result (step S202). . When the same address is registered as an entry way in the address array 33 and the failure flag 52 of the entry way is invalid (in the case of “No” in step S202), the cache memory is Is performed (step S214), a normal reply is returned to the transaction control unit 25 (step S211), and the process ends.

  On the other hand, if the same address is registered in the address array 33 as an entry way and the failure flag 52 of the entry way is set to a valid state as a result of the indexing in step S202 (in step S202) If “Yes”, the following control is performed. The cache control unit 32 first determines the type of received normal transaction (step S203). When the type of the normal transaction is “write” of the write request (in the case of “write” in step S203), the normal transaction indicates that the entry way data is being updated to the latest data. Unusable data in the entry way becomes invalid and is rewritten with a new value.

  Therefore, the cache control unit 32 next checks the status 43 of the entry way in the address array 33 (step S208). If the status 43 is “Modified” (in the case of “Modified” in step S208), the entry way itself of the data array 34 can be used continuously, so the failure of the entry way of the address array 33 After the setting of the flag 52 is canceled (step S209), the data is overwritten and written in the entry way of the data array 34 (step S210), and thereafter, a normal reply indicating that the processing has been normally performed is sent to the transaction control unit. After returning to 25 and performing an operation to notify the processor 21 of the write transaction issuer of normality (step S211), the process is terminated.

  On the other hand, if the status 43 is “Degrade” in step S208 (in the case of “Degrade” in step S208), the entry way itself of the data array 34 is in an unusable state and continues. The failure of the entry way in the address array 33 in order to switch to a state where another usable way of the same entry that substitutes for the entry way is selected and used is indicated. After canceling the setting of the flag 52, the key address 41 and the status 43 of the entry way are newly registered in the available way for the same entry (step S212), and the entry way is replaced in the address array 33. Write data to the same entry-specific way in the same data array 34 as the same entry-specific way registered as (Step S213), and after returning the normal reply to the transaction control unit 25 and performing an operation to notify the write transaction issuing processor 21 of the normality (step S211), The process ends.

  On the other hand, when the type of the normal transaction is “read” in the read request in step S203 (in the case of “read” in step S203), the normal transaction tries to read the data of the entry way (address) that cannot be used. Therefore, a series of processes of a normal transaction using the entry way data needs to be redone. Therefore, by returning an error reply or the like to the transaction control unit 25 and notifying that the entry way (address) data is broken and cannot be used, the information processing system 11 The cache control unit 32 executes an operation for performing a series of processes relating to the normal transaction again or providing an opportunity to execute the failure process.

  That is, the cache control unit 32 first checks the status 43 of the entry way in the address array 33 (step S204). If the status 43 is “Modified” (in the case of “Modified” in step S204), the entry way itself of the data array 34 can be used continuously. 43 is rewritten and set as “Invalid” (step S205), the setting of the failure flag 52 of the entry way in the address array 33 is canceled (step S206), and then an error reply [failure] is sent to the transaction control unit 25. To the processor 21 of the read transaction issuer, and prompts the execution of coherency guarantee control for guaranteeing consistency with the data in the memory 22 (step S207). The process is terminated.

  On the other hand, when the status 43 is “Degrade” in step S204 (in the case of “Degrade” in step S204), the entry way itself of the data array 34 is in an unusable state and continues. Therefore, it is not necessary to rewrite the status 43 of the entry way of the address array 33 to “Invalid”, and the failure flag 52 of the entry way of the address array 33 is immediately set. By canceling the setting (step S206) and then returning an error reply [failure] to the transaction control unit 25 and notifying the processor 21 that issued the read transaction that the processing has become an error, After prompting the execution of the coherency guarantee control (step S207), the process is terminated.

  As shown in the flowchart of FIG. 4 above, after the diagnosis processing, access to the entry way (that is, “the entry way”) to be diagnosed occurs by a normal transaction, and the data of the entry way is If the failure flag 52 indicating that the data is invalid is set, if the normal transaction type is a data write request, a normal write operation to the entry way or another way of the same entry as an alternative is performed. Do. That is, if the status 43 is 'Modified', the setting of the failure flag 52 is canceled and data is written as a new value. If the status 43 is 'Degrade', the setting of the failure flag 52 is canceled and A different way of the same entry as an alternative to the entry way is selected, and data is written as a new value in another way of the selected same entry. On the other hand, if the type of normal transaction is a data read request, it is necessary to perform a series of normal transaction processing again and perform coherency guarantee control, so that the setting of the failure flag 52 is canceled and the normal processing results in an error. Outputs an error reply to the effect.

Next, referring to the flowchart of FIG. 5, when a normal transaction for performing normal processing is in a state of being diagnosed as shown in the flowchart of FIG. 3, the way of the entry to be diagnosed (hereinafter abbreviated as “the entry way”). An example of the operation when referring to (display) will be described.
The

  In the flowchart of FIG. 5, when a normal transaction from the processor 21 occurs, the transaction control unit 25 receives the normal transaction, and the cache control unit 32 stores the address information specified by the normal transaction from the transaction control unit 25. Based on this, the address array 33 is indexed (step S201). As a result of the indexing, it is confirmed whether or not the same address is registered as an entry way in the address array 33 and the diagnostic flag 51 of the entry way is set to a valid state (step S302). When the same address is registered as an entry way in the address array 33 and the entry way diagnostic flag 51 is invalid (in the case of “None” in step S302), the entry way Therefore, the normal processing is performed on the cache memory (step S304), a normal reply is returned to the transaction control unit 25, and the processing is terminated.

  On the other hand, as a result of the indexing in step S302, when the same address is registered as an entry way in the address array 33, and the diagnostic flag 51 of the entry way is set to a valid state (step S302). In the case of “Yes”, the diagnosis is related to the entry way. Therefore, the diagnosis process is prioritized so that the entry way is not used for the normal process until the diagnosis is completed. That is, in such a case, in order to wait for the processing of the normal transaction, an instruction for reissuing the normal transaction is returned to the transaction control unit 25 (step S303), and the processing ends.

  As shown in the flowchart of FIG. 4 above, when an access to a way of an entry to be diagnosed (that is, the entry way) is generated by a normal transaction during the diagnosis, the normal processing of the normal transaction is completed and the diagnosis is completed. By performing control so as to wait until it is performed and prioritizing diagnostic processing, it is possible to quickly determine whether an error is due to an intermittent failure or an error due to a fixed failure, and appropriate failure processing can be performed.

  Next, as a supplementary explanation, when an error that can be corrected occurs when the cache data 45 of any way of the data array 34 (hereinafter abbreviated as “the entry way”) is read (read), the entry An example of the operation when the way diagnosis is performed and the entry way is degraded will be described with reference to the flowchart of FIG. FIG. 6 is a flowchart for supplementary explanation of the operation of the information processing system 11 shown in FIGS. 1 and 2. As a result of the diagnosis, the corrected read data is used as preventive maintenance means, and the cache memory If the fixed failure is determined after the data in the memory 22 is written back, the status 43 of the entry way in which a correctable error has occurred is set to 'Degrade', and the entry way in which the error has occurred is degraded. An example of the operation in the case where early preventive maintenance can be performed by performing is described.

  When a correctable error occurs and the flowchart of FIG. 6 is activated, as in the flowchart of FIG. 3, in the cache control unit 32 that has received the diagnosis start instruction from the error diagnosis control unit 36, the transaction control unit Prior to the transaction processing from 25, the diagnosis start instruction 51 is set in the entry way of the address array 33 in response to the diagnosis start instruction (step S401). Subsequently, as an initial diagnosis, the error diagnosis control unit 36 performs reread (reread) from the entry way to check whether or not an error is detected, to the cache control unit 32, A lead (reading) diagnostic instruction specifying the entry way is performed (step S402).

  In the cache control unit 32 that has received the read diagnosis instruction from the error diagnosis control unit 36, the diagnosis flag 51 of the entry way in the address array 33 is indexed and diagnosed, as in the flowchart of FIG. After confirming that the data is in the middle, the data of the entry way in the data array 34 is read (read). The error detection unit 35 checks whether there is an error in the read operation, and sends the check result to the error diagnosis control unit 36.

  In the error diagnosis control unit 36 that has received the check result from the error detection unit 35, as in the case of the flowchart of FIG. 3, if no error is detected as a read (read) diagnosis result of the entry way (step In the case of “No” in S403, it is determined that the entry way is an intermittent failure at the time of reading (reading), and the read (read) data and the entry way can be used as they are. Assuming that it is in a state, the process proceeds to step S410, and a diagnosis cancellation instruction is issued to the cache control unit 32 to cancel the setting of the diagnostic flag 51 of the entry way. The cache control unit 32 that has received the diagnosis cancellation instruction from the error diagnosis control unit 36 cancels the setting of the diagnostic flag 51 of the entry way in the address array 33 (step S410). Thereafter, the error diagnosis control unit 36 ends the diagnosis process.

  On the other hand, when an error that can correct the read data is detected as a read (read) diagnosis result of the entry way performed as the first diagnosis (in the case of “Yes” in step S403), the flowchart of FIG. Unlike the case, the corrected read data obtained as the correction result of the read data is temporarily held in a separate register or the like (step S404). Thereafter, in order to confirm the possibility of a fixed failure at the time of reading (reading) the entry way, the process proceeds to step S405, and the data of the entry way in the data array 34 is transferred as in the flowchart of FIG. Write (write) & read (read) diagnosis is performed (step S405). Here, as in the case of the flowchart of FIG. 3, the write and read diagnosis includes the error detection and correction bits such as ECC for the first time so that it can be surely determined whether or not it is a fixed failure. In the second round, a diagnosis is performed by checking the expected value as a result of performing two write and read operations using data having a value of “1” and all bits having a value of “0”.

  In the error diagnosis control unit 36 that acquired the check results of the two write & read operations in which all the bits have the value “1” and all the bits have the value “0”, the check results are not errored twice and read after writing. If the (read) data matches the expected values of all bits having a value of “1” and all bits having a value of “0” (in the case of “No” in step S406), the entry way Unlike the case of the flowchart of FIG. 3, it is determined that the entryway is in a state where it can be used as it is because it is determined as an intermittent failure at the time of reading (reading). The corrected read data temporarily stored in the register or the like is written back to the entry way of the data array 34 (step S411), and then the write back process to the entry way is performed. That it has terminated and notifies the error diagnosis control unit 36.

  In the error diagnosis control unit 36 that has received a notification from the cache control unit 32 that the write-back processing to the entry way has been completed, the error diagnosis control unit 36 proceeds to step S410 and instructs the cache control unit 32 to diagnose the entry way. A diagnosis cancellation instruction for canceling the setting of the middle flag 51 is issued. The cache control unit 32 that has received the diagnosis cancellation instruction from the error diagnosis control unit 36 cancels the setting of the diagnostic flag 51 of the entry way in the address array 33 (step S410). Thereafter, the error diagnosis control unit 36 ends the diagnosis process.

  In step S406, the error diagnosis control unit 36 that has acquired the check results of the two write & read operations in which all the bits are “1” values and all the bits are “0” values. Or both have errors, and the data read (read) after writing did not match one or both of the expected values of all bits having a value of '1' and all bits having a value of '0' In this case (in the case of “Yes” in step S406), it is determined that the entry way is a fixed failure at the time of reading (reading), and the entry way cannot be used as it is. Consider what needs to be done. Therefore, in the error diagnosis control unit 36, as in the case of the flowchart of FIG. 3, the degradation instruction is sent to the cache control unit 32 in order to perform the degradation setting so that the entry way cannot be used continuously. And send it out.

  The cache control unit 32 that has received the degradation instruction from the error diagnosis control unit 36 checks the status 43 of the entry way in the address array 33 as in the flowchart of FIG. 3 (step S407). If the status 43 is “Shared” (in the case of “Shared” in step S407), the same data exists in the memory 22, and the data of the entry way in the cache memory cannot be used. Since there is no problem, the process proceeds to step S409, the status 43 of the entry way in the address array 33 is rewritten and set to “Degrade” indicating an unusable state (step S409), and the setting of the status 43 is completed. This is notified to the error diagnosis control unit 36.

  In the error diagnosis control unit 36 that has received the notification of the completion of the setting of the status 43 from the cache control unit 32, the process proceeds to step S410, and the cache control unit 32 is notified of the same as in the flowchart of FIG. A diagnosis cancellation instruction is issued to cancel the setting of the entry way diagnostic flag 51. The cache control unit 32 that has received the diagnosis cancellation instruction from the error diagnosis control unit 36 cancels the setting of the diagnostic flag 51 of the entry way in the address array 33 (step S410). Thereafter, the error diagnosis control unit 36 ends the diagnosis process.

  On the other hand, if the status 43 is “Modified” in step S407 (in the case of “Modified” in step S407), there is a case where valid data exists only in the entry way, and it is left as it is. Since the process cannot be terminated, unlike the flowchart of FIG. 3, the corrected read data temporarily stored in the register or the like in step S404 is stored in the address of the memory 22 corresponding to the entry way. After the writing (step S408), the error diagnosis control unit 36 is notified that the writing process to the memory 22 is finished.

  The error diagnosis control unit 36 that has received the notification of the end of the writing process to the memory 22 from the cache control unit 32 proceeds to step S409 and notifies the cache control unit 32 of the entry way of the address array 33. An instruction to rewrite the status 43 to “Degrade” indicating an unusable state is issued. The cache control unit 32 that has received the rewrite instruction from the error diagnosis control unit 36 rewrites and sets the status 43 of the entry way in the address array 33 to “Degrade” indicating an unusable state (step S409). The error diagnosis control unit 36 is notified that the setting of the status 43 has been completed.

  The error diagnosis control unit 36 that has received the notification of the completion of the setting of the status 43 from the cache control unit 32 moves to step S410 and sets the entryway diagnostic flag 51 for the cache control unit 32. Instructs the diagnosis to be released. The cache control unit 32 that has received the diagnosis cancellation instruction from the error diagnosis control unit 36 cancels the setting of the diagnostic flag 51 of the entry way in the address array 33 (step S410). Thereafter, the error diagnosis control unit 36 ends the diagnosis process.

  As shown in the flowchart of FIG. 6, when a correctable error occurs, unlike the case of an uncorrectable error as shown in the flowchart of FIG. 3, the error of the data read from the cache memory Since the read data after correction can be acquired, the corrected read data is temporarily stored in a register or the like as shown in step S404 of the flowchart of FIG. 6 prior to the execution of the write & read diagnosis. If the entry way is usable after the write & read diagnosis is performed, the corrected read data temporarily stored is written back to the cache memory to return to a normal state. Return. On the other hand, when the entry way cannot be used and the status 43 is “Modified”, the corrected read data temporarily stored is written in the memory 22 corresponding to the entry way. , The status 43 of the entry way is set to 'Degrade' indicating an unusable state. Thus, when a correctable error occurs, early preventive maintenance can be performed.

(Explanation of effect of embodiment)
As described in detail above, the following effects are obtained in the embodiment according to the present invention. That is, when a cache memory error is detected, an error diagnosis control unit 36 is provided as a function for immediately diagnosing the part where the error has occurred (that is, the entry way), and the failure of the cache memory is determined quickly and accurately As a result, cache memory performance degradation due to unnecessary degradation at the time of intermittent failure is minimized, and at the same time, the fixed failure occurrence site is prevented from being inadvertently used continuously. Thus, the reliability of the cache memory can be maintained.

  The configuration of the preferred embodiment of the present invention has been described above. However, it should be noted that such embodiments are merely examples of the present invention and do not limit the present invention in any way. Those skilled in the art will readily understand that various modifications and changes can be made according to a specific application without departing from the gist of the present invention.

11 Information processing system 21 Processor 22 Memory 25 Transaction control unit 30 Cache memory 32 Cache control unit 33 Address array 34 Data array 35 Error detection unit 36 Error diagnosis control unit 41 Key address 42 Set address 43 Status 44 Flag 45 Cache data 51 Under diagnosis Flag 52 Fault flag

Claims (10)

In a cache memory composed of a multi-way set associative address array and data array,
An error detection unit that detects and corrects errors in data read from the way of any entry of the data array; and
An error diagnosis control unit that is activated when an error is detected by the error detection unit, and controls execution of a diagnosis regarding the way of the entry in which the error is detected;
Comprising at least
As a result of diagnosis by the error diagnosis control unit, when the detected error is determined to be an error due to an intermittent failure, the way of the entry in which the error is detected can be continuously used,
When the detected error is determined to be an error due to a fixed failure, the way of the entry in which the error is detected is degraded and set to an unusable state.
A cache memory characterized by that. As a result of diagnosis by the error diagnosis control unit, when the detected error is an uncorrectable error and is determined to be an error due to an intermittent failure,
When the way status of the entry in which the error is detected indicates that the same data is held in both the entry way and the memory, the way status of the entry is Rewrite and set the way not used,
In addition, when the way status of the entry in which the error is detected indicates that the data is held only in the way of the entry, the way data of the entry is invalid data and used. Set a failure flag indicating that the data is impossible to the way of the entry,
Further, as a result of diagnosis by the error diagnosis control unit, when the detected error is an uncorrectable error and is determined to be an error due to a fixed failure,
When the way status of the entry in which the error is detected indicates that the same data is held in both the entry way and the memory, the way status of the entry is Degrade the way, rewrite and set it to an unusable state,
In addition, when the status of the way of the entry in which the error is detected indicates that data is held only in the way of the entry, the failure flag is set in the way of the entry, and the way The entry way status is rewritten and set to an unusable state by degrading the entry way.
The cache memory according to claim 1. As a result of diagnosis by the error diagnosis control unit, when the detected error is a correctable error, temporarily store the data after error correction,
When the detected error is determined to be an error due to intermittent failure,
The error-corrected data temporarily stored is written back to the entry way where the error was detected,
Furthermore, when the detected error is determined to be an error due to a fixed failure,
When the way status of the entry in which the error is detected indicates that the same data is held in both the entry way and the memory, the way status of the entry is Degrade the way, rewrite and set it to an unusable state,
In addition, when the way status of the entry in which the error is detected indicates a state in which data is held only in the way of the entry, the data after the error correction temporarily stored Is written back to the memory corresponding to the way of the entry, and the way status of the entry is rewritten and set to an unusable state by degrading the way of the entry.
The cache memory according to claim 1. After completion of diagnosis by the error diagnosis control unit, when there is an access by way of normal processing to a way of an entry in which the failure flag is set as a diagnosis result,
When the normal processing access is a data write request to the entry way,
When the status of the way of the entry indicates a state in which data is held only in the way of the entry, the setting of the failure flag set in the way of the entry is canceled, and the normal Write the processing data to the way of the entry, and output a normal reply indicating that the processing was successful,
In addition, when the way status of the entry indicates an unusable state after degrading, the setting of the failure flag set in the way of the entry is canceled and the way of the way of the entry is Select and register another way of the same entry as an alternative, write the normal process data to another way of the same entry, and output the normal reply
Further, in the case where the normal processing access is a data read request from the way of the entry,
If the way status of the entry indicates a state in which data is held only in the way of the entry, the way status of the entry is rewritten to a state where the way of the entry is not used. Set and release the setting of the failure flag set in the way of the entry, and output an error reply indicating that the process has an error,
In addition, when the way status of the entry indicates that the entry is degraded and cannot be used, the failure flag set in the way of the entry is canceled and the error reply is output. To
The cache memory according to claim 2 or 3, wherein When there is a request for access to the way of the entry by normal processing while executing the diagnosis on the way of the entry in which the error is detected by the error diagnosis control unit,
Priority is given to the execution of diagnosis for the way of the entry, and control is performed to wait for the normal processing to access the way of the entry until the diagnosis is completed.
5. The cache memory according to claim 1, wherein A cache memory failure control method for controlling a failure of a cache memory composed of a multi-way set associative address array and a data array,
An error detection step for detecting and correcting an error in data read from the way of any entry of the data array;
An error diagnosis control step that is started when an error is detected by the error detection step and controls execution of a diagnosis relating to a way of an entry in which the error is detected;
Having at least
As a result of diagnosis by the error diagnosis control step, when the detected error is determined to be an error due to an intermittent failure, the way of the entry in which the error is detected can be continuously used,
When the detected error is determined to be an error due to a fixed failure, the way of the entry in which the error is detected is degraded and set to an unusable state.
And a cache memory failure control method. As a result of diagnosis by the error diagnosis control step, when the detected error is an uncorrectable error and is determined to be an error due to an intermittent failure,
When the way status of the entry in which the error is detected indicates that the same data is held in both the entry way and the memory, the way status of the entry is Rewrite and set the way not used,
In addition, when the way status of the entry in which the error is detected indicates that the data is held only in the way of the entry, the way data of the entry is invalid data and used. Set a failure flag indicating that the data is impossible to the way of the entry,
Furthermore, as a result of diagnosis by the error diagnosis control step, when the detected error is an uncorrectable error and is determined to be an error due to a fixed failure,
When the way status of the entry in which the error is detected indicates that the same data is held in both the entry way and the memory, the way status of the entry is Degrade the way, rewrite and set it to an unusable state,
In addition, when the status of the way of the entry in which the error is detected indicates that data is held only in the way of the entry, the failure flag is set in the way of the entry, and the way The entry way status is rewritten and set to an unusable state by degrading the entry way.
The cache memory failure control method according to claim 6. If the detected error is a correctable error as a diagnostic result by the error diagnostic control step, temporarily store the data after error correction,
When the detected error is determined to be an error due to intermittent failure,
The error-corrected data temporarily stored is written back to the entry way where the error was detected,
Furthermore, when the detected error is determined to be an error due to a fixed failure,
When the way status of the entry in which the error is detected indicates that the same data is held in both the entry way and the memory, the way status of the entry is Degrade the way, rewrite and set it to an unusable state,
In addition, when the way status of the entry in which the error is detected indicates a state in which data is held only in the way of the entry, the data after the error correction temporarily stored Is written back to the memory corresponding to the way of the entry, and the way status of the entry is rewritten and set to an unusable state by degrading the way of the entry.
The cache memory failure control method according to claim 6. After completion of the diagnosis by the error diagnosis control step, there is a case where there is an access by a normal process to a way of an entry in which the failure flag is set as a diagnosis result,
When the normal processing access is a data write request to the entry way,
When the status of the way of the entry indicates a state in which data is held only in the way of the entry, the setting of the failure flag set in the way of the entry is canceled, and the normal Write the processing data to the way of the entry, and output a normal reply indicating that the processing was successful,
In addition, when the way status of the entry indicates an unusable state after degrading, the setting of the failure flag set in the way of the entry is canceled and the way of the way of the entry is Select and register another way of the same entry as an alternative, write the normal process data to another way of the same entry, and output the normal reply
Further, in the case where the normal processing access is a data read request from the way of the entry,
If the way status of the entry indicates a state in which data is held only in the way of the entry, the way status of the entry is rewritten to a state where the way of the entry is not used. Set and release the setting of the failure flag set in the way of the entry, and output an error reply indicating that the process has an error,
In addition, when the way status of the entry indicates that the entry is degraded and cannot be used, the failure flag set in the way of the entry is canceled and the error reply is output. To
9. The cache memory failure control method according to claim 7 or 8, wherein: In an information processing system including at least a cache memory for absorbing a performance difference between a processor and a memory,
The cache memory comprises the cache memory according to any one of claims 1 to 5,
An information processing system characterized by this.

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