JP4860403B2 - Multiprocessor system, memory control / coherency control device, and coherency guarantee method - Google Patents

Description

  The present invention relates to a multiprocessor system such as a distributed shared memory multiprocessor system including a plurality of CPUs equipped with a cache memory, and in particular, a tag read from a tag memory provided to guarantee data coherency. The present invention relates to a coherency guarantee technique at the time of a tag failure that can prevent a system from going down even when there is an uncorrectable failure in an index result.

  Conventionally, in a multiprocessor system including a plurality of CPUs equipped with a cache memory, a tag memory is used to guarantee data coherency (see, for example, Patent Document 1). In Patent Document 1, in order to guarantee data coherency in a distributed shared memory series computer having a plurality of nodes, each node having a CPU equipped with a cache memory and a main memory shared by each node. A tag memory is provided for each node. The tag memory described in Patent Document 1 has an entry for each block of the main storage device, and each entry has the latest data of the corresponding block on the main storage device or on the cache memory. Or status information indicating whether the data is on the cache memory and has been updated, and the ID of the CPU holding the data are registered. When accessing data that does not exist in the cache memory on the own CPU, if the tag memory is pulled, it can be determined whether the latest data exists on the main storage device or on the cache memory in another CPU. Therefore, the latest data can be accessed, and data coherency can be guaranteed.

  On the other hand, when an error correction code such as ECC (error correcting code) is added to the data registered in the address array of the cache memory and there is a failure in the data read from the address array, the data in the address array is read. A technique for invalidating an entry and writing back the data on the cache memory corresponding to the invalidated entry to the main storage device using the corrected data is also known (see, for example, Patent Document 2). .

Japanese Patent Laid-Open No. 2002-24198 Japanese Patent Laid-Open No. 9-146836

  By the way, according to the conventional technique described in Patent Document 1, the location of the latest data can be known by referring to the tag memory, so that data coherency can be guaranteed. However, if a failure occurs in the tag memory and an error occurs in the tag index result, it will not be possible to know where the latest data is, so it will not be possible to guarantee data coherency and the system will be down. End up.

  Therefore, it is conceivable that the conventional technique described in Patent Document 2 is applied to the conventional technique described in Patent Document 1. Thus, when the detected failure is a correctable failure such as a 1-bit error, the operation can be continued using the corrected tag index result. However, if the detected failure is an uncorrectable failure such as a 2-bit error, it becomes impossible to know where the latest data exists, and the system goes down.

(Object of invention)
Therefore, an object of the present invention is to enable the operation to continue even when there is an uncorrectable failure in the tag index result read from the tag memory.

A first multiprocessor system according to the present invention includes:
A main storage device;
A plurality of CPUs equipped with a cache memory in which a copy of a part of the data stored in the main storage device is stored;
A tag memory that manages the state of data in each cache memory, and a memory control / coherency control device that guarantees data coherency using the tag memory;
When the memory control / coherency control device detects an uncorrectable fault in the tag index result indexed from the tag memory, the CPU is associated with the tag index result in which the uncorrectable fault is detected for each CPU. The main storage device is instructed to sweep out all the data that may be generated.

A second multiprocessor system according to the present invention is the first multiprocessor system,
The memory control / coherency control device includes:
A tag memory stored in an entry corresponding to the lower address of the data, an upper address of the data stored in each cache memory, and a status indicating whether the data is the latest data;
A fault check circuit that checks whether there is an uncorrectable fault in the tag index result indexed from the tag memory by the lower address of the transaction;
When the failure check circuit determines that there is an uncorrectable failure in the tag index result, the lower address of the data stored in the cache memory is used for tag indexing for each CPU. And a coherency control unit for instructing to sweep out all data matching the lower address to the main memory.

A third multiprocessor system according to the present invention is the second multiprocessor system,
The coherency control unit generates, for all upper addresses, a swap transaction including the upper address and the lower address used at the time of tag indexing, and issues the generated swap transaction to each CPU. Features.

A fourth multiprocessor system according to the present invention is the second multiprocessor system,
The coherency control unit generates a swap transaction including the upper address and the lower address used at the time of the tag index for all upper addresses, and the CPU does not perform normal processing on the generated swap transaction. Sometimes, it is issued to each of the CPUs.

A fifth multiprocessor system according to the present invention is the second multiprocessor system,
A service processor, and when the failure check circuit determines that there is an uncorrectable failure in the tag index result, the service processor stores the CPU in the cache memory instead of the coherency control unit It is characterized in that all data whose lower address matches the lower address used at the time of tag indexing is instructed to be swept out to the main memory.

A sixth multiprocessor system according to the present invention is the second multiprocessor system,
The coherency control unit is
When it is determined by the failure check circuit that there is an uncorrectable failure in the tag index result, and based on the contents of the tag memory, it cannot be determined that the latest data to be accessed by the transaction exists on the cache memory Immediately, issue a swap transaction including the full address of the transaction to the CPUs, and then generate a swap transaction including the upper address and the lower address of the transaction for all upper addresses. When the CPU is not performing normal processing, the generated swap transaction is issued to each CPU, the failure check circuit determines that the tag index result has an uncorrectable fault, and the tag memory Cache based on content If it is determined that there is the latest data to be accessed by the transaction on the memory, a swap transaction including the upper address and the lower address of the transaction is generated for all upper addresses, and each CPU When normal processing is not performed, the generated swap transaction is issued to each CPU.

The first memory control / coherency control device according to the present invention is:
Data coherency in a multiprocessor system comprising a main storage device and a plurality of CPUs equipped with a cache memory storing a copy of a portion of the data stored in the main storage device is stored in each cache memory. A memory control / coherency control device that uses a tag memory to manage the data state of
When an uncorrectable failure is detected in the tag index result indexed from the tag memory, all data that may be related to the tag index result in which the uncorrectable failure is detected are stored for each CPU. The main storage device is instructed to be swept out.

A second memory control / coherency control device according to the present invention is the first memory control / coherency control device,
A tag memory stored in an entry corresponding to the lower address of the data, an upper address of the data stored in each cache memory, and a status indicating whether the data is the latest data;
A fault check circuit that checks whether there is an uncorrectable fault in the tag index result indexed from the tag memory by the lower address of the transaction;
When the failure check circuit determines that there is an uncorrectable failure in the tag index result, the lower address of the data stored in the cache memory is used for tag indexing for each CPU. And a coherency control unit for instructing to sweep out all data matching the lower address to the main memory.

A third memory control / coherency control device according to the present invention is the second memory control / coherency control device,
The coherency control unit generates, for all upper addresses, a swap transaction including the upper address and the lower address used at the time of tag indexing, and issues the generated swap transaction to each CPU. Features.

A fourth memory control / coherency control device according to the present invention is the second memory control / coherency control device,
The coherency control unit generates a swap transaction including the upper address and the lower address used at the time of the tag index for all upper addresses, and the CPU does not perform normal processing on the generated swap transaction. Sometimes, it is issued to each of the CPUs.

A fifth memory control / coherency control device according to the present invention is the second memory control / coherency control device,
The coherency control unit is
When it is determined by the failure check circuit that there is an uncorrectable failure in the tag index result, and based on the contents of the tag memory, it cannot be determined that the latest data to be accessed by the transaction exists on the cache memory Immediately, issue a swap transaction including the full address of the transaction to the CPUs, and then generate a swap transaction including the upper address and the lower address of the transaction for all upper addresses. When the CPU is not performing normal processing, the generated swap transaction is issued to each CPU, the failure check circuit determines that the tag index result has an uncorrectable fault, and the tag memory Cache based on content If it is determined that there is the latest data to be accessed by the transaction on the memory, a swap transaction including the upper address and the lower address of the transaction is generated for all upper addresses, and each CPU When normal processing is not performed, the generated swap transaction is issued to each CPU.

A first coherency guarantee method according to the present invention includes:
A coherency guarantee method for guaranteeing data coherency in a multiprocessor system comprising a main storage device and a plurality of CPUs equipped with a cache memory storing a copy of a part of the data stored in the main storage device There,
When an uncorrectable failure is detected in the tag index result indexed from the tag memory that manages the state of data in each cache memory, the tag index result in which the uncorrectable failure is detected for each CPU The main storage device is instructed to sweep out all data that may be related to.

The second coherency guarantee method according to the present invention is:
A coherency guarantee method for guaranteeing data coherency in a multiprocessor system comprising a main storage device and a plurality of CPUs equipped with a cache memory storing a copy of a part of the data stored in the main storage device There,
The tag memory in which the upper address of the data stored in each cache memory and the status indicating whether or not the data is the latest data is stored in the entry corresponding to the lower address of the data is represented as the lower address of the transaction. When an uncorrectable failure is detected in the tag index result obtained by indexing according to the above, the lower address of the data stored in the cache memory is used for tag indexing for each CPU. The main storage device is instructed to sweep out all data that matches the lower address, and each CPU sweeps out the corresponding data to the main storage device in accordance with the instruction.

[Action]
When the memory control / coherency control device detects an uncorrectable failure in the tag index result indexed from the tag memory that manages the state of data in each cache memory, an uncorrectable failure is detected for each CPU. Instructs main memory to sweep all data that may be related to the tagged index results. More specifically, the upper address of the data stored in the cache memory on each CPU and the status indicating whether the data is the latest data are stored in the entry corresponding to the lower address of the data. When an uncorrectable fault is detected in the tag index result obtained by indexing the tag memory with the lower address of the transaction, the memory control / coherency control device stores the cache memory for each CPU. It is instructed that all data whose lower address matches the lower address used at the time of tag indexing to the main storage device. In accordance with this instruction, each CPU sweeps out the corresponding data stored in the cache memory on its own CPU to the main memory. When an uncorrectable failure occurs in a certain entry in the tag memory, with respect to data for which it is managed whether or not the latest data is in the cache memory by the entry, whether the latest data is in the cache memory or not However, as described above, all of the data stored in the cache memory of each CPU whose main address matches the lower address used at the time of tag indexing is mainly used. By sweeping the data to the storage device, the latest data always exists on the main storage device, so that data coherency can be guaranteed.

  According to the present invention, even when an uncorrectable failure is detected in the tag index result read from the tag memory, data coherency can be ensured, so that the operation can be continued. Become. The reason is that if an uncorrectable fault is detected in the tag index result indexed from the tag memory, all data that may be related to the tag index result in which the uncorrectable fault is detected is sent to each CPU. This is because it includes a memory control / coherency control device that instructs the main storage device to be swept out.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings.

[Description of Configuration of First Embodiment]
FIG. 1 is a block diagram showing a configuration example of a first embodiment of a distributed shared memory multiprocessor system according to the present invention. Referring to FIG. 1, the distributed shared memory multiprocessor system according to the present embodiment includes a plurality of cells (nodes) 10, which are connected to each other via second and third interfaces 21 and 22. .

  Each cell 10 includes a plurality of CPUs (central processing units) 11 each having a store-in type cache memory (cache) 15, a memory control / coherency control unit 12 having a tag unit 13, a main storage unit 14, and the like. The CPU 11 and the memory control / coherency control device 12 are connected to each other via the first interface 20. The main storage device 14 in each cell 10 is accessible from all the cells 10.

  A status indicating whether or not the data stored in the cache 15 in the cell 10 is the latest data is registered in the tag unit 13 provided in the memory control / coherency control device 12 in each cell 10. ing.

  FIG. 2 shows a configuration example of the tag unit 13. Referring to the figure, the tag unit 13 includes a tag memory 131, an ECC check & correction circuit 132, and a comparison circuit 133.

  The tag memory 131 has a plurality of levels of entries for each lower address of data. Each entry is stored in the cache 15 and an entry unusable flag F indicating whether or not the entry is usable. The upper address of the existing data, the status indicating whether or not the data is the latest data, and the ECC are registered. When the lower address of the access target data is input, the information stored in the entry selected by the lower address is output as a tag index result.

  The ECC check & correction circuit 132 exists for each level of the tag memory 131, and performs ECC check and correction for the tag index result of the corresponding level. More specifically, the ECC check & correction circuit 132 at each level performs an ECC check on the tag index result at the corresponding level read from the tag memory 131. If there is no error, the tag index result read from the tag memory 131 is output. If a correctable error is detected, the corrected tag index result and correctable information (used during indexing) are output. When a lower address of the access target data and the level of the own circuit 132 are output and an uncorrectable error is detected, uncorrectable information (the lower address of the access target data used at the time of indexing) And the level of its own circuit 132).

  The comparison circuit 133 compares the high-order address in the tag index result output from the ECC check & correction circuit 132 at each level with the high-order address of the access target data used at the time of tag indexing, If there is, it is output to the third interface 22. However, when uncorrectable information exists in the output of the ECC check & correction circuit 132, the uncorrectable information is also output to the third interface 22, and when correctable information exists, the correctable information and the correction are corrected. A pair with a later tag index result is also output to the third interface 22. Note that the bit position to be used is determined for each cell 10, and the third interface 22 can specify which cell 10 is the output information based on the bit position.

  FIG. 3 is a block diagram illustrating a configuration example of the memory control / coherency control device 12. Referring to the figure, the memory control / coherency control device 12 includes a second interface output arbitration unit 101, a main pipe 102 having a tag unit 13 and a main control unit 103, a tag swap control unit 104, a comparison circuit 105, A tag write-back control unit 106, a coherency control unit 107, and a main memory access control unit 108. In FIG. 3, the same reference numerals as those in FIG. 1 denote the same parts.

  The second interface output arbitration unit 101 includes a register (not shown) in which a plurality of transactions (commands such as a write command and a read command) sent from the CPU 11 or an input / output device (not shown) can be stored. The transactions stored in the register are sequentially output to the second interface 21. However, while the swap processing in-progress signal indicating that swap processing is in progress is being input from the main control unit 103 via the path 220, the transaction currently being output (the transaction set at the top of the register) is not processed. The output continues to the second interface 21. Each cell 10 uses the second interface 21 in a time-sharing manner, and the second interface output arbitration unit 101 in each cell 10 sends a transaction to the second interface 21 at the timing assigned to the own cell. Output.

  All the cells 10 constituting the distributed shared memory multiprocessor system are connected to the second interface 21, and the main pipe 102 in each cell 10 performs a transaction on the second interface 21 via a path 212. Receive at the same time. Transactions received via this path 212 are supplied to the tag unit 13 and the main control unit 103.

  When the transaction is input via the path 212, the tag unit 13 in the main pipe 102, as described above, the tag index result with the higher address matched, the pair of correctable information and the corrected tag index result, Uncorrectable information or the like is output to the third interface 22.

  All the cells 10 constituting the distributed shared memory multiprocessor system are also connected to the third interface 22, and the main pipe 102 in each cell 10 is connected to the tag index on the third interface 22 via the path 214. As a result, a pair of correctable information and a corrected tag index result, uncorrectable information, etc. are received simultaneously.

  Based on the information received from the third interface 22 via the path 214, the main control unit 103 in the main pipe 102 determines processing for a transaction that has already been accepted via the path 212 as follows.

Based on the information received from the third interface 22 via the path 214, the tag unit 13 in the own cell 10 is normal and the transaction already received via the path 212 is the access target. If it is determined that there is no cache 15 storing data (latest data), the transaction is sent to the main memory access control unit 108 in the own cell 10. Thereby, the main memory access control unit 108 accesses the data when the data to be accessed by the transaction exists in the main storage device 14 in the own cell 10. That is, if the transaction is a write transaction, the data is rewritten accordingly. If the transaction is a read transaction, the corresponding data is output to a data bus (not shown).
Based on the information received from the third interface 22 via the path 214, the tag unit 13 in the own cell 10 is normal and the transaction already received via the path 212 is the access target. When it is determined that the data exists on the cache 15 in the own cell 10, the transaction is transmitted to each CPU 11 in the own cell 10 through the coherency control unit 107. Each CPU 11 accesses the data when there is data to be accessed in the cache 15 in its own CPU 11.
When it is determined that a correctable failure has occurred in the tag unit 13 in the own cell 10 based on the information received from the third interface 22 via the path 214, that is, the own cell 10 of the third interface 22 When the pair of the correctable information and the corrected tag index result is received via the bit assigned to the tag, the tag swap control unit 104 receives the lower order of the access target data included in the correctable information. The process of registering the address (the lower address of the transaction used at the time of tag indexing) and the ECC check & correction circuit 132 that detects the lower address and the failure included in the correctable information for the tag write-back control unit 106 The process of registering the level, the lower address included in the correctable information for the coherency control unit 107 and the correction Register an upper address contained in the tag index results after performing the processing for instructing issuance of a swap transaction.
When it is determined that an uncorrectable failure has occurred in the tag unit 13 in the own cell 10 based on the information received from the third interface 22 via the path 214, that is, the own cell of the third interface 22 When the uncorrectable information is received via the bit assigned to 10, processing for registering the lower address of the access target data included in the uncorrectable information to the tag swap control unit 104; Processing for registering the lower address included in the uncorrectable information and the level of the ECC check & correction circuit 132 that has detected the failure in the tag write-back control unit 106, and correction not possible in the coherency control 107 A process of instructing the issue of a swap transaction by registering the lower address included in the information is performed.

  Further, when the main control unit 103 registers the lower address included in the correctable information or the uncorrectable information in the tag swap control unit 104, the main control unit 103 performs the following processing until the swap processing described later is completed. The comparison circuit 105 that compares the lower address registered in the tag swap control unit 104 and the lower address of the transaction output to the second interface 21 detects that they match, and issues the transaction. If the source is the own cell 10, a swap processing signal is sent to the second interface output arbitration unit 101 via the path 220. If the transaction issuance source is another cell 10, a cancel signal indicating that the transaction has been canceled is sent to the cell 10 as the issuance source via the third interface 22. This is to ensure coherency even when the same transaction as the lower address registered in the tag swap control unit 104 is issued during the swap process.

When the main control unit 103 issues a swap transaction, the coherency control unit 107 issues a swap transaction to each CPU 11 in the own cell 10 via the path 219. At that time, if the lower address and the higher address are registered by the main control unit 103 (when the failure occurring in the tag unit 13 is a correctable failure), a swap transaction including the lower address and the higher address is issued. If only the lower address is registered (when the failure that occurred in the tag unit 13 is an uncorrectable failure), a swap transaction including the upper address and the lower address is generated for each of the upper addresses. Issue each generated swap transaction. For example, if the upper address is k bits, 2 ^k swap transactions are issued.

  When each CPU 11 receives the swap transaction, the CPU 11 checks whether or not the corresponding data exists in the cache 15. If there is no such data, the main pipe follows the path 210 → path 211 → second interface 21 → path 212. A reply transaction indicating that data corresponding to 102 does not exist is returned. On the other hand, when the corresponding data exists in the cache 15, the cache flush process is performed, the corresponding data stored in the cache 15 is written back to the main memory 14, and the above path is used. A reply transaction indicating that the cache flush process has been completed is returned to the main pipe 102.

  In response to these reply transactions, the main control unit 103 deletes the lower address registered in the tag swap control unit 104. As a result, the same address transaction that has been canceled on the main pipe 102 can be released from the cancel state and return to the normal operation. Further, the main control unit 103 instructs the tag write-back control unit 106 to generate an entry unusable flag in response to a reply transaction from the CPU 11. As a result, the tag write-back control unit 106 sets “1” (indicating unavailable) to the entry unavailable flag of the failure entry in the tag memory 131 specified by the lower address and level registered by the main control unit 103. ) Is set. When the tag index transaction after this is a tag index, referring to the level of the entry unusable flag = “1” determines that the level is invalid and does not use it.

[Description of Operation of First Embodiment]
Next, the operation of the present embodiment will be described in detail with reference to FIGS. 4 is a flowchart showing an example of processing when a correctable failure occurs mainly in the tag memory 131, and FIG. 5 is a flowchart showing an example of processing when an uncorrectable failure occurs mainly in the tag memory 131. .

  At the time of data access, each CPU 11 in each cell 10 sends a transaction including the address of the access target data via the second interface output arbitration unit 101 if there is no access target data in the cache 15 in its own CPU 11. Output to the second interface 21.

  In each cell 10, when the transaction is received via the second interface 21, the tag index is performed with the lower address of the address included in the transaction (step 4-1 in FIG. 4). As a result, the tag index result is read from each level entry corresponding to the lower address of the tag memory 131, and a failure check is performed in the ECC check & correction circuit 132. When it is determined that there is no failure, the ECC check & correction circuit 132 outputs the tag index result as it is, and when it is determined that there is a correctable failure, the corrected tag index result and correctable information (lower address) And a level), and if it is determined that there is an uncorrectable failure, uncorrectable information (including a lower address and a level) is output. The comparison circuit 133 outputs to the third interface 22 a tag index result whose upper address matches the upper address of the access target data among the tag index results of each level. If correctable information is included in the output of the ECC check & correction circuit 132 at each level, the pair of correctable information and the corrected tag index result is also output to the third interface 22. If an uncorrectable signal is included, it is also output to the third interface 22.

  If the main control unit 103 in each cell 10 determines that there is no failure in the tag unit 13 in its own cell 10 based on the information received via the third interface 22, it performs normal operation (step 4-2). NO, 4-3). If it is determined that an uncorrectable failure has occurred in the tag unit 13 in the own cell 10 (YES in step 4-2 and NO in 4-4), the process proceeds to step 4-16. If it is determined that a correctable failure has occurred in the tag unit 13 in the own cell 10 (YES in step 4-2 and YES in 4-4), the following processing is performed.

  When the main control unit 103 receives the correctable information and the corrected tag index result, the main control unit 103 registers the lower address included in the correctable information (the lower address used during tag indexing) in the tag swap control unit 104. (Step 4-5), processing for registering the lower address and level included in the correctable information in the tag write-back control unit 106 (Step 4-7), and the lower address included in the correctable information A process of registering the upper address included in the corrected tag index result in the coherency control unit 107 and instructing the issue of the swap transaction (step 4-10) is performed. Note that the processing in step 4-7 may not be performed. Of course, in this case, the processes of steps 4-8 and 4-9 are not performed.

  After the lower address is registered in the tag swap control unit 104 in step 4-5, when the output of the comparison circuit 105 indicates a comparison match, the main control unit 103 determines that the transaction issuer on the second interface 21 is the source of the transaction. If it is the cell 10, a swap processing signal is output to the second interface output arbitration unit 101 via the path 220, and if the issuer is another cell 10, it is sent to the issuer cell 10 via the third interface 22. Cancel information is sent (step 4-14). The tag unit 13 does not perform tag indexing while the output to the comparison circuit 105 indicates a comparison match.

  On the other hand, when the lower address and the higher address are registered and the issuance of the swap transaction is instructed in Step 4-10, the coherency control unit 107 transmits the swap transaction including the lower address and the upper address in the own cell 10 Is issued to each CPU 11 (step 4-11). Upon receiving the swap transaction, each CPU 11 performs a cache flush process and outputs a reply transaction to the second interface 21 (step 4-12).

  When the main control unit 103 in the main pipe 102 receives a reply transaction indicating that the cache flushing process has been completed (step 4-13), the main control unit 103 deletes the lower address registered in the tag swap control unit 104 and performs the swap process. The output of the medium signal is stopped (step 4-6). As a result, the canceled state of the transaction canceled in the main pipe 102 is canceled (step 4-15). When the main control unit 103 receives the reply transaction (step 4-13), the main control unit 103 instructs the tag write-back control unit 106 to set an entry unusable flag in the failure entry of the tag memory 131. As a result, the tag write-back control unit 106 sets an entry unusable flag in the failure entry (entry specified by the lower address and level registered in step 4-7) in the tag memory 131 (step 4-8). . The entry whose entry unusable flag is lit is no longer used (step 4-9). As a result, the degeneration is completed dynamically only at the level of the failure entry of the tag, and the continuous operation becomes possible.

  Next, an operation when the main control unit 103 determines that an uncorrectable failure has occurred in the tag unit 13 in the own cell 10 in step 4-4 will be described. When an uncorrectable failure occurs in the tag unit 13, the error cannot be corrected by the ECC check & correction circuit 132, so it is not known what the correct upper address was. Therefore, for each of the upper addresses, a swap transaction including the upper address and the lower address used during tag indexing is generated, and each generated swap transaction is issued to each CPU 11 in its own cell 10, All cache information having the lower address can be written back to the main storage device 14.

  If the main control unit 103 determines that an uncorrectable failure has occurred in the tag unit 13 in the own cell 10 based on the uncorrectable information received via the third interface 22 (NO in step 4-4), the correction is performed. A process (step 5-1 in FIG. 5) for registering the lower address (lower address used at the time of tag indexing) included in the impossible information in the tag swap control unit 104, and included in the uncorrectable information Processing for registering the lower address and level in the tag write-back control unit 106 (step 5-3), and registering the lower address included in the uncorrectable information in the coherency control unit 107 to instruct to issue a swap transaction. Processing (step 5-6) is performed.

  After the lower address is registered in the tag swap control unit 104 in step 5-1, when the output of the comparison circuit 105 indicates a comparison match, the main control unit 103 determines that the transaction issuer on the second interface 21 If the cell 10, the swap processing signal is output to the second interface output arbitration unit 101 via the path 220, and if the issuer is another cell 10, the issuer of the issuer is sent via the third interface 22. Cancel information is transmitted to the cell 10 (step 5-10). Such processing is continued until the swap processing is completed and the lower address registered in the tag swap control unit 104 is deleted.

  On the other hand, when only the lower address is registered in step 5-6 and the issue of the swap transaction is instructed, the coherency control unit 107 performs swap transaction including the upper address and the lower address for each of the upper addresses. And issues the generated swap transaction to each CPU 11 in the own cell 10 in ascending order from a small address (step 5-7). As a result, the coherency control unit 107 is in a busy state, and subsequent transactions using the coherency control unit 107 are canceled and waited until the busy state is cleared (until the status processing is completed). When the CPU 11 accepts the swap transaction, it performs a cache flush process and returns a reply transaction to the main control unit 103 (step 5-8).

  When the main control unit 103 receives a reply transaction for the largest address from all the CPUs 11 in the own cell 10 (step 5-9), the main control unit 103 deletes the lower address registered in the tag swap control unit 104, The output of the swap processing signal is stopped (step 5-2). As a result, the canceled state of the transaction canceled by the main pipe 102 is canceled (step 5-11). When the main control unit 103 receives a reply transaction for the largest address from all the CPUs 11 (step 5-9), the main control unit 103 sets an entry unusable flag to the tag write-back control unit 106 as a failure entry in the tag memory 131. Instruct to set. As a result, the tag write-back control unit 106 sets the entry unusable flag in the failure entry of the tag memory 131, and also displays the status in each entry having the same lower address as that of the failure entry, with the latest data on the main storage device 14. (Step 5-4). The entry whose entry unusable flag is lit is no longer used (step 5-5). As a result, the degeneration is completed dynamically only at the level of the failure entry of the tag, and the continuous operation becomes possible.

[Effect of the first embodiment]
According to the present embodiment, even when an uncorrectable failure is detected in the tag index result read from the tag memory 131, data coherency can be ensured, so that the operation is continued. Is possible. The reason for this is that when an uncorrectable failure is detected in the tag index result indexed from the tag memory 131, all the CPUs 11 may be related to the tag index result from which the uncorrectable failure is detected. This is because the memory control / coherency control device 12 that instructs to sweep the data to the main storage device 14 is provided.

[Second Embodiment]
Next, a second embodiment of the distributed shared memory multiprocessor system according to the present invention will be described. The present embodiment is characterized in that, when an uncorrectable failure occurs in the tag memory, a subsequent transaction using the coherency control unit is not waited by preventing the coherency control unit from being in a busy state. To do.

  FIG. 6 is a block diagram showing a configuration example of a distributed shared memory multiprocessor system according to the present embodiment. The difference between the present embodiment and the first embodiment shown in FIG. 1 is that a service processor 112 is added and a cell 10 a is provided instead of the cell 10. The cell 10 a is different from the cell 10 in that the memory control / coherency control device 12 a is provided instead of the memory control / coherency control device 12.

  FIG. 7 is a block diagram showing a configuration example of the memory control / coherency control device 12a. The difference from the memory control / coherency control device 12 shown in FIG. 3 is that a cache flush completion register 111 is added, a tag unit 13 a is provided instead of the tag unit 13, and the main control unit 103. The main control unit 103a is provided instead of the above.

  The cache flush completion register 111 stores a flush completion flag indicating whether or not the cache flush process has been completed. This flushing completion flag is set to “1” by the service processor 112 when the cache flushing process is completed, and indicates that the cache flushing process is completed.

  The tag unit 13a outputs the uncorrectable information (including the lower address at the time of tag index and the level of the failure entry) not only to the third interface 22, but also to the service processor 112 via the path 222. This is different from the tag unit 13 of the first embodiment.

  The main control unit 103a recognizes that the cache flushing process in each CPU 11 in the own cell 10a is completed based on the flushing completion flag stored in the cache flushing completion register 111 (the value of the flushing completion flag is “ The main control according to the first embodiment is that the cache flushing process is completed when it becomes 1), and that the flushing completion flag is set to “0” after the completion of the cache flushing process is recognized. This is different from the unit 103.

  When the firmware (FW) in the service processor 112 receives the uncorrectable information from the tag unit 13a via the path 222, for each of the upper addresses, the upper address and the lower address in the uncorrectable information are displayed. A swap transaction is generated, and the generated swap transaction is issued to each CPU 11 in the own cell 10a in ascending order from the smallest address. The swap transaction is sent to each CPU 11 via a path 223 different from the first interface 20. Further, the service processor 112 has a function of setting the flush completion flag in the cache flush completion register 111 to “1” when it is determined that the cache flush process is completed based on the reply transaction from each CPU 11.

[Operation of Second Embodiment]
Next, the operation of the present embodiment will be described. The operation when no failure has occurred in the tag unit 13a and when a correctable failure has occurred in the tag unit 13a is as described with reference to the flowchart of FIG. The operation when an uncorrectable failure occurs in 13a will be described.

  When the main control unit 103a determines that an uncorrectable failure has occurred in the tag unit 13a in the own cell 10a based on the uncorrectable information received via the third interface 22 and its bit position ( Step 4-2 in FIG. 4 is YES and 4-4 is NO). As shown in the flowchart in FIG. 8, the lower address (lower address used during tag indexing) included in the uncorrectable information is tag swapped. A process of registering in the control unit 104 (step 8-1) and a process of registering the lower address and level included in the uncorrectable information in the tag write-back control unit 106 (step 8-3) are performed.

  When the uncorrectable information is sent from the tag unit 13a via the path 222 to the firmware of the service processor 112 (step 8-6), the upper address and the above-described uncorrectable information for all upper addresses. A swap transaction including the lower address in the information is generated, and the generated swap transaction is issued in ascending order from the smallest address to each CPU 11 in the own cell 10a through the path 223 (step 8-7). Each CPU 11 performs a cache flush process according to the swap transaction, and returns a reply transaction to the service processor 112 via the path 223 (step 8-8).

  After the lower address is registered in the tag swap control unit 104 in step 8-1, when the output of the comparison circuit 105 indicates a comparison match, the main control unit 103a determines that the transaction issuer on the second interface 21 is the source of the transaction. If it is the cell 10a, a swap processing signal is output to the second interface output arbitration unit 101 via the path 220. If the issuer is another cell 10a, the issuer of the issuer is sent via the third interface 22. Cancel information is transmitted to the cell 10a (step 8-10). Such processing is continued until the swap processing is completed and the lower address registered in the tag swap control unit 104 is deleted.

  On the other hand, when the service processor 112 receives a reply transaction for the largest address from all the CPUs 11 in the own cell 10a, the service processor 112 sets the flush completion flag in the cache flush completion register 111 to “1” and the cache flush process has been completed. Is displayed (step 8-9).

  When the flush completion flag becomes “1”, the main control unit 103a recognizes that the cache flushing process is completed, deletes the lower address registered in the tag swap control unit 104, and outputs a signal during swap processing. Is stopped (step 8-2). As a result, the canceled state of the transaction canceled in the main pipe 102 is released (step 8-11). Further, in step 8-2, the main control unit 103a also performs a process of changing the flush completion flag in the cache flush completion register 111 to “0”.

  Further, when the sweep-out completion flag becomes “1”, the main control unit 103a instructs the tag write-back control unit 106 to set the entry unusable flag in the failure entry of the tag memory 131. As a result, the tag write-back control unit 106 sets the entry unusable flag in the failure entry of the tag memory 131, and also displays the status in each entry having the same lower address as that of the failure entry, and the latest data is stored on the main storage device 14. (Step 8-4). The entry whose entry unusable flag is lit is no longer used (step 8-5). As a result, the degeneration is completed dynamically only at the level of the failure entry of the tag, and the continuous operation becomes possible.

[Effects of Second Embodiment]
In this embodiment, when there is an uncorrectable failure in the tag memory 131, a swap transaction is issued using the service processor 112. Therefore, as in the first embodiment, an uncorrectable failure is performed. The coherency control unit 107 does not become busy when it occurs. For this reason, subsequent transactions using the coherency control unit 107 are not canceled, and the performance is improved as compared with the first embodiment.

[Third Embodiment]
Next, a third embodiment of the distributed shared memory multiprocessor system according to the present invention will be described. The present embodiment is characterized in that, when an uncorrectable fault occurs in the tag memory, the fault entry in the tag memory can be dynamically degenerated without substantially affecting the normal processing performed by the CPU. And

  In the present embodiment, when an uncorrectable failure occurs in the tag unit 13 in each cell 10 (having the configuration shown in FIG. 3) which is a component of the distributed shared memory multiprocessor system as shown in FIG. This is realized by performing the processing shown in the flowcharts of FIGS. The operation when no failure has occurred in the tag unit 13 and when a correctable failure has occurred in the tag unit 13 is as described with reference to the flowchart of FIG. An operation when an uncorrectable failure occurs in 13 will be described.

  When the main control unit 103 determines that an uncorrectable failure has occurred in the tag unit 13 in the own cell 10 based on the uncorrectable information received via the third interface 22 and its bit position ( Step 4-2 in FIG. 4 is YES and 4-4 is NO). As shown in the flowchart of FIG. 9, P hit is included in the tag index result output from the own cell 10 and the other cell 10 to the third interface 22. It is checked whether or not it exists (step 9-0). That is, it is checked whether there is a tag index result whose status indicates that the latest data is in the cache.

  If there is a P hit (YES in step 9-0), that is, if the access target data exists on the cache 15, the process proceeds to step 9-15. On the other hand, when there is no P hit (NO in step 9-0), that is, when it cannot be determined that the access target data exists in the cache 15, the full address of the transaction used for the tag index is replaced with the tag swap. Processing for registering in the control unit 104 (step 9-1), processing for registering the lower address used at the time of tag indexing and the level of the failure entry in the tag write-back control unit 106 (step 9-3), and a coherency control unit A process of registering the full address in 107 and instructing the issue of a swap transaction (step 9-6) is performed.

  After the full address is registered in the tag swap control unit 104 in step 9-1, if the output of the comparison circuit 105 indicates a comparison match (in this case, the comparison circuit 105 compares the output when the full address matches). If the transaction source on the second interface 21 is the own cell 10, the main control unit 103 is performing swap processing on the second interface output arbitration unit 101 via the path 220. A signal is output, and if the issue source is another cell 10, cancel information is transmitted to the issue source cell 10 via the third interface 22 (step 9-13). Such processing is continued until the swap processing is completed and the full address registered in the tag swap control unit 104 is deleted.

  When the issue of the swap transaction is instructed in step 9-6, the coherency control unit 107 issues a swap transaction including the registered full address to each CPU 11 in the own cell 10 (step 9). -7). When each CPU 11 receives a swap transaction including a full address, the CPU 11 performs a cache flushing process in accordance with the swap transaction, and returns a reply transaction to the main control unit 103 in the main pipe 102 (step 9-8). When the main control unit 103 receives a reply transaction to the effect that the cache flush processing corresponding to the full address from any of the CPUs 11 in the own cell 10 has been completed (step 9-9), the main control unit 103 registers in the tag swap control unit 104. The full address is deleted, and the output of the swap processing in-progress signal is stopped (step 9-2). As a result, the canceled state of the transaction canceled by the main pipe 102 is released (step 9-14). If there is the latest data in the cache 15 of the CPU 11, the data is written back to the main storage device 14, and if there is no latest data, the data in the main storage device 14 is originally the latest. The tag index transaction that has been canceled in (1) can obtain the latest data by accessing the main memory 14.

  When the processing of step 9-6 is completed, the main control unit 103 registers the lower address used at the time of tag indexing in the coherency control unit 107, and performs a swap transaction at a timing when the first interface 20 is not used in normal processing. Instruct to issue. Thereby, the coherency control unit 107 first generates a swap transaction including the upper address and the registered lower address for all upper addresses. Thereafter, the coherency control unit 107 monitors the availability of the first interface 20, and at the timing when the CPU 11 does not use the first interface 20 for normal processing, the generated swap transaction is performed in the own cell 10 in ascending order of addresses. (Step 9-10).

  When each CPU 11 accepts the swap transaction, it performs a cache flush process and returns a reply transaction to the main control unit 103 (step 9-11). When the main control unit 103 receives a reply transaction for the largest address from all the CPUs 11 in its own cell 10 (step 9-12), the main control unit 103 sets an entry unusable flag to the tag write-back control unit 106 in the tag memory 131. Instructs the failure entry to be set. As a result, the tag write-back control unit 106 sets the entry unusable flag in the failure entry of the tag memory 131, and also displays the status in each entry having the same lower address as that of the failure entry, and the latest data is stored on the main storage device 14. (Step 9-4). The entry whose entry unusable flag is lit is no longer used (step 9-5). As a result, the degeneration is completed dynamically only at the level of the failure entry of the tag, and the continuous operation becomes possible.

  Next, the operation when it is determined in step 9-0 that there is a P hit will be described with reference to the flowchart of FIG. When there is a P hit in the tag index result of the own cell 10 or the other cell 10, the main control unit 103 performs a process for accessing the cache 15 of the CPU 11 of the P hit cell (step 10-8). In this embodiment, even if there is a tag failure, if there is a P hit including the failure level, the P hit processing is prioritized. Therefore, the main control unit 103 does not perform the process of registering the lower address used at the time of tag indexing in the tag swap control unit 104 (step 10-1), and the lower address used at the time of tag indexing in the tag write back control unit 106 and Processing for registering the level at which the failure occurred (step 10-2) and processing for instructing the issue of a swap transaction by registering the lower address used at the time of tag indexing in the coherency control unit 107 are performed. Thereby, the coherency control unit 107 first generates a swap transaction including the upper address and the registered lower address for all upper addresses. Thereafter, the coherency control unit 107 monitors the availability of the first interface 20, and at the timing when the CPU 11 does not use the first interface 20 for normal processing, the generated swap transaction is performed in the own cell 10 in ascending order of addresses. Issued to each of the CPUs.

When each CPU 11 accepts a swap transaction, it performs a cache flush process and returns a reply transaction to the main control unit 103 (step 10-6). When the main control unit 103 receives a reply transaction for the largest address from all the CPUs 11 in its own cell 10 (step 10-7), the main control unit 103 sets an entry unusable flag to the tag write-back control unit 106 in the tag memory 131. Instructs the failure entry to be set. As a result, the tag write-back control unit 106 sets the entry unusable flag in the failure entry of the tag memory 131, and also displays the status in each entry having the same lower address as that of the failure entry, with the latest data on the main storage device 14. (Step 10-3). The entry whose entry unusable flag is lit is no longer used (step 10-4). As a result, the degeneration is completed dynamically only at the level of the failure entry of the tag, and the continuous operation becomes possible.

  In the first embodiment, instead of step 5-7 in FIG. 5, the processing in step 9-10 in FIG. 9 described in the third embodiment may be performed.

[Effect of the third embodiment]
In this embodiment, when an uncorrectable failure occurs in the tag memory 131, the normal process performed by the CPU 11 is prioritized over the cache flush process, and the cache flush process is performed aiming at the gap of the normal process of the CPU 11. This makes it possible to guarantee data coherency with almost no degradation in processing performance.

  The present invention can be applied to a multiprocessor system that includes a plurality of CPUs having a cache memory, such as a distributed shared memory multiprocessor system, and in which it is necessary to guarantee data coherency.

1 is a block diagram showing a configuration example of a first embodiment of a distributed shared memory multiprocessor system according to the present invention. FIG. 3 is a block diagram illustrating a configuration example of a tag unit 13. FIG. 3 is a block diagram illustrating a configuration example of a memory control / coherency control device 12. FIG. 10 is a flowchart illustrating a processing example of the first exemplary embodiment when a correctable failure mainly occurs in a tag memory. 10 is a flowchart illustrating a processing example of the first exemplary embodiment when an uncorrectable failure occurs mainly in the tag memory. It is a block diagram which shows the structural example of 2nd Embodiment of the distributed shared memory type | mold multiprocessor system concerning this invention. It is a block diagram which shows the structural example of the memory control / coherency control apparatus 12a used in 2nd Embodiment. 10 is a flowchart illustrating a processing example of the second exemplary embodiment when an uncorrectable failure occurs mainly in the tag memory. 10 is a flowchart illustrating a processing example of the third exemplary embodiment when an uncorrectable failure occurs mainly in the tag memory 131 and there is no P hit. 10 is a flowchart illustrating a processing example of the third exemplary embodiment mainly when correction is impossible in the tag memory 131 and there is a P hit.

Explanation of symbols

10, 10a ... cell 11 ... CPU
DESCRIPTION OF SYMBOLS 12, 12a ... Memory control / coherency control apparatus 101 ... 2nd interface output arbitration part 102 ... Main pipe 103, 103a ... Main control part 104 ... Tag swap control part 105 ... Comparison circuit 106 ... Tag write-back control part 107 ... Coherency control Unit 108 ... main memory access control unit 111 ... cache flush completion register 112 ... service processor 13, 13a ... tag unit 131 ... tag memory 132 ... ECC check & correction circuit 133 ... comparison circuit 14 ... main storage device 15 ... cache (cache memory) )
20 ... 1st interface 21 ... 2nd interface 22 ... 3rd interface

Claims (13)

A main storage device;
A plurality of CPUs equipped with a cache memory in which a copy of a part of the data stored in the main storage device is stored;
A tag memory that manages the state of data in each cache memory, and a memory control / coherency control device that guarantees data coherency using the tag memory;
When the memory control / coherency control device detects an uncorrectable fault in the tag index result indexed from the tag memory, the CPU is associated with the tag index result in which the uncorrectable fault is detected for each CPU. A multiprocessor system characterized by instructing that main data be swept out of all data that may be generated. The multiprocessor system of claim 1, wherein
The memory control / coherency control device includes:
A tag memory stored in an entry corresponding to the lower address of the data, an upper address of the data stored in each cache memory, and a status indicating whether the data is the latest data;
A fault check circuit that checks whether there is an uncorrectable fault in the tag index result indexed from the tag memory by the lower address of the transaction;
When the failure check circuit determines that there is an uncorrectable failure in the tag index result, the lower address of the data stored in the cache memory is used for tag indexing for each CPU. A multiprocessor system comprising: a coherency control unit that instructs to sweep out all data that matches a lower address to a main storage device. The multiprocessor system according to claim 2, wherein
The coherency control unit generates, for all upper addresses, a swap transaction including the upper address and the lower address used at the time of tag indexing, and issues the generated swap transaction to each CPU. A featured multiprocessor system. The multiprocessor system according to claim 2, wherein
The coherency control unit generates a swap transaction including the upper address and the lower address used at the time of the tag index for all upper addresses, and the CPU does not perform normal processing on the generated swap transaction. Sometimes a multiprocessor system is issued to each of the CPUs. The multiprocessor system according to claim 2, wherein
A service processor, and when the failure check circuit determines that there is an uncorrectable failure in the tag index result, the service processor stores the CPU in the cache memory instead of the coherency control unit A multiprocessor system for instructing main memory to sweep out all data whose lower address matches the lower address used at the time of tag indexing. The multiprocessor system according to claim 2, wherein
The coherency control unit is
When it is determined by the failure check circuit that there is an uncorrectable failure in the tag index result, and based on the contents of the tag memory, it cannot be determined that the latest data to be accessed by the transaction exists on the cache memory Immediately, issue a swap transaction including the full address of the transaction to the CPUs, and then generate a swap transaction including the upper address and the lower address of the transaction for all upper addresses. When the CPU is not performing normal processing, the generated swap transaction is issued to each CPU, the failure check circuit determines that the tag index result has an uncorrectable fault, and the tag memory Cache based on content If it is determined that there is the latest data to be accessed by the transaction on the memory, a swap transaction including the upper address and the lower address of the transaction is generated for all upper addresses, and each CPU A multiprocessor system, wherein the generated swap transaction is issued to each CPU when normal processing is not performed. Data coherency in a multiprocessor system comprising a main storage device and a plurality of CPUs equipped with a cache memory storing a copy of a portion of the data stored in the main storage device is stored in each cache memory. A memory control / coherency control device that uses a tag memory to manage the data state of
When an uncorrectable failure is detected in the tag index result indexed from the tag memory, all data that may be related to the tag index result in which the uncorrectable failure is detected are stored for each CPU. A memory control / coherency control device having a configuration for instructing main memory to sweep out. The memory control / coherency control device according to claim 7,
A tag memory stored in an entry corresponding to the lower address of the data, an upper address of the data stored in each cache memory, and a status indicating whether the data is the latest data;
A fault check circuit that checks whether there is an uncorrectable fault in the tag index result indexed from the tag memory by the lower address of the transaction;
When the failure check circuit determines that there is an uncorrectable failure in the tag index result, the lower address of the data stored in the cache memory is used for tag indexing for each CPU. A memory control / coherency control device comprising: a coherency control unit that instructs to sweep out all data that matches a lower address to a main storage device. The memory control / coherency control device according to claim 8,
The coherency control unit generates, for all upper addresses, a swap transaction including the upper address and the lower address used at the time of tag indexing, and issues the generated swap transaction to each CPU. Feature memory control / coherency control device. The memory control / coherency control device according to claim 8,
The coherency control unit generates a swap transaction including the upper address and the lower address used at the time of the tag index for all upper addresses, and the CPU does not perform normal processing on the generated swap transaction. Sometimes a memory control / coherency control device is issued to each of the CPUs. The memory control / coherency control device according to claim 8,
The coherency control unit is
When it is determined by the failure check circuit that there is an uncorrectable failure in the tag index result, and based on the contents of the tag memory, it cannot be determined that the latest data to be accessed by the transaction exists on the cache memory Immediately, issue a swap transaction including the full address of the transaction to the CPUs, and then generate a swap transaction including the upper address and the lower address of the transaction for all upper addresses. When the CPU is not performing normal processing, the generated swap transaction is issued to each CPU, the failure check circuit determines that the tag index result has an uncorrectable fault, and the tag memory Cache based on content If it is determined that there is the latest data to be accessed by the transaction on the memory, a swap transaction including the upper address and the lower address of the transaction is generated for all upper addresses, and each CPU A memory control / coherency control device that issues the generated swap transaction to each of the CPUs when normal processing is not performed. A coherency guarantee method for guaranteeing data coherency in a multiprocessor system comprising a main storage device and a plurality of CPUs equipped with a cache memory storing a copy of a part of the data stored in the main storage device There,
When an uncorrectable failure is detected in the tag index result indexed from the tag memory that manages the state of data in each cache memory, the tag index result in which the uncorrectable failure is detected for each CPU A coherency guarantee method characterized by instructing main memory to sweep out all data that may be related to. A coherency guarantee method for guaranteeing data coherency in a multiprocessor system comprising a main storage device and a plurality of CPUs equipped with a cache memory storing a copy of a part of the data stored in the main storage device There,
The tag memory in which the upper address of the data stored in each cache memory and the status indicating whether or not the data is the latest data is stored in the entry corresponding to the lower address of the data is represented as the lower address of the transaction. When an uncorrectable failure is detected in the tag index result obtained by indexing according to the above, the lower address of the data stored in the cache memory is used for tag indexing for each CPU. A coherency guarantee method characterized by instructing that all data matching a lower address be swept out to the main memory, and in accordance with the instruction, each CPU sweeps out the corresponding data to the main memory.

Images