JP2014075856A - Control circuit of power supply, power-supply device, electronic apparatus, and method of controlling power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control circuit of a power supply capable of improving conversion efficiency.SOLUTION: A DC-DC converter 1 generates an output voltage Vo at an output terminal Po by switching an output transistor T1 connected between an input terminal Pi receiving an input voltage Vin and a node LX. A control circuit 3 of the DC-DC converter 1 has a delay circuit 20 controlling the lowest frequency of the switching frequency of the output transistor T1 in response to a control signal SG1 that switching-controls the output transistor T1, and a charge pump 30. The charge pump 30 regenerates electrical charges accumulated in a capacitor C1 connected between the ground and the output terminal Po to the input terminal Pi according to the control signal SG1 when the switching frequency is less than or equal to a predetermined frequency.

Description

  The present invention relates to a power supply control circuit, a power supply device, an electronic device, and a power supply control method.

  Conventionally, a DC-DC converter is used as a power source in electronic devices such as personal computers and audio devices. This DC-DC converter controls on / off of a switching element to convert a DC input voltage into a DC output voltage of a desired voltage level and output it (for example, refer to Patent Document 1).

  As a control method of the DC-DC converter, there are a separately excited type that performs a switching operation (oscillation operation) in synchronization with a clock signal, and a self-excited type that performs an oscillation operation with a time constant of the system of the DC-DC converter. In the separately excited DC-DC converter, since the switching frequency of the switching element is determined by the clock signal generated by the oscillator, the switching frequency is constant. On the other hand, in the self-excited DC-DC converter, as shown in FIG. 12, the switching frequency of the switching element varies depending on the load weight, that is, the load current supplied to the load, and the load is very light. When the load current approaches 0 A, the switching frequency may be applied to the audible range (for example, 20 Hz to 20 KHz) (see broken line). Then, noise in the audible range is generated by switching of the switching element, and thus it is difficult to use the self-excited DC-DC converter as a power supply device for electronic equipment such as audio equipment.

  In view of this, there has been proposed a technique for limiting the switching frequency so as not to be lowered below a predetermined frequency as shown by a solid line in FIG. Reference 2).

  FIG. 13 shows an example of a conventional self-excited DC-DC converter, specifically, an on-time fixed type DC-DC converter. The DC-DC converter 4 is an asynchronous rectification type DC-DC converter, and includes a converter unit 5 and a control circuit 6. The converter unit 5 includes an output transistor T11 that is a switching element, a diode D11, a coil L11, and a smoothing capacitor C11. The converter unit 5 generates an output voltage Vo1 obtained by stepping down the input voltage Vin1, and supplies the output voltage Vo1 to the load RL1.

  The comparator 50 of the control circuit 6 compares the feedback voltage VFB1 generated by dividing the output voltage Vo1 by the resistors R11 and R12 with the reference voltage Vr1. The comparator 50 generates an output signal S11 of L level (low potential power supply voltage level, eg, ground voltage level) when the feedback voltage VFB1 is higher than the reference voltage Vr1, and the feedback voltage VFB1 is higher than the reference voltage Vr1. When it is low, an output signal S11 of H level (high potential power supply voltage level, for example, input voltage Vin1 level) is generated.

  The output signal S11 of the comparator 50 is supplied to the set terminal S of the RS-flip flop circuit (RS-FF circuit) 51. The RS-FF circuit 51 outputs an L level control signal SG11 from the inverting output terminal XQ in response to the H level output signal S11. In response to the L level control signal SG11, the output transistor T11 is turned on. Further, in response to the L level control signal SG11, the one-shot circuit 52 outputs the L level output signal S12 for a certain period of time, and outputs the H level output signal S12 after the certain period of time has elapsed. In response to the H level output signal S12, the RS-FF circuit 51 outputs an H level control signal SG11 from the inverting output terminal XQ. In response to the H level control signal SG11, the output transistor T11 is turned off.

  The control circuit 6 has a delay circuit 53 and a discharge circuit 54 including a resistor R13 and a discharge transistor T12. The control signal SG11 from the RS-FF circuit 51 is input to the delay circuit 53. The delay circuit 53 immediately transitions from the H level to the L level in response to the transition of the control signal SG11 from the H level to the L level, and in response to the transition of the control signal SG11 from the L level to the H level, A control signal SG12 that transitions from the L level to the H level is generated at a timing delayed by a predetermined time from the transition. Here, the predetermined time is in a frequency range where the minimum frequency fmin (see FIG. 12) of the switching frequency of the output transistor T11 can become the noise at a light load (for example, an audible range of audio equipment: about 20 Hz to 20 KHz). The frequency is set to be higher than the upper limit value. The control signal SG12 is supplied to the gate of the transistor T12 in the discharge circuit 54.

  In such a DC-DC converter 4, the delay circuit 53 and the discharge circuit 54 are set so that the minimum frequency fmin (see FIG. 12) of the switching frequency of the output transistor T11 does not enter a frequency range that may cause noise. Yes. That is, in the DC-DC converter 4, when the switching frequency (switching cycle) is lowered to a cycle determined by the delay circuit 53 at light load, the transistor T12 of the discharge circuit 54 is turned on, and the excessive charge of the capacitor C11 is discharged to the ground. The Thereby, it can suppress that a switching frequency falls until it enters into the frequency range which can become noise.

JP 2011-149777 A JP 2011-010450 A

  However, in the DC-DC converter 4, the minimum frequency fmin of the switching frequency is clamped to a predetermined frequency (a frequency determined according to the delay time of the delay circuit 53) by discharging the excessive charge of the capacitor C <b> 11 to the ground. . For this reason, there is a problem that the loss increases as the charge of the capacitor C11 is discharged to the ground, and the conversion efficiency of the DC-DC converter 4 decreases.

  According to one aspect of the present invention, there is provided a power supply control circuit that generates an output voltage at an output terminal by switching a switching element connected between an input terminal to which an input voltage is supplied and a first node. A control unit that controls a minimum frequency of the switching frequency of the switching element in response to a control signal for controlling the switching of the switching element, and the control unit is configured such that when the switching frequency becomes a predetermined frequency or less. And a first circuit that regenerates the charge accumulated in the first capacitor connected between the first power supply line having a potential different from the input voltage and the output terminal according to the control signal to the input terminal. .

  According to one aspect of the present invention, there is an effect that the conversion efficiency can be improved.

The block circuit diagram which shows the DC-DC converter of one Embodiment. A circuit diagram showing a charge pump of one embodiment. The circuit diagram showing the delay circuit of one embodiment. The wave form diagram which shows the operation | movement of the delay circuit of one Embodiment. The circuit diagram which shows the delay circuit of a modification. The wave form diagram which shows the operation | movement of the DC-DC converter of one Embodiment. The circuit diagram which shows the charge pump of a modification. The wave form diagram which shows the operation | movement of the DC-DC converter which has a charge pump of a modification. The circuit diagram which shows the delay circuit of a modification. (A)-(c) is a wave form diagram which shows operation | movement of the delay circuit of a modification. 1 is a schematic configuration diagram illustrating an electronic device. The characteristic view which shows the relationship between switching frequency and load current. The block circuit diagram which shows the conventional DC-DC converter.

Hereinafter, an embodiment will be described with reference to FIGS.
A DC-DC converter 1 shown in FIG. 1 is a self-excited DC-DC converter, specifically, a fixed on-time type DC-DC converter. The DC-DC converter 1 includes a converter unit 2 that generates an output voltage Vo obtained by stepping down the input voltage Vin, and a control circuit 3 that controls the converter unit 2.

The converter unit 2 includes an output transistor T1, a diode D1, a coil L1, and a smoothing capacitor C1.
The output transistor T1 is, for example, a P channel MOS transistor. A control signal SG1 is supplied from the control circuit 3 to the gate of the output transistor T1. The output transistor T1 has a first terminal (source) connected to the input terminal Pi to which the input voltage Vin is supplied, and a second terminal (drain) connected to the cathode of the diode D1. The anode of the diode D1 is connected to a power supply line (here, ground) having a potential lower than the input voltage Vin. As described above, the output transistor T1 and the diode D1 are connected in series between the input terminal Pi and the ground (first power supply line).

  A node LX between the output transistor T1 and the diode D1 is connected to the first terminal of the coil L1. The second terminal of the coil L1 is connected to the output terminal Po. As described above, the output transistor T1 and the coil L1 are connected in series between the input terminal Pi and the output terminal Po. The second terminal of the coil L1 is connected to the first terminal of the capacitor C1, and the second terminal of the capacitor C1 is connected to the ground. The capacitor C1 is included in a smoothing circuit that smoothes the output voltage Vo.

  In such a converter unit 2, the output transistor T <b> 1 is controlled to be turned on / off based on the control signal SG <b> 1 from the control circuit 3, so that the output voltage Vo lower than the input voltage Vin is generated at the output terminal Po. Specifically, when the output transistor T1 is turned on, the input terminal Pi is connected to the output terminal Po through the output transistor T1 and the coil L1, so that a current path from the input terminal Pi to the output terminal Po through the coil L1 is formed. . Therefore, during the ON period of the output transistor T1, the coil current IL corresponding to the potential difference between the input voltage Vin and the output voltage Vo flows through the coil L1, and energy is accumulated in the coil L1. When the output transistor T1 is turned off, the ground is connected to the output terminal Po through the diode D1 and the coil L1, so that a current path from the ground to the output terminal Po through the diode D1 and the coil L1 is formed. For this reason, in the off period of the output transistor T1, the energy stored in the coil L1 in the on period is released toward the output terminal Po, and an induced current flows through the coil L1. By such an operation, an output voltage Vo that is stepped down from the input voltage Vin is generated at the output terminal Po. The output voltage Vo is supplied to a load RL connected to the output terminal Po. Note that a load current Io is also supplied to the load RL.

  Based on the output voltage Vo fed back from the converter unit 2, the control circuit 3 generates a control signal SG1 for on / off control (switching control) of the output transistor T1 so that the output voltage Vo approaches the target voltage. The control circuit 3 includes resistors R1 and R2, a comparator 10, an RS-flip flop circuit (RS-FF circuit) 11, a one-shot circuit 12, a delay circuit 20, and a charge pump 30. Yes.

  A feedback voltage VFB corresponding to the output voltage Vo is supplied to the inverting input terminal of the comparator 10. In the present embodiment, the feedback voltage VFB generated by the resistors R1 and R2 is supplied to the inverting input terminal of the comparator 10. Specifically, the output voltage Vo is fed back by connecting the output terminal Po to the first terminal of the resistor R1. The second terminal of the resistor R1 is connected to the first terminal of the resistor R2, and the second terminal of the resistor R2 is connected to the ground. A connection point between the resistors R1 and R2 is connected to the inverting input terminal of the comparator 10. Here, the resistors R1 and R2 generate a feedback voltage VFB obtained by dividing the output voltage Vo according to the respective resistance values. The value of the feedback voltage VFB corresponds to the ratio of the resistance values of the resistors R1 and R2 and the potential difference between the output voltage Vo and the ground. Therefore, the resistors R1 and R2 generate a feedback voltage VFB that is proportional to the output voltage Vo.

  A reference voltage Vr generated by the reference power supply E1 is supplied to the non-inverting input terminal of the comparator 10. The voltage value of the reference voltage Vr is set according to the target value (target voltage) of the output voltage Vo.

  The comparator 10 generates an output signal S1 corresponding to the comparison result between the feedback voltage VFB and the reference voltage Vr. For example, the comparator 10 generates the L level output signal S1 when the feedback voltage VFB is higher than the reference voltage Vr. The comparator 10 generates an H level output signal S1 when the feedback voltage VFB is lower than the reference voltage Vr.

  The output signal S1 of the comparator 10 is input to the set terminal S of the RS-FF circuit 11. The output signal S2 output from the one-shot circuit 12 is supplied to the reset terminal R of the RS-FF circuit 11. The RS-FF circuit 11 outputs an L level control signal SG1 from the inverting output terminal XQ in response to the H level output signal S1. Further, the RS-FF circuit 11 outputs an H level control signal SG1 from the inverting output terminal XQ in response to the H level output signal S2. That is, for the RS-FF circuit 11, the H level output signal S1 is a set signal, and the H level output signal S2 is a reset signal. The control signal SG1 output from the RS-FF circuit 11 is supplied to the gate of the output transistor T1 and to the one-shot circuit 12 and the delay circuit 20. The output transistor T1 is turned off in response to the H level control signal SG1, and is turned on in response to the L level control signal SG1.

  The one-shot circuit 12 outputs the L-level output signal S2 to the reset terminal R of the RS-FF circuit 11 for a predetermined time in response to the transition of the control signal SG1 from the H level to the L level. When a certain time has elapsed, the one-shot circuit 12 outputs an H-level output signal S2 (reset signal) to the reset terminal R of the RS-FF circuit 11.

  As described above, the RS-FF circuit 11 and the one-shot circuit 12 output the control signal SG1 at the L level for a certain time in response to the output signal S1 at the H level, and turn on the output transistor T1 for the certain time. When a predetermined time has elapsed, in response to the H level output signal S2 output from the one-shot circuit 12, the RS-FF circuit 11 outputs the H level control signal SG1 and turns off the output transistor T1. . That is, the RS-FF circuit 11 and the one-shot circuit 12 are pulse generators that output an on-pulse (L-level control signal SG1) having a fixed pulse width to the output transistor T1 based on the H-level output signal S1. Specifically, the RS-FF circuit 11 and the one-shot circuit 12 receive the control signal SG1 whose on-pulse width is constant and whose frequency (cycle) varies according to the comparison result between the feedback voltage VFB and the reference voltage Vr. Generate.

  A reference voltage Vc is supplied to the delay circuit 20 together with the control signal SG1 from the RS-FF circuit 11. In response to the transition of the control signal SG1 from the L level (first level) to the H level (second level), the delay circuit 20 responds to a predetermined time A1 corresponding to the reference voltage Vc from the transition (see FIG. 4). A delay signal SG2 that makes a transition from the L level to the H level is generated at a timing delayed by an amount of time. The delay circuit 20 generates a delay signal SG2 that immediately transitions from the H level to the L level in response to the transition of the control signal SG1 from the H level to the L level. Here, the predetermined time A1 is, for example, a frequency range where the minimum frequency fmin (see FIG. 12) of the switching frequency of the output transistor T1 can become noise in an electronic device to which the DC-DC converter 1 is applied (for example, an audio device audible) The frequency (first frequency) is set to be higher than the upper limit value (range: about 20 Hz to 20 KHz).

  The delay signal SG <b> 2 is supplied from the delay circuit 20 to the charge pump 30. For example, when the load frequency of the output transistor T1 is equal to or lower than the second frequency higher than the first frequency at the time of light load, the charge pump 30 is excessively accumulated in the capacitor C1 based on the delay signal SG2. Charge is regenerated at the input terminal Pi. The charge pump 30 includes a capacitive element C2 provided between the node LX and the output terminal Po, a first switch circuit SW1 provided between the node LX and the capacitive element C2, a capacitive element C2, and an output. A second switch circuit SW2 provided between the terminal Po and a diode D2 provided between the second switch circuit SW2 and the input terminal Pi are provided.

  The first switch circuit SW1 has a first terminal connected to the node LX and a second terminal connected to the ground. The common terminal of the first switch circuit SW1 is connected to the first terminal of the capacitive element C2. The second terminal of the capacitive element C2 is connected to the common terminal of the second switch circuit SW2. The second switch circuit SW2 has a first terminal connected to the anode of the diode D2, and a second terminal connected to the output terminal Po. The cathode of the diode D2 is connected to the input terminal Pi.

  In the first switch circuit SW1 and the second switch circuit SW2, the connection between the common terminal and the first terminal or the second terminal is switched in response to the delay signal SG2. More specifically, in response to the H level delay signal SG2, the common terminal and the second terminal of the first switch circuit SW1 are connected, and the common terminal and the second terminal of the second switch circuit SW2 are connected ( First state). For this reason, the first terminal of the capacitive element C2 is connected to the ground via the first switch circuit SW1, and the second terminal of the capacitive element C2 is connected to the output terminal Po via the second switch circuit SW2. Thereby, the electric charge accumulated in the capacitor C1 connected to the output terminal Po is transitioned to the capacitive element C2. Thereafter, in response to the delay signal SG2 of L level, the common terminal and the first terminal of the first switch circuit SW1 are connected, and the common terminal and the first terminal of the second switch circuit SW2 are connected (the second terminal). State). For this reason, the first terminal of the capacitive element C2 is connected to the node LX via the first switch circuit SW1, and the second terminal of the capacitive element C2 is connected to the diode D2 via the second switch circuit SW2. At this time, when the voltage of the second terminal of the capacitive element C2 (the anode of the diode D2) is higher than the voltage value obtained by adding the output voltage Vo to the voltage of the node LX (here, the input voltage Vin), that is, the input voltage Vin. The electric charge accumulated in the capacitive element C2 is discharged toward the input terminal Pi through the diode D2. That is, in this case, the charge accumulated in the capacitive element C2 is regenerated at the input terminal Pi.

  In this embodiment, the output transistor T1 is an example of a switching element, the capacitor C1 is an example of a first capacitor, the delay circuit 20 and the charge pump 30 are examples of a control unit, the charge pump 30 is an example of a first circuit, and the node LX Is an example of a first node.

Here, a specific internal configuration example of the charge pump 30 (particularly, the first switch circuit SW1 and the second switch circuit SW2) will be described.
As shown in FIG. 2, the first switch circuit SW1 has a P-channel MOS transistor T31 and an N-channel MOS transistor T32. The transistor T31 has a first terminal (source) connected to the node LX and a second terminal (drain) connected to the first terminal (drain) of the transistor T32. A second terminal (source) of the transistor T32 is connected to the ground. The delay signal SG2 is supplied to the gates (control terminals) of these transistors T31 and T32. The node between these transistors T31 and T32 is connected to the first terminal of the capacitive element C2.

  The second switch circuit SW2 has a P-channel MOS transistor T33 and an N-channel MOS transistor T34. The transistor T33 has a first terminal (source) connected to the anode of the diode D2, and a second terminal (drain) connected to the second terminal (drain) of the transistor T34. A second terminal (source) of the transistor T34 is connected to the output terminal Po. The delay signal SG2 is supplied to the gates (control terminals) of these transistors T33 and T34. The node between these transistors T33 and T34 is connected to the second terminal of the capacitive element C2.

  In such a charge pump 30, N channel MOS transistors T32 and T34 are turned on and P channel MOS transistors T31 and T33 are turned off in response to the H level delay signal SG2 (first state). For this reason, the first terminal of the capacitive element C2 is connected to the ground via the transistor T32, and the second terminal of the capacitive element C2 is connected to the output terminal Po via the transistor T34. As a result, current flows from the output terminal Po to the ground through the transistor T34 turned on, the capacitive element C2 and the turned on transistor T32 (see the solid line arrow), and the charge accumulated in the capacitor C1 connected to the output terminal Po is capacitance. Transition to the element C2. In response to the L level delay signal SG2, N channel MOS transistors T32 and T34 are turned off, and P channel MOS transistors T31 and T33 are turned on (second state). For this reason, the first terminal of the capacitive element C2 is connected to the node LX via the transistor T31, and the second terminal of the capacitive element C2 is connected to the diode D2 via the transistor T33. At this time, if the voltage of the second terminal (the anode of the diode D2) of the capacitive element C2 is higher than the voltage value obtained by adding the output voltage Vo to the voltage of the node LX (here, the input voltage Vin), the node LX Current flows to the input terminal Pi through the transistor T31, the capacitive element C2, the transistor T33 that is turned on, and the diode D2 (see the dashed line arrow). Then, the electric charge accumulated in the capacitive element C2 is discharged toward the input terminal Pi through the diode D2.

  The transistor T31 is an example of a first switch, the transistor T32 is an example of a second switch, the transistor T33 is an example of a third switch, and the transistor T34 is an example of a fourth switch.

Next, an example of the internal configuration of the delay circuit 20 will be described.
As shown in FIG. 3, the delay circuit 20 includes an inverter circuit 21, an N-channel MOS transistor T21, a P-channel MOS transistor T22, a current source 22, a capacitor C21, a comparator 23, and a reference power supply E2. Have.

  A control signal SG1 is supplied to the inverter circuit 21. The inverter circuit 21 logically inverts the control signal SG1 to generate an inverted signal XSG1, and supplies the inverted signal XSG1 to the gates of the transistors T21 and T22.

  The source of the transistor T22 is connected to a power supply line (second power supply line) to which the bias voltage VB is supplied. Here, the bias voltage VB is, for example, a voltage (such as a power supply voltage on the high potential side) generated by a power supply circuit (not shown) or the input voltage Vin. The drain of the transistor T22 is connected to the first terminal of the current source 22.

  A control signal S21 is supplied to the current source 22 from the outside. The current source 22 passes a current I21 having a current value corresponding to the control signal S21. That is, the current source 22 varies the current value of the current I21 according to the control signal S21. The second terminal of the current source 22 is connected to the drain of the transistor T21. The source of the transistor T21 is connected to the ground. A capacitor C21 is connected in parallel with the transistor T21. Specifically, the first terminal of the capacitor C21 is connected to a node N21 between the current source 22 and the transistor T21, and the second terminal of the capacitor C21 is connected to the ground.

  The node N21 is connected to the non-inverting input terminal of the comparator 23. Therefore, the voltage VN21 of the node N21 (the voltage of the first terminal of the capacitor C21) is supplied to the non-inverting input terminal of the comparator 23. The reference voltage Vc generated by the reference power supply E2 is supplied to the inverting input terminal of the comparator 23.

  The comparator 23 generates the delay signal SG2 corresponding to the comparison result between the voltage VN21 and the reference voltage Vc. For example, the comparator 23 generates the L-level delay signal SG2 when the voltage VN21 is lower than the reference voltage Vc. The comparator 23 generates an H level delay signal SG2 when the voltage VN21 is higher than the reference voltage Vc. The delay signal SG2 is supplied to the charge pump 30 (see FIG. 1).

  The transistor T22 is an example of a fifth switch, the transistor T21 is an example of a sixth switch, the capacitor C21 is an example of a second capacitor, and the current I21 is an example of a first current.

The operation of the delay circuit 20 will be described with reference to FIG. In FIG. 4, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.
At time t1, when the control signal SG1 transits from H level to L level, the inverted signal XSG1 transits from L level to H level. In response to the H level inversion signal XSG1, the transistor T21 is turned on and the transistor T22 is turned off. When the transistor T21 is turned on, since both terminals of the capacitor C21 are connected to each other, the voltage VN21 at the first terminal (node N21) of the capacitor C21 becomes the ground level. As a result, the voltage VN21 becomes lower than the reference voltage Vc, so that the delay signal SG2 output from the comparator 23 transitions from the H level to the L level. Thus, in the delay circuit 20, when the control signal SG1 transits from the H level to the L level, the delay signal SG2 transits immediately from the H level to the L level. At this time, the transistor T22 is turned off and the supply of the bias voltage VB to the current source 22 is stopped, so that the current I21 can be prevented from flowing to the ground through the transistor T21 that is turned on. That is, by turning off the transistor T22, current consumption when the transistor T21 is turned on can be reduced.

  Subsequently, at time t2, when the control signal SG1 transits from L level to H level, the inverted signal XSG1 transits from H level to L level. In response to the inverted signal XSG1 at L level, the transistor T21 is turned off and the transistor T22 is turned on. Then, the capacitor C21 is charged by the current I21 supplied from the current source 22. As a result, the voltage VN21 at the node N21 rises from the ground level with a predetermined slope corresponding to the current value of the current I21.

  Next, when the voltage VN21 at the node N21 becomes higher than the reference voltage Vc at the time t3 when the predetermined time A1 has elapsed from the time t2, the delay signal SG2 output from the comparator 23 is changed from the L level to the H level. Thus, in the delay circuit 20, when the control signal SG1 transits from the L level to the H level, the delay signal SG2 transits from the L level to the H level at a timing delayed by a predetermined time A1 from the transition (time t2). . Here, the predetermined time A1 is a time for the voltage VN21 to rise from the ground level to the reference voltage Vc. Therefore, the predetermined time A1 is set according to the voltage value of the reference voltage Vc, the current value of the current I21, and the capacitance value of the capacitor C21. In other words, the delay circuit 20 can adjust the predetermined time A1 to a desired time by adjusting the voltage value of the reference voltage Vc and the current value of the current I21.

  The delay circuit 20 may be provided with a buffer circuit 24 instead of the comparator 23 as shown in FIG. In this case, the predetermined time A1 is set according to the logical threshold value of the buffer circuit 24, the current value of the current I21, and the capacitance value of the capacitor C21. Therefore, in such a delay circuit 20, the predetermined time A1 can be adjusted to a desired time by adjusting the current value of the current I21 set by the control signal S21, for example.

  Next, the operation of the DC-DC converter 1 will be described. First, the operation of the DC-DC converter 1 at a heavy load in which the amount of power supply is large and the peak value of the load current Io is high will be briefly described.

  When the output voltage Vo rises based on the ON operation of the output transistor T1 and the output transistor T1 is turned off, the energy stored in the coil L1 is released. When the energy stored in the coil L1 decreases and the output voltage Vo decreases and the divided voltage (feedback voltage VFB) by the resistors R1 and R2 becomes lower than the reference voltage Vr, the comparator 10 outputs an H level output signal S1. Is output. Then, in response to the H level output signal S1, an L level control signal SG1 is output from the RS-FF circuit 11 for a certain period of time. As a result, the output transistor T1 is turned on for a predetermined time. In such on / off operation of the output transistor T1, when the output voltage Vo when the output transistor T1 is turned off increases, the feedback voltage VFB at that time increases, and the output signal S1 of the comparator 10 becomes H level. Therefore, the off time of the output transistor T1 becomes long. Further, when the output voltage Vo when the output transistor T1 is turned off is lowered, the feedback voltage VFB at that time is lowered, and the time until the output signal S1 of the comparator 10 becomes H level is shortened. The off time of T1 is shortened. By such an operation, the output transistor T1 is turned on for a predetermined time and the off timing at which the output transistor T1 is turned off is determined based on the output voltage Vo. Then, the off timing changes based on the level of the output voltage Vo, the switching frequency of the output transistor T1 changes, and the output voltage Vo is maintained at the target voltage (constant voltage) based on the reference voltage Vr.

  Next, the operation of the DC-DC converter 1 at a light load when the amount of power supply is small and the peak value of the load current Io is low will be described. Specifically, the operation of the DC-DC converter 1 when the coil current IL, in which the switching frequency of the output transistor T1 tends to decrease, is in the discontinuous current mode (DCM) will be described with reference to FIG. In FIG. 6, the vertical axis and the horizontal axis are enlarged or reduced as appropriate for the sake of brevity.

  As shown in FIG. 6, when the control signal SG1 transitions from the H level to the L level at time t10, the output transistor T1 is turned on in response to the control signal SG1 of the L level. Based on the ON operation of the output transistor T1, the output voltage Vo and the feedback voltage VFB increase with a predetermined slope as time passes, and the coil current IL increases with a predetermined slope as time passes.

  When the H level control signal SG1 is output for a certain time from time t10 (time t11), the control signal SG1 transitions from the L level to the H level. In response to the H level control signal SG1, the output transistor T1 is turned off. Based on the off operation of the output transistor T1, the output voltage Vo and the feedback voltage VFB decrease with a predetermined slope as time passes, and the coil current IL decreases with a predetermined slope as time passes. In response to the H level control signal SG1, the transistor T21 in the delay circuit 20 is turned off, the transistor T22 is turned on, and charging of the capacitor C21 by the current I21 is started. As a result, the voltage VN21 at the node N21 gradually increases. That is, the counting of the predetermined time A1 is started from time t11.

  When the peak value of the load current Io is low as described above in the off time of the output transistor T1, the coil current IL becomes 0A before the feedback voltage VFB becomes lower than the reference voltage Vr (time t12). . At this time, in the DC-DC converter 1 of the asynchronous rectification method, the coil current IL cannot be caused to flow backward to the input side by the diode D1, and thus the coil current IL is maintained at 0A. That is, in the cycle (switching cycle) T of the switching operation of the output transistor T1, the coil current IL is maintained at 0A and the operation is performed in the current discontinuous mode (DCM) in which the change of the coil current IL is discontinuous. The output voltage Vo and the feedback voltage VFB during the DCM operation (after time t12) decrease with a gentler slope than the slopes at times t11 to t12.

  Next, when the predetermined time A1 determined by the delay circuit 20 has elapsed from the time t11 (see time t13), if the feedback voltage VFB has not decreased to the reference voltage Vr, the delay circuit 20 outputs it. Delay signal SG2 transits from L level to H level. In response to the H-level delay signal SG2, the first terminal of the capacitive element C2 in the charge pump 30 is connected to the ground, and the second terminal of the capacitive element C2 is connected to the output terminal Po (the first terminal of the capacitor C1). Connected. As a result, a current flows from the capacitor C1 to the ground through the capacitive element C2, and the charge accumulated in the capacitor C1 is transferred to the capacitive element C2. For this reason, the output voltage Vo and the feedback voltage VFB during the period in which the delay signal SG2 is at the H level (time t13 to t14) decrease with a steeper slope than the slope at the time t12 to t13.

  Here, when the delay circuit 20 and the charge pump 30 are not provided, the output voltage Vo and the feedback voltage VFB after time t13 have the same slope as that at time t12 to t13, as shown by the broken line waveform, that is, Decrease with a gentle slope. For this reason, it takes a long time for the feedback voltage VFB to drop to the reference voltage Vr, and the switching period T becomes longer and the switching frequency becomes lower. On the other hand, in the DC-DC converter 1 of the present embodiment, when the predetermined time A1 elapses from the off timing of the output transistor T1, the charge accumulated in the capacitor C1 is transferred to the capacitive element C2, so that the output voltage Vo and The feedback voltage VFB is rapidly reduced. Thereby, since the time until the feedback voltage VFB reaches the reference voltage Vr can be shortened, it is possible to suppress the switching cycle T from becoming long and to suppress the switching frequency from being lowered.

  When the feedback voltage VFB decreases to the reference voltage Vr (see time t14), the comparator 10 outputs an H level output signal S1, and in response to the H level output signal S1, the L level control signal SG1 is output. It is output for a certain time (time t14 to t15). As a result, the predetermined switching period T from time t10 to t14 ends, and the next switching period T in which the output transistor T1 is turned on for a certain period of time is started. That is, by adjusting the length of the predetermined time A1, the length of the switching period T is adjusted, and the switching frequency is adjusted. Therefore, by appropriately adjusting the length of the predetermined time A1, it is possible to set the minimum frequency of the switching frequency so as not to be applied to a frequency range that may be a noise of a circuit using the DC-DC converter 1. it can. In the present embodiment, the predetermined time A1 can be adjusted to a desired time by adjusting the voltage value of the reference voltage Vc and the current value of the current I21 in the delay circuit 20, and the minimum frequency of the switching frequency is desired. Frequency can be set.

  Further, in response to the transition of the control signal SG1 from the H level to the L level, the delay signal SG2 transitions from the H level to the L level. In response to the delay signal SG2 at L level, the first terminal of the capacitive element C2 in the charge pump 30 is connected to the node LX, and the second terminal of the capacitive element C2 is connected to the input terminal Pi via the diode D2. The At this time, the voltage of the second terminal of the capacitive element C2 (the anode of the diode D2) is a voltage value obtained by adding the output voltage Vo to the voltage of the node LX (here, the input voltage Vin), that is, a voltage higher than the input voltage Vin. Value. Therefore, a current flows from the node LX to the input terminal Pi through the capacitive element C2 and the diode D2, and the charge accumulated in the capacitive element C2 is discharged to the input terminal Pi. That is, the charge transferred from the capacitor C1 to the capacitive element C2 at times t14 to t15 is regenerated to the input terminal Pi (input voltage Vin).

  For example, in the switching cycle T that starts from time t14, a series of operations similar to those at times t10 to t14 are executed. As a result, the above series of operations is repeatedly executed at the switching frequency set according to the predetermined time A1 of the delay circuit 20, that is, the lowest switching frequency.

According to this embodiment described above, the following effects can be obtained.
(1) The delay circuit 20 and the charge pump 30 do not cause the minimum frequency fmin (see FIG. 12) of the switching frequency of the output transistor T1 to be applied to a frequency range that may be noise of a circuit using the DC-DC converter 1. Set to. That is, at a light load, when a predetermined time A1 set by the delay circuit 20 elapses from the OFF timing of the output transistor T1, the charge accumulated in the capacitor C1 is transferred to the capacitive element C2 in the charge pump 30. As a result, the output voltage Vo can be quickly reduced, and the feedback voltage VFB can be rapidly reduced to the reference voltage Vr. Therefore, by appropriately adjusting the predetermined time A1, it is possible to suppress the switching frequency of the output transistor T1 from decreasing until it falls within the frequency range that can be the noise.

  (2) Further, after the output transistor T1 is turned on, the charge transferred from the capacitor C1 to the capacitive element C2 is regenerated to the input terminal Pi. Thereby, since the electric charge which was discharged to the ground can be regenerated to the input terminal Pi, the loss can be reduced and the conversion efficiency of the DC-DC converter 1 can be improved.

  (3) In the charge pump 30, the diode D2 is provided between the second switch circuit SW2 and the input terminal Pi. Accordingly, for example, during a period in which the potential of the node LX is lower than the input voltage Vin as at times t11 to t13 in FIG. 6, the second terminal of the capacitive element C2 is connected to the input terminal Pi through the second switch circuit SW2 and the diode D2. Even in such a case, the reverse flow of the current from the input terminal Pi to the charge pump 30 can be suppressed by the diode D2.

  (4) In the delay circuit 20, the transistor T22 is provided between the power supply line to which the bias voltage VB is supplied and the current source 22. The transistors T21 and T22 are complementarily turned on / off in response to the control signal SG1 (inverted signal XSG1). As a result, in the period in which the voltage VN21 at the node N21 is maintained at the ground level (period in which the transistor T21 is turned on), the transistor T22 is turned off and the supply of the bias voltage VB to the current source 22 is stopped. Can be prevented from flowing to the ground through the transistor T21 which is turned on.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
-The internal structure of the charge pump 30 in the said embodiment is not limited to the circuit shown in FIG. That is, when the switching frequency is equal to or lower than a predetermined frequency (second frequency) set by the delay circuit 20, the charge accumulated in the capacitor C1 is supplied to the input terminal Pi according to the control signal SG1 (delay signal SG2). As long as the circuit can regenerate, the internal configuration of the charge pump 30 (first circuit) is not particularly limited.

  As shown in FIG. 7, for example, the diode D2 may be omitted, and the control signal SG1 may be supplied to the gate of the transistor T33 instead of the delay signal SG2. The operation of the DC-DC converter 1 having the charge pump 30 shown in FIG. 7 will be described below.

  As shown in FIG. 8, when the control signal SG1 transits from the L level to the H level at time t21, the delay signal SG2 transits from the L level to the H level at a timing delayed by a predetermined time A1 from the transition (see time t22). Is done. At this time, the control signal SG1 is maintained at the H level. In response to these H level control signal SG1 and H level delay signal SG2, N channel MOS transistors T32 and T34 are turned on, and P channel MOS transistors T31 and T33 are turned off. Then, the first terminal of the capacitive element C2 in the charge pump 30 is connected to the ground, and the second terminal of the capacitive element C2 is connected to the output terminal Po (the first terminal of the capacitor C1). Therefore, in the first period P1 (see times t22 to t23) in which both the control signal SG1 and the delay signal SG2 are at the H level, current flows from the capacitor C1 to the ground through the capacitive element C2, and is accumulated in the capacitor C1. Charge is transferred to the capacitive element C2. As a result, the output voltage Vo and the feedback voltage VFB can be quickly reduced.

  When the feedback voltage VFB decreases to the reference voltage Vr (see time t23), the comparator 10 outputs an H level output signal S1, and the L level control signal SG1 is output in response to the H level output signal S1. It is output for a certain time (time t23 to t24). At this time, in response to the transition of the control signal SG1 from the H level to the L level, the delay signal SG2 transitions from the H level to the L level. In response to the L level control signal SG1 and the L level delay signal SG2, the N channel MOS transistors T32 and T34 are turned off and the P channel MOS transistors T31 and T33 are turned on. Then, the first terminal of the capacitive element C2 in the charge pump 30 is connected to the node LX, and the second terminal of the capacitive element C2 is connected to the input terminal Pi. At this time, the voltage of the second terminal of the capacitive element C2 is a voltage value obtained by adding the output voltage Vo to the voltage of the node LX (here, the input voltage Vin), that is, a voltage value higher than the input voltage Vin. Therefore, in the second period P2 (see times t23 to t24) in which both the control signal SG1 and the delay signal SG2 are at the L level, current flows from the capacitive element C2 toward the input terminal Pi, and is accumulated in the capacitive element C2. The generated charge is regenerated at the input terminal Pi.

  Then, after a predetermined time has elapsed from time t23, the control signal SG1 changes from the L level to the H level (time t24). At this time, the delay signal SG2 maintains the L level until a predetermined time A1 has elapsed from time t24. In response to the H level control signal SG1 and the L level delay signal SG2, the transistor T31 is turned on and the transistors T32 to T34 are turned off. Then, the charge pump 30 is disconnected from the input terminal Pi by the off operation of the transistor T33. Therefore, in the third period P3 (time t24 to t25) in which the control signal SG1 is at the H level and the delay signal SG2 is at the L level, the backflow of current from the input terminal Pi to the charge pump 30 can be suppressed. More specifically, when the output transistor T1 is turned off in response to the transition of the control signal SG1 from the L level to the H level, the potential of the node LX decreases. At this time, when the diode D2 is simply omitted from the charge pump 30, the transistor T33 is turned on in response to the L-level delay signal SG2 in the third period P3, which reduces the potential of the node LX. Along with this, a current flows from the input terminal Pi toward the charge pump 30. On the other hand, in the present modification, the transistor T33 is turned off in response to the H level control signal SG1 in the third period P3, and the charge pump 30 is disconnected from the input terminal Pi. Even if the potential is lowered, it is possible to suppress a current from flowing from the input terminal Pi to the charge pump 30. That is, the ON / OFF control of the P-channel MOS transistor T33 in the second switch circuit SW2 is individually performed in accordance with the switching of the output transistor T1, thereby omitting the diode D2 and then from the input terminal Pi to the charge pump 30. Current backflow can be suppressed. Furthermore, since the loss due to the diode D2 can be eliminated by omitting the diode D2, the conversion efficiency of the DC-DC converter 1 can be further improved.

  The internal configuration of the delay circuit 20 in the above embodiment is not limited to the circuits shown in FIGS. For example, as shown in FIG. 9, the internal configuration of the delay circuit 20 may be changed. Specifically, in the delay circuit 20 shown in FIG. 9, the adjustment circuit 25 that adjusts the predetermined time A1 so that the switching frequency corresponding to the predetermined time A1 of the delay circuit 20 matches the reference frequency is shown in FIG. It is added to the delay circuit 20 shown.

  The adjustment circuit 25 includes D-FF circuits 26 and 27, a NAND circuit 28, an inverter circuit 29, a P-channel MOS transistor T23, an N-channel MOS transistor T24, a resistor R21, and a capacitor C22. .

  An inverted signal XSG1 of the control signal SG1 is supplied to the clock terminal CK of the D-FF circuit 26. A bias voltage VB is supplied to the input terminal D of the D-FF circuit 26. The output signal S22 of the NAND circuit 28 is supplied to the clear terminal CL of the D-FF circuit 26. The D-FF circuit 26 outputs an output signal DN of H level (bias voltage VB level) from the output terminal Q in response to the rising edge of the inverted signal XSG1. The D-FF circuit 26 outputs an output signal DN of L level (ground level) from the output terminal Q in response to the output signal S22 of L level.

  A reference clock signal CLK having the reference frequency is supplied to the clock terminal CK of the D-FF circuit 27. The reference clock signal CLK is a pulse signal having a fixed period (fixed frequency) generated by an oscillator (not shown), for example. Here, for example, the reference frequency is a frequency (first frequency) higher than an upper limit value of a frequency range (for example, an audible range of an audio device: about 20 Hz to 20 KHz) that may become noise in an electronic device to which the DC-DC converter 1 is applied. Frequency). The bias voltage VB is supplied to the input terminal D of the D-FF circuit 27. The output signal S22 of the NAND circuit 28 is supplied to the clear terminal CL of the D-FF circuit 27. The D-FF circuit 27 outputs an output signal UP of H level (bias voltage VB level) from the output terminal Q in response to the rising edge of the reference clock signal CLK. The D-FF circuit 27 outputs an output signal UP of L level (ground level) from the output terminal Q in response to the output signal S22 of L level.

  The NAND circuit 28 generates an output signal S22 having a result obtained by performing a NAND operation on the output signal UP and the output signal DN, and outputs the output signal S22 to the clear terminals CL of the D-FF circuits 26 and 27.

  The output signal UP of the D-FF circuit 27 is supplied to the inverter circuit 29. The inverter circuit 29 logically inverts the output signal UP to generate an inverted signal XUP, and supplies the inverted signal XUP to the gate of the transistor T23.

  A bias voltage VB is supplied to the source of the transistor T23. The drain of the transistor T23 is connected to the drain of the transistor T24. The source of the transistor T24 is connected to the ground. The output signal DN of the D-FF circuit 26 is supplied to the gate of the transistor T24.

  A node between the transistors T23 and T24 is connected to the first terminal of the resistor R21. The second terminal of the resistor R21 is connected to the first terminal of the capacitor C22, and the second terminal of the capacitor C22 is connected to the ground. The voltage at the first terminal of the capacitor C22 is supplied to the current source 22 as the control signal S21.

In the delay circuit 20 shown in FIG. 9, the comparator 23 shown in FIG. 3 may be provided instead of the buffer circuit 24.
Next, the operation of the delay circuit 20 (particularly the adjustment circuit 25) shown in FIG. 9 will be described.

  As shown in FIG. 10A, when the phase of the control signal SG1 is delayed from the phase of the reference clock signal CLK, the adjustment circuit 25 generates the H level output signal UP for the delayed time. The voltage value of the control signal S21 is increased. More specifically, when the reference clock signal CLK changes from the L level to the H level at time t31, the H-level output signal UP is output from the D-FF circuit 27 in response to the rising edge of the reference clock signal CLK. At this time, since the control signal SG1 is maintained at the H level, the rising edge of the inverted signal XSG1 does not occur, and the D-FF circuit 26 outputs the L level output signal DN. Therefore, the transistor T23 is turned on in response to the H level output signal UP (L level inversion signal XUP), and the transistor T24 is turned off in response to the L level output signal DN. Then, a current flows through the turned-on transistor T23 to the capacitor C22, and the capacitor C22 is charged. As a result, during the period in which the transistor T23 is on (see times t31 to t32), the voltage value of the control signal S21 gradually increases with time. Thereafter, at time t32, when the control signal SG1 transitions from the H level to the L level, the H level output signal DN is changed to the D-FF circuit in response to the falling edge of the control signal SG1 (the rising edge of the inverted signal XSG1). 27. Then, an L level output signal S22 is output from the NAND circuit 28, and L level output signals DN and UP are output from the D-FF circuits 26 and 27 in response to the L level output signal S22. In response to these L level output signals UP and DN, the transistors T23 and T24 are turned off. For this reason, the charging voltage of the capacitor C22 charged while the transistor T23 is on becomes the control signal S21. Therefore, the longer the period during which the transistor T23 is on, that is, the longer the phase of the control signal SG1 with respect to the phase of the reference clock signal CLK, the higher the voltage value of the control signal S21. Along with this, the current value of the current I21 flowing from the current source 22 increases and the predetermined time A1 becomes shorter, that is, the falling timing of the control signal SG1 becomes earlier.

  Thus, when the phase of the control signal SG1 is delayed from the phase of the reference clock signal CLK, the adjustment circuit 25 advances the phase of the control signal SG1 so as to approach the phase of the reference clock signal CLK. The voltage value of the control signal S21 is increased.

  On the other hand, as shown in FIG. 10B, when the phase of the control signal SG1 is advanced from the phase of the reference clock signal CLK, the adjustment circuit 25 outputs the output signal DN at the H level for the advanced time. And the voltage value of the control signal S21 is reduced. More specifically, when the control signal SG1 transitions from the H level to the L level at time t33, the output signal DN at the H level is D-FF in response to the falling edge of the control signal SG1 (the rising edge of the inverted signal XSG1). Output from the circuit 26. At this time, since the reference clock signal CLK is maintained at the L level, the D-FF circuit 27 outputs the L level output signal UP. For this reason, the transistor T24 is turned on in response to the H level output signal DN, and the transistor T23 is turned off in response to the L level output signal UP. Then, the electric charge accumulated in the capacitor C22 is discharged to the ground through the transistor T24 that is turned on. As a result, during the period in which the transistor T24 is on (see times t33 to t34), the voltage value of the control signal S21 gradually decreases with time. Thereafter, at time t34, when the reference clock signal CLK transitions from the L level to the H level, the H-level output signal UP is output from the D-FF circuit 26 in response to the rising edge of the reference clock signal CLK. Then, in response to the L level output signal S22 output from the NAND circuit 28, the L level output signals DN and UP are output from the D-FF circuits 26 and 27. In response to these L level output signals UP and DN, the transistors T23 and T24 are turned off, and the voltage at the first terminal of the capacitor C22 at that time becomes the control signal S21. For this reason, the longer the period during which the transistor T24 is on, that is, the more the phase of the control signal SG1 is advanced with respect to the phase of the reference clock signal CLK, the lower the voltage value of the control signal S21. Along with this, the current value of the current I21 flowing from the current source 22 decreases and the predetermined time A1 becomes longer, that is, the falling timing of the control signal SG1 is delayed.

  As described above, when the phase of the control signal SG1 is ahead of the phase of the reference clock signal CLK, the adjustment circuit 25 performs control so that the phase of the control signal SG1 is delayed to approach the phase of the reference clock signal CLK. The voltage value of the signal S21 is reduced.

  As described above, the adjustment circuit 25 determines the voltage value of the control signal S21 according to the comparison result between the cycle T of the control signal SG1 (switching cycle T according to the predetermined time A1) and the reference cycle Tc of the reference clock signal CLK. That is, the current value of the current I21 is adjusted, and the predetermined time A1 is adjusted so that the period T and the reference period Tc coincide. In other words, the adjustment circuit 25 adjusts the current value of the current I21 so that the switching frequency approaches the reference frequency according to the comparison result between the switching frequency of the output transistor T1 and the reference frequency of the reference clock signal CLK.

  As shown in FIG. 10C, when the cycle T of the control signal SG1 and the reference cycle Tc of the reference clock signal CLK match, the NAND circuit 28 always outputs an L level output signal S22. Then, the D-FF circuits 26 and 27 are maintained in a clear state. Therefore, the L-level output signals DN and UP are output from the D-FF circuits 26 and 27, and the transistors T23 and T24 are turned off. Therefore, the voltage value of the control signal S21 is maintained at the voltage value of the control signal S21 in the immediately preceding switching cycle T.

The P-channel MOS transistor T22 in the delay circuit 20 shown in FIGS. 3, 5, and 9 may be omitted.
In the above embodiment, the predetermined time A1 is set by the delay circuit 20, but the present invention is not limited to this. For example, the predetermined time A1 may be set by a timer circuit.

  In the above embodiment, the divided voltage obtained by dividing the output voltage Vo by the resistors R1 and R2 is used as the feedback voltage VFB. For example, the output voltage Vo itself may be used as the feedback voltage VFB.

  In the above embodiment, a P-channel MOS transistor is disclosed as an example of the output transistor T1 (switching element), but an N-channel MOS transistor may be used. A bipolar transistor may be used as the switching element. Alternatively, a switching element including a plurality of transistors may be used.

In the above embodiment, the reference voltage Vr may be generated outside the control circuit 3. That is, the reference power source E1 may be provided outside the control circuit 3.
In the above embodiment, the reference voltage Vc may be generated outside the control circuit 3. That is, the reference power source E2 may be provided outside the control circuit 3.

The feedback voltage VFB in the above embodiment may be generated outside the control circuit 3. That is, the resistors R1 and R2 may be provided outside the control circuit 3.
The output transistor T1 in the above embodiment may be included in the control circuit 3. Further, the converter unit 2 may be included in the control circuit 3.

  In the above-described embodiment, the asynchronous rectification DC-DC converter is embodied. However, the synchronous rectification DC-DC converter may be embodied. In particular, in the case of a synchronous rectification type DC-DC converter that operates in a current discontinuous mode at a light load or the like, the same effects as in the above embodiment can be obtained.

In the above-described embodiment, the DC-DC converter 1 with a fixed on-time is embodied, but it may be embodied with a DC-DC converter with a fixed off-time.
In the above embodiment, the self-excited DC-DC converter using the RS-FF circuit 11 and the one-shot circuit 12 is embodied. However, for example, the self-excited DC-DC converter using the hysteresis comparator is embodied. May be. Further, the output voltage Vo and the reference voltage are always compared by a comparator, and when the output voltage Vo crosses the reference voltage due to a ripple component, the output voltage Vo is controlled by switching the output transistor T1. A DC converter may be embodied.

  FIG. 11 shows an example of an electronic device 100 having the DC-DC converter 1. The electronic device 100 includes a main body 110 (internal circuit) and a power supply 130 that supplies power to the main body 110.

First, an internal configuration example of the main body 110 will be described.
A central processing unit (CPU) 111 that executes a program is connected to a memory 112 that stores a program executed by the CPU 111 or data processed by the CPU 111. In addition, a keyboard 114 </ b> A and a pointing device 114 </ b> B are connected to the CPU 111 via an interface (I / F) 113. The pointing device 114B is, for example, a flat device having a mouse, a trackball, a touch panel, or an electrostatic sensor.

  In addition, a display 116 is connected to the CPU 111 via an interface 115, and a communication unit 118 is connected via an interface 117. The display 116 is, for example, a liquid crystal display or an electroluminescence panel. The communication unit 118 is, for example, a local area network board.

  Further, an external storage device 120 is connected to the CPU 111 via an interface 119, and a removable recording medium access device 122 is connected via an interface 121. The external storage device 120 is, for example, a hard disk. Examples of the removable recording medium accessed by the access device 122 include a CD (Compact Disc), a DVD (Digital Versatile Disk), and a flash memory card.

Next, an internal configuration example of the power supply unit 130 will be described.
The DC-DC converter 1 and the AC adapter 131 are connected to the main body 110 via the switch SW. Power is supplied to the main body 110 from either the DC-DC converter 1 or the AC adapter 131. In the example of FIG. 11, the DC-DC converter 1 converts, for example, an input voltage Vin from the battery 132 into an output voltage Vo, and supplies the output voltage Vo to the main body 110.

  Such electronic devices include notebook personal computers, communication devices such as mobile phones, information processing devices such as personal digital assistants (PDAs), video equipment such as digital cameras and video cameras, and receivers such as television devices. Etc. In addition, the DC-DC converter 1 can be applied to electronic devices such as audio devices.

1 DC-DC converter (power supply, power supply)
2 Converter unit 3 Control circuit 20 Delay circuit 22 Current source 25 Adjustment circuit 30 Charge pump 100 Electronic device 110 Main unit T1 Output transistor T21 N channel MOS transistor T22 P channel MOS transistor T31 P channel MOS transistor T32 N channel MOS transistor T33 P channel MOS transistor T34 N-channel MOS transistor C1 capacitor C21 capacitor D2 diode I21 current Vin input voltage Vo output voltage SG1 control signal SG2 delay signal Pi input terminal Po output terminal LX node A1 predetermined time

Claims (10)

A power supply control circuit that generates an output voltage at an output terminal by switching a switching element connected between an input terminal to which an input voltage is supplied and a first node,
In response to a control signal for controlling the switching of the switching element, the controller has a control unit for controlling the lowest switching frequency of the switching element,
The control unit includes a first capacitor connected between the first power supply line having a potential different from the input voltage and the output terminal according to the control signal when the switching frequency is equal to or lower than a predetermined frequency. A power supply control circuit comprising a first circuit for regenerating the charge accumulated in the input terminal to the input terminal. The control unit includes a delay circuit that generates a delay signal obtained by delaying the control signal for a predetermined time,
The first circuit includes:
A capacitive element provided between the first node and the output terminal;
A first switch circuit provided between the first node and the capacitive element;
A second switch circuit provided between the capacitive element and the output terminal,
Based on the delay signal, a first state in which the first switch circuit is connected to the first power supply line, and the second switch circuit is connected to the output terminal, and the first switch circuit is connected to the first node. 2. The power supply control circuit according to claim 1, wherein the control circuit is switched to a second state in which the second switch circuit is connected to the input terminal. The first switch circuit includes a first switch having a first terminal connected to the first node, a second terminal connected to the capacitor, and a control terminal to which the delay signal is supplied; A second switch having a first terminal connected to a second terminal of the switch, a second terminal connected to the first power supply line, and a control terminal to which the delay signal is supplied;
The second switch circuit includes a third switch having a first terminal connected to the input terminal, a second terminal connected to the capacitor, and a control terminal to which the control signal is supplied, and the third switch 3. A fourth switch having a first terminal connected to the second terminal, a second terminal connected to the output terminal, and a control terminal to which the delay signal is supplied. The power supply control circuit described. The first circuit has a diode provided between the second switch circuit and the input terminal,
The first switch circuit includes a first switch having a first terminal connected to the first node, a second terminal connected to the capacitor, and a control terminal to which the delay signal is supplied; A second switch having a first terminal connected to a second terminal of the switch, a second terminal connected to the first power supply line, and a control terminal to which the delay signal is supplied;
The second switch circuit includes a third switch having a first terminal connected to an anode of the diode, a second terminal connected to the capacitor, and a control terminal to which the delay signal is supplied, and the third switch 3. A fourth switch having a first terminal connected to a second terminal of the switch, a second terminal connected to the output terminal, and a control terminal to which the delay signal is supplied. The power supply control circuit described in 1.   In response to the transition from the first level to the second level different from the first level, the delay circuit sets the signal level of the delayed signal at a timing delayed by a predetermined time from the transition. 5. The power supply control circuit according to claim 2, wherein transition is made from the first level to the second level. 6. The delay circuit is
A current source for generating a first current;
A fifth switch provided between a second power supply line different from the first power supply line and the current source and turned on / off in response to the control signal;
A second capacitor connected to the current source and charged or discharged by the first current;
A sixth switch connected in parallel with the second capacitor and turned on / off complementarily with the fifth switch in response to the control signal;
6. The power supply control according to claim 5, wherein when the voltage of the second capacitor reaches a predetermined voltage value, the signal level of the delay signal is changed from the first level to the second level. circuit. The delay circuit is
The adjustment circuit according to claim 6, further comprising: an adjustment circuit that adjusts a current value of the first current so that the switching frequency approaches the reference frequency according to a comparison result between the switching frequency and the reference frequency. Power supply control circuit. A switching element connected between an input terminal to which an input voltage is supplied and the first node; and a control circuit that controls the switching of the switching element, and the output voltage is applied to the output terminal by switching the switching element. A power supply that generates
The control circuit has a control unit that controls a minimum switching frequency of the switching element in response to a control signal for switching control of the switching element,
The control unit includes a first capacitor connected between the first power supply line having a potential different from the input voltage and the output terminal according to the control signal when the switching frequency is equal to or lower than a predetermined frequency. A power supply device comprising: a first circuit for regenerating charge accumulated in the input terminal. A switching element connected between an input terminal to which an input voltage is supplied and the first node; and a control circuit that controls the switching of the switching element, and the output voltage is applied to the output terminal by switching the switching element. Generating power,
An internal circuit to which the output voltage is supplied,
The control circuit has a control unit that controls a minimum switching frequency of the switching element in response to a control signal for switching control of the switching element,
The control unit includes a first capacitor connected between the first power supply line having a potential different from the input voltage and the output terminal according to the control signal when the switching frequency is equal to or lower than a predetermined frequency. An electronic apparatus comprising: a first circuit for regenerating the charge accumulated in the input terminal. A power supply control method for generating an output voltage at an output terminal by switching a switching element connected between an input terminal to which an input voltage is supplied and a first node,
In response to a control signal for controlling the switching of the switching element, the minimum frequency of the switching frequency of the switching element is controlled,
When the switching frequency is equal to or lower than a predetermined frequency, the electric charge accumulated in the first capacitor connected between the first power supply line having a potential different from the input voltage and the output terminal according to the control signal Is regenerated at the input terminal.