JP2014072847A - Clock generation device, method of operating clock generation device, and system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate an output clock of a desired frequency from an input clock by means of a multiplication circuit of an arbitrary frequency specification.SOLUTION: A clock generation device includes: a first frequency division circuit for generating a first clock from an input clock by using a first division ratio; the multiplication circuit for generating a second clock from the first clock; and a second frequency division circuit for generating an output clock from the second clock by using a second division ratio. An expected value of a frequency of the second clock that the multiplication circuit can output is divided by a frequency of the first clock to produce an expected value of a multiplication number of the multiplication circuit. A product of an inverse number of a multiplication number that is a ratio of a frequency of the output clock to a frequency of the input clock and the expected value of the multiplication number thus produced is calculated, and an integral value resulting from dividing the calculated product by the first division ratio is determined as the second division ratio. A product of the multiplication number that is the ratio of the frequency of the output clock to the frequency of the input clock, the integral value and the first division ratio is calculated as the multiplication number given to the multiplication circuit.

Description

  The present invention relates to a clock generation device, an operation method of the clock generation device, and a system in which the clock generation device is mounted.

  A clock generation device such as a PLL (Phase-locked loop) circuit is used when generating an output clock having a frequency different from the frequency of the input clock. For example, a method has been proposed in which a frequency dividing circuit is arranged in each of the input and output of a PLL circuit and a feedback path, and a combination with low power consumption is selected from a plurality of combinations of the frequency dividing ratios of these frequency dividing circuits. (For example, refer to Patent Document 1). The PLL circuit is also used when generating an audio clock from a clock transmitted using a digital interface such as HDMI (registered trademark; High-Definition Multimedia Interface) (see, for example, Patent Document 2). For example, in HDMI, a transmission clock and two integers N and CTS are output to the receiving device. The receiving device divides the frequency of the transmission clock by the division ratio CTS, and further multiplies the divided clock by the multiplication number N (feeds back the clock divided by the division ratio N) to generate an audio clock. .

Special table 2009-553331 gazette WO2009-013860 publication

  However, for example, in the generation of an audio clock using an HDMI interface, if the integer CTS or the integer N is larger than the maximum value of the frequency division ratio of the frequency dividing circuit, the audio clock cannot be generated. In other words, in order to generate an audio clock, an integer CTS that is less than or equal to the maximum frequency division ratio that can be set in the frequency divider circuit on the input side, and a frequency that is less than or equal to the maximum frequency division ratio that can be set in the frequency divider circuit of the feedback path It is necessary to use the integer N. Therefore, the frequency of the audio clock that can be generated is limited.

  In one aspect, an object of the present invention is to generate an output clock having a desired frequency from an input clock using a multiplier circuit having an arbitrary frequency specification.

  In one form of the present invention, the clock generation device divides the frequency of the input clock by the first division ratio to generate the first clock, and multiplies the frequency of the first clock by multiplying the frequency of the first clock. A multiplication circuit that generates two clocks, a second division circuit that generates an output clock by dividing the frequency of the second clock by the second division ratio, and an expectation of the frequency of the second clock that can be output from the multiplication circuit Dividing the value by the frequency of the first clock to obtain an expected value of the multiplication number of the multiplication circuit, a reciprocal of the multiplication number that is a ratio of the frequency of the output clock to the frequency of the input clock, and a first A second calculation circuit for calculating a product of the multiplication number obtained by the calculation circuit and an expected value and dividing the calculated product by the first division ratio to obtain an integer value as the second division ratio; and an input clock Is the ratio of the frequency of the output clock to the frequency of The product of the number of integer value and the first division ratio, and a third calculation circuit for calculating a multiplication number given to the multiplier circuit.

  An output clock having a desired frequency can be generated from an input clock using a multiplier circuit having an arbitrary frequency specification.

2 illustrates an example of a clock generation device according to an embodiment. The example of the clock generation apparatus in another embodiment is shown. The example of the clock generation apparatus in another embodiment is shown. The example of the clock generation apparatus in another embodiment is shown. 5 shows an example of the operation of the clock generator shown in FIG. The example of the clock generation apparatus in another embodiment is shown. The example of the clock generation apparatus in another embodiment is shown. 5 shows an example of a system in which the clock generation device shown in FIG. 4 is mounted. 8 shows an example of a multiplication circuit mounted on the clock generation device shown in FIGS. 10 shows an example of a multiplier circuit in which a frequency divider is connected to the input of the phase comparator shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a clock generation device CLKG1 according to an embodiment. The clock generation device CLKG1 includes a frequency divider circuit 10, a frequency multiplier circuit 12, a frequency divider circuit 14, a detection circuit 16, and calculation circuits 18, 20, 22, 24, and 26. For example, the calculation circuits 18, 20, 22, 24, and 26 are described by RTL (Register Transfer Level) and are designed by being converted into a net list (logic circuit) by a logic synthesis tool. The calculation circuits 18, 20, 22, 24, and 26 may be designed individually or may be designed as one calculation module.

The clock generation device CLKG1 multiplies the frequency FCLKI of the input clock CLKI according to the ratio FO / FI to generate the output clock CLKO. That is, the frequency FCLKO of the output clock CLKO is expressed by the equation (1).
FCLKO = FCLKI × (FO / FI) (1)
The frequency dividing circuit 10 divides the frequency FCLKI of the input clock CLKI by the frequency division ratio DIVI to generate the clock FIN. The frequency FFIN of the clock FIN is expressed by Expression (2).
FFIN = FCLKI / DIVI (2)
The multiplier circuit 12 is, for example, a PLL circuit, and multiplies the frequency FFIN of the clock FIN based on the multiplication number MLT to generate the clock FOUT. The frequency FFOUT of the clock FOUT is expressed by Expression (3). The frequency range of the clock FIN that can be supplied to the multiplier circuit 12, the frequency range of the clock FOUT that can be output from the multiplier circuit 12, and the multiplication number MLT that can be set in the multiplier circuit 12 are input for each type of the multiplier circuit 12. It is determined as an output specification (frequency specification).
FFOUT = FFIN × MLT (3)
The frequency dividing circuit 14 divides the frequency FFOUT of the clock FOUT by the frequency dividing ratio DIVO to generate the output clock CLKO. The frequency FCLKO of the output clock CLKO is expressed by Expression (4). As will be described later, since the frequency division ratio DIVO is an integer, the circuit scale of the frequency divider circuit 14 can be made smaller than that of the frequency divider circuit whose frequency division ratio can be set to a decimal number.
FCLKO = FFOUT / DIVO (4)
The detection circuit 16 detects the frequency of the input clock CLKI and outputs frequency information FII indicating the detected frequency. For example, the detection circuit 16 has a counter that counts the number of rising edges of the input clock CLKI. Then, the detection circuit 16 detects the frequency of the input clock CLKI according to the number of rising edges (counter value) of the input clock CLKI that appears during a predetermined clock cycle of the reference clock.

  The calculation circuit 18 obtains a frequency division ratio DIVI to be given to the frequency divider circuit 10 based on the frequency information FII detected by the detection circuit 16. The frequency division ratio DIVI obtained by the calculation circuit 18 is set so that the frequency FFIN of the clock FIN satisfies the frequency input specification of the multiplier circuit 12. For example, when the frequency FFIN of the clock FIN that can be supplied to the multiplier circuit 12 is the value F1, the frequency division ratio DIVI is obtained by dividing the frequency FCLKI of the input clock CLKI by the value F1. The frequency value F1 of the clock FIN that can be supplied to the multiplication circuit 12 is set in a ROM (Read Only Memory) or a register, and is transmitted to the calculation circuit 18.

  The calculation circuit 18 receives the minimum value and the maximum value of the frequency FFIN of the clock FIN as the frequency input specification of the multiplier circuit 12, and the frequency FFIN of the clock FIN is included between the minimum value and the maximum value. A frequency division ratio DIVI may be set. Alternatively, the calculation circuit 18 may obtain the division ratio DIVI with reference to a table showing the relationship between the frequency FCLKI of the input clock CLKI, the frequency FFIN of the clock FIN, and the division ratio DIVI.

The calculation circuit 20 obtains the frequency FFIN of the clock FIN actually supplied to the multiplication circuit 12 based on the frequency information FII and the frequency division ratio DIVI. For example, the calculation circuit 20 obtains the frequency FFIN by dividing the frequency information FII by the frequency division ratio DIVI as shown in Expression (10). By using the frequency information FII and the frequency division ratio DIVI actually supplied to the frequency dividing circuit 10, the frequency FFIN of the clock FIN can be accurately obtained.
FFIN = FII / DIVI (10)
When the frequency of the input clock CLKI is known, the clock generation device CLKG1 may not have the detection circuit 16. In this case, the frequency information FII is supplied from the outside of the clock generation device CLKG1, or is held in advance inside the clock generation device CLKG1. Further, when the frequency of the input clock CLKI is known and the frequency FFIN of the clock FIN is a fixed value, the clock generation device CLKG1 may not include the calculation circuit 18 or the calculation circuit 20. In this case, the frequency division ratio DIVI or the frequency FFIN is supplied from the outside of the clock generation device CLKG1, or is held in advance inside the clock generation device CLKG1. Similarly, the clock generation devices CLKG2, CLKG3, CLKG4, CLKG5, and CLKG6 described in the following embodiments may not include one or more of the detection circuit 16 and the calculation circuits 18 and 20.

The calculation circuit 22 divides the expected value FOe of the frequency FFOUT of the clock FOUT output from the multiplier circuit 12 by the frequency FFIN of the clock FIN to obtain the expected value MLTe of the multiplication number of the multiplier circuit 12. That is, the expected value MLTe is expressed by the equation (11).
MLTe = FOe / FFIN (11)
For example, the expected value FOe is set to a value close to the minimum value in the output specification range of the frequency FFOUT of the clock FOUT that can be output by the multiplier circuit 12. The expected value FOe is set in a ROM or a register and transmitted to the calculation circuit 22. Since the frequency FFIN and the expected value FOe satisfy the frequency input / output specification of the multiplication circuit 12, the expected value MLTe of the multiplication number also satisfies the input specification of the multiplication circuit 12.

The calculation circuit 24 calculates the product of the reciprocal of the ratio FO / FI and the expected value MLTe of the multiplication number. The ratio FO / FI indicates a ratio of the frequency FCLKO of the output clock CLKO to the frequency FCLKI of the input clock CLKI, and indicates a multiplication number for generating the output clock CLKO from the input clock CLKI. The calculation circuit 24 calculates an integer obtained by dividing the calculated product (MLTe × FI / FO) by the frequency division ratio DIVI as the frequency division ratio DIVO, and calculates the frequency division ratio DIVO to the frequency divider 14 and the calculation circuit 26. To give. The frequency division ratio DIVO is expressed by Expression (12).
DIVO≈ (MLTe × FI / FO) / DIVI (12)
The division ratio DIVO may be obtained by rounding down the decimal part, may be obtained by rounding up, or may be obtained by rounding off. By using the division ratio DIVO as an integer, the precision of multiplication and division used in Expressions (10) to (12) can be made lower than the precision when the division ratio DIVO is calculated to the decimal point. As a result, the number of bits of registers and the like used for multiplication and division can be suppressed, so that the circuit scale can be reduced, the calculation speed can be increased, and the power consumption can be reduced.

The calculation circuit 26 obtains a product of the frequency division ratio DIVO, the ratio FO / FI, and the frequency division ratio DIVI, and supplies the obtained product to the multiplication circuit 12 as a multiplication number MLT. The multiplication number MLT is expressed by Expression (13). The number of bits of the register or the like used for multiplication and division in Expression (13) is set in accordance with the precision of the multiplication number MLT that can generate the frequency FFOUT of the clock FOUT with a desired precision. However, as described above, since the precision of multiplication and division executed from Expression (10) to Expression (12) can be reduced, the circuit scale can be reduced as the whole of the calculation circuits 18, 20, 22, 24, and 26. The calculation speed can be increased and the power consumption can be reduced.
MLT = (DIVO × FO / FI) × DIVI (13)
Substituting equation (12) into equation (13) yields equation (14). That is, the multiplication number MLT given to the multiplication circuit 12 is substantially equal to the expected value MLTe of the multiplication number, and therefore satisfies the input specifications of the multiplication circuit 12.
MLT≈ ((MLTe × FI / FO) / DIVI) × (FO / FI) × DIVI = MLTe (14)
Note that the division ratio DIVO obtained as an integer value by the approximation according to the equation (12) has a predetermined error with respect to “(MLTe × FI / FO) / DIVI”. When the frequency division ratio DIVO is shifted to the smaller side, the multiplication number MLT of Expression (13) is smaller than the expected value MLTe, and the frequency FFOUT of the clock FOUT is lower than the value corresponding to the expected value MLTe. Since the expected value FOe is set to be larger than the minimum value of the output specification of the frequency of the multiplier circuit 12, the frequency FFOUT of the clock FOUT is equal to the frequency of the multiplier circuit 12 even when the frequency division ratio DIVO is swung to the smaller side. Satisfies output specifications. In other words, the expected value FOe is set such that the frequency FFOUT of the clock FOUT satisfies the frequency output specification of the multiplier circuit 12 even when the frequency division ratio DIVO is shifted to a smaller side.

As described above, the frequency of the clock FIN, the frequency of the clock FOUT, and the multiplication number MLT all satisfy the input / output specifications of the multiplication circuit 12. Therefore, the output clock CLKO can be generated from the input clock CLKI using the ratio FO / FI regardless of the input / output specification of the multiplier circuit 12. In addition, FFOUT in Expression (4) is replaced with FFIN × MLT in Expression (3), the replaced FFIN is replaced with FCLKI / DIVI in Expression (2), and the replaced MLT is replaced with (DIVO × FO in Expression (13). When replaced with / FI) × DIVI, equation (15) is obtained. Expression (15) is equal to Expression (1), and it can be seen that the clock generation device CLKG1 can generate the output clock CLKO by converting the frequency FCLKI of the input clock CLKI into a value corresponding to the ratio FO / FI.
FCLKO = (FCLKI / DIVI) × ((DIVO × FO / FI) × DIVI) / DIVO (15)
The detection circuit 16 performs a detection operation for detecting the frequency FFIN of the clock FIN during initialization of the system on which the clock generation device CLKG1 is mounted, and holds the detected frequency FFIN as frequency information FII in a built-in register or latch. . The detection circuit 16 outputs the held frequency information FII and stops the operation after the detection operation. The register or latch of the detection circuit 16 may continue to hold the frequency information FII even after the detection operation, and may output the held frequency information FII. A system in which the clock generation device CLKG1 is mounted will be described with reference to FIG.

  The calculation circuits 18, 20, 22, 24, and 26 execute a calculation operation during initialization of a system in which the clock generation device CLKG1 is mounted. The calculation circuit 18 holds the obtained division ratio DIVI in a built-in register or latch. The calculation circuit 24 holds the obtained division ratio DIVO in a built-in register or latch. The calculation circuit 26 holds the obtained multiplication number MLT in a built-in register or latch. The calculation circuits 18, 20, 22, 24, and 26 stop operating after the calculation operation. The calculation circuits 18, 24, and 26 continue to hold the division ratios DIVI and DIVO and the multiplication number MLT, respectively, after the calculation operation, and output the held division ratios DIVI and DIVO and the multiplication number MLT.

  As described above, in this embodiment, even when the frequency FCLKI of the input clock CLKI or the ratio FO / FI indicating the multiplication number does not satisfy the input / output specification of the multiplication circuit 12, the clock CLKO of the frequency FCLKO shown in the expression (1). Can be generated. In other words, the output clock CLKO having a desired frequency can be generated from the input clock CLKI using the multiplication circuit 12 having an arbitrary frequency specification.

  Since the computations (Equation (10), Equation (11), Equation (12)) executed by the computation circuits 20, 22, 24 need only be accurate to obtain the division ratio DIVO represented by an integer, the computation circuit The circuit scale of 20, 22, 24 can be reduced. Since the circuit scale is small, the calculation speed can be increased and the power consumption can be reduced.

  FIG. 2 shows an example of the clock generation device CLKG2 in another embodiment. Elements that are the same as or the same as those shown in FIG. 1 are given the same reference numerals, and detailed descriptions thereof are omitted. The clock generation device CLKG2 includes a calculation circuit 22A instead of the calculation circuit 22 illustrated in FIG. 1, and newly includes a determination circuit 28A. The other configuration of the clock generation device CLKG2 is the same as that of the clock generation device CLKG1 shown in FIG.

  The determination circuit 28A multiplies the frequency FFIN of the clock FIN obtained by the calculation circuit 20 by the multiplication number MLT obtained by the calculation circuit 26 to obtain the frequency of the clock FOUT output from the multiplication circuit 12. The determination circuit 28A determines whether or not the obtained frequency is lower than the minimum value FOmin of the frequency FFOUT of the clock FOUT, and generates a determination signal JDG1. For example, the determination circuit 28A sets the determination signal JDG1 to the active level when the determined frequency is lower than the minimum value FOmin, and sets the determination signal JDG1 to the inactive level when the determined frequency is equal to or higher than the minimum value FOmin. That is, the determination circuit 28A outputs the determination signal JDG1 to the calculation circuit 22A when the product of the frequency FFIN and the multiplication number MLT is smaller than the minimum value FOmin of the frequency of the clock FOUT that can be output from the multiplication circuit 12. Here, the minimum value FOmin is information indicating the minimum value of the frequency FFOUT of the clock FOUT in the frequency output specification of the multiplier circuit 12.

  The calculation circuit 22A receives the minimum value FOmin of the frequency FFOUT of the clock FOUT. In the initial operation of calculating the expected value MLTe of the multiplication number of the multiplier circuit 12, the calculation circuit 22A divides the minimum value FOmin by the frequency FFIN of the clock FIN to obtain the expected value MLTe and outputs it to the calculation circuit 24. When the determination signal JDG1 received after the first calculation operation is in an inactive level, the calculation circuit 22A holds the expected value MLTe obtained by the first calculation operation, and outputs the held expected value MLTe to the calculation circuit 24. That is, when the frequency of the clock FOUT obtained by the determination circuit 28A is equal to or higher than the minimum value FOmin, the frequency division ratio DIVO and the multiplication number MLT are set based on the expected value MLTe obtained by the first calculation operation.

  On the other hand, when the determination circuit 28A that receives the multiplication number MLT obtained by the first calculation operation outputs the determination signal JDG1 of the active level, the calculation circuit 22A uses a value obtained by adding a predetermined value to the minimum value FOmin as the frequency of the clock FIN. Divide by FFIN to obtain a new expected value MLTe. The new expected value MLTe is larger than the expected value MLTe obtained by the first calculation operation. The calculation circuit 22A holds the newly obtained expected value MLTe, and outputs the held new expected value MLTe to the calculation circuit 24. When the determination signal JDG1 received after the first calculation operation is at the active level, the calculation circuit 22A adds a predetermined value to the held expected value MLTe, newly holds it, and newly holds the expected value MLTe. May be output to the calculation circuit 24.

  As described above, when the determination circuit 28A determines that the frequency FFOUT of the clock FOUT is lower than the minimum value FOmin, the frequency division ratio DIVO (integer value) is reset based on the increased new expected value MLTe. The calculation circuit 26 obtains the multiplication number MLT based on the new frequency division ratio DIVO. From equation (12), the reset frequency division ratio DIVO is larger than the frequency division ratio DIVO obtained by the first calculation operation. From Expression (13), the reset multiplication number MLT is larger than the multiplication number MLT obtained by the first calculation operation. For this reason, the frequency of the clock FOUT output from the multiplier circuit 12 is higher than the frequency obtained by the first calculation operation.

  Thereafter, until the frequency of the clock FOUT obtained by multiplying the frequency FFIN by the multiplication number MLT becomes equal to or higher than the minimum value FOmin (until the determination signal JDG1 becomes the inactive level), the expected value MLTe, the division ratio DIVO, and the multiplication number MLT is gradually increased. As a result, the frequency FFOUT of the clock FOUT output from the multiplier circuit 12 can be set to the minimum value within the range of the output specification of the frequency of the multiplier circuit 12. The power consumption of the multiplier circuit 12 increases as the frequency FFOUT of the clock FOUT increases. Therefore, the power consumption of the multiplier circuit 12 can be reduced by setting the frequency FFOUT of the clock FOUT to the minimum value.

  As described above, also in this embodiment, similarly to the embodiment shown in FIG. 1, the output clock CLKO having a desired frequency can be generated from the input clock CLKI by using the multiplier circuit 12 having an arbitrary frequency specification. Furthermore, the frequency FFOUT of the clock FOUT can be set to the minimum value that satisfies the output specification of the frequency of the multiplier circuit 12 even when the frequency division ratio DIVO is shifted to a smaller side than the error generated by the calculation of Expression (12). As a result, the power consumption of the multiplier circuit 12 can be reduced, and the power consumption of the clock generation device CLKG2 can be reduced.

  FIG. 3 shows an example of the clock generation device CLKG3 in another embodiment. Elements that are the same as or the same as those shown in FIGS. 1 and 2 are given the same reference numerals, and detailed descriptions thereof are omitted. The clock generation device CLKG3 includes a calculation circuit 18B and a determination circuit 28B instead of the calculation circuit 18 and the determination circuit 28A illustrated in FIG. Other configurations of the clock generation device CLKG3 are the same as those of the clock generation device CLKG2 shown in FIG.

  The determination circuit 28B adds a function for generating the determination signal JDG2 to the determination circuit 28A shown in FIG. That is, as in the determination circuit 28A shown in FIG. 2, the determination circuit 28B has a function of determining the frequency FFOUT of the clock FOUT from the frequency FFIN and the multiplication number MLT, and a determination indicating the relationship between the determined frequency FFOUT and the minimum value FOmin. And a function of generating the signal JDG1.

  In addition, the determination circuit 28B determines the magnitude relationship between the frequency FFOUT and the minimum value FOmin and sets the determination signal JDG2 to, for example, an inactive level during a period in which the determination signal JDG1 is output. Furthermore, the determination circuit 28B has a function of setting the determination signal JDG1 to an inactive level based on the determination result and then outputting the determination result of the magnitude relationship between the frequency FFOUT and the minimum value FOmin as the determination signal JDG2. .

  The inactive level of the determination signal JDG2 indicating the determination result indicates that the frequency FFOUT of the clock FOUT obtained by multiplying the frequency FFIN of the clock FIN generated according to the frequency division ratio DIVI is equal to or higher than the minimum value FOmin. The active level of the determination signal JDG2 indicating the determination result indicates that the frequency FFOUT of the clock FOUT is lower than the minimum value FOmin.

  In addition to the function of the calculation circuit 18 shown in FIG. 1, the calculation circuit 18B has a function of increasing the frequency division ratio DIVI for each operation of the determination circuit 28B when the determination signal JDG2 is at an inactive level. Yes. As the frequency division ratio DIVI increases, the frequency FFIN of the clock FIN supplied to the multiplier circuit 12 decreases. For example, the calculation circuit 18B increases the frequency division ratio DIVI by 2 for each operation of the determination circuit 28B. When the division ratio DIVI is increased, the calculation circuits 20, 22A, 24, and 26 recalculate the frequency FFIN, the expected value MLTe, the division ratio DIVO, and the multiplication number MLT according to the new division ratio DIVI.

  Further, the calculation circuit 18B receives the minimum value FImin and the maximum value FImax indicating the input specification range of the frequency FFIN of the clock FIN in the multiplication circuit 12, and the frequency information FII indicating the frequency of the input clock CLKI. The calculation circuit 18B sets the frequency division ratio DIVI so that the frequency of the clock FIN is included between the minimum value FImin and the maximum value FImax.

  The determination circuit 28B multiplies the frequency FFIN of the clock FIN generated according to the increased frequency division ratio DIVI by the newly set multiplication number MLT during the period in which the determination result is output as the determination signal JDG2. The frequency FFOUT of FOUT is obtained. The determination circuit 28B receives the determination signal JDG2 when the determined frequency is equal to or greater than the minimum value FOmin and the multiplication number MLT satisfies the input specifications of the multiplication circuit 12 during the period in which the determination result is output as the determination signal JDG2. Keep at active level.

  On the other hand, the determination circuit 28B determines the determination signal when the determined frequency is lower than the minimum value FOmin during the period when the determination result is output as the determination signal JDG2 or when the multiplication number MLT exceeds the input specification of the multiplication circuit 12. Set JDG2 to active level. Note that the determination circuit 28B maintains the determination signal JDG1 at the inactive level during the period in which the determination result is output as the determination signal JDG2.

  The calculation circuit 18B decreases the frequency division ratio DIVI based on the active level determination signal JDG2 (for example, returns it to the previous set value). Then, based on the reduced frequency division ratio DIVI, the final frequency division ratio DIVO and the multiplication number MLT are obtained. As a result, the frequency division ratios DIVI and DIVO are used to lower the frequencies FFIN and FFOUT of both the clocks FIN and FOUT using the frequencies FFIN and FFOUT of the clocks FIN and FOUT that satisfy the input / output specifications of the multiplier circuit 12 and the multiplication number MLT. Can be requested. By reducing the frequencies FFIN and FFOUT, the power consumption of the multiplier circuit 12 can be reduced.

  In the embodiment shown in FIG. 3, after the frequency FFOUT of the clock FOUT is set to the minimum value that can be set, the frequency division ratio DIVI is set to the maximum value that can be set, and the frequency FFIN of the clock FIN can be set. Set to the minimum value. However, the determination circuit 28B may alternately output the determination signals JDG1 and JDG2 to alternately set the frequency FFOUT of the clock FOUT and the frequency division ratio DIVI. Alternatively, the frequency FFOUT of the clock FOUT may be set after the division ratio DIVI is set by the determination circuit 28B outputting the determination signal JDG1 after the determination signal JDG2 is output.

  Further, the frequency division ratio DIVI may be set to a maximum value that can be set without changing the frequency FFOUT of the clock FOUT. In this case, the determination circuit 28B sets the determination signal JDG1 to the inactive level regardless of the determination result. Alternatively, the determination circuit 28B does not have a function of outputting the determination signal JDG1, and the clock generation device CLKG3 calculates the expected value MLTe using the calculation circuit 22 shown in FIG. 1 instead of the calculation circuit 22A.

  As described above, also in this embodiment, similarly to the embodiment shown in FIG. 1, the output clock CLKO having a desired frequency can be generated from the input clock CLKI by using the multiplier circuit 12 having an arbitrary frequency specification. Further, the frequency FFOUT of the clock FOUT output from the multiplier circuit 12 and the frequency FFIN of the clock FIN input to the multiplier circuit 12 can be lowered. As a result, the power consumption of the multiplier circuit 12 can be reduced, and the power consumption of the clock generation device CLKG2 can be reduced.

  FIG. 4 shows an example of the clock generation device CLKG4 in another embodiment. Elements that are the same as or the same as those shown in FIG. 1 are given the same reference numerals, and detailed descriptions thereof are omitted. The clock generation device CLKG4 has a multiplication circuit 12C and calculation circuits 18C, 24C, and 26C instead of the multiplication circuit 12 and calculation circuits 18, 24, and 26 shown in FIG. 1, and newly has holding circuits 30C and 32C. ing. The other configuration of the clock generation device CLKG4 is the same as that of the clock generation device CLKG1 shown in FIG.

The clock generation device CLKG4 generates the output clock CLKO from the input clock CLKI using the multiplication circuit 12C that is a fractional PLL circuit. For example, the clock generation device CLKG4 generates an output clock CLKO that is an audio clock for audio from an input clock CLKI that is a video clock TMDS (Transition Minimized Differential Signaling) for video based on the HDMI standard. The relationship between the frequency FCLKI of the input clock CLKI and the frequency FCLKO of the output clock CLKO is defined by a ratio N / CTS of integers CTS and N, as shown in Expression (20). The ratio N / CTS indicates the multiplication number of the clock. For example, the source device that supplies the input clock CLKI to the clock generation device CLKG4 outputs the ratio N / CTS.
FCLKO = FCLKI × (N / CTS) (20)
The holding circuit 30C holds the minimum value FImin and the maximum value FImax of the input specifications of the frequency FFIN of the clock FIN supplied to the multiplier circuit 12C. For example, the holding circuit 30C includes a rewritable nonvolatile memory cell such as a ROM, a register, or a flash memory that stores the minimum value FImin and the maximum value FImax.

  The holding circuit 32C holds the expected value FOe of the frequency FFOUT of the clock FOUT output from the multiplier circuit 12C. For example, the expected value FOe is set to a value close to the minimum value in the output specification range of the frequency FFOUT of the clock FOUT that can be output by the multiplier circuit 12C, as in FIG. For example, the holding circuit 32C includes a rewritable nonvolatile memory cell such as a ROM, a register, or a flash memory that stores the expected value FOe. Note that the holding circuits 30C and 32C may be arranged outside the clock generation device CLKG4.

  The calculation circuit 18C receives the minimum value FImin and the maximum value FImax of the frequency FFIN of the clock FIN in the multiplication circuit 12C, and frequency information FII indicating the frequency FCLKI of the input clock CLKI. The calculation circuit 18C sets the frequency division ratio DIVI so that the frequency FFIN of the clock FIN generated by the frequency divider circuit 10 is included between the minimum value FImin and the maximum value FImax.

The calculation circuit 24C obtains the product of the reciprocal of the ratio N / CTS and the expected value MLTe of the multiplication number, and divides the obtained product (MLTe × CTS / N) by the division ratio DIVI to divide the integer. It is obtained as DIVO, and the obtained division ratio DIVO is supplied to the frequency dividing circuit 14 and the calculating circuit 26. The frequency division ratio DIVO is expressed by the equation (21) similarly to the equation (12).
DIVO≈ (MLTe × CTS / N) / DIVI (21)
The calculation circuit 26C calculates a product of the frequency division ratio DIVO, the ratio N / CTS, and the frequency division ratio DIVI, and supplies the calculated product to the frequency multiplier circuit 12C as a multiplication number MLT. In this embodiment, the multiplication number MLT is represented by an integer part IDIV and a decimal part FNUM / FDEN. The multiplication number MLT is expressed by the equation (22), similarly to the equation (13).
MLT = (DIVO × N / CTS) × DIVI (22)
Substituting equation (21) into equation (22) yields equation (23). That is, the multiplication number MLT given to the multiplication circuit 12C is substantially equal to the expected value MLTe of the multiplication number, and therefore satisfies the input / output specification of the multiplication circuit 12C.
MLT≈ ((MLTe × CTS / N) / DIVI) × (N / CTS) × DIVI = MLTe (23)
As in FIG. 1, since the expected value FOe is set higher than the minimum value of the output specification of the frequency FFOUT of the clock FOUT in the multiplier circuit 12C, the frequency FFOUT is shifted when the frequency division ratio DIVO is reduced. In addition, the output specifications of the multiplier circuit 12 are satisfied. The frequency FFIN of the clock FIN, the frequency FFOUT of the clock FOUT, and the multiplication number MLT all satisfy the input / output specifications of the multiplication circuit 12C. Therefore, the output clock CLKO can be generated from the input clock CLKI using the ratio N / CTS regardless of the input / output specification of the multiplier circuit 12C. Similarly to FIG. 1, Expression (24) can be generated from the relationship between Expression (1), Expression (3), Expression (4), and Expression (23), and Expression (24) Will be equal. Therefore, it can be seen that the clock generation device CLKG4 can generate the output clock CLKO by converting the frequency FCLKI of the input clock CLKI into a value corresponding to the ratio N / CTS.
FCLKO = (FCLKI / DIVI) × ((DIVO × N / CTS) × DIVI) / DIVO (24)
FIG. 5 shows an example of the operation of the clock generator CLKG4 shown in FIG. For example, the input specification of the frequency FCLKI of the input clock CLKI is from 25 MHz to 340 MHz, the input specification of the integer CTS is 5461 to 1011145, and the input specification of the integer N is 2730 to 1048575.

  For example, the input specification of the frequency FFIN of the clock FIN in the multiplier circuit 12C is 10 MHz to 50 MHz, and the output specification of the frequency FFOUT of the clock FOUT in the multiplier circuit 12C is 1000 MHz to 2000 MHz. For example, the input specification of the integer part IDIV supplied to the multiplication circuit 12C is 20 to 120, the input specification of the integer FNUM of the decimal part is 0 to 65534, and the input specification of the integer FDEN of the decimal part is FNUM + 1. To 65535.

  When the 5.644800 MHz output clock CLKO is generated from the 331 MHz input clock CLKI, the clock generator CLKG4 receives the integer N = 17836 and the integer CTS = 1045868. The ratio N / CTS indicating the multiplication number is 0.170553777. For example, the expected value FOe is set to 1200 MHz, which is higher than the minimum value (1000 MHz) of the frequency FFOUT of the clock FOUT.

  The calculation circuit 18C shown in FIG. 4 obtains a frequency division ratio DIVI (any of 8, 16, 32) that satisfies the input specification of the frequency FFIN. The calculation circuit 20 obtains the frequency FFIN by dividing the frequency information FII of the input clock CLKI by the division ratio DIVI as shown in the equation (10). As shown in Expression (11), the calculation circuit 22 divides the expected value FOe by the frequency FFIN to obtain the expected value MLTe of the multiplication number.

  The calculation circuit 24C obtains the frequency division ratio DIVO (integer) based on the expected value MLTe, the integer CTS, N, and the frequency division ratio DIVI as shown in the equation (21). The calculation circuit 26C multiplies the frequency division ratio DIVO, the ratio N / CTS, and the frequency division ratio DIVI to obtain the multiplication number MLT as shown in the equation (22). The calculation circuit 26C obtains the integer part IDIV and the decimal part FNUM / FDEN that satisfy the obtained multiplication number, and outputs the obtained integer IDIV, FNUM, FDEN to the multiplication circuit 12C.

  Then, the multiplying circuit 12C multiplies the frequency FFIN of the clock FIN by the multiplication number MLT (= IDIV + FNUM / FDEN) to generate the clock FOUT. The frequency dividing circuit 14 divides the frequency of the clock FOUT by the frequency dividing ratio DIVO to generate the output clock CLKO. In the example shown in FIG. 5, the output clock CLKO can be generated when the frequency division ratio DIVI is 8, 16, or 32.

  On the other hand, when the output clock CLKO of 1465.950886 MHz is generated from the input clock CLKI of 25 MHz, the clock generator CLKG4 receives, for example, the integer N = 1045868 and the integer CTS = 17836. The ratio N / CTS indicating the multiplication number is 58.6303543.

  The calculation circuit 18C sets the division ratio DIVI to “1” in order to satisfy the input specification (10 MHz to 50 MHz) of the frequency FFIN of the clock FIN supplied to the multiplication circuit 12C. The calculation circuit 24C obtains the frequency division ratio DIVO (integer) based on the expected value MLTe, the integer CTS, N, and the frequency division ratio DIVI as shown in the equation (21). In this example, since the right side of the equation (21) is 0.8185813124, the frequency division ratio DIVO is set to “1”.

  As described above, in this embodiment, the output clock CLKO having a desired frequency is generated from the input clock CLKI using the multiplication circuit 12C having an arbitrary frequency specification in which the multiplication number MLT is divided into the integer part IDIV and the decimal part FNUM / FDEV. it can.

  FIG. 6 shows an example of the clock generation device CLKG5 in another embodiment. Elements that are the same as or the same as those shown in FIG. 1 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The clock generation device CLKG5 includes a calculation circuit 22A illustrated in FIG. 2 instead of the calculation circuit 22 illustrated in FIG. 4, and newly includes a determination circuit 28D. Other configurations of the clock generation device CLKG5 are the same as those of the clock generation device CLKG4 shown in FIG. The clock generation device CLKG5 generates the output clock CLKO from the input clock CLKI using the multiplication circuit 12C that is a fractional PLL circuit.

  The determination circuit 28D has the same function as the determination circuit 28A shown in FIG. 2 except that it receives the integer part IDIV and the decimal part FNUM / FDEN as the multiplication number MLT. That is, the determination circuit 28D obtains the frequency FFOUT of the clock FOUT by multiplying the frequency FFIN of the clock FIN by the multiplication number MLT (= IDIV + FNUM / FDEN). The determination circuit 28D sets the determination signal JDG1 to the active level when the obtained frequency FFOUT is lower than the minimum value FOmin, and sets the determination signal JDG1 to the inactive level when the obtained frequency FFOUT is equal to or higher than the minimum value FOmin. To do. The clock generation device CLKG5 operates in the same manner as the clock generation device CLKG2 shown in FIG. 2 except that it operates by receiving integers CTS and N (ratio N / CTS) instead of the ratio FO / FI as the multiplication number.

  As described above, also in this embodiment, similarly to the embodiment shown in FIG. 4, the output clock CLKO having a desired frequency can be generated from the input clock CLKI by using the multiplier circuit 12C having an arbitrary frequency specification. Further, similarly to the embodiment shown in FIG. 2, the frequency FFOUT of the clock FOUT can be set to the minimum value that satisfies the output specification of the multiplier circuit 12C. As a result, the power consumption of the multiplier circuit 12C can be reduced, and the power consumption of the clock generation device CLKG5 can be reduced.

  FIG. 7 shows an example of the clock generation device CLKG6 in another embodiment. Elements that are the same as or the same as those shown in FIGS. 1, 3, and 4 are given the same reference numerals, and detailed descriptions thereof are omitted.

  The clock generation device CLKG6 includes calculation circuits 18B and 22A illustrated in FIG. 3 instead of the calculation circuits 18C and 22 illustrated in FIG. 4 and a determination circuit 28E. Other configurations of the clock generation device CLKG6 are the same as those of the clock generation device CLKG4 shown in FIG. The clock generation device CLKG6 generates an output clock CLKO from the input clock CLKI by using a multiplication circuit 12C that is a fractional PLL circuit.

  The determination circuit 28E has the same function as the determination circuit 28B shown in FIG. 3 except that the integer part IDIV and the decimal part FNUM / FDEN are received as the multiplication number MLT. That is, the determination circuit 28E determines the magnitude relationship between the frequency FFOUT and the minimum value FOmin and sets the determination signal JDG2 to an inactive level during a period in which the determination signal JDG1 is output. Thereafter, the determination circuit 28E determines the magnitude relationship between the frequency FFOUT and the minimum value FOmin and sets the determination signal JDG1 to an inactive level during a period in which the determination signal JDG2 is output. The operation of the clock generation device CLKG6 is the same as that of the clock generation device CLKG3 shown in FIG. 3 except that integers CTS and N (ratio N / CTS) are supplied instead of the ratio FO / FI.

  As described above, in this embodiment as well, as in the embodiment shown in FIG. 4, the multiplication number MLT is input using the multiplication circuit 12C having an arbitrary frequency specification for setting the integer number IDIV and the fractional part FNUM / FDEV separately. An output clock CLKO having a desired frequency can be generated from the clock CLKI. Further, similarly to the embodiment shown in FIG. 3, the frequency of the frequency of the clock FIN input to the multiplier circuit 12C can be lowered together with the frequency of the clock FOUT output from the multiplier circuit 12C. As a result, the power consumption of the multiplier circuit 12C can be reduced, and the power consumption of the clock generation device CLKG6 can be reduced.

  FIG. 8 shows an example of a system SYS on which the clock generation device CLKG4 shown in FIG. 4 is mounted. For example, the system SYS is a digital television. For example, the system SYS includes a semiconductor chip 100, a display 200, a memory 300, a hard disk 400, a connector 500, and a card slot 600.

  The semiconductor chip 100 includes a receiving unit 110, an image output interface 120, an audio output interface 130, a logic circuit 140, a memory interface 150, a hard disk interface 160, a serial bus interface 170, and a memory card interface 180. The reception unit 110 includes the data reception unit 112 and the clock generation device CLKG4 illustrated in FIG. That is, the receiving unit 110 has a function of receiving the input clock CLKI (corresponding to the video clock TMDS), the integers CTS, N, and data based on the HDMI standard, and generating an output clock CLKO that is an audio clock from the input clock CLKI. Have. The logic circuit 140 includes a video data processing unit 142 and an audio data processing unit 144.

  The clock generation device CLKG4 receives an input clock CLKI that is a video clock for video and integers CTS and N, and generates an output clock CLKO that is an audio clock for audio. The clock generation device CLKG4 performs initialization each time the frequency of the input clock CLKI is changed or whenever the multiplication number indicated by the integer CTS, N ratio N / CTS is changed. Then, by the initialization, the frequency division ratios DIVI and DIVO and the multiplication number MLT shown in FIG. 4 are obtained, and the output clock CLKO is output.

  The data receiver 112 operates during the normal mode after the clock generator CLKG4 is initialized. During the normal operation mode, the data receiving unit 112 extracts video data included in the data based on the input clock CLKI, extracts audio data included in the data based on the output clock CLKO, and outputs the control signal CNTL. Generate. That is, the data receiving unit 112 receives video data in synchronization with the input clock CLKI, and receives audio data in synchronization with the output clock CLKO. The data receiving unit 112 outputs the extracted video data VDT, audio data ADT, and the generated control signal CNTL to the logic circuit 140.

  The video data processing unit 142 of the logic circuit 140 converts the video data VDT into data that can be received by the display 200, and outputs the converted data to the image output interface 120. The audio data processing unit 144 of the logic circuit 140 converts the audio data ADT into data that can be received by the display 200, and outputs the converted data to the audio output interface 130.

  The image output interface 130 outputs the video data VDT from the video data processing unit 142 to the display 200. The audio output interface 140 outputs the audio data ADT from the audio data processing unit 144 to the display 200. For example, the display 200 is a liquid crystal display with a speaker. The display 200 displays an image included in the video data VDT on a liquid crystal display, and outputs sound included in the audio data ADT from a speaker.

  The memory interface 150 writes data supplied from the logic circuit 140 into the memory 300 in accordance with the control signal supplied from the logic circuit 140. Further, the memory interface 150 reads data from the memory 300 in accordance with the control signal supplied from the logic circuit 140. For example, the memory 300 is an SDRAM (Synchronous Dynamic Random Access Memory).

  The hard disk interface 160 writes the data supplied from the logic circuit 140 to the hard disk 400 in response to the control signal supplied from the logic circuit 140. In addition, the hard disk interface 160 reads data from the hard disk 400 in accordance with the control signal supplied from the logic circuit 140. For example, the hard disk interface 160 is a SATA (Serial Advanced Technology Attachment) interface.

  The serial bus interface 170 outputs the control signal and data supplied from the logic circuit 140 to the connector 500, and outputs the control signal and data supplied from the connector 500 to the logic circuit 140. For example, the serial bus interface 170 is a USB (Universal Serial Bus) interface.

  The memory card interface 180 outputs the control signal and data supplied from the logic circuit 140 to the card slot 600, and outputs the control signal and data supplied from the card slot 600 to the logic circuit 140. For example, the memory card interface 180 is an SD memory card interface, and an SD memory card is inserted into the card slot 600.

  Note that the reception unit 110 may include the clock generation device CLKG5 illustrated in FIG. 6 or the clock generation device CLKG6 illustrated in FIG. 7 instead of the clock generation device CLKG4. When the semiconductor chip 100 receives the ratio FO / FI instead of the integers CTS and N, the reception unit 110 receives the clock generation device CLKG1 illustrated in FIG. 1 instead of the clock generation device CLKG4, and illustrated in FIG. The clock generation device CLKG2 or the clock generation device CLKG3 illustrated in FIG. 3 may be included.

  FIG. 9 shows an example of the multiplier circuits 12 and 12C mounted on the clock generators CLKG1 to CLKG6 shown in FIGS. Each of the multiplier circuits 12 and 12C includes a phase comparator PFD, a charge pump CP, a low-pass filter LPF, a voltage controlled oscillator VCO, and a frequency divider PD.

  The phase comparator PFD detects the phase difference (frequency difference) between the clocks FIN and DFIN by comparing the phase of the clock FIN with the phase of the clock DFIN from the frequency divider circuit PD. The phase comparator PFD generates a control signal VUP or a control signal VDW according to the detected phase difference, and outputs the generated control signal VUP or control signal VDW to the charge pump CP.

  The charge pump CP generates a current pulse LCP indicating the phase difference between the clocks FIN and DFIN according to the control signals VUP and VDW, and outputs the generated current pulse LCP to the low-pass filter LPF. The low pass filter LPF converts the current pulse LCP into a control voltage VCNTL and outputs it to the voltage controlled oscillator VCO. The voltage controlled oscillator VCO outputs a clock FOUT having a frequency corresponding to the voltage from the low pass filter LPF.

  The frequency dividing circuit PD divides the frequency of the clock FOUT according to the multiplication number MLT to generate the clock DFIN, and outputs the generated clock DFIN to the phase comparator PFD. The frequency dividing ratio of the frequency dividing circuit PD is 1 / MLT. The frequency divider PD is a programmable frequency divider that can change the frequency of the clock DFIN according to the multiplication number MLT. In frequency multiplication circuit 12C shown in FIGS. 4, 6 and 7, frequency divider circuit PD receives integers IDIV, FNUM, and FDEN as multiplication numbers MLT (IDIV + FNUM / FDEN).

  FIG. 10 shows an example of a multiplier circuit in which a frequency divider circuit PD0 is connected to the input of the phase comparator PFD shown in FIG. For example, the multiplication circuit shown in FIG. 10 tries to generate the output clock CLKO by multiplying the input clock CLKI by the multiplication number N / CTS. That is, for example, instead of the clock generation devices CLKG1 to CLKG6 shown in FIGS. 1 to 4, 6, and 7, use of the multiplier circuit shown in FIG. 10 is attempted.

  In order to realize the multiplication number N / CTS, the integer CTS is supplied to the frequency dividing circuit PD0, and the integer N is supplied to the frequency dividing circuit PD. The frequency divider PD0 is a programmable frequency divider that can change the frequency of the output clock in accordance with the integer CTS. The frequency divider PD is a programmable frequency divider that can change the frequency of the output clock in accordance with the integer N. As described above, for example, the integer CTS is set in the range of 5461 to 1071145, and the integer N is set in the range of 2730 to 81920.

  Since the minimum value of the integer CTS is 5461, the frequency dividing circuit PD0 divides the frequency of the clock CLKI by at least one thousandth and outputs it to the phase comparator PFD. Since the minimum value of the integer N is 2730, the frequency dividing circuit PD divides the frequency of the clock CLKO by at least 1 / thousand and outputs it to the phase comparator PFD. For this reason, the frequency of the clock received by the phase comparator PFD is considerably lower than the frequency of the original clock.

  Thereby, when the phase difference of the clock supplied to the phase comparator PFD exceeds the output range of the control signals VUP and VDW, the control signals VUP and VDW following the phase difference are not generated, and the multiplication number N / CTS is set. The combined output clock CLKO is not output. Even when the control signals VUP and VDW exceed the input possible range of the charge pump CP, the current pulse LCP that follows the phase difference is not generated, and the output clock CLKO that matches the multiplication number N / CTS is not output.

  On the other hand, in the clock generation devices CLKG1 to CLKG6 shown in FIGS. 1 to 4, 6, and 7, the clock FIN having the frequency that matches the input specifications and the multiplication number MLT are supplied to the multiplication circuit 12 (or 12C). it can. As a result, the clock FOUT having a frequency suitable for the output specification can be output from the multiplier circuit 12 (or 12C), and the output clock CLKO having a desired frequency can be generated using the clock FOUT.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A first frequency dividing circuit for generating a first clock by dividing the frequency of the input clock by a first frequency division ratio;
A multiplier for multiplying the frequency of the first clock to generate a second clock;
A second frequency divider for generating an output clock by dividing the frequency of the second clock by a second frequency division ratio;
A first calculation circuit that obtains an expected value of the multiplication number of the multiplication circuit by dividing the expected value of the frequency of the second clock that can be output from the multiplication circuit by the frequency of the first clock;
A product of a reciprocal of the multiplication number, which is a ratio of the frequency of the output clock to the frequency of the input clock, and an expected value of the multiplication number obtained by the first calculation circuit is obtained, and the obtained product is obtained as the first division ratio. A second calculation circuit for obtaining an integer value obtained by dividing by the second division ratio;
A third calculation circuit for obtaining a product of a multiplication number, which is a ratio of the frequency of the output clock to the frequency of the input clock, the integer value, and the first division ratio, as a multiplication number to be given to the multiplication circuit. A clock generator characterized by comprising:
(Appendix 2)
First when the product of the frequency of the first clock and the multiplication number given to the multiplication circuit obtained by the third calculation circuit is smaller than the minimum value of the frequency of the second clock that can be output from the multiplication circuit. A determination circuit that outputs a determination signal to the first calculation circuit;
When the first calculation circuit receives the first determination signal, the first calculation circuit adds a predetermined value to the expected value of the multiplication number of the multiplication circuit to the second calculation circuit as a new expected value of the multiplication number. The clock generation device according to attachment 1, wherein the clock generation device outputs the clock.
(Appendix 3)
A fourth calculation circuit for determining the first frequency division ratio for generating the first clock having a frequency that can be supplied to the multiplication circuit;
When the product of the frequency of the first clock and the multiplication number given to the multiplication circuit obtained by the third calculation circuit is equal to or greater than the minimum value of the frequency of the second clock that can be output from the multiplication circuit, A determination circuit that outputs a determination signal to the fourth calculation circuit;
The fourth calculation circuit, when receiving the second determination signal, outputs a value obtained by adding a predetermined value to the obtained first division ratio as a new first division ratio. The clock generator according to appendix 1 or appendix 2.
(Appendix 4)
A fifth calculation circuit for determining the frequency of the first clock by dividing the frequency of the input clock by the first division ratio;
Any one of appendix 1 to appendix 3, wherein the first calculation circuit obtains an expected value of the multiplication number of the multiplication circuit using the frequency of the first clock obtained by the fifth calculation circuit. The clock generator according to Item.
(Appendix 5)
The clock generation device according to appendix 4, further comprising: a detection circuit that detects a frequency of the input clock and outputs the detected frequency to the fourth calculation circuit and the fifth calculation circuit.
(Appendix 6)
The clock according to any one of appendix 1 to appendix 5, wherein the third calculation circuit divides a multiplication number given to the multiplication circuit into an integer part and a decimal part and outputs the divided part to the multiplication circuit. Generator.
(Appendix 7)
A first frequency dividing circuit for generating a first clock by dividing the frequency of the input clock by a first frequency dividing ratio; a frequency multiplier for multiplying the frequency of the first clock to generate a second clock; A method of operating a clock generator comprising: a second frequency dividing circuit that divides a frequency of two clocks by a second frequency division ratio to generate an output clock;
Dividing the expected value of the frequency of the second clock that can be output from the multiplier circuit by the frequency of the first clock to obtain the expected value of the multiplication number of the multiplier circuit;
The product of the reciprocal of the multiplication number that is the ratio of the frequency of the output clock to the frequency of the input clock and the expected value of the multiplication number of the multiplication circuit is obtained, and the obtained product is divided by the first division ratio. The obtained integer value is obtained as the second division ratio,
A product of a multiplication number that is a ratio of the frequency of the output clock to the frequency of the input clock, the integer value, and the first division ratio is obtained as a multiplication number to be given to the multiplication circuit. How it works.
(Appendix 8)
A first determination signal is output when a product of the frequency of the first clock and the multiplication number given to the multiplication circuit is smaller than a minimum value of the frequency of the second clock that can be outputted from the multiplication circuit;
The additional value according to claim 7, wherein when the first determination signal is output, a value obtained by adding a predetermined value to an expected value of the multiplication number of the multiplication circuit is output as an expected value of a new multiplication number. A method of operating a clock generator.
(Appendix 9)
Determining the first frequency division ratio for generating the first clock having a frequency that can be supplied to the multiplier circuit;
A second determination signal is output when a product of the frequency of the first clock and the multiplication number given to the multiplication circuit is equal to or greater than a minimum value of the frequency of the second clock that can be output from the multiplication circuit;
When the second determination signal is output, a value obtained by adding a predetermined value to the obtained first division ratio is output as a new first division ratio. The operation | movement method of the clock generation apparatus of description.
(Appendix 10)
Dividing the frequency of the input clock by the first division ratio to obtain the frequency of the first clock;
The operation method of the clock generation device according to any one of appendix 7 to appendix 9, wherein an expected value of the multiplication number of the multiplication circuit is obtained using the obtained frequency of the first clock.
(Appendix 11)
A clock generator that converts the frequency of the input clock to generate an output clock; and
A data receiving unit for receiving data in synchronization with the output clock,
The clock generation device includes:
A first frequency divider that divides the frequency of the input clock by a first frequency division ratio to generate a first clock;
A multiplier for multiplying the frequency of the first clock to generate a second clock;
A second frequency divider for generating the output clock by dividing the frequency of the second clock by a second frequency division ratio;
A first calculation circuit that obtains an expected value of the multiplication number of the multiplication circuit by dividing the expected value of the frequency of the second clock that can be output from the multiplication circuit by the frequency of the first clock;
A product of a reciprocal of the multiplication number, which is a ratio of the frequency of the output clock to the frequency of the input clock, and an expected value of the multiplication number obtained by the first calculation circuit is obtained, and the obtained product is obtained as the first division ratio. A second calculation circuit for obtaining an integer value obtained by dividing by the second division ratio;
A third calculation circuit for obtaining a product of a multiplication number, which is a ratio of the frequency of the output clock to the frequency of the input clock, the integer value, and the first division ratio, as a multiplication number to be given to the multiplication circuit. A system characterized by that.
(Appendix 12)
The clock generation device is configured such that a product of a frequency of the first clock and a multiplication number given to the multiplication circuit obtained by the third calculation circuit is a minimum value of the frequency of the second clock that can be output from the multiplication circuit. A determination circuit that outputs a first determination signal to the first calculation circuit when the output is smaller than the first determination circuit;
When the first calculation circuit receives the first determination signal, the first calculation circuit adds a predetermined value to the expected value of the multiplication number of the multiplication circuit to the second calculation circuit as a new expected value of the multiplication number. The system according to appendix 11, characterized in that output.
(Appendix 13)
The clock generation device includes:
A fourth calculation circuit for determining the first frequency division ratio for generating the first clock having a frequency that can be supplied to the multiplication circuit;
When the product of the frequency of the first clock and the multiplication number given to the multiplication circuit obtained by the third calculation circuit is equal to or greater than the minimum value of the frequency of the second clock that can be output from the multiplication circuit, A determination circuit that outputs a determination signal to the fourth calculation circuit;
The fourth calculation circuit, when receiving the second determination signal, outputs a value obtained by adding a predetermined value to the obtained first division ratio as a new first division ratio. The system according to Supplementary Note 11 or Supplementary Note 12.
(Appendix 14)
The clock generation device includes a fifth calculation circuit that obtains the frequency of the first clock by dividing the frequency of the input clock by the first division ratio,
Any one of appendix 11 to appendix 13, wherein the first calculation circuit obtains an expected value of the multiplication number of the multiplication circuit using the frequency of the first clock obtained by the fifth calculation circuit. The system described in the section.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  DESCRIPTION OF SYMBOLS 10 ... Dividing circuit; 12, 12C ... Multiplication circuit; 14 ... Dividing circuit; 16 ... Detection circuit; 18, 18B, 18C, 20, 22, 22A, 24, 24C, 26, 26C ... Calculation circuit; 28A, 28B 28C, determination circuit; 30C, 32C, holding circuit, 100, semiconductor chip, 110, receiving unit, 112, data receiving unit, 120, image output interface, 130, audio output interface, 140, logic circuit, 142, video data Processing unit: 144 Audio data processing unit 150 Memory interface 160 Hard disk interface 170 Serial bus interface 180 Memory card interface 200 Display 300 Memory 400 Hard disk 500 Connector 600 Card slot; AD CLKG1, CLKG2, CLKG3, CLKG4, CLKG5, CLKG6 Clock generator; CLKI Input clock; CLKO Output clock; CNTL Control signal; CP Charge pump; CTS Integer; DIVI Divide ratio; DIVO: Dividing ratio; FCLKI: Frequency; FDEN: Integer; FFIN: Frequency; FII: Frequency information; FImin: Minimum value: FImax: Maximum value; FIN: Clock; FFOUT: Frequency; FNUM: Integer; FOmin, minimum value; FOUT, clock; IDIV, integer part; LCP, current pulse; LPF, low-pass filter; MLT, multiplication factor; MLTe, expected value; N, integer; PD, PD0, divider circuit; SYS; System; VCNTL ... Control voltage VCO ‥ voltage controlled oscillator; VDT ‥ video data; VDW, VUP ‥ control signal

Claims (6)

A first frequency dividing circuit for generating a first clock by dividing the frequency of the input clock by a first frequency division ratio;
A multiplier for multiplying the frequency of the first clock to generate a second clock;
A second frequency divider for generating an output clock by dividing the frequency of the second clock by a second frequency division ratio;
A first calculation circuit that obtains an expected value of the multiplication number of the multiplication circuit by dividing the expected value of the frequency of the second clock that can be output from the multiplication circuit by the frequency of the first clock;
A product of a reciprocal of the multiplication number, which is a ratio of the frequency of the output clock to the frequency of the input clock, and an expected value of the multiplication number obtained by the first calculation circuit is obtained, and the obtained product is obtained as the first division ratio. A second calculation circuit for obtaining an integer value obtained by dividing by the second division ratio;
A third calculation circuit for obtaining a product of a multiplication number, which is a ratio of the frequency of the output clock to the frequency of the input clock, the integer value, and the first division ratio, as a multiplication number to be given to the multiplication circuit. A clock generator characterized by comprising: First when the product of the frequency of the first clock and the multiplication number given to the multiplication circuit obtained by the third calculation circuit is smaller than the minimum value of the frequency of the second clock that can be output from the multiplication circuit. A determination circuit that outputs a determination signal to the first calculation circuit;
When the first calculation circuit receives the first determination signal, the first calculation circuit adds a predetermined value to the expected value of the multiplication number of the multiplication circuit to the second calculation circuit as a new expected value of the multiplication number. The clock generation device according to claim 1, wherein the clock generation device outputs the clock. A fourth calculation circuit for determining the first frequency division ratio for generating the first clock having a frequency that can be supplied to the multiplication circuit;
When the product of the frequency of the first clock and the multiplication number given to the multiplication circuit obtained by the third calculation circuit is equal to or greater than the minimum value of the frequency of the second clock that can be output from the multiplication circuit, A determination circuit that outputs a determination signal to the fourth calculation circuit;
The fourth calculation circuit, when receiving the second determination signal, outputs a value obtained by adding a predetermined value to the obtained first division ratio as a new first division ratio. The clock generation device according to claim 1. A fifth calculation circuit for determining the frequency of the first clock by dividing the frequency of the input clock by the first division ratio;
The said 1st calculation circuit calculates | requires the expected value of the multiplication number of the said multiplication circuit using the frequency of the said 1st clock calculated | required by the said 5th calculation circuit. 2. The clock generator according to claim 1. A first frequency dividing circuit for generating a first clock by dividing the frequency of the input clock by a first frequency dividing ratio; a frequency multiplier for multiplying the frequency of the first clock to generate a second clock; A method of operating a clock generator comprising: a second frequency dividing circuit that divides a frequency of two clocks by a second frequency division ratio to generate an output clock;
Dividing the expected value of the frequency of the second clock that can be output from the multiplier circuit by the frequency of the first clock to obtain the expected value of the multiplication number of the multiplier circuit;
The product of the reciprocal of the multiplication number that is the ratio of the frequency of the output clock to the frequency of the input clock and the expected value of the multiplication number of the multiplication circuit is obtained, and the obtained product is divided by the first division ratio. The obtained integer value is obtained as the second division ratio,
A product of a multiplication number that is a ratio of the frequency of the output clock to the frequency of the input clock, the integer value, and the first division ratio is obtained as a multiplication number to be given to the multiplication circuit. How it works. A clock generator that converts the frequency of the input clock to generate an output clock; and
A data processing unit that receives data in synchronization with the output clock,
The clock generation device includes:
A first frequency divider that divides the frequency of the input clock by a first frequency division ratio to generate a first clock;
A multiplier for multiplying the frequency of the first clock to generate a second clock;
A second frequency divider for generating the output clock by dividing the frequency of the second clock by a second frequency division ratio;
A first calculation circuit that obtains an expected value of the multiplication number of the multiplication circuit by dividing the expected value of the frequency of the second clock that can be output from the multiplication circuit by the frequency of the first clock;
A product of a reciprocal of the multiplication number, which is a ratio of the frequency of the output clock to the frequency of the input clock, and an expected value of the multiplication number obtained by the first calculation circuit is obtained, and the obtained product is obtained as the first division ratio. A second calculation circuit for obtaining an integer value obtained by dividing by the second division ratio;
A third calculation circuit for obtaining a product of a multiplication number, which is a ratio of the frequency of the output clock to the frequency of the input clock, the integer value, and the first division ratio, as a multiplication number to be given to the multiplication circuit. A system characterized by that.

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