JP2014072646A - Voltage output device and offset cancellation method for voltage output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage output device and an offset cancellation method for a voltage output device which quickly finish an offset cancellation process.SOLUTION: While a voltage appearing at an output terminal OUT of a differential amplifier 6 with a first switch element 1 establishing a short circuit between a non-inverting input terminal INP and an inverting input terminal INN thereof is supplied to current regulation means via a second switch element 2 to regulate a current value of an output current, the voltage on the output terminal OUT acquired via the second switch element 2 is held as an offset adjustment value. The non-inverting input terminal INP and the inverting input terminal INN of the differential amplifier 6 are released from the short circuit state made by the first switch element 1, and the current regulation means regulates the output current in accordance with the offset adjustment value held in the holding means.

Description

  The present invention relates to a voltage output device, and more particularly to a voltage output device having a differential amplifier and a method of offset cancellation implemented in the voltage output device.

  As such a voltage output device, a device including an offset cancel circuit that cancels an offset due to manufacturing variations of transistors formed in a differential amplifier is known (for example, Patent Document 1). reference). In such a voltage output device, a variable resistor (for example, FIG. 1 of Patent Document 1) is used as a load resistor connected to one of a pair of transistors serving as a differential pair in order to perform offset cancellation of the differential amplifier. R1) is adopted. In the offset cancellation process, first, the inverting input terminal and the non-inverting input terminal in the differential pair are short-circuited, and in this state, the resistance value of the variable resistor is gradually changed while the output signal of the differential amplifier is changed. It is determined whether or not the level is reversed (see S2 to S5 in FIG. 3 of Patent Document 1). At this time, the offset is canceled by fixing the resistance value of the variable resistor at the resistance value of the variable resistor at the time when the level of the output signal of the differential amplifier is inverted.

  However, in the method as described above, since it takes time to adjust the resistance value of the variable resistor to an appropriate resistance value, there is a problem in that it takes a long time to complete the offset cancellation.

JP2011-205515A

  An object of the present invention is to provide a voltage output device and an offset cancellation method for the voltage output device that can solve such a problem and can quickly end the offset cancellation processing.

  The voltage output device according to the present invention is a differential amplifier that outputs a voltage generated at the output terminal by sending a current according to a signal supplied to each of the non-inverting input terminal and the inverting input terminal to the output terminal; An offset cancel circuit for canceling an offset of the differential amplifier, wherein the differential amplifier adjusts a current value of the current in accordance with a signal supplied to a control terminal. The offset cancel circuit is in an ON state together with the first switch element that short-circuits the inverting input terminal and the non-inverting input terminal in the ON state, and is in the ON state. A second switch element connecting the output terminal and the control terminal, and a voltage on the output terminal supplied via the second switch element. While retaining the offset adjustment value, having a holding means for applying it to the control terminal.

  The offset cancel method of the voltage output device according to the present invention outputs the voltage generated at the output terminal by sending a current corresponding to the signal supplied to each of the non-inverting input terminal and the inverting input terminal to the output terminal. An offset canceling method for a voltage output device including a differential amplifier that adjusts a current value of the current based on a voltage generated at the output terminal in a state where the non-inverting input terminal and the inverting input terminal are short-circuited to each other On the other hand, the first step of holding the voltage generated at the output terminal as an offset adjustment value, and releasing the short-circuit state between the non-inverting input terminal and the inverting input terminal, and at the offset adjustment value of the current A second step of performing adjustment.

The voltage output device according to the present invention sends a current (I ₃ ) corresponding to a signal supplied to each of the non-inverting input terminal and the inverting input terminal (INP, INN) to the output terminal (OUT). The following offset cancellation processing is performed on the differential amplifiers (6, 11) that output the voltage generated in the above. That is, the voltage generated at the output terminal of the differential amplifier in a state in which the non-inverting input terminal and the inverting input terminal are short-circuited in the first switch element (1) through the second switch element (2). 67, 122). Accordingly, the voltage on the output terminal acquired through the second switch element is held as an offset adjustment value (AD _OFS ) while adjusting the current value of the current (I ₃ ) (RS). According to such processing, the offset amount converges to zero as the execution time elapses, and the offset adjustment value for adjusting to this offset amount state is held in the holding means (7). Thereafter, when the first and second switch elements are set to the OFF state, the short-circuit state between the non-inverting input terminal and the inverting input terminal of the differential amplifier is released, and the offset adjustment value held in the holding unit is set. The current (I ₃ ) is adjusted according to the current adjusting means (CS, AS).

  Therefore, according to the present invention, when the offset amount allowed in the specification is reached, the above-described processing (RS) can be ended, so that the variable resistor for adjusting the offset amount can be reduced. Compared with the case where an appropriate resistance value is retrieved by cut-and-try, the offset cancellation process can be completed quickly.

1 is a circuit diagram showing a voltage comparison circuit 100 as an example of a voltage output device according to the present invention. 3 is a circuit diagram showing an internal configuration of a differential amplifier section 6. FIG. 3 is a time chart showing an internal operation of the voltage comparison circuit 100. It is a circuit diagram which shows the amplifier circuit 200 as another example of the voltage output device which concerns on this invention. 2 is a circuit diagram showing an internal configuration of a differential amplifier section 11. FIG. 3 is a time chart showing an internal operation of the amplifier circuit 200. FIG. 6 is a circuit diagram showing a modification of the internal configuration of the differential amplifier section 6. FIG. 6 is a circuit diagram showing a modification of the amplifier circuit 200.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a circuit diagram showing a voltage comparison circuit 100 as an example of a voltage output device according to the present invention.

A voltage comparison circuit 100 shown in FIG. 1 is an inverter chopper type comparator, and is mounted on, for example, an A / D converter that converts an analog value into a digital value. Voltage comparator circuit 100 includes an input signal IA, which are respectively supplied to the input terminal T _A and T _B and the input signal IB and compares outputs a comparison result signal CMP indicating the comparison result from an output terminal T _OUT. The voltage comparison circuit 100 includes switch elements 1 to 5, a differential amplifier unit 6, capacitors 7 and 8, an inverter 9, and a control unit 10.

In FIG. 1, the switch element 1 is turned on only when the switch signal S1 supplied from the control unit 10 indicates that the switch is turned on. At this time, the non-inverting input terminal INP and the inverting input terminal INN of the differential amplifier unit 6 are turned on. Short-circuit each other. The switch element 2 is turned on only when the switch signal S2 supplied from the control unit 10 indicates that the switch is on. At this time, the output terminal OUT of the differential amplifier unit 6 is connected to the control terminal of the differential amplifier unit 6. The RSN, the switch element 4 and the capacitor 7 are connected to one end. Switching element 3, the switch signal S3 supplied becomes only turned on to indicate the switch-on from the control unit 10, this time, the input signal IB supplied through the input terminal T _B, the differential amplifier section 6 To the inverting input terminal INN. Note that the non-inverting input terminal INP of the differential amplifier unit 6, the input signal IA through the input terminal T _A is supplied. Switching element 4, a switch signal S4 supplied from the control unit 10 is turned only on state to indicate switch-on, this time, the reference voltage V _REF supplied through the reference voltage input terminal T _VR, differential The voltage is applied to the control terminal RSN of the amplifier unit 6, one end of the switch element 2, and one end of the capacitor 7, respectively. The ground voltage VSS is applied to the other end of the capacitor 7. The reference voltage V _REF is also supplied directly to the control terminal RSP of the differential amplifier unit 6 without going through the switch element 4.

The bias terminal BIAS of the differential amplifier 6, is biased voltage V _BIAS supplied via the bias terminal T _BS is applied to its output terminal OUT, and one end of the other end and the capacitor 8 of the switching element 2 Are connected to each other. The other end of the capacitor 8 is connected to the input end of the inverter 9 and one end of the switch element 5. The output terminal of the inverter 9 is connected to the other end of the switch element 5 and the output terminal T _OUT . The switch element 5 is turned on only when the switch signal S5 supplied from the control unit 10 indicates that the switch is on, and the input terminal and the output terminal of the inverter 9 are short-circuited. Thus, this time, the voltage of the other end of the capacitor 8 is output from the output terminal T _OUT as it is as the comparison result signal CMP. On the other hand, when the switch signal S5 indicates that the switch is off, the switch element 5 is in the off state. Therefore, a signal obtained by inverting the logic level corresponding to the voltage at the other end of the capacitor 8 by the inverter 9 is the comparison result signal CMP. Is output as

  Here, the differential amplifier section 6 forms the core of the voltage comparison circuit 100, and has an internal configuration as shown in FIG. 2, for example.

  As shown in FIG. 2, the differential amplifier section 6 includes n-channel MOS (Metal Oxide Semiconductor) transistors 61 to 63 and p-channel MOS transistors 64 to 67.

  The ground voltage VSS is applied to the source terminal of the transistor 61 as a constant current source, and the gate terminal thereof is connected to the bias terminal BIAS. The drain terminal of the transistor 61 is connected to the source terminals of the transistors 62 and 63. The transistors 62 and 63 serve as a differential pair of the input stage in the differential amplifier section 6, and the transistor 61 serves as a constant current source that generates a current flowing through the differential pair. . The gate terminal of the transistor 62 is connected to the above-described non-inverting input terminal INP, and the drain terminals thereof are connected to the gate terminals of the transistors 64 and 65 and the drain terminal of the transistor 64, respectively. The gate terminal of the transistor 63 is connected to the inverting input terminal INN, and the drain terminal thereof is connected to the output terminal OUT and the drain terminal of the transistor 65. The gate terminal of the transistor 66 is connected to the control terminal RSP, and the power supply voltage VDD is applied to its source terminal. The gate terminal of the transistor 67 is connected to the control terminal RSN, and the power supply voltage VDD is applied to its source terminal. Transistors 66 and 67 serve as an offset cancel circuit.

In the configuration shown in FIG. 2, when the input signal IA is supplied to the gate terminal of the transistor 62 via the non-inverting input terminal INP, the current I ₁ corresponding to the voltage value of the input signal IA is supplied to the transistors 62, 64, and 66. Flowing into. The transistor 66 has its on-resistance adjusted according to the reference voltage V _REF supplied to its gate terminal, thereby adjusting the current value of the current I ₁ described above. On the other hand, when the input signal IB through the inverting input terminal INN is supplied to the gate terminal of the transistor 63, the current I ₂ corresponding to the voltage value of the input signal IB flowing through the transistor 63. The transistor 61 generates a current obtained by adding the current I ₁ and the current I ₂ transmitted from each of the transistors 62 and 63 as a differential pair, according to the bias voltage V _BIAS supplied to the gate terminal. The current mirror circuit including the transistors 64 and 65 causes the current I ₃ having the same current as the current I ₁ flowing in the input-side transistor 64 to flow in the output-side transistor 65. At this time, the transistor 67 has its own on-resistance adjusted according to the voltage supplied to its gate terminal, thereby adjusting the current value of the current I ₃ described above. The operation described above, the output terminal OUT of the differential amplifier 6, the current _{I 2} and the current _{I 3} and the synthesized current, i.e. a current obtained by subtracting the current _{I 2} from the current _{I 3 (I} 3 -I ₂₎ flows The output terminal OUT has a voltage value corresponding to the amount of current. That is, when the voltage value of the input signal IA is larger than IB, the current I ₃ becomes larger than the current I ₂ , and the current (I ₃ −I ₂ ) is sent to the output terminal OUT, The voltage value increases. On the other hand, when the voltage value of the input signal IA is smaller than IB, the current I ₃ is small becomes than the current I _2, the current is extracted from the output terminal OUT side to the transistor 63. Therefore, at this time, the voltage value on the output terminal OUT decreases.

  With the above-described configuration, the differential amplifier unit 6 has a high voltage when the input signal IA is larger among the input signals IA and IB supplied to the non-inverting input terminal INP and the inverting input terminal INN, respectively. When the input signal IB is larger, an output signal having a low voltage is output from the output terminal OUT.

  Here, in the configuration shown in FIG. 1, the switch element 5, the capacitor 8, and the inverter 9 are responsible for the inverter chopper type output stage in each module excluding the differential amplifier section 6, and the switch elements 1 to 4. The capacitor 7 and the control unit 10 serve as an offset cancel circuit.

  The control unit 10 performs on / off control of the switch elements 1 to 5 according to the sequence illustrated in FIG. 3, thereby performing the above-described operation control of the output stage and offset cancellation with respect to the differential amplifier unit 6.

  In FIG. 3, first, the control unit 10 supplies switch signals S4, S1, S2 and S5 of logic level 1 indicating switch-on to the switch elements 4, 2, 4 and 5, respectively, and also indicates logic indicating switch-off. A level 0 switch signal S3 is supplied to the switch element 3 (set step SS).

By executing the set step SS, the gate terminals of the transistors 66 and 67 of the differential amplifier unit 6, the output terminal OUT of the differential amplifier unit 6, and one end of each of the capacitors 7 and 8 are set to the reference voltage _VREF . At this time, the capacitor 7 is charged in response to the application of the reference voltage V _REF , and the voltage value at one end thereof is held at the reference voltage V _REF . The reference voltage V _REF has a voltage value that is ½ of the power supply voltage VDD. Further, the switch element 1 is turned on, by an input terminal T _A and T _B between the differential amplifier 6 is connected, both the transistors 62 and 63 each of the gate terminals of the differential amplifier 6 _A voltage is applied based on the input signal IA supplied through the input terminal TA. Thus, the transistor 62 flows a current I ₁ corresponding to the input signal IA, a current I ₂ flows with the current I ₁ and the same current to the transistor 63. Further, the current I ₃ having the same current value as the current I ₁ flows into the transistor 65 by the current mirror circuit including the transistors 64 and 65. Further, since the switch element 5 is turned on by executing the set step SS and the input terminal and the output terminal of the inverter 9 are short-circuited, a p-channel MOS transistor and an n-channel MOS transistor (see FIG. Both are turned on. As a result, the voltages on the input terminal and the output terminal of the inverter 9 are both ½ of the power supply voltage VDD, that is, the same voltage (VDD / 2) as the reference voltage _VREF . Therefore, the voltage value at the other end of the capacitor 8 is set to the voltage (VDD / 2).

  Next, as shown in FIG. 3, the control unit 10 supplies switch signals S1, S2 and S5 having a logic level 1 indicating switch-on to the switch elements 1, 4 and 5, respectively, and a logic level indicating switch-off. Switch signals S4 and S3 of 0 are supplied to the switch elements 4 and 3, respectively (reset step RS).

By executing the reset step RS, the switch element 4 is switched to the OFF state, so that the voltage of the control terminal RSN of the differential amplifier unit 6 is set to the voltage of the output terminal OUT. Thereby, the voltage at the drain terminal of the transistor 65 as shown in FIG. 2 is applied to the gate terminal of the transistor 67. Here, the manufacturing variation in the transistor 62-67 has occurred, the current error is generated in the current I ₃ flowing into the current I ₂ and the transistor 65 flows to the transistor 63, the output terminal OUT, by the direction of the current Continue to descend or rise. This variation in potential is hereinafter defined as voltage drift. In the reset step RS, the output terminal OUT is connected to the gate terminal of the transistor 67 via the switch element 2. Thus, for example, when the direction of current I ₃ flowing into the transistor 65 than the current I ₂ flowing in the transistor 63 becomes large, the output terminal OUT drift to the power supply voltage VDD side, as shown in FIG. 3, the output terminal OUT Gradually increases from the state of the reference voltage V _REF to reach a peak value. Then, the voltage on the output terminal OUT drifted to the power supply voltage VDD side is supplied to the gate terminal of the transistor 67 via the control terminal RSN, so that the on-resistance of the transistor 67 provided for offset cancellation is It is adjusted to increase by the amount of drift. When the ON resistance of the transistor 67 is increased, since the gate-source voltage of the transistor 65 decreases, the current I ₃ flowing through the transistor 65 decreases.

Here, in the reset step RS, the on-resistance of the transistor 67 as described above until the current I ₂ flowing into the transistor 63 serving as the differential pair becomes equal to the current I ₃ flowing through the transistor 65 on the output side of the current mirror circuit. Adjustments are made. At this time, the state in which the current I ₂ and the current I ₃ coincide with each other is the offset canceled state, and the voltage value on the output terminal OUT obtained in this state is the offset adjustment value for canceling the offset. It is held in the capacitor 7 as AD _OFS .

  In order to make the offset amount completely zero, the control unit 10 continuously executes the reset step RS described above until the fluctuation of the voltage value on the output terminal OUT becomes zero.

  Next, as shown in FIG. 3, the control unit 10 supplies a switch signal S3 having a logic level 1 indicating switch-on to the switch element 3, and switches signals S4, S1, S2 having a logic level 0 indicating switch-off. And S5 are supplied to the switch elements 4, 2, 4 and 5, respectively (comparison step CS).

By executing the comparison step CS, the switch element 1 is turned off and the switch element 3 is turned on. For example, an input signal IA as shown in FIG. 3 is supplied to the non-inverting input terminal INP of the differential amplifier section 6. At the same time, the input signal IB is supplied to the inverting input terminal INN of the differential amplifier section 6 through the switch element 3. As a result, a current (I ₃ −I ₂ ) corresponding to the comparison result of the voltage values of the input signals IA and IB is sent to the output terminal OUT of the differential amplifier section 6. At this time, for example, when the input signal IB is larger than the input signal IA as shown in FIG. 3, a current is drawn from the output terminal OUT toward the transistor 63, and the voltage on the output terminal OUT, that is, the differential amplifier. The voltage value of the output signal of the unit 6 decreases. Further, in the comparison step CS, since the switch element 5 is turned off, the output signal is supplied to the inverter 9 via the capacitor 8. As a result, when the voltage value of the output signal falls below the threshold value, the inverter 9 sends out a comparison result signal CMP in which the voltage value transitions to a voltage value (VDD) corresponding to the logic level 1 as shown in FIG.

In the comparison step CS, since the switch element 2 is switched to the OFF state, the offset adjustment value AD _OFS held in the capacitor 7 is supplied to the control terminal RSN of the differential amplifier unit 6. Thereby, during the execution period of the comparison step CS, the differential amplifier section 6 has the offset adjustment value generated by itself, that is, the voltage drift attributed to the manufacturing variation of the transistors 62 to 67. A state of being removed by adjusting the on-resistance of the transistor 63 according to AD _OFS , that is, an offset cancel state. By the way, when the switch element 2 is switched from the on state to the off state, so-called clock feedthrough occurs in which the charge of the parasitic capacitance existing in the switch element 2 flows into the capacitor 7, thereby causing a reduction in offset cancellation accuracy. There is a fear. However, if the on-resistances of the transistors 66 and 67 provided for offset cancellation are set low, the error due to clock feedthrough is negligible. Therefore, the accuracy of the final offset cancellation is determined by the variation width of the on-resistance of each of the transistors 66 and 67.

As described above, in the voltage output apparatus (100) shown in FIGS. 1 and 2, the current (I ₃ ) corresponding to the signal supplied to the non-inverting input terminal and the inverting input terminal (INP, INN) is output to the output terminal ( The following offset cancellation processing is performed on the differential amplifier (6) that outputs the voltage generated at this output terminal by sending it to (OUT). That is, first, in the state where the non-inverting input terminal and the inverting input terminal of the differential amplifier are short-circuited by the first switch element (1), the voltage generated at the output terminal is supplied to the current via the second switch element (2). This is supplied to the adjusting means (67). Accordingly, the voltage on the output terminal acquired through the second switch element is held as an offset adjustment value (AD _OFS ) while adjusting the current value of the current (I ₃ ) (RS). According to such processing, the offset amount converges to zero as the execution time elapses, and the offset adjustment value for adjusting to this offset amount state is held in the holding means (7). Thereafter, when the first and second switch elements are turned off, the short-circuit state between the non-inverting input terminal and the inverting input terminal of the differential amplifier is released, and the offset adjustment value held in the holding means is set. The current (I ₃ ) is adjusted in the current adjusting means (CS).

  Therefore, according to the offset cancellation process in the voltage output device (100) shown in FIG. 1 and FIG. 2, the above-described process (RS) can be terminated when the offset amount allowed in the specification is reached. It becomes. Therefore, according to the voltage output device (100), the offset cancellation can be quickly performed as compared with the variable resistor for adjusting the offset amount, which is searched for an appropriate resistance value by cut and try. It can be terminated.

  In the embodiment shown in FIGS. 1 and 2, the operation of the present invention has been described using the voltage comparison circuit 100 as a voltage output device having a differential pair in the input stage. However, the voltage output device is an amplifier circuit. May be.

  FIG. 4 is a circuit diagram showing an amplifier circuit 200 as another example of the voltage output apparatus according to the present invention.

The amplifier circuit 200 shown in FIG. 4 is used as an output buffer that generates drive pulses to be supplied to a display panel such as a liquid crystal or an organic EL (Electro-Luminescence) panel. Amplifier circuit 200 and outputs the amplified signal AMP obtained by amplifying the input signal IA supplied to the input terminal _{T A} from the output terminal _{T OUT.} The amplifier circuit 200 includes switch elements 1 to 4, a capacitor 7, a control unit 10 a and a differential amplifier unit 11.

In FIG. 4, the switch element 1 is turned on only when the switch signal S1 supplied from the control unit 10a indicates that the switch is on. At this time, the non-inverting input terminal INP and the inverting input terminal INN of the differential amplifier unit 11 are turned on. Short-circuit each other. The switch element 2 is turned on only when the switch signal S2 supplied from the control unit 10a indicates that the switch is on. At this time, the output terminal OUT of the differential amplifier unit 11 is connected to the control terminal of the differential amplifier unit 11. The RSN, the switch element 4 and the capacitor 7 are respectively connected to one end. The switch element 3 is turned on only when the switch signal S3 supplied from the control unit 10a indicates that the switch is on. At this time, the output terminal OUT of the differential amplifier unit 11 and the inverting input terminal of the differential amplifier unit 11 are turned on. Connect to INN. Therefore, since the output terminal OUT of the differential amplifier section 11 is directly fed back and connected to its own inverting input terminal INN, the amplifier circuit 200 operates as a voltage follower. Note that the non-inverting input terminal INP of the differential amplifier unit 11, the input signal IA through the input terminal T _A is supplied. The switch element 4 is turned on only when the switch signal S4 supplied from the control unit 10a indicates that the switch is turned on. At this time, the reference voltage _VREF supplied via the reference voltage input terminal _{TVR is changed} to the differential signal. The voltage is applied to the control terminal RSN of the amplifier unit 11, one end of the switch element 2, and one end of the capacitor 7, respectively. The ground voltage VSS is applied to the other end of the capacitor 7. The reference voltage V _REF is also supplied directly to the control terminal RSP of the differential amplifier unit 11 without passing through the switch element 4.

The bias terminal BIAS of the differential amplifier unit 11, which is the bias voltage _{V BIAS} supplied via the bias terminal _{T BS} is applied, an output terminal OUT, the switch element 3, and the other end of the switch element 2 It is connected.

  Here, the differential amplifier unit 11 serves as the core of the amplifier circuit 200, and has an internal configuration as shown in FIG. 5, for example.

  As shown in FIG. 5, the differential amplifier section 11 includes n-channel MOS transistors 111 to 117 and p-channel MOS transistors 118 to 123.

  A ground voltage VSS is applied to the source terminal of the transistor 111 as a constant current source, and the gate terminal thereof is connected to the bias terminal BIAS of the differential amplifier unit 11 described above. The drain terminal of the transistor 111 is connected to the source terminal of each of the transistors 112 and 113. The transistors 112 and 113 are responsible for the differential pair of the input stage in the differential amplifier section 11, and the transistor 111 is responsible for a constant current source that generates a current that flows through the differential pair. . The gate terminal of the transistor 112 is connected to the above-described non-inverting input terminal INP, and the drain terminals thereof are connected to the gate terminals of the transistors 118 and 123 and the drain terminal of the transistor 118, respectively. The gate terminal of the transistor 113 is connected to the inverting input terminal INN described above, and the drain terminal thereof is connected to the gate terminals of the transistors 120 and 121 and the drain terminal of the transistor 120, respectively. The gate terminal of the transistor 119 is connected to the control terminal RSP, and the drain terminal thereof is connected to the source terminal of the transistor 118. A power supply voltage VDD is applied to the source terminals of the transistors 119 to 122. The drain terminal of the transistor 121 is connected to the gate terminals of the transistors 115 and 116 and the drain terminal of the transistor 115, respectively. The source terminal of the transistor 115 is connected to the drain terminal of the transistor 114. The gate terminal of the transistor 114 is connected to the control terminal RSP, and the ground voltage VSS is applied to its source terminal. The gate terminal of the transistor 122 is connected to the gate terminal of the transistor 117 and the control terminal RSN. The drain terminal of the transistor 122 is connected to the source terminal of the transistor 123. The drain terminal of the transistor 123 is connected to the output terminal OUT and the drain terminal of the transistor 116. A ground voltage VSS is applied to the source terminal of the transistor 117, and its drain terminal is connected to the source terminal of the transistor 116. The transistors 114, 117, 119, and 122 serve as an offset cancel circuit.

In the configuration shown in FIG. 5, when the input signal IA is supplied to the gate terminal of the transistor 112 via the non-inverting input terminal INP, a current I ₁ corresponding to the voltage value of the input signal IA is supplied to the transistors 112, 118, and 119. Flowing into. The transistor 119 has its own on-resistance adjusted in accordance with the reference voltage V _REF supplied to its gate terminal, thereby adjusting the current value of the current I ₁ described above. On the other hand, when the voltage on the output terminal OUT is supplied to the gate terminal of the transistor 113 via the inverting input terminal INN, a current I ₂ corresponding to this voltage flows in the transistors 113 and 120. The transistor 111 generates a current obtained by adding the current I ₁ and the current I ₂ sent from each of the transistors 112 and 113 as a differential pair, according to the bias voltage V _BIAS supplied to the gate terminal. The current mirror circuit including the transistors 118 and 123 causes the current I ₃ having the same current as the current I ₁ flowing in the input-side transistor 118 to flow in the output-side transistor 123. Here, the on-resistance of the transistor 122 is adjusted according to the voltage supplied to the gate terminal thereof, thereby adjusting the current value of the current I ₃ described above. The current mirror circuit including the transistors 120 and 121 causes the current I ₄ having the same current as the current I ₂ to flow through the transistors 114 and 115 in accordance with the current I ₂ flowing through the transistors 113 and 120. Here, the on-resistance of the transistor 114 is adjusted according to the reference voltage V _REF supplied to the gate terminal thereof, thereby adjusting the current value of the current I ₄ described above. Note that the current mirror circuit composed of the transistors 115 and 116 allows the current I ₅ having the same current as the current I ₄ to flow through the transistors 116 and 117. Here, the on-resistance of the transistor 117 is adjusted according to the voltage supplied to the gate terminal thereof, thereby adjusting the current value of the current I ₅ described above. The operation described above, the output terminal OUT of the differential amplifier unit 11, by subtracting the current obtained by synthesizing the current _{I 5} flowing through the current _{I 3} and the transistor 116 flowing through the transistor 123, i.e. the current _{I 5} from the current _{I 3} current (I ₃ -I ₅ ) flows.

With the configuration as described above, the differential amplifier unit 11 supplies the current (I ₃ −I ₅ ) corresponding to the difference in voltage value of the signals supplied to the non-inverting input terminal INP and the inverting input terminal INN to the output terminal OUT. An amplified signal having a voltage value corresponding to the current (I ₃ -I ₅ ) is output from the output terminal OUT.

  Here, in the configuration shown in FIG. 4, the switch elements 1 to 4, the capacitor 7, and the control unit 10 a in each module excluding the differential amplifier unit 11 serve as an offset cancel circuit.

  The control unit 10a performs offset cancellation on the differential amplifier unit 11 by performing on / off control of the switch elements 1 to 4 according to the sequence illustrated in FIG.

  In FIG. 6, first, the control unit 10a supplies switch signals S4, S1, and S2 of logic level 1 indicating switch-on to the switch elements 4, 2, and 4, respectively, and switches of logic level 0 indicating switch-off. The signal S3 is supplied to the switch element 3 (set step SS).

By the execution of the set step SS, transistors 114,117,119 and 122 each of the gate terminals of the differential amplifier unit 11, an output terminal OUT of the differential amplifier unit 11, one end of the capacitor 7 is set to the reference voltage _{V REF} . At this time, the capacitor 7 is charged in response to the application of the reference voltage V _REF , and the voltage value at one end thereof is held at the reference voltage V _REF . The reference voltage V _REF has a voltage value that is ½ of the power supply voltage VDD. Further, the switch element 1 is turned on, by an input terminal T _A and T _B between the differential amplifier unit 11 is connected, both the transistors 112 and 113 each of the gate terminals of the differential amplifier section 11 _A voltage is applied based on the input signal IA supplied through the input terminal TA. Thus, the transistor 112 flows current _{I 1} corresponding to the input signal IA, also the current _{I 2} flows having the same current value and the current _{I 1} to the transistor 113. At this time, the current I ₃ having the same current value as the current I ₁ flows into the transistor 123 by the current mirror circuit including the transistors 118 and 123. Further, a current mirror circuit consisting of transistors 120 and 121, the transistor 115, the current _{I 4} of the current _{I 2} and the same current flowing through the transistor 113 as described above flows. Further, a current mirror circuit consisting of transistors 115 and 116, the current _{I 5} of the same current value and the current _{I 4} flows through the transistors 116 and 117.

  Next, as shown in FIG. 6, the control unit 10a supplies switch signals S1 and S2 having a logic level 1 indicating switch-on to the switch elements 1 and 4, respectively, and a switch signal having a logic level 0 indicating switch-off. S4 and S3 are supplied to the switch elements 4 and 3, respectively (reset step RS).

By executing the reset step RS, the switch element 4 is switched to the OFF state, so that the voltage of the control terminal RSN of the differential amplifier unit 11 is set to the voltage of the output terminal OUT. Thereby, the voltage of the drain terminal of the transistor 123 shown in FIG. 5 is applied to the gate terminals of the transistors 17 and 122. Here, the manufacturing variation in the transistor 112 to 123 is generated, and the current error is generated in the current _{I 5} flowing into the current _{I 2} and the transistor 116 flows to the transistor 123, the voltage drift in the output terminal OUT, and that is offset Occurs. In the reset step RS, the output terminal OUT is connected to the gate terminals of the transistors 117 and 122 via the switch element 2. Therefore, when the current I ₃ flowing into the transistor 123 is larger than the current I ₅ flowing into the transistor 116, the output terminal OUT drifts to the power supply voltage VDD side, and as shown in FIG. 6, the output terminal OUT The upper voltage value gradually increases from the state of the reference voltage _VREF and reaches a peak value. Then, the voltage on the output terminal OUT drifted to the power supply voltage VDD side is supplied to the gate terminals of the transistors 117 and 122 via the control terminal RSN, so that the drift is provided for offset cancellation. Adjustment is performed so that the on-resistance of the transistor 122 increases and the on-resistance of the transistor 117 decreases. Thus, when the on-resistance of the transistor 122 increases, the gate-source voltage of the transistor 123 decreases, the current I ₃ flowing through the transistor 123 is reduced. Further, when the on-resistance of the transistor 117 is decreased, the voltage between the gate and the source of the transistor 116 is decreased, so that the current I ₅ flowing through the transistor 116 is increased.

In the reset step RS, the on-resistance of each of the transistors 117 and 122 as described above until the current I ₂ flowing into the transistor 113 serving as the differential pair becomes equal to the current I ₅ flowing through the transistor 116 on the output side of the current mirror circuit. Adjustments are made. At this time, the state in which the current I ₂ and the current I ₅ coincide with each other is the state in which the offset is canceled, and the voltage value on the output terminal OUT obtained in this state is an offset adjustment value for canceling the offset. It is held in the capacitor 7 as AD _OFS .

  In order to make the offset amount completely zero, the control unit 10a continuously executes the above-described reset step RS until the fluctuation of the voltage value on the output terminal OUT becomes zero.

  Next, as shown in FIG. 6, the control unit 10a supplies the switch element 3 with a logic level 1 switch signal S3 indicating switch-on, and also switches the logic level 0 switch signals S4, S1, and S2 indicating switch-off. Are supplied to the switch elements 4, 2 and 4, respectively (amplification step AS).

By executing the amplification step AS, the switch element 1 is turned off and the switch element 3 is turned on, so that the input signal IA is supplied to the non-inverting input terminal INP of the differential amplifier section 11 and the differential amplifier section. The eleven output terminals OUT and the inverting input terminal INN are electrically connected. Thus, the amplifier circuit 200 operates as a voltage follower and outputs the amplified signal AMP obtained an input signal IA supplied through the input terminal T _A is amplified by a gain 1 from the output terminal T _OUT.

In the amplification step AS, the switch element 2 is switched to the OFF state, so that the offset adjustment value AD _OFS held in the capacitor 7 is supplied to the control terminal RSN of the differential amplifier unit 6. Thereby, during the execution period of the amplification step AS, the differential amplifier unit 11 causes the offset generated in itself, that is, the voltage drift due to the manufacturing variation of the transistors 112 to 123 to be the offset adjustment value AD. _The transistor is removed by adjusting the on resistance of the transistors 117 and 122 according to the _OFS , that is, in an offset cancel state.

  By the way, when the switch element 2 is switched from the on state to the off state, so-called clock feedthrough occurs in which the charge of the parasitic capacitance existing in the switch element 2 flows into the capacitor 7, thereby causing a reduction in offset cancellation accuracy. There is a fear. However, if the on-resistances of the transistors 114, 117, 119, and 122 provided for offset cancellation are set low, the error due to clock feedthrough is negligible. Therefore, the final offset cancellation accuracy is determined by the ON resistance variation width of each of the transistors 114, 117, 119, and 122.

As described above, in the voltage output device (200) shown in FIGS. 4 and 5, the current (I ₃ ) corresponding to the signals supplied to the non-inverting input terminal and the inverting input terminal (INP, INN) is output to the output terminal ( The following offset cancellation processing is performed on the differential amplifier (11) that outputs the voltage generated at the output terminal by sending it to (OUT). That is, first, in the state where the non-inverting input terminal and the inverting input terminal of the differential amplifier are short-circuited by the first switch element (1), the voltage generated at the output terminal is supplied to the current via the second switch element (2). This is supplied to the adjusting means (122). Accordingly, the voltage on the output terminal acquired through the second switch element is held as an offset adjustment value (AD _OFS ) while adjusting the current value of the current (I ₃ ) (RS). According to such processing, the offset amount converges to zero as the execution time elapses, and the offset adjustment value for adjusting to this offset amount state is held in the holding means (7). Thereafter, when both the first and second switch elements are turned off, the short-circuit state between the non-inverting input terminal and the inverting input terminal of the differential amplifier is released, and the offset adjustment value held in the holding unit is set. The corresponding current (I ₃ ) is adjusted in the current adjusting means (AS).

  Therefore, according to the offset cancellation process in the voltage output device (200) shown in FIGS. 4 and 5, the process (RS) described above can be terminated when the offset amount allowed in the specification is reached. It becomes. Therefore, according to the voltage output device (200), the offset cancellation can be quickly performed as compared with a variable resistor for adjusting the offset amount, which is searched for an appropriate resistance value by cut and try. It can be terminated.

  Here, in the differential amplifier unit 6 shown in FIG. 2 or the differential amplifier unit 11 shown in FIG. 5, the output terminal OUT is directly connected to the transistors (65, 123) on the output side of the current mirror circuit. However, an output buffer for amplifying the voltage value may be provided between the two.

  FIG. 7 is a circuit diagram showing a modification of the differential amplifier section 6 shown in FIG. 2 made in view of the above points.

  The configuration shown in FIG. 7 is the same as that shown in FIG. 2 except that a p-channel MOS transistor 71 and an n-channel MOS transistor 72 as output buffers are added to the configuration shown in FIG. Is the same.

  A power supply voltage VDD is applied to the source terminal of the transistor 71, and its drain terminal is connected to the output terminal OUT and the drain terminal of the transistor 72. The gate terminal of the transistor 71 is connected to the drain terminals of the transistors 65 and 63. A ground voltage VSS is applied to the source terminal of the transistor 71, and its gate terminal is connected to the bias terminal BIAS.

According to the output buffer including these transistors 71 and 72, it is possible to output an output signal having a large amplitude via the output terminal OUT as compared with the case where the configuration shown in FIG. 2 is adopted. This increases the charging speed of the capacitor 7 that holds the voltage value on the output terminal OUT as the offset adjustment value AD _OFS , so that the driving time and the period spent for the reset step RS can be shortened.

In the above embodiment, the reference voltage V _REF whose voltage value is fixed to ½ of the power supply voltage VDD is received from the outside through the reference voltage input terminal T _VR , but this is generated in the voltage output device. You may make it do. Further, the reference voltage V _REF is not fixed to (1/2) · VDD, but is set to the same voltage value as the voltage value of the input signal supplied to the inverting input terminal or the non-inverting input terminal of the differential amplifier unit 6. You may make it do.

  FIG. 8 is a diagram showing a modification of the amplifier circuit 200 shown in FIG. 4 made in view of this point.

In the configuration shown in FIG. 8, omitting the reference voltage input terminal T _VR shown in Figure 4, the configuration other than a point that is newly provided a reference voltage generating circuit 15 is the same as that shown in Figure 4 .

8, the reference voltage generating circuit 15 generates a reference voltage V _REF voltage value of the supplied input signal IA through the input terminal T _A, and supplies it to the switching element 4 and the differential amplifier section 11 .

  Moreover, in the Example shown in FIG.1 and FIG.4, although the control part 10 (10a) which performs switch on / off control of the switch elements 1-5 is provided in a voltage output device (100,200), The control unit 10 (10a) may be provided outside the voltage output device (100, 200).

1 to 5 Switch elements 6 and 11 Differential amplifier section 7 and 8 Capacitor 9 Inverter 10 and 10a Control section

Claims (9)

A differential amplifier that outputs a voltage generated at the output terminal by sending a current corresponding to a signal supplied to each of the non-inverting input terminal and the inverting input terminal to the output terminal, and cancels the offset of the differential amplifier A voltage output device having an offset cancel circuit,
The differential amplifier has current adjusting means for adjusting a current value of the current according to a signal supplied to a control terminal,
The offset cancel circuit is
A first switch element that short-circuits the inverting input terminal and the non-inverting input terminal when in an on state;
A second switch element that is turned on together with the first switch element and connects the output terminal and the control terminal in the on state;
A voltage output device comprising: holding means for holding a voltage on the output terminal supplied via the second switch element as an offset adjustment value, and applying the offset adjustment value to the control terminal.   2. The voltage according to claim 1, further comprising a control unit that performs switch control for switching both the first and second switches to an off state after both the first and second switches are set to an on state. Output device. The differential amplifier generates a first current according to a voltage supplied to the non-inverting input terminal and generates a second current according to a voltage supplied to the inverting input terminal; A current mirror circuit that generates a third current having the same current value as the first current, and the output terminal that outputs a voltage corresponding to a current obtained by combining the second current and the third current,
3. The voltage output device according to claim 1, wherein the current adjusting unit adjusts a current value of the third current in accordance with a signal supplied to the control terminal. The current mirror circuit includes: an input-side first transistor into which the first current flows; and an output-side second transistor that sends out the third current;
The current adjusting means includes a third transistor that relays the first current to the first transistor in accordance with a reference voltage, and the second value that has been adjusted in current value in accordance with a signal supplied to the control terminal. The voltage output device according to claim 3, further comprising: a fourth transistor that relays a current to the second transistor.   5. The voltage according to claim 2, wherein the control unit maintains both the first switch and the second switch in an ON state until a variation in voltage on the output terminal becomes zero. Output device.   The voltage output device according to claim 4, wherein the reference voltage has a voltage value that is ½ of a power supply voltage for driving the differential amplifier.   6. The reference voltage generation circuit according to claim 4, further comprising a reference voltage generation circuit configured to generate a voltage having the same voltage value as a voltage value of a signal supplied to the non-inverting input terminal or the inverting input terminal as the reference voltage. The voltage output apparatus as described. An offset canceling method for a voltage output device including a differential amplifier that outputs a voltage generated at the output terminal by sending a current corresponding to a signal supplied to each of a non-inverting input terminal and an inverting input terminal to the output terminal. And
The current value of the current is adjusted based on the voltage generated at the output terminal in a state where the non-inverting input terminal and the inverting input terminal are short-circuited, while the voltage generated at the output terminal is held as an offset adjustment value. One step,
An offset canceling method for a voltage output device, comprising: a second step of canceling a short-circuit state between the non-inverting input terminal and the inverting input terminal and adjusting the current based on the offset adjustment value. .   8. The method of canceling an offset of a voltage output device according to claim 7, wherein the first step is continuously executed until the voltage fluctuation on the output terminal becomes zero.

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