JP2014072380A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the short-circuit between a contact plug and an LDD layer.SOLUTION: A gate electrode 106 is covered with a side wall 107, and the side wall 107 is covered with a protective film 108. A channel layer is formed under the gate electrode 106, and an LDD layer 111 is formed at the boundary between the channel layer and a high-concentration layer 112. A first interlayer insulating film 115 and a second interlayer insulating film 116 are formed on a semiconductor substrate 101, and a contact hole is etched to the first interlayer insulating film 115 and the second interlayer insulating film 116. In etching the contact hole, the protective film 108 protects the LDD layer 111 from the etching.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a contact plug in a semiconductor device.

  In a manufacturing process of a semiconductor device such as a DRAM (Dynamic Random Access Memory), a transistor formed on a semiconductor substrate is covered with an interlayer insulating film. Next, contact holes are formed in the interlayer insulating film until reaching the source and drain of the transistor, and a contact plug is formed by filling the contact hole with a conductor. The contact plug electrically connects the wiring layer formed on the interlayer insulating film and the source and drain in the semiconductor substrate (see Patent Documents 1 and 2).

JP 2005-150493 A JP 2012-019017 A

  With the recent reduction in transistor pitch, contact hole alignment is required to have higher accuracy. If the contact hole is too close to the gate electrode, there is a possibility that the contact plug contacts an LDD (Lightly-Doped-Drain) layer under the gate electrode. In order to reduce the transistor pitch, the pn junction of the LDD layer is formed to be very shallow. When the contact plug comes into contact with the LDD layer, an excessive leakage current flows between the contact plug and the semiconductor substrate. Problems may occur.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a sidewall on a side surface of a gate electrode formed on a semiconductor substrate, a step of forming a protective film covering the sidewall, a gate electrode and a protective film. A step of covering with a first interlayer insulating film, a step of forming a second interlayer insulating film on the first interlayer insulating film, and a step of forming a second groove extending in the second direction in the second interlayer insulating film A step of forming a mask material on the second interlayer insulating film, a step of forming a first groove extending in the first direction in the mask material, and using the mask material and the second interlayer insulating film as an etching mask And a step of forming a contact hole by etching an intersection of the first and second grooves in the first interlayer insulating film.

  According to the present invention, when a semiconductor device such as a DRAM is manufactured, it is possible to avoid a malfunction of a transistor operation due to an increase in a pn junction leakage current generated when a contact plug is in contact with an LDD layer.

FIG. 10 is a plan view of one transistor formed in a semiconductor device. It is a mask pattern figure which forms the wiring groove | channel of a transistor. It is sectional drawing which shows the manufacturing process (1st process) of the semiconductor device in 1st Embodiment. It is sectional drawing which shows the manufacturing process (2nd process) of the semiconductor device in 1st Embodiment. It is sectional drawing which shows the manufacturing process (3rd process) of the semiconductor device in 1st Embodiment. It is sectional drawing which shows the manufacturing process (4th process) of the semiconductor device in 1st Embodiment. It is sectional drawing which shows the manufacturing process (5th process) of the semiconductor device in 1st Embodiment. It is sectional drawing which shows the manufacturing process (6th process) of the semiconductor device in 1st Embodiment. It is sectional drawing which shows the manufacturing process (7th process) of the semiconductor device in 1st Embodiment. It is sectional drawing which shows the manufacturing process (8th process) of the semiconductor device in 1st Embodiment. It is sectional drawing which shows the manufacturing process (9th process) of the semiconductor device in 1st Embodiment. FIG. 3 is a cross-sectional view showing a state where the contact plug of the semiconductor device is displaced in the x direction in the first embodiment. It is sectional drawing which shows the state which the contact plug of the semiconductor device shifted | deviated to the x direction in the comparative example. It is sectional drawing which shows the manufacturing process (1st process) of the semiconductor device in 2nd Embodiment. It is sectional drawing which shows the manufacturing process (2nd process) of the semiconductor device in 2nd Embodiment. It is sectional drawing which shows the manufacturing process (3rd process) of the semiconductor device in 2nd Embodiment. It is sectional drawing which shows the manufacturing process (4th process) of the semiconductor device in 2nd Embodiment. It is sectional drawing which shows the manufacturing process (5th process) of the semiconductor device in 2nd Embodiment. It is sectional drawing of the semiconductor device in 3rd Embodiment.

  FIG. 1 is a plan view of one transistor 150 formed in the semiconductor device 100. The transistor 150 is formed in an active region partitioned by the element isolation insulating layer 102. Let P be the transistor pitch, that is, the distance between the source S and the drain D. Wiring grooves 104, 121, and 126 (second grooves) are formed in the y direction (second direction). The distance between the center of the wiring groove 104 and the center of the wiring groove 126 corresponds to the distance P between the source S and the drain D.

  Contact plugs 110 a and 110 b are formed in the wiring groove 104. The wiring formed in the wiring groove 104 is connected to the drain D of the transistor 150 through the two contact plugs 110a and 110b. Contact plugs 114 a and 114 b are also formed in the wiring groove 126. The wiring formed in the wiring groove 126 is connected to the source S of the transistor 150 through the two contact plugs 114a and 114b. A contact plug 123 is formed in the central wiring groove 121. A gate electrode 106 is formed in the wiring groove 121, and the gate electrode 106 is drawn to the outside by a contact plug 123.

  An LDD layer 111 is formed at the boundary between the gate G and the source S and between the gate G and the drain D, and a high concentration layer 112 is formed below the source S and the drain D. The contact plugs 110a and 110b and the contact plugs 114a and 114b are connected to the high concentration layer 112 (details will be described later), but should not be connected to the LDD layer 111. When the transistor pitch P is reduced, the risk that the contact plugs 110 and 114 come into contact with the LDD layer 111 increases. In the following, a method for preventing contact between the contact plugs 110 and 114 and the LDD layer 111 will be mainly described.

  FIG. 2 is a mask pattern diagram for forming a wiring groove of the transistor 150. The wiring grooves 104, 121, and 126 shown in FIG. 1 are formed by the second wiring patterns 128, 130, and 132 extending in the y direction. The first wiring patterns 134, 136, 138 extend in the x direction (first direction). The first wiring patterns 134, 136, 138 are formed below the second wiring patterns 128, 130, 132 as will be described later. Contact plugs 123, 110, 114 are formed in the cross regions of the first wiring patterns 134, 136, 138 and the second wiring patterns 128, 130, 132.

[First Embodiment]
Next, a manufacturing process of the semiconductor device 100 according to the first embodiment will be described. Hereinafter, the cross-sectional views of the AA ′ cross section and the BB ′ cross section of FIGS. 1 and 2 are shown side by side. An element isolation insulating layer 102 is formed on the semiconductor substrate 101, and a high concentration layer 112 (a source region and a drain region) is formed in a region partitioned by the element isolation insulating layer 102 (FIG. 3). A metal silicide 113 is formed on the surface of the high concentration layer 112.

  The gate electrode 106 covers the semiconductor substrate 101 with the gate insulating film 105 interposed therebetween. A lower portion of the gate insulating film 105 becomes a channel layer. An LDD layer 111 is formed in the channel layer near the boundary with the high concentration layer 112. The LDD layer 111 is a low-concentration impurity region, and suppresses generation of a high electric field in the vicinity of the high-concentration layer 112 (source S or drain D). Side surfaces of the gate electrode 106 and the gate insulating film 105 are covered with a sidewall 107 containing silicon oxide or the like as a main component. Since the LDD layer 111 is formed by ion implantation using the gate electrode 106 as a mask, and the high concentration layer 112 is formed by ion implantation using the gate electrode 106 and the sidewall 107 as a mask, the LDD layer 111 and the high concentration layer 112 are formed. Are formed in a self-aligned manner with respect to the gate electrode 106. Up to this point, it is an application of known technology.

  In the first embodiment, the protective film 108 is further formed by LPCVD (Low Pressure Chemical Vapor Deposition). The main component of the protective film 108 is silicon nitride. The protective film 108 is left only on the side surface portion of the sidewall 107 (silicon oxide) by etching back by anisotropic etching. The protective film 108 desirably has a thickness that can cover the LDD layer 111.

  Next, a first interlayer insulating film 115 is formed on the transistor 150 (FIG. 4). The main component of the first interlayer insulating film 115 is silicon oxide. Specifically, silicon oxide is deposited by CVD (Chemical Vapor Deposition) and planarized by CMP (Chemical Mechanical Polishing) to form the first interlayer insulating film 115. After the planarization, a second interlayer insulating film 116 is similarly formed on the first interlayer insulating film 115. The main component of the second interlayer insulating film 116 is silicon nitride like the protective film 108. Here, the material of the first interlayer insulating film 115 is not limited to silicon oxide, and a similar effect can be obtained by using a silicon oxide film to which impurities such as BPSG and PSG are added, or an SOD (Spin On Dielectric) film. Further, the protective film 108 and the second interlayer insulating film 116 are not limited to the silicon nitride film, and a similar effect can be obtained with a SiON film or a SiCN film.

  A first mask material 122 is further formed on the second interlayer insulating film 116 (FIG. 5). On the first mask material 122, second wiring patterns 128, 130, 132 extending in the y direction (second direction) are formed. Specifically, amorphous carbon is formed on the second interlayer insulating film 116 by plasma CVD, and the first mask material 122 is formed by covering the surface with a thin silicon oxide film. Then, the second wiring patterns 128, 130, and 132 are processed on the first mask material 122 by photolithography.

  Using the first mask material 122 as an etching mask, the second interlayer insulating film 116 is etched until the first interlayer insulating film 115 is exposed (FIG. 6). In accordance with the second wiring patterns 128, 130, and 132, wiring grooves 104, 121, and 126 (second grooves) extending in the y direction are formed in the second interlayer insulating film 116. The first mask material 122 is removed by oxygen plasma treatment (FIG. 7).

  Next, a second mask material 124 (mask material) is formed so as to bury the wiring trench 121 (FIG. 8). Specifically, the second mask material 124 is formed by applying Bottom Anti-Reflection Coating (BARC), and the first wiring patterns 134, 136, and 138 are processed on the second mask material 124 by a photolithography technique. That is, the second mask material 124 has five openings (first grooves) of the first wiring patterns 134, 136a, 136b, 138a, and 138b extending in the x direction (first direction). In summary, the second wiring patterns 128, 130, and 132 shown in FIG. 2 are formed as openings in the second interlayer insulating film 116, and the first wiring patterns 134, 136 a, 136 b, 138 a, and 138 b are formed on the second mask material 124. It is formed as an opening. As a result, the first interlayer insulating film 115 is exposed only from the cross regions of these patterns. These cross regions correspond to the five contact plugs 123, 110a, 110b, 114a, 114b (see FIGS. 1 and 2).

  Using the second interlayer insulating film 116 and the second mask material 124 as a mask, the first interlayer insulating film 115 is etched to form a contact hole 118 in the first interlayer insulating film 115 (FIG. 9). The size of the contact hole 118 is determined by the pattern width of the first wiring pattern 134 and the like and the second wiring pattern 128 and the like. The etching at this time is performed under an etching condition in which the etching rate of the first interlayer insulating film 115 is higher than the etching rates of the second interlayer insulating film 116 and the second mask material 124. In other words, the etching is performed under the condition that the second interlayer insulating film 116 and the second mask material 124 are less likely to be etched than the first interlayer insulating film 115.

  When the contact hole 118 is formed, the protective film 108 may be exposed. However, in this embodiment, since the protective film 108 and the second interlayer insulating film 116 are both composed mainly of silicon nitride, the protective film 108 can withstand etching even if the first interlayer insulating film 115 is etched. be able to. Note that the protective film 108 and the second interlayer insulating film 116 need not be made of the same material. At least the etching of the contact hole 118 needs to be performed under the etching conditions that the etching rate of the first interlayer insulating film 115 is higher than the etching rate of the protective film 108. In other words, since the protective film 108 serves as an etching stopper to protect the LDD layer 111 from etching, the connection between the LDD layer 111 and the contact hole 118 can be prevented.

  After the contact hole 118 is formed, the second mask material 124 is removed (FIG. 10). A barrier metal 125 is formed in the contact hole 118, filled with wiring material, and excess wiring material is removed by CMP to form the wiring layer 120 (FIG. 11). The barrier metal 125 is a laminated film in which titanium and titanium nitride are sequentially formed, and tungsten is used as a wiring material.

  In the present embodiment, a contact plug that penetrates the first interlayer insulating film 115 and the second interlayer insulating film 116 in the z direction can be formed (FIG. 12). Further, the interval between the wiring grooves 104, 121, and 126 can be maintained. As shown in FIG. 1, the contact hole 118 is aligned with respect to the element isolation insulating layer 102, the wiring trench 126, and the like. Further, even if the position of the contact hole 118 is slightly shifted in the x direction or the y direction, the LDD layer 111 and the contact plug can be prevented from being short-circuited by the protective film 108.

  On the other hand, a manufacturing method is also conceivable in which a contact hole is once formed in the first interlayer insulating film 115, a second interlayer insulating film 116 is formed, and a wiring layer 120 is further formed in the second interlayer insulating film 116 ( FIG. 13: Comparative example). In this case, a positional shift occurs between the contact hole of the first interlayer insulating film 115 and the wiring layer 120 of the second interlayer insulating film 116. Therefore, the width of the wiring layer 120 must be designed to be larger than the width of the contact hole. I must. As a result of the widening of the wiring layer 120, the inter-wiring distance is shortened, so that parasitic capacitance increases and signal quality deteriorates. Further, when the protective film 108 is not provided as shown in FIG. 13, there is a possibility that the LDD layer 111 may be short-circuited with the wiring layer 120 via the contact plug 123 when the contact hole reaches the LDD layer 111. is there. In particular, such a risk becomes more apparent as the transistor pitch is reduced. On the other hand, according to the semiconductor device 100 shown in the first embodiment, the wiring layer 120 does not need to be excessively thick, and a short circuit between the LDD layer 111 and the contact plug 123 can be prevented.

[Second Embodiment]
In the first embodiment, after the protective film 108 is formed by LPCVD (Low Pressure Chemical Vapor Deposition), the protective film 108 is left only on the side surface portion of the sidewall 107 by etch back by anisotropic etching. In the second embodiment, anisotropic etch back is not performed (FIG. 14). Therefore, the protective film 108 remains not only on the side surface of the sidewall 107 but also on the gate electrode 106 and the upper surface of the semiconductor substrate 101 (the high concentration layer 112 and the element isolation insulating layer 102). The process of forming the first interlayer insulating film 115 and the second interlayer insulating film 116 and forming the wiring trench 104 and the like in the second interlayer insulating film 116 is the same as in the first embodiment.

  A second mask material 124 for embedding the wiring groove 121 is formed, and first wiring patterns 136, 138, etc. are processed in the second mask material 124 (FIG. 15). Using the second mask material 124 and the second interlayer insulating film 116 as a mask, the first interlayer insulating film 115 (silicon oxide) is etched (hereinafter referred to as “first etching”) to form a contact hole 118 (FIG. 16). ). At this time, since the protective film 108 remaining on the semiconductor substrate 101 functions as an etching stopper, the possibility that the contact hole 118 penetrates the high concentration layer 112 and is drilled to the semiconductor substrate 101 is remarkably reduced.

  When the protective film 108 is exposed, the etching conditions for the protective film 108 (silicon nitride) are changed, and etching (hereinafter referred to as “second etching”) is continued (FIG. 17). Thus, a contact hole 118 connected to the high concentration layer 112 (source region and drain region) is formed. In the second embodiment, there is an advantage that the depth of the contact hole 118 can be easily adjusted to the position of the high concentration layer 112 by using the protective film 108 as an etching stopper. Finally, the barrier metal 125 and the wiring trench 126 are embedded in the protective film 108 (FIG. 18). Thus, the conductive contact plug 123 is formed in the contact hole 118.

[Third Embodiment]
In the third embodiment, instead of using an arbitrary material for the second interlayer insulating film 116, an etching stopper layer 117 of silicon nitride is formed on the second interlayer insulating film 116 (FIG. 19). In general, the relative dielectric constant of silicon nitride is about 7, but the relative dielectric constant of silicon oxide is about 4. Therefore, if the second interlayer insulating film 116 is formed using silicon oxide as a main component, there is an advantage that the capacitance between wirings can be suppressed.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  DESCRIPTION OF SYMBOLS 100 Semiconductor device, 101 Semiconductor substrate, 102 Element isolation insulating layer, 104 Wiring groove, 105 Gate insulating film, 106 Gate electrode, 107 Side wall, 108 Protective film, 110 Contact plug, 111 LDD layer, 112 High concentration layer, 113 Metal Silicide, 114 contact plug, 115 first interlayer insulating film, 116 second interlayer insulating film, 117 etching stopper layer, 118 contact hole, 120 wiring layer, 121 wiring groove, 122 first mask material, 123 contact plug, 124 second Mask material, 125 barrier metal, 126 wiring groove, 128 second wiring pattern, 130 second wiring pattern, 132 second wiring pattern, 134 first wiring pattern, 136 first wiring pattern, 138 first wiring pattern, 150 ton Njisuta.

Claims (10)

Forming a sidewall on the side surface of the gate electrode formed on the semiconductor substrate;
Forming a protective film covering the sidewall;
Covering the gate electrode and the protective film with a first interlayer insulating film;
Forming a second interlayer insulating film on the first interlayer insulating film;
Forming a second groove extending in a second direction in the second interlayer insulating film;
Forming a mask material on the second interlayer insulating film;
Forming a first groove extending in a first direction in the mask material;
Forming a contact hole by etching an intersection of the first and second grooves in the first interlayer insulating film using the mask material and the second interlayer insulating film as an etching mask;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 1, wherein the protective film is exposed when the contact hole is formed.   The etching conditions for the first interlayer insulating film and the protective film are set so that the etching rate of the protective film is smaller than that of the first interlayer insulating film when the contact hole is formed. Item 3. A method for manufacturing a semiconductor device according to Item 1 or 2.   4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of embedding a conductor in both the contact hole and the second groove after forming the contact hole. 5. .   5. The method of manufacturing a semiconductor device according to claim 1, wherein the first interlayer insulating film is formed with silicon oxide as a main component, and the protective film is formed with silicon nitride as a main component. .   6. The method of manufacturing a semiconductor device according to claim 1, wherein the second interlayer insulating film and the protective film are mainly composed of the same material.   7. The protective film according to claim 1, wherein the protective film is formed on the surfaces of the gate electrode and the semiconductor substrate, and the rest of the protective film is removed by anisotropic etching while leaving a side surface portion of the gate electrode. The manufacturing method of the semiconductor device in any one. The protective film is formed on the surface of the gate electrode and the semiconductor substrate,
7. The method of manufacturing a semiconductor device according to claim 1, wherein when forming the contact hole, the protective film on the surface of the semiconductor substrate is used as an etching stopper. 8.   9. The method of manufacturing a semiconductor device according to claim 8, wherein when the protective film on the surface of the semiconductor substrate is exposed, the opening of the contact hole is continued after changing the etching conditions.   The method for manufacturing a semiconductor device according to claim 8, further comprising a step of forming an etching stopper layer on the second interlayer insulating film.

Images