JP2014068208A - Chattering removal circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a chattering removal circuit that easily selects a chattering-removable interval.SOLUTION: The chattering removal circuit includes: a section for detecting a rising edge of an input signal; a falling edge detection section; a Hi signal generation section for generating a predetermined pulse in response to detecting an edge of an output signal of the rising edge detection section; a Low signal generation section; a state machine section for generating an output signal whose state transitions on the basis of such pulses generated and output from the Hi signal generation section and Low signal generation section; and an output generation section comprising a first gate fed with output signals of a plurality of flip-flops constituting the Hi signal generation section, a second gate fed with output signals of a plurality of flip-flops constituting the Low signal generation section, and a third gate for generating an output signal on the basis of output signals of the first and second gates and the output signal of the state machine section.

Description

  The present invention relates to a chattering removal circuit, and more particularly to removal of chattering that occurs at the time of toggling an electrical signal.

  When an electrical signal is turned on / off using a switch or relay with a mechanical on / off contact, chattering that repeats intermittent contact at high speed within a short time due to the influence of mechanical fine vibration from the outside. May occur.

  When chattering occurs in the digital signal system of the digital circuit, the digital circuit recognizes that on / off due to chattering is the same on / off as a normal digital signal, which may cause a malfunction.

  Therefore, for example, when trying to measure the pulse width of a digital signal by sampling with a clock, a circuit that removes chattering is used to prevent malfunction of the digital circuit due to chattering that occurs during toggle. It is done.

  FIG. 11 is a logic circuit provided in the preceding stage of the input signal pulse width measuring circuit, and FIG. 12 is a timing chart for explaining the operation thereof.

  This logic circuit samples the input signal D with the clock CLK in order to measure the pulse width by the clock synchronous operation.

  When chattering exists in the input signal D, the output signal Q can take changes as shown in 1) to 4), for example. It is unpredictable which change will depend on the timing of the input signal D and the clock CLK.

  In the example of FIG. 12, in the case of 1), two pulses are observed, a pulse having a pulse width PW11 corresponding to one clock cycle and a pulse having a pulse width PW12 corresponding to seven clock cycles. Becomes PW2 for nine clock cycles, the pulse width of 3) becomes PW3 for nine clock cycles, and the pulse width of 4) becomes PW4 for seven clock cycles. That is, the measurement result varies from the minimum pulse width PW11 for one clock cycle to the maximum PW2 and PW3 for nine clock cycles.

  5) is a signal from which chattering is removed, and is an idea that the first toggle at the start of chattering is regarded as a true signal toggle. When the signal 5) is sampled with the clock CLK, the pulse width of the output signal becomes PW6 corresponding to 9 cycles of the clock as shown in 6), and the pulse width measurement result does not vary.

  FIG. 13 is an example of a conventional circuit used for generating a signal from which chattering is removed as in 5). This is a general circuit that eliminates chattering generated at the contacts a and b of the two-contact switch SW, and chattering is removed from the output signal Q by using the characteristics of the SR latch. Here, “˜S” indicates an inverted signal of the set signal S at the contact a, and “˜R” indicates an inverted signal of the reset signal R at the contact b.

  The SR latch is composed of two NOR gates NG1 and NG2. One input terminal a of the NOR gate NG1 is connected to the contact a of the switch SW and is connected to the + 5V power line through a 1 KΩ resistor, and the other input terminal b is connected to the output terminal c of the NOR gate NG2. . One input terminal a of the NOR gate NG2 is connected to the output terminal c of the NOR gate NG1, and the other input terminal b is connected to the contact b of the switch SW and connected to the + 5V power supply line through a 1 KΩ resistor. .

  FIG. 14 is a timing chart for explaining the operation of FIG. In FIG. 14, chattering occurs on the contact b side when the switch SW is switched from the contact a to b, and chattering occurs on the contact a side when the switch SW is switched from the contact b to a.

  In the time slot (a) immediately before chattering occurs on the contact b side, ~ S = 1 and ~ R = 1, and the output Q maintains the current state. In the time slot (b) immediately after chattering occurs on the contact b side, ~ S = 1 and ~ R = 0, and the output Q transitions to “0”. In the time slot (c) in which chattering is occurring on the contact b side, ˜S = 1 and ˜R = 1, and the output Q maintains the current state. In the time slot (d) when the chattering on the contact b side ends, ~ S = 1 and ~ R = 0, so the output Q becomes "0".

  In the time slot (e) immediately before chattering occurs on the contact a side, ~ S = 1 and ~ R = 1, and the output Q maintains the current state. In the time slot (f) immediately after chattering occurs on the contact a side, ~ S = 0 and ~ R = 1, and the output Q transitions to “1”. In the time slot (g) in which chattering is occurring on the contact a side, ~ S = 1 and ~ R = 1, and the output Q maintains the current state. In the time slot (h) in which chattering is occurring on the contact a side, since ~ S = 0 and ~ R = 1, the output Q becomes “1”. In the time slot (i) in which chattering is occurring on the contact a side, ~ S = 1 and ~ R = 1, and the output Q maintains the current state. In the time slot (j) at which the chattering on the side of the contact a ends, ˜S = 0 and ˜R = 1, so the output Q becomes “1”.

  FIG. 15 shows a modified circuit of FIG. 13 using an SR latch, which is not limited to a two-contact switch and is modified so that it can be applied to general signals. In FIG. 15, one input terminal a of the AND gates AG1 and AG2 is commonly connected to the output terminal of the D flip-flop circuit LC2, and the input signal D is commonly input to the other input terminal b.

  The output terminal of the AND gate AG1 is connected to one input terminal a of the AND gate AG3 constituting the SR latch, and the output terminal of the AND gate AG2 is connected to the other input terminal b of the AND gate AG4 constituting the SR latch. Yes. The other input terminal b of the AND gate AG3 is connected to the output terminal of the AND gate AG4, and the output terminal of the AND gate AG3 is connected to one input terminal a of the AND gate AG4.

  The output terminal of the AND gate AG4 outputs the output signal Q and is connected to the input terminal of the D flip-flop circuit LC1, and the output terminal of the D flip-flop circuit LC1 is connected to the input terminal of the D flip-flop circuit LC2. . That is, the AND gates AG1, AG2, SR latch, and D flip-flop circuits LC1, LC2 are connected in a loop.

  FIG. 16 is a timing chart for explaining the operation of FIG. In one area (a) surrounded by a broken line, the output signal vth_2 of the D flip-flop circuit LC2 is fixed to “1” and the signal S is fixed to “0”. Therefore, the signal R shown in FIG. When the output signal Q transitions to “0” at the first rise of the output signal Q, the output signal Q is subsequently maintained at “0”.

  On the other hand, in the other region (c) surrounded by a broken line, the output signal vth_2 of the D flip-flop circuit LC2 is fixed to “0” and the signal R is fixed to “0”. When the output signal Q transitions to “1” at the first rising edge of the signal S shown in FIG.

However, according to the circuit configuration of FIG. 15, there is the following problem when trying to mount on the ASIC.
1) SR latch cannot be used in a general ASIC library.
2) It contains a loop of combinational circuits that is prohibited in general ASIC design.

  Therefore, as a circuit for realizing the chattering removal function without using the SR latch, a circuit as shown in FIG. 17 described in Patent Document 1 has been proposed. An outline of the operation of the circuit of FIG. 17 will be described with reference to the timing chart of FIG.

  Reference numeral 211 denotes an input terminal, 212 denotes a clock pulse input terminal, and 213 denotes a signal output terminal. In the following description, the input signal is 211, the clock pulse is 212, and the output signal is 213.

  The D flip-flop circuit 201 has a reset terminal R that resets the output Q to L, and takes in the input D (in this case, H) at the rising edge of the clock CK. An output terminal 213 is connected to one input terminal of the OR circuit 202, a signal input terminal 211 is connected to the other input terminal, and an output terminal is connected to the clock terminal CK of the D flip-flop 201. The D flip-flop circuit 201 and the OR circuit 202 constitute a first flip-flop circuit 203.

  The D flip-flop circuit 204 has a reset terminal R that resets the output Q to L, and takes in the input D (in this case, H) at the falling edge of the clock NCK. A signal input terminal 211 is connected to one input terminal of the AND circuit 205, an output terminal 213 is connected to the other input terminal, and an output terminal is connected to the clock terminal NCK of the D flip-flop 204. The D flip-flop circuit 204 and the AND circuit 205 constitute a second flip-flop circuit 206.

  The D flip-flop circuit 207 takes in the input D at the rising edge of the clock CK, and the output terminal NQ is connected to the input terminal D. The output terminal Q of the D flip-flop 201 is connected to one input terminal of the OR circuit 208, the output terminal Q of the D flip-flop 204 is connected to the other input terminal, and the output terminal is the clock terminal of the D flip-flop 207. Connected to CK. The D flip-flop circuit 207 and the OR circuit 208 constitute a third flip-flop circuit 209.

  In the first flip-flop circuit 203, when the input signal 211 rises when the output signal 213 is 0 (low level, hereinafter low), the output signal 215 of the D flip-flop 201 becomes 1 (high level, hereinafter hi). Once the output signal 215 becomes Hi, it remains Hi until it returns to Low due to the rise of the clock pulse 212. That is, until the clock pulse 212 rises after the input signal 211 rises, the output signal 215 rises once (Low → Hi transition), no matter how many times the input signal 211 toggles.

  When the output signal 213 is Hi, the output signal 215 of the D flip-flop 201 is not Hi with respect to the rising edge of the input signal 211. When the output signal 215 is originally Hi, Hi is maintained.

  In the second flip-flop circuit 206, when the input signal 211 falls when the output signal 213 is Hi, the output signal 217 of the D flip-flop 204 becomes Hi. Once the output signal 217 becomes Hi, Hi remains until it returns to Low due to the rise of the clock pulse 212. That is, until the clock pulse 212 rises after the input signal 211 falls, the output signal 217 rises once (Low → Hi transition) no matter how many times the input signal 211 toggles.

  When the output signal 213 is Low, the output signal 217 of the D flip-flop 204 does not become Hi with respect to the fall of the input signal 211. When the output signal 217 is originally Hi, Hi is maintained.

  The output signal 213 is inverted by the rise of the output signal 215 of the D flip-flop 201 or the output signal 217 of the D flip-flop 204.

  When the output signal 213 is low, the output signal 215 of the D flip-flop 201 rises due to the rise of the input signal 211, but the output signal 217 of the D flip-flop 204 does not rise due to the fall of the input signal 211. As described above, until the clock pulse 212 rises, the output signal 215 of the D flip-flop 201 rises once even if the input signal 211 is toggled many times. As the output signal 215 rises, the output signal 213 is inverted and becomes Hi.

  When the output signal 213 is Hi, the output signal 217 of the D flip-flop 204 rises due to the fall of the input signal 211, but the output signal 215 of the D flip-flop 201 does not rise due to the rise of the input signal 211. Further, as described above, until the clock pulse 212 rises, the output signal 217 of the D flip-flop 204 rises once even if the input signal 211 is toggled many times. As the output signal 217 rises, the output signal 213 is inverted and becomes Low.

  As described above, even if the input signal 211 includes chattering, the output signal 213 is inverted only at the first signal toggle of chattering, so that the output signal 213 becomes a signal from which chattering has been removed.

  As the clock pulse 212 rises, the output signal 215 of the D flip-flop 201 and the output signal 217 of the D flip-flop 204 become Low, and can rise again due to the change of the input signal 211.

  In this way, chattering in the section from the first signal toggle to the falling edge of the clock pulse 212 is eliminated, but if the chattering continues for a long time after the falling edge of the clock pulse 212, the output signal 213 is invalid. Become.

JP-A-10-126231

However, the circuit of FIG. 17 has the following problems.
That is, as shown in the timing chart of FIG. 19, chattering removal can be hardly performed depending on the timing due to a change in the section where chattering can be removed depending on the timing relationship between the occurrence of chattering in the input signal 211 and the clock pulse 212. is there.

  Section A is a case where chattering occurs in the input signal 211 between the clock pulses 212, and the level of the output signal 213 is kept constant without being affected by chattering. On the other hand, the section B is a case where chattering occurs in the input signal 211 at the timing at which the clock pulse 212 is sandwiched, and the level of the output signal 213 is affected by chattering as shown in a region C surrounded by a broken line. Have changed.

  Further, the signal 212 for controlling the reset input of the D flip-flops 201 and 204 is required. The signal 212 is based on the assumption that pulses are periodically input, and a clock signal is considered as a general candidate.

  However, since there are design restrictions based on the following two points, it is difficult to use a clock signal, and a special circuit for generating this signal is required outside.

1) Since it is connected to the reset input instead of the clock input of the D flip-flops 201 and 204, normal clock tree synthesis cannot be applied.
2) Since the circuit behavior can be changed depending on the duty ratio of the signal 212, it is preferable that the Hi width is narrow, which is a restriction on the clock signal waveform.

  The present invention pays attention to these conventional problems, and its purpose is to be compatible with ASIC design, to reliably eliminate chattering within a predetermined period, and to easily remove a chattering-removable section. An object of the present invention is to provide a chattering elimination circuit that can be selected.

The invention of claim 1 which achieves such a problem,
A rising edge detector that includes a gate in the input unit and a flip-flop in the output unit to detect the rising edge of the input signal;
A falling edge detection unit for detecting a falling edge of an input signal in which a gate is provided in an input unit and a flip-flop is provided in an output unit;
It is composed of a plurality of flip-flops and gates to which the output signals of these flip-flops are input, detects an edge of the output signal of the rising edge detector, generates a predetermined pulse, and uses this pulse as a flip-flop of the rising edge detector Hi signal generator for feedback input to the
It comprises a plurality of flip-flops and a gate to which the output signals of these flip-flops are input, detects an edge of the output signal of the falling edge detector, generates a predetermined pulse, and generates this pulse as the falling edge detector Low signal generator for feedback input to the flip-flop,
A state machine unit that generates an output signal whose state transitions based on a pulse generated and output from the Hi signal generation unit and the Low signal generation unit and inputs the feedback to each gate of the rising edge detection unit and the falling edge detection unit,
A first gate to which output signals of a plurality of flip-flops constituting the Hi signal generation unit are input; a second gate to which output signals of a plurality of flip-flops constituting the Low signal generation unit are input; An output generation unit composed of an output signal of the first and second gates and a third gate for generating an output signal based on the output signal of the state machine unit;
Is a chattering elimination circuit.

The invention of claim 2 provides the chattering elimination circuit of claim 1,
A chattering-removable section is set according to the number of stages of flip-flops connected to the Hi signal generation unit and the Low signal generation unit.

The invention of claim 3 is the chattering elimination circuit according to claim 1 or 2,
A selector is provided that changes a chattering-removable section by interlockingly switching the number of stages of flip-flops connected to the Hi signal generation unit and the Low signal generation unit.

  Accordingly, it is possible to realize a chattering removal circuit that facilitates ASIC design, can reliably remove chattering within a predetermined period, and can easily select a chattering-removable section.

It is a block diagram which shows one Example of this invention. 2 is a timing chart for explaining operations of a rising edge detection unit 1 and a falling edge detection unit 2 in FIG. 1. 6 is a timing chart for explaining the operation of the Hi signal generation unit 3. 2 is a timing chart for explaining the operation of the entire circuit of FIG. It is a timing chart explaining the operation | movement of the example in which chattering is included at the time of the rising of input signal S1. It is a timing chart explaining the chattering removal area based on this invention. It is a timing chart explaining the length of the chattering removal section based on this invention. It is a block diagram which shows the other Example of this invention. It is a timing chart explaining the operation | movement of FIG. It is a block diagram which shows the other Example of this invention. It is a logic circuit provided in the preceding stage of the pulse width measuring circuit of the input signal. 12 is a timing chart illustrating the operation of FIG. 11. It is an example of a conventional circuit used for generating a signal from which chattering has been removed. It is a timing chart explaining the operation | movement of FIG. 14 is a modified circuit of FIG. 13 using an SR latch. 16 is a timing chart illustrating the operation of FIG. It is a conventional circuit example figure which implement | achieves a chattering removal function, without using SR latch. 18 is a timing chart for explaining the operation of FIG. 18 is another timing chart for explaining the operation of FIG.

  Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. The chattering elimination circuit of FIG. 1 includes a rising edge detection unit 1, a falling edge detection unit 2, a Hi signal generation unit 3, a Low signal generation unit 4, a state machine unit 5, and an output generation unit 6. Has been.

  It is assumed that chattering may occur when the input signal S1 is toggled between 0 (Low level, hereinafter also referred to as Low) / 1 (High level, hereinafter also referred to as Hi). The input signal S 1 is input to the Hi signal generation unit 3 through the rising edge detection unit 1 and also input to the Low signal generation unit 4 through the falling edge detection unit 2. The Hi signal generation unit 3 and the Low signal generation unit 4 are connected to the state machine unit 5 and also to the output generation unit 6.

  Accordingly, as described below, the output signal S2 from which chattering has been removed is output from the output generation unit 6.

  The rising edge detector 1 is composed of a gate G1 and a flip-flop FF1, the falling edge detector 2 is composed of a gate G2 and a flip-flop FF2, and the Hi signal generator 3 is composed of three flip-flops FF3 to FF5. The low signal generation unit 4 includes three flip-flops FF6 to FF8 and a gate G4, and the output generation unit 6 includes three gates G5 to G7.

  The input signal S1 is input to one input terminal of the gate G1 constituting the rising edge detection unit 1, the output signal S5 of the state machine unit 5 is input to the other input terminal, and the output signal SG1 is the flip-flop FF1. Is input to the clock terminal. The data input terminal of the flip-flop FF1 is fixed at the Hi level, and the output signal SF1 is input to the input terminal of the Hi signal generation unit 3 and also to the first input terminal of the gate G5 constituting the output generation unit 6. The asynchronous reset terminal R is connected to the output terminal of the gate G3 constituting the Hi signal generation unit 3.

  The input signal S1 is input to one input terminal of the gate G2 constituting the falling edge detection unit 2, the output signal S5 of the state machine unit 5 is input to the other input terminal, and the output signal SG2 is the flip-flop FF2. Is input to the clock terminal. The data input terminal of the flip-flop FF2 is fixed to Hi level, and the output signal SF2 is input to the input terminal of the Low signal generation unit 4 and input to the first input terminal of the gate G6 constituting the output generation unit 6, The asynchronous reset terminal R is connected to the output terminal of the gate G4 constituting the Low signal generator 4.

  The output signal SF3 of the flip-flop FF3 constituting the Hi signal generation unit 3 is input to the data input terminals of the flip-flops FF4 and FF5 and also input to the second input terminal of the gate G5 constituting the output generation unit 6. Yes. The output signal SF4 of the flip-flop FF4 is input to one input terminal of the gate G3, and the output signal SF5 of the flip-flop FF5 is input to the other input terminal of the gate G3, and the output signal SF5 of the gate G5 constituting the output generation unit 6 is output. 3 is input to the input terminal.

  The output signal SF6 of the flip-flop FF6 that constitutes the Low signal generation unit 4 is input to the data input terminals of the flip-flops FF7 and FF8, and is also input to the second input terminal of the gate G6 that constitutes the output generation unit 6. Yes. The output signal SF7 of the flip-flop FF7 is input to one input terminal of the gate G4, the output signal SF8 of the flip-flop FF8 is input to the other input terminal of the gate G4, and the output of the gate G6 constituting the output generation unit 6 is output. 3 is input to the input terminal.

  The state machine unit 5 has two internal states of stat = 0 and stat = 1, and updates the internal state at the rising edge of the clock CLK. During the state stat = 0, 0 is output as the output signal S5, and during the state stat = 1, 1 is output as the output signal S5.

  The output signal S5 is input to the second input terminal of the gate G7 constituting the output generation unit 6, and the other input terminal of the gate G1 constituting the rising edge detection unit 1 and the falling edge as described above. The signal is input to the other input terminal of the gate G2 constituting the edge detection unit 2.

  When the edger input (signal SG3) becomes 1 when the state stat = 0, the state stat = 1 transitions. When the edgef input (signal SG4) becomes 1 when the state stat = 1, the state stat = 0 transitions. The current state is maintained for other state / input combinations.

  The clock terminals of the three flip-flops FF3 to FF5 constituting the Hi signal generation unit 3, the clock terminals of the three flip-flops FF6 to FF8 constituting the Low signal generation unit 4, and the clock of the state machine unit 5 The clock CLK from the clock generator 7 is input to the terminal.

  FIG. 2A is a timing chart for explaining the operation of the rising edge detector 1, and FIG. 2B is a timing chart for explaining the operation of the falling edge detector 2.

(A) In the rising edge detection unit 1, when the output signal S5 of the state machine unit 5 is Low, the output signal SF1 of the flip-flop FF1 transitions to Hi due to the rising edge of the input signal S1.
(B) Thereafter, the output signal SF1 of the flip-flop FF1 is fixed to Hi until the output signal SG3 of the gate G3 becomes Hi.
(C) When the output signal SG3 of the gate G3 becomes Hi, the output signal SF1 of the flip-flop FF1 is fixed to Low.

(D) When the output signal SG3 of the gate G3 returns to Low, the state again waits for the rising edge of the input signal S1 when the output signal S5 of the state machine unit 5 is Low.
(E) When the output signal S5 of the state machine unit 5 is Hi, the output signal SF1 of the flip-flop FF1 does not change even if the input signal S1 has a rising edge.

(A) In the falling edge detection unit 2, when the output signal S5 of the state machine unit 5 is Hi, the output signal SF2 of the flip-flop FF2 transitions to Hi due to the falling edge of the input signal S1.
(B) Thereafter, the output signal SF2 of the flip-flop FF2 is fixed to Hi until the output signal SG4 of the gate G4 becomes Hi.
(C) When the output signal SG4 of the gate G4 becomes Hi, the output signal SF2 of the flip-flop FF2 is fixed to Low.

(D) When the output signal SG4 of the gate G4 returns to Low, the state again waits for transition to Hi due to the falling edge of the input signal S1 when the signal S5 is Hi.
(E) When the output signal S5 of the state machine unit 5 is Low, the output signal SF2 of the flip-flop FF2 does not change even if the input signal S1 has a falling edge.

FIG. 3 is a timing chart for explaining the operation of the Hi signal generation unit 3.
(A) The flip-flops FF3 and FF4 update their output signals SF3 and SF4 at the rising edge of the clock CLK.
(B) The flip-flop FF5 updates its output signal SF5 at the falling edge of the clock CLK.
(C) Since the output signal SF1 of the flip-flop FF1 changes asynchronously with the clock CLK, the flip-flop FF3 operates as a so-called synchronized flip-flop.

  (D) A flip-flop FF4, FF5 and gate G3 constitute a pulse generation circuit for detecting a rising edge. In the output signal SG3 of the gate G3, one pulse having a width of a half cycle of the clock CLK appears with respect to the rise of the output signal SF1 of the flip-flop FF1.

  The operation of the Low signal generation unit 4 is the same as that of the Hi signal generation unit 3 except that the input signal and the output signal are different.

  The state machine unit 5 transitions to the state stat = 1 when the edger input (the output signal SG3 of the gate G3) becomes 1 when the state stat = 0. If the edgef input (the output signal SG4 of the gate G4) becomes 1 when the state stat = 1, the state stat = 0 transitions. The current state is maintained for other state / input combinations.

  In the output generator 6, the gate G5 includes an output signal SF1 of the flip-flop FF1, an output signal SF3 of the flip-flop FF3 obtained by sampling the signal SF1 at the rising edge of the clock CLK, and a flip-flop obtained by sampling the signal SF3 at the falling edge of the clock CLK. The logical sum signal SG5 of the output signal SF5 of the output FF5 is output.

  On the other hand, the gate G6 outputs the output signal SF2 of the flip-flop FF1, the output signal SF6 of the flip-flop FF6 obtained by sampling the signal SF2 at the rising edge of the clock CLK, and the output of the flip-flop FF8 obtained by sampling the signal SF6 at the falling edge of the clock CLK. A logical sum signal SG6 of the signal SF8 is output.

  The gate G7 generates an output signal S2 from the output signal SG5 of the gate G5, the output signal SG6 of the gate G6, and the output signal S5 of the state machine unit 5. Details of the operation will be described later.

FIG. 4 is a timing chart for explaining the operation of the entire circuit of FIG.
First, an example in which chattering is not included when the input signal S1 rises will be described.
(A) When the output signal S5 of the state machine unit 5 is Low, the output signal SF1 of the flip-flop FF1 transitions to Hi by the rising edge of the input signal S1. When the output signal S5 of the state machine unit 5 is Hi, the output signal SF1 of the flip-flop FF1 does not change even if the input signal S1 has a rising edge.
(B) The rising edge of the output signal SF1 of the flip-flop FF1 is detected by the Hi signal generator 3, and a Hi pulse appears in the output signal SG3 of the gate G3.

(C) Until the Hi pulse of the output signal SG3 of the gate G3 falls, no rising edge appears in the output signal SF1 of the flip-flop FF1 regardless of how the input signal S1 changes.
(D) When the Hi pulse of the signal SG3 is input to the state machine unit 5, the output signal S5 of the state machine unit 5 transitions to Hi.
(E) From the rise of the input signal S1 in (a) until the output signal S5 of the state machine unit 5 transits to Hi, the output signal SF2 of the flip-flop FF2, which is the output of the falling edge detection unit 2, is low. Fixed to.

(F) The output signal SG5 of the gate G5 is generated as a logical sum of the output signals SF3, SF4, SF5 of the flip-flops FF3, FF4, FF5. The output signal S2 is held at the Hi level until the output signal SG6 of the gate G6 transitions to Hi by the output signal SG5 of the gate G5 and the output signal S5 of the state machine unit 5.
(G) As is clear from these (c), (e), and (f), from the rising of the input signal S1 shown in (a) until the output signal S5 of the state machine unit 5 transitions to Hi, No matter how much the input signal S1 toggles, that is, no matter how chattering occurs, the output signal S2 does not toggle.

Next, an example in which chattering is not included when the input signal S1 falls will be described.
(H) When the output signal S5 of the state machine unit 5 is Hi, the output signal SF2 of the flip-flop FF2 transitions to Hi by the falling edge of the input signal S1. When the output signal S5 of the state machine unit 5 is low, the output signal SF2 of the flip-flop FF2 does not change even if the input signal S1 has a falling edge.
(I) The rising edge of the output signal SF2 of the flip-flop FF2 is detected by the Low signal generation unit 4, and a Hi pulse appears in the output signal SG4 of the gate G4.
(J) No rising edge appears in the output signal SF2 of the flip-flop FF2 until the Hi pulse of the output signal SG4 of the gate G4 falls, no matter how the input signal S1 changes.

(K) When the Hi pulse of the output signal SG4 of the gate G4 is input to the state machine unit 5, the output signal S5 of the state machine unit 5 transitions to Low.
(L) From the rising edge of the input signal S1 shown in (h) until the output signal S5 of the state machine unit 5 transitions to Low, the output signal SF1 of the flip-flop FF1, which is the output of the rising edge detection unit 1, is low. Fixed to.
(M) The output signal SG6 of the gate G6 is generated as a logical sum of the output signals SF6, SF7, SF8 of the flip-flops FF6, FF7, FF8. The output signal S2 is kept at the low level until the output signal SG5 of the gate G5 transits to Hi due to the output signal SG6 of the gate G6 and the output signal S5 of the state machine unit 5.
(N) As is clear from these (j), (l), and (m), from the falling edge of the input signal S1 shown in (h) until the output signal S5 of the state machine unit 5 transitions to Low. No matter how much the input signal S1 toggles, that is, no matter how chattering occurs, the output signal S2 does not toggle.

  FIG. 5 is a timing chart for explaining the operation of an example in which chattering is included when the input signal S1 rises. The operations of the parts denoted by reference numerals (a) to (g) are the same as those in FIG.

The input signal S1 includes chattering, but attention is paid to the section (g) as follows.
1) Once the output signal SF1 of the flip-flop FF1 of the rising edge detector 1 rises, it does not rise again until the Hi pulse of the output signal SG3 of the gate G3 constituting the Hi signal generator 3 falls 2) The output signal SF2 of the flip-flop FF2 of the falling edge detection unit 2 is low until the output signal S5 of the state machine unit 5 falls until the Hi pulse of the output signal SG3 of the gate G3 constituting the Hi signal generation unit 3 falls. Never stand up because it is fixed

  Therefore, in this section, after the input signal S1 rises first and the output signal SG5 of the gate G5 rises, the state machine unit no matter how many times the input signal S1 toggles, that is, no chattering occurs. 5, the output signal S5 of 5, the output signal SG5 of the gate G5, and the output signal SG6 of the gate G6 do not change.

  Since the fall of the Hi pulse in the output signal SG3 of the gate G3 occurs at the second rising edge of the clock CLK from the rise of the input signal S1, the second of the clock CLK counted from the toggle of the input signal S1. It can be seen that the period up to the rising edge is the chattering removal period.

  (O) When the input signal S1 toggles after the chattering removal period has passed, the output signal S5 of the state machine unit 5 is Hi, so this time the output of the flip-flop FF2 of the falling edge detection unit 2 SF2 stands up. In this way, the output signal S2 changes following the toggle of the input signal S1 after the chattering removal interval.

From these (g), (n), and (o), the following can be said.
1) The chattering elimination period is from the first toggle after the steady state of the input signal S1 to the second rising edge of the clock CLK.
2) The output signal S2 toggles with the first toggle of the input signal S1. Thereafter, even if the input signal S1 is toggled (even if chattering is present), the output signal S2 is not toggled during the chattering elimination period.

3) After the chattering elimination period has elapsed, the output signal S2 toggles again by the toggle of the input signal S1.
4) The length of the chattering elimination period is as short as one cycle of the clock CLK and as long as two cycles of the clock CLK, depending on the timing relationship between the clock CLK and the first toggle of the input signal S1.

  FIG. 6 is a timing chart for explaining the chattering elimination section according to the present invention. In FIG. 6, it is in a steady state until time t1 when the output signal S2 is toggled by the first edge of chattering of the input signal S1. The time from the time t1 when the output signal S2 is toggled to the time t2 when the second edge of the clock CLK rises is within the chattering elimination interval, and the output signal S2 does not change even if the input signal S1 is toggled within this interval. Not toggled.

  After time t2, it is outside the chattering-removable section, and when the input signal S1 falls at time t3, the output signal S2 is toggled, and this becomes the first edge. Then, the time from the time t3 when the output signal S2 is toggled to the time t4 when the second edge of the clock CLK rises again falls within the chattering elimination interval, and the output is performed even if the input signal S1 is toggled within this interval. Signal S2 is not toggled.

  FIG. 7 is a timing chart for explaining the length of the chattering elimination section according to the present invention. In FIG. 7, the chattering elimination interval A from time t1 when the output signal S2 is toggled by the first edge of chattering of the input signal S1 to time t2 when the second edge of the clock CLK rises is the rising edge of the clock CLK. This is an example in which the first edge of the chattering of the input signal S1 rises immediately after the occurrence of toggle. This chattering elimination section A is the longest in the length of two periods of the clock CLK.

  On the other hand, the chattering elimination interval B from the time t3 when the output signal S2 is toggled by the first edge of the chattering of the input signal S1 to the time t4 when the second edge of the clock CLK rises is the rising edge of the clock CLK. This is an example in which the first edge of the chattering of the input signal S1 falls immediately before the occurrence of toggle. This chattering elimination section B is the shortest in the length of one cycle of the clock CLK.

  According to such a configuration, since the control signal for masking the input signal S1 is generated for a period of a predetermined number of cycles of the clock CLK starting from the toggle of the input signal S1, chattering within a certain period is reliably removed. be able to.

  Since the SR latch is not used, no special signal input from the outside is required, the operation can be performed with a general clock, and the compatibility with the clock tree generation is easy, so that the mounting design to the ASIC can be easily performed.

  FIG. 8 is a block diagram showing another embodiment of the present invention, and the same reference numerals are given to portions common to FIG. In FIG. 8, a flip-flop FF9 is added after the flip-flop FF3 constituting the Hi signal generation unit 3, and a flip-flop FF10 is added after the flip-flop FF6 constituting the Low signal generation unit 4, and the output generation unit 6 Are changed from three inputs to four inputs.

  The output signal SF9 of the flip-flop FF9 is input to the data input terminals of the flip-flops FF4 and FF5, and is also input to the third input terminal of the gate G5 constituting the output generation unit 6.

  The output signal SF10 of the flip-flop FF10 is input to the data input terminals of the flip-flops FF7 and FF8, and is also input to the third input terminal of the gate G6 that constitutes the output generation unit 6.

  FIG. 9 is a timing chart for explaining the operation of FIG. With the configuration shown in FIG. 8, the chattering-removable section can be extended by one clock compared to the configuration shown in FIG.

  In FIG. 9, the chattering elimination interval C from time t1 when the output signal S2 is toggled by the first edge of chattering of the input signal S1 to time t2 when the third edge of the clock CLK rises is the rising edge of the clock CLK. This is an example in which the first edge of the chattering of the input signal S1 rises immediately after the occurrence of toggle. This chattering elimination section C is the longest with the length of three periods of the clock CLK.

  On the other hand, the chattering elimination interval D from the time t3 when the output signal S2 is toggled by the first edge of the chattering of the input signal S1 to the time t4 when the third edge of the clock CLK rises is the rising edge of the clock CLK. This is an example in which the first edge of the chattering of the input signal S1 falls immediately before the occurrence of toggle. This chattering elimination section D is the shortest in the length of two periods of the clock CLK.

  As shown in the block diagram of FIG. 8 and the timing chart of FIG. 9, chattering elimination is performed according to the number of flip-flops connected in series between the flip-flops FF3 and FF4 and between the flip-flops FF6 and FF7. The possible section is extended. The number of flip-flops connected in series may be arbitrarily selected as 0, 1, 2, 3,... According to the chattering-removable section to be set.

  Note that the number of input terminals of the gates G5 and G6 of the output generation unit 6 also needs to be changed according to the number of stages of flip-flops connected in series.

  In each of the above embodiments, an example in which an OR gate is used as the gate G5 of the output generation unit 6 is shown. However, the present invention is not limited to this, and the output signal S5 of the state machine unit 5 is Hi from the rising edge of the input signal S1. Any other combination of gates may be used as long as the Hi state of the output signal S2 can be output until the switch is made.

  Similarly, an example in which an OR gate is used as the gate G6 of the output generation unit 6 is shown, but the present invention is not limited to this. From the falling edge of the input signal S1 until the output signal S5 of the state machine unit 5 switches to Low. Meanwhile, other gate combinations may be used as long as the low state of the output signal S2 can be output.

  The flip-flops FF4 and FF5 of the Hi signal generation unit 3, the gate G3, and the flip-flops FF7 and FF8 and the gate G4 of the Low signal generation unit 4 constitute a rising detection pulse generation circuit, respectively, but the outputs of the flip-flops FF1 and FF2 Any circuit may be used as long as it detects the rising edges of the signals SF1 and SF2 and generates a pulse, and the pulse generation latency and pulse width can be arbitrarily set.

  However, the chattering elimination interval varies depending on the latency and the pulse width. Specifically, the latency + pulse width including the synchronized flip-flops FF3 and FF6 from the output signals SF1 and SF2 of the flip-flops FF1 and FF2 is a chattering-removable section.

As long as the state machine unit 5 follows the following operation, the mounting method and the number of internal states are not limited.
1) Update the internal state at the rising edge of the clock CLK.
2) Output signal S5 outputs Low during state stat = 0, and outputs Hi during state stat = 1.
3) When edger input (output signal SG3 of gate G3) becomes Hi when state stat = 0, transition to state stat = 1, and when edge stat = 1, edgef input (output signal SG4 of gate G4) becomes Hi Then, the state transits to stat = 0, and the current state is maintained for other state / input combinations.

  In the above embodiments, the data input terminals of the flip-flop FF1 constituting the rising edge detector 1 and the flip-flop FF2 constituting the falling detector 2 are fixed at the Hi level, but may be fixed at the Low level. In this case, assuming that the data input is fixed at the low level, a level change of Hi → Low occurs due to the rise of the clock of the flip-flops FF1 and FF2. In order to return this state to Low, an asynchronous set input is used instead of an asynchronous reset input. A falling detection pulse generation circuit is used to detect a level change from Hi to Low.

  FIG. 10 is also a block diagram showing another embodiment of the present invention, and the same reference numerals are given to portions common to FIG. In FIG. 10, the selector that selects the output signal SF3 of the flip-flop FF3 and the output signal SF9 of the flip-flop FF9 at the subsequent stage of the flip-flop FF9 constituting the Hi signal generation unit 3 and inputs the selected signal to the data input terminals of the flip-flops FF4 and FF5. SEL1 is provided, and a selector that selects the output signal SF6 of the flip-flop FF6 and the output signal SF10 of the flip-flop FF10 at the subsequent stage of the flip-flop FF10 constituting the Low signal generation unit 4 and inputs it to the data input terminals of the flip-flops FF7 and FF8 SEL2 is provided.

  These selectors SEL1 and SEL2 are driven in response to a select signal Ssel, and select the output signal of any flip-flop and output it to the subsequent stage. That is, the selector SEL1 selects the output signal SF3 of the flip-flop FF3 or the output signal SF9 of the flip-flop FF9 and inputs it to the data input terminals of the flip-flops FF4 and FF5, and the selector SEL2 selects the output signal SF6 or flip-flop of the flip-flop FF6. The output signal SF10 of the FF10 is selected and input to the data input terminals of the flip-flops FF7 and FF8.

  The selector SEL1 selects the output signal SF3 of the flip-flop FF3 and inputs it to the data input terminals of the flip-flops FF4 and FF5. The selector SEL2 selects the output signal SF6 of the flip-flop FF6 and the data input terminals of the flip-flops FF7 and FF8. The state input to is substantially the same as that of the embodiment circuit of FIG. Therefore, as shown in the timing chart of FIG. 7, the longest chattering removal section A having the length of two periods of the clock CLK and the shortest chattering removal section B having the length of one period of the clock CLK can be set. .

  The selector SEL1 selects the output signal SF9 of the flip-flop FF9 and inputs it to the data input terminals of the flip-flops FF4 and FF5, and the selector SEL2 selects the output signal SF10 of the flip-flop FF10 and the data input terminals of the flip-flops FF7 and FF8. The state input to is substantially the same as that of the embodiment circuit of FIG. Therefore, as shown in the timing chart of FIG. 9, the longest chattering removal section C having the length of three periods of the clock CLK and the shortest chattering removal section D having the length of two periods of the clock CLK can be set. .

  In this manner, the rise detection pulse generation latency in the Hi signal generation unit 3 and the Low signal generation unit 4 changes according to the switching of the select signal Ssel, and the chattering elimination interval according to the switching of the selection signal Ssel. You can control the length.

  According to the embodiment of FIG. 10, the length of the chattering-removable section can be switched and adjusted according to the state of the input signal S1.

  Note that the number of flip-flops in the Hi signal generation unit 3 and the Low signal generation unit 4 and the number of input terminals of the selectors SEL1 and SEL2 may be increased or decreased as necessary, and the options of the chattering-removable section are expanded to two or more. It is possible.

  As described above, according to the present invention, there is provided a chattering removal circuit that is compatible with ASIC design, can reliably remove chattering within a predetermined period, and can easily select a chattering removal section. For example, it is suitable as a means for preventing malfunction of a digital circuit caused by chattering that occurs during toggle.

DESCRIPTION OF SYMBOLS 1 Rising edge detection part 2 Falling edge detection part 3 Hi signal generation part 4 Low signal generation part 5 State machine part 6 Output generation part 7 Clock generation part

Claims (3)

A rising edge detector that includes a gate in the input unit and a flip-flop in the output unit to detect the rising edge of the input signal;
A falling edge detection unit for detecting a falling edge of an input signal in which a gate is provided in an input unit and a flip-flop is provided in an output unit;
It is composed of a plurality of flip-flops and gates to which the output signals of these flip-flops are input, detects an edge of the output signal of the rising edge detector, generates a predetermined pulse, and uses this pulse as a flip-flop of the rising edge detector Hi signal generator for feedback input to the
It comprises a plurality of flip-flops and a gate to which the output signals of these flip-flops are input, detects an edge of the output signal of the falling edge detector, generates a predetermined pulse, and generates this pulse as the falling edge detector Low signal generator for feedback input to the flip-flop,
A state machine unit that generates an output signal whose state transitions based on a pulse generated and output from the Hi signal generation unit and the Low signal generation unit and inputs the feedback to each gate of the rising edge detection unit and the falling edge detection unit,
A first gate to which output signals of a plurality of flip-flops constituting the Hi signal generation unit are input; a second gate to which output signals of a plurality of flip-flops constituting the Low signal generation unit are input; An output generation unit composed of an output signal of the first and second gates and a third gate for generating an output signal based on the output signal of the state machine unit;
Chattering elimination circuit consisting of   2. The chattering elimination circuit according to claim 1, wherein a chattering elimination section is set according to the number of stages of flip-flops connected to the Hi signal generation unit and the Low signal generation unit.   3. The selector for changing a chattering-removable section by switching the number of flip-flops connected to the Hi signal generation unit and the Low signal generation unit in conjunction with each other. Chattering removal circuit.

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