JP2014064603A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine which reduces excessive sound output.SOLUTION: A sound-outputting Pachinko machine 10 comprises: an amplifier 275' for amplifying a sound signal; a sound control CPU 542 for controlling an amplification amount of the amplifier 275'; a peak hold part 291 for periodically holding the maximum value of the amplified sound signal; a first comparator 292' for comparing the held maximum value with a predetermined first threshold; and a second comparator 547 for comparing a predetermined second threshold larger than the first threshold with the maximum value. The sound control CPU 542 reduces the amplification amount on the basis of the results of discrimination by the first comparator 292' and the second comparator 547.

Description

  The present invention relates to a gaming machine such as a pachinko machine.

  Conventionally, there is a pachinko machine, for example, as a representative example of a gaming machine. In this pachinko machine, for example, when a game ball wins a start opening provided in the game board (start winning prize), the symbols displayed on the variable display device in the game board start changing, and are determined in advance. A jackpot state (specific game state) is entered when the symbol pattern that has stopped after the elapse of time is a jackpot symbol. When the big win state is reached, the big winning opening is opened, and a plurality of game balls are won in the big winning opening, so that the player can acquire a large number of outgoing balls.

  Such a pachinko machine includes a symbol display device and a speaker, and various effects are produced by image display and sound output (for example, refer to Patent Document 1). Sound data output from the speaker is stored in the memory. The sound reproduction LSI reproduces the sound data stored in the memory and outputs it to the speaker, so that the sound corresponding to the image display can be heard from the speaker.

  The speaker 25 provided in the pachinko machine will be described with reference to FIG. The speaker 25 is a general cone type speaker. The cone paper 25a is supported on the frame 25c by the edge 25b. Further, the base end of the cone paper 25a is connected to the coil 25d. The coil 25d is sandwiched between magnets 25e. When an AC voltage corresponding to the sound signal is applied to the coil 25d, the coil 25d vibrates. The cone paper 25a vibrates in conjunction with the vibration of the coil 25d, and a sound is generated.

JP 2006-81588 A

However, the conventional example having such a configuration has the following problems.
That is, in the conventional gaming machine, the sound data stored in the memory is individually created and stored. As a result, the sound volume reference level of each sound data stored in the memory varies. Depending on the sound data, the sound output level may become excessive even with the same amplification amount. If the sound output is excessive, the edge 25b is damaged by the vibration of the cone paper 25a, and the sound cannot be output from the speaker 25. In addition, if the sound output is such that a slight amount of sound cracking occurs, a dramatic effect is obtained, which may be preferred by game machine managers and players. Therefore, it is desirable to generate sound cracking while avoiding damage to the speaker.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a gaming machine that reduces excessive sound output.

In order to achieve such an object, the present invention has the following configuration.
That is, the invention described in claim 1
In gaming machines that output sound,
An amplifier for amplifying the sound signal;
A sound control unit for controlling the amplification amount of the amplifier;
A holding unit for periodically holding the maximum value of the amplified sound signal;
A first comparison unit that compares the sampled maximum value with a predetermined first threshold;
A second comparison unit that compares a predetermined second threshold value greater than the first threshold value with the maximum value;
The gaming machine according to claim 1, wherein the sound control unit reduces the amplification amount based on a determination result by the first comparison unit and the second comparison unit.

  According to the first aspect of the present invention, a gaming machine that reduces excessive sound output can be provided.

  According to the gaming machine according to the present invention, it is possible to provide a gaming machine that reduces excessive sound output.

It is a front view of the pachinko machine of the present invention. It is a rear view of a pachinko machine. It is a front view of a game board. It is a block diagram which shows the electric constitution of a pachinko machine. It is explanatory drawing which shows the display content of a 3rd symbol display apparatus. It is explanatory drawing which shows the outline | summary of the various counters used for game control. It is a flowchart which shows the main process by the main controller. It is a flowchart which shows the normal process by the main controller. It is a flowchart which shows a 1st symbol fluctuation | variation process. It is a flowchart which shows a change start process. It is a flowchart which shows a timer interruption process. It is a flowchart which shows a start winning process. It is a flowchart which shows a NMI interruption process. It is a flowchart which shows the main process by the payout control apparatus. It is a flowchart which shows payout control processing. It is a flowchart which shows a prize ball control process. It is a flowchart which shows a ball rental control process. It is a flowchart which shows the main process by a sub control apparatus. It is a flowchart which shows the normal process by a sub control apparatus. It is a block diagram which shows the electric constitution of a sound output control apparatus. It is a figure which shows a response | compatibility with the setting value of a volume switch, and an amplified signal. It is a circuit diagram which shows a volume level detection part. It is a flowchart which shows a sound output process. It is explanatory drawing which shows holding | maintenance of the maximum value of a sound signal. It is a block diagram which shows the electric constitution of a sound output control apparatus. It is a block diagram which shows the electric constitution of a sound output control apparatus. It is a figure which shows a response | compatibility with an amplification amount and an amplified signal. It is a flowchart which shows a sound output process. It is a block diagram which shows the electric constitution of a sound output control apparatus. It is a figure which shows a response | compatibility with an amplification amount and an amplified signal. It is a flowchart which shows a sound output process. It is a block diagram which shows the electric constitution of a sound output control apparatus. It is a flowchart which shows a sound output process. It is a block diagram which shows the electric constitution of a sound output control apparatus. It is a block diagram which shows the electric constitution of a sound output control apparatus. It is a flowchart which shows a sound output process. It is a block diagram which shows the electric constitution of a sound output control apparatus. It is a schematic sectional drawing which shows the structure of a speaker.

  Hereinafter, various embodiments of a pachinko gaming machine (hereinafter simply referred to as “pachinko machine”) will be described in detail with reference to the drawings.

  The pachinko machine of Example 1 is demonstrated in detail based on drawing. FIG. 1 is a front view of the pachinko machine 10, and FIG. 2 is a rear view of the pachinko machine 10. FIG. 3 is a front view of the game board 30. FIG. 4 is a block diagram showing an electrical configuration of the pachinko machine 10. FIG. 5 is an explanatory diagram showing display contents of the third symbol display device 42.

  As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 that forms an outer shell of the pachinko machine 10 and is fixed to a game island of a game hall (hole), and one side portion (for example, a front surface) of the outer frame 11. The inner frame 12 is supported so as to be openable / closable with respect to the outer frame 11 with the left-hand side in view) as the opening / closing axis J1, and the inner frame with one side portion (for example, the left-hand side in front view) as the opening / closing axis J2. And a front frame set 14 that can be freely opened and closed.

  The inner frame 12 roughly includes a resin base (not shown) as a main member that forms the outer shape thereof, and a game board 30 (see FIG. 3) attached to the resin base. The game board 30 (see FIG. 2) is detachably attached from the back side of the resin base (not shown) so that the game area 30a is positioned at the opening of the resin base (not shown). Further, as shown in FIG. 1, the inner frame 12 includes a front frame set 14 that can be freely opened on the front side of the resin base.

  As shown in FIG. 1, the front frame set 14 is attached to the inner frame 12 so as to be openable and closable about a vertical opening / closing axis J2 on the left side when viewed from the front. Specifically, the front frame set 14 is configured to be capable of rotating forward with the left side as the open / close base end side and the right side as the open / close front end side in front view.

  Further, when the front frame set 14 is viewed from the front, the lower plate portion 13 located at the lowermost portion, the upper plate portion 21 located above the lower plate portion 13, and the upper plate portion 21 are located above the upper plate portion 21. And a large three-dimensional character portion 26 located on the right side of the lower plate portion 13 and the upper plate portion 21.

  The lower plate part 13, the upper plate part 21, the glass frame part 23, and the large three-dimensional character part 26 are respectively attached to respective portions on the front side of a base plate body (not shown) which is a resin molded part of the front frame set 14. Thus, the front frame set 14 is configured.

  As shown in FIG. 1, the lower platen portion 13 is a component in which the components that form the lower plate 15 and the components that surround the component are integrated, and is positioned at the lowermost portion of the front frame set 14. The base plate (not shown) is fixed to the lowermost portion by a fastener such as a screw when viewed from the front. The lower plate part 13 includes a lower plate 15 and a ball removal lever 17 on the front side.

  As shown in FIG. 1, the lower tray 15 as a ball tray is provided at the left side of the large three-dimensional character portion 26 in the front view of the pachinko machine 10, and is about half the width of the front frame set 14. The game ball discharged from the discharge port 16 can be stored in the lower plate 15. The ball removal lever 17 is for removing (discharging) the game ball in the lower plate 15, and by moving the ball removal lever 17 to the left in FIG. 1, a predetermined position (on the bottom surface of the lower plate 15 ( For example, a circular discharge portion (not shown) formed in a substantially central portion is opened, and the game balls stored in the lower plate 15 are passed downward through the open circular discharge portion (not shown) on the bottom surface of the lower plate 15. Can be pulled out.

  The large three-dimensional character unit 26 includes a game ball launch handle 18 as shown in FIG. The game ball launching handle 18 is disposed so as to protrude to the front side on the right side of the lower plate 15. In accordance with the operation of the game ball launch handle 18 by the player, the game ball is driven toward the game board 30 (see FIG. 3) by the launching device 229 (see FIGS. 2 and 4).

  As shown in FIG. 1, the upper plate portion 21 is a component in which the components that form the upper plate 19 and the components that surround the component are integrated, and the lower portion of the front frame set 14 (the lower plate 15 described above). The base plate body (not shown) is fixed to the lower portion of the base plate body (not shown) by a fastener such as a screw so as to be positioned at the upper position), and is provided with an upper plate 19 as a tray for playing balls. Here, the upper plate 19 is a ball receiving tray for temporarily storing the game balls and guiding them to the launching device 229 while aligning them in a line.

  As shown in FIG. 1, the glass frame portion 23 includes a window portion 101 formed on the upper side of the upper plate portion 21, and various electric decoration portions (first electric decoration portion 300) provided around the window portion 101. , Second electrical decoration unit 302 and third electrical decoration unit 304) and sound output unit 24.

  As shown in FIG. 1, the sound output unit 24 is provided at two locations on the left and right of the upper part of the front frame set 14 as viewed from the front, and outputs sound from the speakers 25 provided in the front frame set 14 or at the rear position. A plurality of output ports 24a for outputting are formed. Only a part of the output port 24a is shown in FIG. 1, and the whole illustration is omitted.

  As shown in FIG. 1, in the front frame set 14, most of the game area 30a (see FIG. 3) of the game board 30 is visually recognized from the outside at the central portion of the glass frame portion 23 located above the upper plate portion 21. A window portion 101 having a substantially vertically long elliptical shape is formed so as to be able to.

  Furthermore, the glass frame part 23 is provided with the 1st electrical decoration part 300, the 2nd electrical decoration part 302, and the 3rd electrical decoration part 304 around the window part 101, as shown in FIG. These lighting parts play a role of enhancing the effect of the game by changing the light emission mode such as lighting and blinking according to the change of the game state at the time of big hit or predetermined reach.

  In the pachinko machine 10, the first electric decoration unit 300, the second electric decoration unit 302, and the third electric decoration unit 304 function as jackpot lamps, and are turned on and blinking at the jackpot to notify that the jackpot is being hit. To do. In addition, the first and second illumination units 300 and 302 of the pachinko machine 10 are provided with a prize ball lamp 105 that is lit during the payout of the prize ball and an error display lamp 106 that is lit when a predetermined error occurs. Yes.

  In addition, a ball lending operation unit 120 is provided in the large three-dimensional character unit 26 on the lower right side of the window unit 101, and the ball lending operation unit 120 is provided with a ball lending button 121 and a return button 122. When the lending operation unit 120 is operated in a state where a bill or a card (for example, a prepaid card) is inserted into a card unit (ball lending unit) (not shown) arranged on the side of the pachinko machine 10, according to the operation. Game balls are rented out. The ball lending button 121 is operated to obtain a lending ball based on information recorded on a card or the like (recording medium), and the lending ball is supplied to the upper plate 19 as long as there is a remaining amount on the card or the like. Is done.

  The return button 122 is operated when requesting the return of a card or the like inserted into the card unit. The lending operation unit 120 may be further provided with a frequency display unit (not shown). This frequency display unit (not shown) displays the remaining amount information such as a card. It should be noted that the ball rental operation unit 120 is not necessary for a pachinko machine in which game balls are lent directly to the upper plate from a ball lending device or the like without using a card unit, that is, a so-called cash machine. Therefore, a decorative seal or the like is attached to the installation portion of the ball rental operation unit 120. Thereby, the common use of the lending operation unit of the pachinko machine using the card unit and the cash machine can be achieved.

  Next, the configuration of the game board 30 will be described with reference to FIG. As shown in FIG. 3, the game board 30 is provided with a game board 30 b having a rectangular shape (for example, plywood) in the front view and having a shape in which both left corners are removed. The outer portions of the rails 51 and 52 are attached in contact with the back side of the resin base (not shown) of the inner frame 12. The game area 30a, which is a substantially central portion on the front side of the game board 30, is passed through the glass plate 137 of the window 101 shown in FIG. 1 of the base plate body (not shown) of the front frame set 14 shown in FIG. It is visible from the front outside of the frame set 14.

  In addition, the game board 30 includes a general winning opening 31, a variable winning device 32, a starting winning device 33 (for example, an operation chucker), a third starting port 34 (for example, a through gate), and a variable display unit 35.

  As shown in FIG. 3, the start winning device 33 is a single unit in which a first start port 33a (for example, an operation chucker) and a second start port 33b (for example, an operation chucker) are arranged in order from the top to the bottom. It consists of a winning device. The first start port 33a on the upper side is provided with an operation port switch (passage detection switch) (not shown) for the first start port 33a. It is detected by an operation port switch for the first start port 33a.

  The lower second start port 33b is provided with an unillustrated operating port switch (passage detection switch) for the second start port 33b. It is detected by the operation port switch for the second start port 33b. In either case of entering the game ball into the first start port 33a on the upper side or entering the game ball into the second start port 33b on the lower side, it is a start prize. There is no change, and those balls can be detected individually.

  In addition, a ball entering the general winning award 31 is detected by a detection switch (a winning port switch not shown), and a ball entering the variable winning device 32 is detected by a detection switch (a count switch not shown). Based on the output of the detection switch, a predetermined number of prize balls are paid out to the upper plate 19 (or the lower plate 15).

  For example, in the case of entering the first start port 33a and the second start port 33b, three prize balls are paid out. In addition, in the case of entering the general winning opening 31 and the variable winning device 32, ten prize balls are paid out. In addition, the number of these prize balls is arbitrary and may be various.

  Note that a game ball enters the third start port 34 and the detected ball is detected by a detection switch (passage detection switch not shown), but even if it enters the third start port 34, The payout of game balls is not executed.

  In addition, as shown in FIG. 3, the game board 30 is provided with an out port 36, and game balls that have not entered the various winning devices or the like pass through the out port 36 in a ball discharge path (not shown). You will be guided toward. A number of nails 39 are implanted in the game board 30 in order to appropriately disperse and adjust the falling direction of the game ball, and various members (instruments) such as a windmill 37 are arranged.

  As shown in FIG. 3, the variable display device unit 35 variably displays the first symbol (for example, special symbol) as identification information with a winning at the first starting port 33 a and the second starting port 33 b as a trigger. Triggered by the passage of the first symbol display device 40 and the third starting port 34, the second symbol display device 41 for variably displaying the second symbol (for example, a normal symbol), the first starting port 33a, the second A third symbol display device 42 that displays a third symbol (for example, a decorative symbol) in a variable manner with a winning at the start port 33b as a trigger is provided.

  As shown in FIG. 3, the first symbol display device 40 is, for example, a first segment display that is a segment display (for example, a 7-segment LED display with a decimal point) in which a plurality of segment light emitting units are arranged in a predetermined manner. A portion 40a is provided. The first segment display unit 40a performs variable emission based on the ball entering the first start port 33a or the second start port 33b. Furthermore, the 1st symbol display apparatus 40 is provided with the holding | maintenance lamp 40c which shows the holding | maintenance number of the variable display in the 1st segment display part 40a, as shown in FIG.

  The first segment display unit 40a displays the variation of the first symbol by changing the light emission of each segment light emitting unit randomly or in sequence based on the ball entering the first start port 33a or the second start port 33b. When a state (in this embodiment, the light emission fluctuation mode of each segment light emitting portion) is generated and the light emission fluctuation is stopped, for example, when the first symbol (for example, a number or a letter) is displayed and lighted, a probable big hit (specific hit) is meant. When the second symbol (for example, numbers or letters) is displayed in a flashing manner, the latent probability variation big hit (latent specific hit) is indicated, and when the third symbol (for example, numbers or letters) is displayed in a flashing manner, a normal big hit (non-specific hit) is indicated. This means that if a fourth symbol (for example, a number or a letter) is displayed in a light-emitting manner, it means that the symbol is off. In addition, since the display of the 1st symbol-the 4th symbol by the 1st segment display part 40a does not know what a general player means even if it sees, if a player just sees it, a probable big hit, It is a display that does not know (or is difficult to understand) whether the latent probability variation jackpot, normal jackpot or missed.

  In this way, when the probability variation jackpot (specific hit), the latent probability variation jackpot (latency specific hit), or the normal jackpot (non-specific hit), the variable winning device 32 enters a specific gaming state (for example, a jackpot state) described later.

  In addition, as this 1st symbol display apparatus 40, you may employ | adopt single or several LED of the type which can light-emit at least 2 colors or more. Specifically, as an example of the case where two LEDs capable of emitting red and blue are employed as the first symbol display device 40, for example, by changing the emission color of each LED alternately, A variation display state of a pattern (light emission color mode of each LED) is generated. For example, when both LEDs stop in a red light emission state, a probable big hit (specific hit) is shown, and one LED stops in a red light emission state and the other When the LED of the LED goes off, a latent probability variation big hit (latent specific hit) is indicated, when both LEDs stop in a blue light emitting state, a normal big hit (non-specific hit) is indicated, and when both LEDs stop in a light emitting state of different colors, they come off. Can be mentioned. Further, at least one of the first segment display section 40a and the holding lamp 40c constituting the first symbol display device 40 is used as a display device of another type such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display. Or may be configured to be displayed on the display screen 42a of the third symbol display device 42 in particular. In addition, as a pattern displayed on the first symbol display device 40, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a plurality of types of characters are displayed. A configuration in which colors are displayed is conceivable.

  The second symbol display device 41 includes, for example, a display unit 41a on which “○” is drawn for the second symbol, a display unit 41b on which “x” is drawn for the second symbol, and a holding lamp 41c. When the game ball passes through the third starting port 34, for example, the display symbol (ordinary symbol) by the display units 41a and 41b fluctuates, and when the variation display stops at a predetermined symbol, The two start ports 33b are configured to be activated (opened) for a predetermined time. The number of times that the game ball has passed through the third starting port 34 is held up to a maximum of 4 times, and the number of times of holding is lit and displayed by the holding lamp 41c. The display units 41a and 41b have LEDs (light emitting diodes) inside thereof, and are configured to be variably displayed by switching light emission of the LEDs (or lighting of the lamps). Further, at least one of the second symbol display device 41 and the holding lamp 41c may be constituted by other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display, and in particular. It is good also as a structure displayed on the display screen 42a of the 3rd symbol display apparatus 42. FIG.

  In the third symbol display device 42, the first symbol display device 40 performs variable display of the first symbol and predetermined display (stop display) on the basis of winning in the first start port 33a and the second start port 33b. In response to this, a variation display of the third symbol and a predetermined display (stop display) are performed accordingly. In addition, in the 3rd symbol display apparatus 42, not only the display effect which triggered the winning to the 1st start opening 33a or the 2nd start opening 33b but the display in the specific game state which transfers after winning a big win Production is performed.

  The 3rd symbol display apparatus 42 is comprised, for example with the liquid crystal display device, and the display content is controlled by the display control apparatus 45 mentioned later. On the third symbol display device 42, for example, as shown in FIG. 5, three decorative symbol rows L, M, and R of left, middle, and right are displayed. Each of the decorative symbol rows L, M, R is composed of a plurality of decorative symbols, and these decorative symbols are variably displayed on the third symbol display device 42 so as to be scrolled for each of the decorative symbol rows L, M, R. The In the present embodiment, the third symbol display device 42 (liquid crystal display device) includes, for example, a large liquid crystal display of 11 inch size. The variable display device unit 35 is provided with a center frame 47 on the front side of the third symbol display device 42 so as to substantially surround the display screen 42a of the third symbol display device 42 when viewed from the front. In the present embodiment, a liquid crystal display device is adopted as the third symbol display device 42, but other types of image display devices (for example, PDP: plasma display panel, EL: electroluminescence display, organic EL, etc.) May be adopted.

  The variable winning device 32 shown in FIG. 3 is normally in a closed state in which a game ball cannot be won (or may be in a closed state in which it is difficult to win a prize). It is operated repeatedly in the closed state. Thus, the state in which the variable winning device 32 is repeatedly operated in the open state and the normal closed state in the case of a big win is called a specific gaming state (for example, a big winning state), and the variable winning device 32 has a number of games. Since the ball enters (wins) and a lot of game balls are paid out for the winning, the game state is advantageous to the player. That is, in the pachinko machine 10 according to the present embodiment, the number of game balls thrown in (the number of game balls fired into the game area 30a by the launching device 229) is greater than the number of game balls awarded (general winning port 31, variable). More than the normal game state (game ball consumption state) than the number of prize balls paid out based on the entry of game balls into the winning device 32, the first start port 33a, the second start port 33b, etc. It is possible to change the state to a specific gaming state (for example, a big hit state) in which the number of balls paid out is larger than the number of game balls inserted.

  More specifically, when a game ball wins the first start port 33a or the second start port 33b, the first segment display unit 40a of the first symbol display device 40 is displayed in a variable manner, and the first segment after the change is stopped. A specific gaming state occurs when the display on the display unit 40a stops at a preset symbol.

  When a specific gaming state occurs, the variable winning device 32 is configured such that the big winning opening 32a is in a predetermined open state, and the game ball is likely to win (a big hit state). Specifically, with the passage of a predetermined time or a predetermined number of winnings in the open state as one round, the big winning opening 32a of the variable winning device 32 is repeatedly opened a predetermined number of times (for example, 16 rounds). The number of times that the game ball has passed through the first start port 33a and the second start port 33b is held up to a maximum of four times, and the hold number is displayed by the hold lamp 40c. The hold lamp 40c may have a configuration in which a hold display is performed on a part of the display screen 42a of the third symbol display device 42.

  Further, as shown in FIG. 3, the game board 30 is provided with two rails 51 and 52 for guiding a game ball launched from the launching device 229 (see FIG. 2) to the upper part of the game board 30. In addition, the game balls launched in accordance with the turning operation of the game ball launching handle 18 are guided to a predetermined game area 30a through a ball guide passage 49 described later of the two rails 51 and 52. The two rails 51 and 52 are long metal strip members made of stainless steel, and are attached to the game board 30 in an inner and outer double. The inner rail 51 is formed in a shape excluding a portion from the upper left corner of the substantially vertical ellipse to the lower right corner in the clockwise direction in the front view of the game board 30. The outer rail 52 is formed so that a part (mainly the left side) faces the inner rail 51. In such a case, a guide rail is constituted by the inner rail 51 and the outer rail 52, and a ball guide passage 49 is formed by a portion (the left portion toward the left) where the rails 51 and 52 are parallel to each other at a predetermined interval. . The ball guide passage 49 is formed in a groove shape having a contact surface with the game board 30, that is, a groove shape in which the front side is opened.

  A return ball preventing member 53 is attached to the tip portion of the inner rail 51 (upper left portion in FIG. 3). This prevents a situation in which the game ball once guided from the ball guide passage 49 between the inner rail 51 and the outer rail 52 to the upper portion of the game board 30 returns to the ball guide passage 49 again. Further, in a state where the game board 30 is attached to the inner frame 12, a position corresponding to the maximum flight portion of the game ball on the outer rail 52 (upper right portion in FIG. 3: a portion corresponding to the tip portion of the outer rail 52). , The return rubber 54 is located. Therefore, the game ball fired at a predetermined momentum or more hits the return rubber 54 and is bounced back. Since the outer rail 52 is made of a long metal strip made of stainless steel, the flight of the game ball can be made smoother, that is, the frictional resistance of the game ball can be reduced. In addition, as shown in FIG. 3, from the front-end | tip part (upper right part of FIG. 3) of the outer rail 52 to the right front-end | tip part (lower right part of FIG. 3) of the inner rail 51, the game area | region in the 1st symbol display apparatus 40 is shown. The game area 30a is partitioned by positioning the wall part 56 on the 30a side and the wall part 55 (shown by a broken line in FIG. 3) formed on the inner frame 12.

  Next, the game area 30a of the game board 30 will be described. As shown in FIG. 3, the game area 30 a is partitioned and formed in a substantially vertically long circle shape by inner peripheral portions (inner and outer rails) of the inner rail 51 and the outer rail 52. In particular, in this embodiment, the game board 30 The game area 30a partitioned on the board surface is greatly configured.

  In the present embodiment, the game area 30a is viewed from the front of the pachinko machine 10, and the area of the guide rail that is a parallel part of the inner and outer rails 51 and 52 is excluded from the area surrounded by the inner rail 51 and the outer rail 52. As an area. Accordingly, when the game area 30 a is referred to, the guide rail portion is not included, and therefore the left limit position toward the game area 30 a is specified by the inner rail 51, not by the outer rail 52. The right limit position toward the game area 30a is specified by the wall 55 (a part of the inner frame 12). Further, the lower limit position of the game area 30 a is specified by the inner rail 51. The upper limit position of the game area 30 a is specified by the outer rail 52.

  Although detailed disclosure of the drawings is omitted, game balls are supplied to the launching device 229 one by one from a ball outlet (not shown) of the front frame set 14 (ball outlet leading from the most downstream portion of the upper plate 19). .

  Next, the configuration of the back surface of the pachinko machine 10 will be described. As shown in FIG. 2, the pachinko machine 10 has various control boards arranged vertically and horizontally on the back side (actually the back side of the inner frame 12 and the game board 30), and a predetermined control board is stacked on the front and back (see FIG. 2). For example, a payout control board 311a shown in FIG. 4 to be described later is on the front side in a rear view, and a power supply control board of the power supply device 313 and a launch control board of the launch control apparatus 312 are located behind the payout control board 311a. Furthermore, a game ball supply device (payout mechanism unit 352) for supplying game balls, a protective cover 353 made of resin, and the like are attached. In this embodiment, various control boards are divided and mounted on a plurality (three) of mounting bases 230 to 232 shown in FIG. 2 to form each control board unit, and each control board unit is individually divided into the inner frame 12 or The game board 30 is mounted on the back side. Specifically, as shown in FIG. 2, the main control device 261 is mounted on the mounting base 230 and the sub-control device 262 is mounted on the mounting base 232 to be unitized, and the payout control device 311 and the launch control device. 312 and the power supply device 313 are mounted on the mounting base 231 and unitized.

  The mounting base 232 is provided with a volume switch 29 that adjusts the volume of the sound output from the speaker 25. In the pachinko machine 10, a slide-type changeover switch that can be adjusted in any of six levels of “0”, “1”, “2”, “3”, “4”, and “5” is used as a volume switch. Is provided. The volume switch 29 is provided with an “f” position. In the first embodiment, the “f” position is a spare position and no control is performed. An example in which automatic volume control is assigned to the “f” position is described in the third embodiment. The volume switch 29 is a mechanical switch that maintains the switching state.

  Further, as shown in FIG. 2, the payout mechanism unit 352 has various components (a tank 355, a tank rail 356, a case rail 357, a payout device 358, and a power switch board 382, which will be described later) in a reverse view in the back view of the pachinko machine 10. The payout mechanism 352 and the protective cover 353 are integrated as one unit, and the unit is sometimes referred to as a back pack. This is referred to as “pack unit 203”.

  In addition, on the back side of the game board 30, a winning detection mechanism for detecting passage of game balls such as various winning holes is provided. Specifically, a prize opening switch (not shown) is provided at a position corresponding to the general prize opening 31 on the front side of the game board 30, and a count switch (not shown) is provided in the variable prize winning device 32. The count switch is a switch for counting winning balls. In addition, an operating port switch (not shown) for the first starting port 33a and an operating port switch (not shown) for the second starting port 33b are located at positions corresponding to the first starting port 33a and the second starting port 33b. (Omitted) (not shown) are provided, and the entry of the game ball into the first start port 33a and the second start port 33b is detected by the respective operation port switches. A gate switch is provided at a position corresponding to the third start port 34, and the passage of the game ball to the third start port 34 is detected by the gate switch.

  A prize opening switch (not shown) of the general winning opening 31 and a gate switch of the third start opening 34 are connected to a board connection board (not shown) through an electric wiring (not shown), and this board connection board is a main control described later. It is connected to a main control board 261a (see FIG. 4) in the device 261. Further, the count switch of the variable winning device 32 is connected to a large winning opening relay terminal board (not shown), and this large winning opening relay terminal board is also connected to the main control board 261a. On the other hand, the operation port switches of the first start port 33a and the second start port 33b are directly connected to the main control board 261a without going through the relay board.

  Although not shown in the drawings, the variable winning device 32 is provided with a large winning opening solenoid for opening the large winning opening 32a, and the second start opening 33b on the lower side is used to open the electric accessory. Is provided.

  The detection results detected by the winning detection mechanism are taken into a main control board 261a in a main control device 261, which will be described later, and the main control board 261a issues a payout command (a game ball of each game ball) according to the winning situation each time. The number of payouts) is transmitted to the payout control board 311a. Then, a predetermined number of game balls are paid out by the output of the payout control board 311a.

  As shown in FIG. 2, the main control device 261 is mounted on the lower mounting base 230 in the rear view of the pachinko machine 10, and the sub control device 262 is mounted on the upper mounting base 232 in the rear view of the pachinko machine 10. Has been. Here, as shown in FIG. 4, the main control device 261 includes a CPU 501 that performs main control, a ROM 502 that stores a game program, a RAM 503 that stores necessary data according to the progress of the game, and various devices. Main control including an input / output port 505 for communication, a random number generator (not shown) used in various lotteries, a clock pulse generation circuit (not shown) used for time counting and synchronization, etc. The main control board 261a is configured to be accommodated in a board box 263 (encapsulating means) made of a transparent resin material or the like.

  In addition, the sub control device 262, for example, in accordance with an instruction from the main control board 261a in the main control device 261, controls the sound and lamp display and the control of the display control device 45, the other ROM 552, RAM 553, bus line 554, A sub-control board 262a including an input / output port 555 and the like is provided, and the sub-control board 262a is accommodated in a board box made of a transparent resin material or the like. Power supplied from a power supply board described later is output to the display control device 45 via the sub control device 262.

  As shown in FIG. 2, a payout control device 311, a firing control device 312, a power supply device 313, and a card unit connection board 314 are mounted on the mounting base 231. The payout control device 311 includes a control board including a CPU that is the center of control, and other ROM, RAM, various ports, and the like. The launch control device 312 includes a launch control board. In addition, the power supply device 313 includes a power supply control board. The payout control board 311a of the payout control device 311 controls payout of prize balls and rental balls. In addition, the launch control board of the launch control apparatus 312 controls the launch apparatus 229 (see FIG. 4) in accordance with the operation of the game ball launch handle 18 by the player. The required power supply voltage required is generated and output. The launching device 229 of the present embodiment employs a solenoid-type launching part that strikes and launches a game ball with a launching rod (not shown) that can advance and retreat according to energization / non-energization of a launching solenoid (not shown). In addition, as other launching devices 229, there are various types such as a mechanical launching component that strikes and launches a game ball with a launcher that operates according to the driving of the launching motor, and an electromagnetic launching component that launches a game ball by generating an electromagnetic field. The following types may be adopted. The card unit connection board 314 is electrically connected to the ball lending operation unit 120 (see FIG. 1) on the front surface of the pachinko machine and a card unit (not shown), and receives a ball lending operation command by the player and pays it out. Is output. Note that the card unit connection board 314 is unnecessary in a cash machine in which game balls are lent directly to the upper plate 19 from a ball lending device or the like without using a card unit.

  The payout control device 311, the firing control device 312, the power supply device 313, and the card unit connection board 314 are each housed and configured in a board box made of a transparent resin material or the like. In particular, in the dispensing control device 311, similarly to the main control device 261 described above, the box base and the box cover that constitute the substrate box 311 b (encapsulating means) are connected by the sealing unit (sealing means) so that they cannot be opened. The substrate box 311b is sealed.

  The payout control device 311 is provided with a state return switch 311c as shown in FIG. For example, when the state return switch 311c is pressed when a payout error occurs, such as a ball jam in the payout motor unit, the payout motor 358a (see FIG. 4) slowly rotates forward to eliminate the ball jam (return to the normal state). ) Is planned.

  Further, a RAM erase switch 323 is provided on the power supply monitoring board 261b. The pachinko machine 10 has a backup function, and maintains the state at the time of a power failure even if a power failure occurs, and can return to the state at the time of a power failure when returning from a power failure (power recovery). Therefore, if the power is turned off in the normal procedure (for example, when the hall is closed), the state before the power is turned off is stored. If you want to return to the initial state when the power is turned on, turn on the power while holding down the RAM erase switch 323. We are going to throw it in.

  Next, the configuration of the back pack unit 203 will be described. As shown in FIG. 2, the back pack unit 203 is a unit in which a protective cover 353 made of resin and a payout mechanism 352 for a game ball are integrated.

  The back pack unit 203 is provided with a tank 355 that opens upward at the top, and the tank 355 is sequentially replenished with game balls supplied from the island equipment (game island equipment) of the game hall. Below the tank 355 is connected, for example, a tank rail 356 that has two rows of spherical passages in the horizontal direction and gently descends and inclines toward the downstream side. Further, a case rail 357 is installed on the downstream side of the tank rail 356 in the vertical direction. Are connected. A payout device 358 is provided at the most downstream portion of the case rail 357, and a required number of game balls are paid out appropriately according to a predetermined electrical configuration such as a payout motor 358a. Then, the game balls paid out from the payout device 358 are supplied to the upper plate 19 through a payout passage (not shown) or the like.

  The payout mechanism 352 is provided with a payout relay board (not shown) for relaying a payout command signal from the payout control device 311 to the payout device 358, and a power switch board 382 for taking in the main power from outside. is set up. The power switch board 382 is supplied with, for example, AC 24V main power via a voltage converter, and the power switch 382a is switched to turn the power on or off.

  Each of the dispensing mechanisms 352 from the tank 355 to the dispensing passage (not shown) is formed of a conductive resin material (for example, conductive polycarbonate resin) and grounded (grounded) at a part thereof. . Thereby, generation | occurrence | production of the noise by charging of a game ball is suppressed.

  As shown in FIG. 2, an inner frame open detection switch 388 for detecting that the inner frame 12 is opened with respect to the outer frame 11 is provided on the upper right side of the inner frame 12. When the inner frame 12 is opened, it is output from the inner frame opening detection switch 388 to the computer for the hall (in the pachinko parlor).

  Next, the electrical configuration of the pachinko machine 10 will be described with reference to FIG. The pachinko machine 10 includes a main control device 261, a payout control device 311, a launch control device 312, a sub control device 262, a display control device 45, a power supply device 313, and the like. In the following, these devices will be described in detail individually.

  The main control device 261 of the pachinko machine 10 is equipped with a CPU 501 as a one-chip microcomputer that is an arithmetic device. The CPU 501 includes a ROM 502 that stores various control programs executed by the CPU 501 and fixed value data, and a memory that temporarily stores various data when the control program stored in the ROM 502 is executed. A RAM 503 and various circuits such as an interrupt circuit, a timer circuit, and a data transmission / reception circuit are incorporated.

  The RAM 503 is configured so that the backup voltage is supplied from the power supply device 313 even after the power of the pachinko machine 10 is turned off and data can be retained (backed up). The RAM 503 temporarily stores various data and the like. Has memory and area.

  That is, when the power is cut off due to the occurrence of a power failure or the like, the CPU 501 of the main control device 261 executes the normal processing up to the end, so that the RAM 503 is when the power is turned off (including when a power failure occurs, and so on). It is only necessary to store and hold the contents of the counter buffer and the holding ball storage area, and the state of the pachinko machine 10 can be restored to the state before the power is turned off when the power is turned on again. Specifically, there is no need to provide a dedicated backup area in the RAM 503 for storing values of registers, I / O, and the like for game information during normal processing when the power is turned off.

  The N501 terminal (non-maskable interrupt terminal) of the CPU 501 is configured to receive a power failure signal S1 output from a power failure monitoring circuit 542, which will be described later, when a power failure occurs due to the occurrence of a power failure or the like. Due to the occurrence, the power failure process (NMI interrupt process) is immediately executed.

  An input / output port 505 is connected to the CPU 501 incorporating the ROM 502 and RAM 503 via a bus line 504 including an address bus and a data bus. The input / output port 505 includes a RAM erasing switch circuit 543, a payout control device 311, a firing control device 312, a sub control device 262, a first symbol display device 40, a second symbol display device 41, and other switches not shown. Etc. are connected. The main controller 261 also has a function of controlling the first symbol variation display on the first symbol display device 40 and the second symbol variation display on the second symbol display device 41.

  The RAM 513 of the payout control device 311 is configured so that the backup voltage is supplied from the power supply device 313 and data can be retained (backup) even after the pachinko machine 10 is turned off, like the RAM 503 of the main control device 261 described above. The RAM 513 includes a memory and an area for temporarily storing various data.

  The RAM 513 stores and holds information related to the state when the power is turned off in order to return the state of the pachinko machine 10 to the state before the power is turned off when the power is turned off due to a power failure or the like. In other words, the storage of the RAM 513 is executed when the power is turned off by the NMI interrupt process and the second half of the payout control process, and the storage information stored in the RAM 513 is restored in the power recovery process when the power is turned on. .

  An input / output port 515 is connected to the CPU 511 incorporating the ROM 512 and the RAM 513 through a bus line 514 including an address bus and a data bus. The main controller 261, the launch controller 312 and the payout motor 358a are connected to the input / output port 515, respectively.

  As shown in FIG. 4, the launch control device 312 permits or prohibits the launch of the game ball by the launch device 229, and the launch device 229 is permitted to drive when a predetermined condition is met. Specifically, the launch control device 312 receives a card unit connection signal S4 from the payout control device 311 (a signal that is output when the card unit described above is connected to the pachinko machine 10), and the player Touch detection signal S5 output when the game ball launch handle 18 is touched and output when the launch stop switch 18a provided on the game ball launch handle 18 for stopping the launch is not operated. The firing permission signal S7 is output to the main controller 261 on condition that all of the fired maintenance signals S6 to be performed are inputted. Further, a volume signal S10 corresponding to the operation amount of the game ball launch handle 18 is input from the game ball launch handle 18 to the launch control device 312. The launch control device 312 outputs this volume signal S10 to the main control device 261. To do.

  That is, the period during which the firing permission signal S7 is ON (high level) is a firing permission state, and the period during which the firing permission signal S7 is OFF (low level) is a firing non-permission state. That is, the main control device 261 controls the launch control signal S8 (pulse signal) for controlling the launch solenoid (not shown) for launching the game ball and the launch rail during the period when the launch permit signal S7 that is input is ON. A ball feed control signal S9 (pulse signal) for controlling a ball feed solenoid for sending a game ball is repeatedly output to the firing control device 312 at a predetermined repetition cycle. The amplitude value of the firing control signal S8 (pulse signal) is determined based on the volume signal S10 in the main controller 261. For example, the larger the operation amount of the game ball launching handle 18, the greater the firing control signal S8 (pulse signal). ) Becomes larger. The launch control device 312 drives and controls the launch device 229 based on the launch control signal S8 and the ball feed control signal S9, and a game ball is launched with an intensity corresponding to the amount of operation of the game ball launch handle 18. Conversely, the main control device 261 does not output the firing control signal S8 and the ball feed control signal S9 to the firing control device 312 during the period when the input firing permission signal S7 is OFF, and the gaming device 229 plays the game ball. Will never be fired.

  The display control device 45 controls the variable display of the third symbol (decorative symbol) on the third symbol display device 42. The display control device 45 includes a CPU 521, a ROM (program ROM) 522, a work RAM 523, a video RAM 524, a character ROM 525, an image controller 526, an input port 527, an output port 529, and bus lines 530 and 531. And. The output of the sub-control device 262 is connected to the input of the input port 527, and the CPU 521, ROM 522, work RAM 523, and image controller 526 are connected to the output of the input port 527. Further, an output port 529 is connected to the image controller 526 via a bus line 531, and a third symbol display device 42 which is a liquid crystal display device is connected to an output of the output port 529.

  The CPU 521 of the display control device 45 controls the decorative symbol display on the third symbol display device 42 based on the various commands transmitted by editing the various commands from the main control device 261 by the sub-control device 262. The ROM 522 is a memory for storing various control programs executed by the CPU 521 and fixed value data, and the work RAM 523 temporarily stores work data and flags used when the CPU 521 executes various programs. It is a memory for.

  The video RAM 524 is a memory for storing display data displayed on the third symbol display device 42, and the display contents of the third symbol display device 42 are changed by rewriting the contents of the video RAM 524. The character ROM 525 is a memory for storing character data such as decorative symbols displayed on the third symbol display device 42. The image controller 526 adjusts the timings of the CPU 521, the video RAM 524, and the output port 529 to intervene in reading and writing data, and reads display data stored in the video RAM 524 from the character ROM 525 at a predetermined timing. It is displayed on the symbol display device 42.

  The power supply device 313 includes a power supply unit 541 for supplying power to each unit of the pachinko machine 10. The power supply unit 541 supplies necessary operation power to the main control device 261, the payout control device 311 and the like through a power supply path (not shown). As its outline, the power supply unit 541 takes in an AC 24 volt power supply supplied from the outside, and generates a + 12V power supply for driving various switches and motors, a + 5V power supply for logic, a backup power supply for RAM backup, and the like. Then, these + 12V power supply, + 5V power supply and backup power supply are supplied to the main control device 261, the payout control device 311 and the like. Note that operation power (+12 V power, +5 V power, etc.) is supplied to the launch control device 312 via the payout control device 311.

  As shown in FIG. 4, the main control device 261 includes a main control board 261a and a power monitoring board 261b separate from the main control board 261a in the board box 263. The power monitoring board 261b includes a power failure monitoring circuit 542 that monitors power interruption due to a power failure or the like, and a RAM erase switch circuit 543 connected to the RAM erase switch 323.

  The power failure monitoring circuit 542 is a circuit that outputs a power failure signal S1 to each NMI terminal of the CPU 501 of the main control device 261 and the CPU 511 of the payout control device 311 when the power is cut off due to the occurrence of a power failure or the like. The power failure monitoring circuit 542 monitors the voltage of AC 24 volts with the power supply unit 541, and determines that a power failure (power failure) has occurred when the time when this voltage has become less than 22 volts exceeds, for example, 20 milliseconds. The power failure signal S1 is output to the main controller 261 and the payout controller 311. Based on the output of the power failure signal S1, the main control device 261 and the payout control device 311 recognize the occurrence of a power failure and execute a power failure process (NMI interrupt process).

  Note that the power supply unit 541 has a sufficient time to execute the power failure process even after the time when the AC 24 volts monitored by the power supply unit 541 becomes less than 22 volts exceeds 20 milliseconds. The control system is configured to maintain the output of 5 volts, which is the drive voltage of the control system, at a normal value. Therefore, the main control device 261 and the payout control device 311 can normally execute and complete the power failure process.

  The RAM erase switch circuit 543 is a circuit for taking in the switch signal of the RAM erase switch 323 and clearing backup data in the RAM 503 of the main controller 261 and the RAM 513 of the payout controller 311 in accordance with the state of the switch 323. When the RAM erase switch 323 is pressed, the RAM erase switch circuit 543 outputs a RAM erase signal S2 to the main control board 261a. When the power of the pachinko machine 10 is turned on with the RAM erase switch 323 pressed (including power-on due to power failure cancellation), the data in the RAM 503 is cleared in the main controller 261, and the payout controller 311 is in the main controller. When the initialization command from H.261 is received, the data in RAM 513 is cleared.

  By the way, in the third symbol display device 42 (liquid crystal display device), as shown in FIG. 5, three decorative symbol rows L, M, and R of left, middle, and right are set. For each of M and R, three decorative symbols, an upper decorative symbol, a middle decorative symbol, and a lower decorative symbol, are variably displayed. In the present embodiment, the series of symbols is composed of a main decorative symbol SZ with numbers “0” to “9” and a sub-decorative symbol FZ consisting of rhombus-shaped symbols. A main decorative symbol SZ is displayed in ascending or descending order, and a sub decorative symbol FZ is arranged between the main decorative symbols SZ to form a series of decorative symbol strings L, M, and R. Then, the main decorative design SZ and the secondary decorative design FZ are displayed variably from top to bottom with periodicity.

  In this case, in the left decorative design row L, the above-mentioned series of decorative designs are displayed in descending order (that is, in the order of decreasing the number of the main decorative design SZ), and in the middle decorative design row M and the right decorative design row R, the same The series of decorative symbols is displayed in ascending order (that is, in order of increasing the number of the main decorative symbols SZ). Then, the variable display stops in the order of the left decorative symbol row L → the right decorative symbol row R → the middle decorative symbol row M, and at the time of the stop, five effective lines on the third symbol display device 42, that is, the upper line L1, the middle line If the main decorative symbol SZ is a big hit symbol combination (in this embodiment, the same main decorative symbol SZ combination) in any of L2, the lower line L3, the right upward line L4, and the left upward line L5, it is special as a big hit A game video is displayed.

  Next, the operation of the pachinko machine 10 configured as described above will be described.

  In the present embodiment, the CPU 501 in the main control device 261 uses the random number relating to the actuating action and other random numbers used for the game to draw the first symbol display device 40 (lottery lottery: first Symbol jackpot lottery), symbol display settings, lottery drawing of the second symbol display device 41 (second symbol hitting lottery), symbol display settings, and decorative symbols (third symbol) of the third symbol display device 42 A lottery and setting related to variable display will be performed.

  Specifically, in the pachinko machine 10 according to the present embodiment, as shown in FIG. 6, as a random number related to the operation of the accessory, a jackpot random number counter C <b> 1 used for the jackpot lottery of the first symbol display device 40, The jackpot symbol counter C2 used to select the jackpot symbol of the symbol display device 40, the initial value random number counter CINI1 used to set the initial value of the jackpot random number counter C1, and the second symbol used to win the second symbol display device 41. A 2 symbol random number counter C4 and an initial value second symbol random number counter CINI2 used for setting an initial value of the second symbol random number counter C4 are used.

  Further, in this pachinko machine 10, as other random numbers used for the game, as shown in FIG. 6, when the variation pattern of the decoration symbol of the third symbol display device 42 is selected, the type of the variation pattern is roughly specified. Stop pattern selection counter C3 used for selection of the stop pattern of the symbol, variation type counters CS1, CS2, CS3 used for variation pattern selection of the decorative symbol of the third symbol display device 42, and outlier symbol of the second symbol display device 41 A second off-design symbol counter C5 used for selection is used. Each counter described above is constituted by a program executed by the CPU 501.

  For example, “stop pattern 0” indicates a complete deviation variation pattern group including a plurality of types of complete deviation variation patterns, and “stop pattern 1” indicates a front / rear deviation variation pattern group including a plurality of types of front / rear deviation variation patterns. “Stop pattern 2” indicates a reach variation pattern group other than front / rear out of reach variation patterns consisting of a plurality of types of reach variation patterns other than front / rear out, and “Stop pattern 3” indicates a plurality of types of normal jackpot variation patterns. In this case, “stop pattern 4” indicates a probability variation jackpot variation pattern group including a plurality of types of probability variation jackpot variation patterns.

  All of these counters C1 to C5, CINI1 to CINI2, and CS1 to CS3 are incremented by “1” (hereinafter referred to as “update”) every time they are updated, and then set to “0” after reaching the maximum value. It is a return loop counter. Each counter is periodically updated, and the updated value is appropriately stored in a counter buffer set in a predetermined area of the RAM 503 shown in FIG. The RAM 503 is provided with a holding ball storage area including one execution area and four holding areas (holding first to fourth areas). Each of these areas has a first start port 33a. The values of the jackpot random number counter C1, the jackpot symbol counter C2, and the stop pattern selection counter C3 are stored in time series in accordance with the winning history of the game balls to the second start port 33b.

  Each counter described above will be described in detail below with reference to FIG. The jackpot random number counter C1 is, for example, incremented by 1 within a range of “0” to “599”, and returns to “0” after reaching the maximum value (that is, “599”). In particular, when the jackpot random number counter C1 makes one round, the value of the initial value random number counter CINI1 at that time is read as the initial value of the jackpot random number counter C1. The initial value random number counter CINI1 is a loop counter similar to the big hit random number counter C1 (value = 0 to 599), and is updated once every timer interrupt (see FIG. 11) described later, and a normal process described later. It is repeatedly updated within the remaining time (see FIG. 8). The jackpot random number counter C1 is updated periodically (once every timer interrupt (see FIG. 11) described later in this embodiment), and the game ball wins the first start port 33a and the second start port 33b. It is stored in the reserved ball storage area of the RAM 503 at the timing.

  The hit value of the jackpot random number counter C1, that is, the number of random number values that are jackpots is set at low probability and high probability, and the number of random number values that are jackpots at low probability is two The value is “150, 450”, the number of random numbers that are jackpots at high probability is four, and the value is “50, 150, 350, 450”. That is, the jackpot probability is 1/300 when the probability is low, and the jackpot probability is 1/150 when the probability is high. Note that the high probability means, for example, a state where the jackpot is determined by a predetermined probability variation pattern and the subsequent jackpot probability is increased as added value, that is, a so-called “probability change”. Means the time when it is not in such a probable state. Further, at the time of high probability (probability variation state), after the probability variation jackpot or latent probability variation jackpot ends (after the prize winning opening 32a of the variable prize winning device 32 is opened for 16 rounds, for example), it continues until the next jackpot.

  The jackpot symbol counter C2 is a symbol when the first segment display unit 40a of the first symbol display device 40 stops changing in the case of a jackpot (in this embodiment, the final display symbol after the variable display of the first segment display unit 40a) ). In the present embodiment, the jackpot symbol counter C2 is incremented one by one within a range of “0” to “9”, for example, and reaches a maximum value (that is, “9”) and then returns to “0”. Yes. The jackpot symbol counter C2 is updated periodically (once for each timer interrupt (see FIG. 11) described later) as in the case of the jackpot random number counter C1 described above. 2 is stored in the reserved ball storage area of the RAM 503 at the timing of winning the start port 33b. When the jackpot random number counter C1 is a win and the values of the jackpot symbol counter C2 are “1”, “4”, “7”, the first segment display unit 40a of the first symbol display device 40 is used. Stops at the third symbol, indicating a jackpot at low probability, a so-called regular jackpot (non-specific hit). In addition, when the aforementioned jackpot random number counter C1 is a win and the value of the jackpot symbol counter C2 is “0”, “2”, “5”, “8”, the first symbol display device 40 of the first The segment display unit 40a stops at the first symbol and indicates a big hit at the time of high probability, that is, a so-called probable big hit (specific hit). In addition, when the aforementioned jackpot random number counter C1 is hit and the value of the jackpot symbol counter C2 is “3”, “6”, “9”, the first segment display section 40a of the first symbol display device 40 is used. Stops at the second symbol and represents a big hit when the latency is high, that is, a so-called latent probability variation jackpot (latency specific hit). When the jackpot random number counter C1 is off, regardless of the value of the jackpot symbol counter C2, the first segment display unit 40a of the first symbol display device 40 stops at the fourth symbol to indicate a loss. In other words, as the sort of jackpot type, probability variation: latent probability variation: normal = 4: 3: 3.

  Further, the stop pattern selection counter C3 is, for example, incremented one by one within a range of “0” to “238”, and returns to “0” after reaching the maximum value (that is, 238). In the present embodiment, the stop pattern selection counter C3 causes the last stop decorative symbol to stop by one shift before and after the reach decorative symbol after the reach of the decorative symbol on the third symbol display device 42 occurs. "Leach other than front-rear detachment" where the final stop decorative symbol stops other than before and after the reach decorative symbol after the reach has occurred, and "completely disengagement" where the reach does not occur. For example, C3 = 0 to 201 corresponds to complete detachment, C3 = 202 to 208 corresponds to anteroposterior reach, and C3 = 209 to 238 corresponds to reach other than anteroposterior detachment. In addition, the lottery (reach lottery) contents of the stop pattern selection counter C3 indicate whether the pachinko machine 10 has a low probability or a high probability, or the fluctuation time reduction function of the first symbol display device 40 has not been activated. It may be set individually depending on whether it is an operation or an operation, or the number of operation holding balls at the start of the variation of the first symbol. The stop pattern selection counter C3 is periodically updated (once for each timer interrupt (see FIG. 11) described later), and the RAM 503 is used when the game ball wins the first start port 33a and the second start port 33b. Stored in the reserved ball storage area.

  Of the three variation type counters CS1 to CS3, the variation type counter CS1 is incremented one by one in the range of “0 to 198”, for example, and reaches “0” after reaching the maximum value (ie, “198”). For example, the variation type counter CS2 is incremented one by one within a range of “0 to 240”, for example, and reaches a maximum value (that is, “240”) and then returns to “0”. For example, the variation type counter CS3 is sequentially incremented by 1 within a range of “0 to 162”, and reaches a maximum value (that is, “162”) and then returns to “0”. In the following description, the variation type counter CS1 is also referred to as “first variation type counter”, the variation type counter CS2 is also referred to as “second variation type counter”, and the variation type counter CS3 is also referred to as “third variation type counter” as appropriate. .

  The first variation type counter CS1 determines a rough decorative pattern variation pattern group, such as a reach type of a decorative symbol (third symbol), such as a normal reach, a super reach, a premium reach, or a completely unacceptable type. . Here, for example, it is assumed that the stop pattern selection counter C3 has a value indicating “stop pattern 1” (that is, a value indicating the front / rear out of reach reach variation pattern group), and the first variation among the front / rear out of reach reach variation pattern group. It is assumed that the variation pattern of the normal reach group (consisting of a plurality of different normal reach types) is determined by the type counter CS1.

  Subsequently, one more variation pattern is determined by the second variation type counter CS2 from the variation pattern group determined by the first variation type counter CS1 in this way. Here, for example, it is assumed that one type of normal reach from the normal reach group is determined by the second variation type counter CS2. Note that a plurality of different types of normal reach can be realized by giving different differences such as the elapsed time until the final stop decorative symbol (for example, the middle decorative symbol in this embodiment) stops after the occurrence of reach. Is mentioned.

  Subsequently, the third variation type counter CS3 determines which time the variation time is added in one variation pattern determined by the second variation type counter CS2. For example, as the addition time, when the decorative symbol (third symbol) of the middle decorative symbol row stops on the third symbol display device 42, the decorative symbol of the middle decorative symbol row slips after that. Additional time, which is the time until stop display is given. In this way, the decoration pattern variation mode can be determined more finely by the variation type counters CS1 to CS3. In other words, a variety of variation patterns can be easily realized by combining these variation type counters CS1 to CS3.

  Note that the symbol variation mode is determined only by the first variation type counter CS1, the symbol variation mode is determined only by the first variation type counter CS1 and the second variation type counter CS2, or the first variation type counter CS1 and the stop symbol. It is also possible to determine the symbol variation mode in the same manner as described above, or to determine the symbol variation mode in the combination of the first variation type counter CS1 and the second variation type counter CS2 and the stop symbol.

  The variation type counters CS <b> 1 to CS <b> 3 are updated once every time a normal process to be described later is executed once, and are repeatedly updated even within the remaining time in the normal process. Then, the buffer values of the variation type counters CS1 to CS3 are acquired when the variation pattern is determined when the variation of the first symbol is started by the first symbol display device 40. Therefore, as shown in FIG. 6, since the variation type counters CS1 to CS3 are acquired at the start of the first symbol variation by the first symbol display device 40, it is not necessary to store them in the reserved ball storage area. It is only necessary to sequentially update and store the data in the counter buffer.

  In addition, the magnitude | size and range of each counter mentioned above are only examples, and can be changed arbitrarily. However, the big hit random number counter C1, the stop pattern selection counter C3, and the variation type counters CS1 to CS3 are all different prime numbers, and it is desirable that they are numerical values that are not synchronized in any case.

  Further, as shown in FIG. 6, the second symbol random number counter C4 is used for the lottery of the second symbol of the second symbol display device 41. The second symbol random number counter C4 is configured, for example, as a loop counter that is incremented by 1 in the range of “0” to “250” and returns to “0” after reaching the maximum value (that is, 250). The second symbol random number counter C4 is updated periodically (once for each timer interruption (see FIG. 11) described later), and is acquired when the game ball passes through the second start port 34 on either the left or right side. The number of random number values to be won is 149, and the range is “5 to 153”.

  In particular, when the second symbol random number counter C4 makes one round, the initial value of the second symbol random number counter CINI2 at that time is read as the initial value of the second symbol random number counter C4. The initial value second symbol random number counter CINI2 is a loop counter similar to the second symbol random number counter C4 (value = 0 to 250) and is updated once every timer interrupt (see FIG. 11) described later. These are repeatedly updated within the remaining time of normal processing (see FIG. 8) described later. The second symbol random number counter C4 is updated periodically (once every timer interrupt (see FIG. 11) described later in the present embodiment), and the second time of the game ball passes through the second start port 34, the second of the RAM 503 2 Stored in the symbol hold storage area.

  That is, the RAM 503 also has a second symbol holding storage area which is an area different from the holding ball storage area, and includes one execution area for the second symbol and four holding areas for the second symbol (second A second symbol holding storage area comprising symbol holding first to fourth areas) is provided, and in each of these areas, in accordance with the winning history of game balls to the second starting port 34, the second symbol holding storage area is provided. Each value of the 2 symbol random number counter C4 is stored in time series.

  Further, the second symbol out-of-symbol counter C5 is updated once every time the second symbol control process of the normal process in FIG. 8 described later is executed once, and the value thereof is updated in the second symbol out-of-symbol of the counter buffer. When the second symbol random number counter C4 stores and updates the second symbol random number counter C4 in the second symbol holding ball storage area, the second symbol outlier symbol counter C5 updated and acquired in the second symbol outlier symbol buffer is also the second symbol. Stored in the holding ball storage area. Therefore, as shown in FIG. 6, when the value of the second symbol random number counter C4 is lost, “x” is drawn based on the value of the second symbol off symbol counter C5 in the second symbol holding ball storage area. The displayed display portion 41b is lit up. The second symbol variation display result may be performed based only on the second symbol random number counter C4 without providing the second symbol outlier symbol counter C5. That is, if the second symbol random number counter C4 is won, the display unit 41a on which “O” is drawn is lit up, and if it is lost, the display unit 41b on which “x” is drawn is lit up.

  Next, each control process executed by the CPU 501 in the main controller 261 will be described with reference to the flowcharts of FIGS. The processing of the CPU 501 is broadly divided into main processing that is started when the power is turned on, timer interrupt processing that is started periodically (in this embodiment, at a cycle of 2 msec), and power failure to the NMI terminal (non-maskable terminal). There is an NMI interrupt process activated by the input of a signal. For convenience of explanation, the timer interrupt process and the NMI interrupt process are described first, and then the main process is described.

  FIG. 11 is a flowchart showing timer interrupt processing. This processing is executed by the CPU 501 of the main control device 261 every 2 msec, for example.

  In FIG. 11, first, in step S601, various winning switch reading processes are executed. That is, the state of various switches (except for the RAM erase switch 323) connected to the main controller 261 is read, and the state of the switch is determined and the detection information (winning detection information) is stored.

  Thereafter, in step S602, the initial value random number counter CINI1 and the initial value second symbol random number counter CINI2 are updated. Specifically, the initial value random number counter CINI1 is incremented by 1 and cleared to “0” when the counter value reaches the maximum value (“599” in this embodiment), and the initial value second symbol random number counter While CINI2 is incremented by 1, it is cleared to “0” at the time of increment of 1 after the counter value reaches the maximum value (“250” in this embodiment). Then, the updated value of the initial value random number counter CINI1 is stored in the corresponding buffer area of the RAM 503 (see FIG. 6).

  Further, as shown in FIG. 11, in the subsequent step S603, the big hit random number counter C1, the big hit symbol counter C2, and the stop pattern selection counter C3 are updated. Specifically, the jackpot random number counter C1, the jackpot symbol counter C2 and the stop pattern selection counter C3 are each incremented by 1 and their counter values are maximum values (in this embodiment, “599”, “9”, In the case of 1 increment after reaching “250”), each is cleared to “0”. Then, the updated values of the counters C1 to C3 are stored in the corresponding buffer area of the RAM 503 (see FIG. 6).

  After that, as shown in FIG. 11, in step S604, a start winning process is performed in accordance with winning in the first starting port 33a and the second starting port 33b. This start winning process will be described with reference to the flowchart of FIG. 12. In step S701, whether or not the game ball has won the first start opening 33a and the second start opening 33b is determined based on the detection information of the operation opening switch. When it is determined that the game ball has won the first start port 33a and the second start port 33b, in the subsequent step S702, the number N of the operation reservation balls of the first symbol display device 40 is the upper limit value (this embodiment). Then, it is determined whether it is less than 4). The process proceeds to step S703 on the condition that there is a winning at the first start port 33a and the second start port 33b and the number N of activated balls is <4, and the number N of activated balls is incremented by one.

  In subsequent step S704, a random number related to the winning of the first symbol is acquired. Specifically, the values of the jackpot random number counter C1, the jackpot symbol counter C2 and the stop pattern selection counter C3 updated in step S603 are used as the first of the free storage areas in the reserved ball storage area of the RAM 503 shown in FIG. Store in the area.

  Further, as shown in FIG. 11, in the subsequent step S605, a firing control process is executed. Specifically, in the launch control process, the CPU 501 of the main control device 261, as shown in FIG. 4, when the launch permission signal S7 from the launch control device 312 is ON, the launch control signal S8 and the ball feed control. The signal S9 is output to the launch control device 312, and the game ball launch control by the launch device 229 is performed. After performing the firing control process in this way, the CPU 501 once ends this timer interrupt process.

  FIG. 13 is a flowchart showing the NMI interrupt process. This process is executed by the CPU 501 of the main controller 261 when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like. By this NMI interruption, the state of the main controller 261 at the time of power-off is stored in the backup area of the RAM 503.

  That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like, the power failure signal S1 is output from the power failure monitoring circuit 542 to the NMI terminal of the CPU 501 in the main controller 261. Then, the CPU 501 interrupts the control being executed and starts the NMI interrupt process of FIG. The NMI interrupt process in FIG. 13 is stored in the ROM 502 of the main controller 261. For a predetermined time after the power failure signal S1 is output, power is supplied from the power supply unit 541 so that the processing of the main controller 261 can be executed, and the NMI interrupt processing is executed within the predetermined time.

  In the NMI interrupt process of FIG. 13, in step S801, information on occurrence of power interruption is set in the backup area. In this embodiment, a power off occurrence information flag is set and stored in the backup area.

Next, the main process will be described.
FIG. 7 is a flowchart showing an example of a main process executed by the CPU 501 in the main control device 261. This main process is started upon a reset at power-on.

  First, in step S101, the CPU 501 of the main control device 261 executes an initial setting process associated with power-on. Specifically, a predetermined value set in advance for the stack pointer is set. In step S102, the CPU 501 of the main control device 261 waits for, for example, about 1 second in order to wait for the sub-side control devices (sub-control device 262, payout control device 311, etc.) to become operable. Execute. In the subsequent step S103, the CPU 501 of the main control device 261 permits RAM access.

  Thereafter, data backup processing is executed for the RAM 503 in the CPU 501. That is, in step S104, the CPU 501 of the main controller 261 determines whether or not the RAM erase switch 323 provided on the power monitoring board 261b is pressed (ON). If there is, the process proceeds to step S113. In the subsequent step S105, the CPU 501 of the main control device 261 determines whether or not power-off occurrence information is set in the backup area of the RAM 503 (whether or not a power-off occurrence information flag is set). In step S106, the CPU 501 of the main control device 261 calculates a RAM determination value. In the subsequent step S107, the CPU 501 of the main control device 261 matches the RAM determination value stored when the power is turned off. Whether the backup is valid. The RAM determination value is a checksum value at a work area address of the RAM 503, for example. Note that it is possible to determine the effectiveness of backup based on whether or not the keywords written in a predetermined area of the RAM 503 are correctly stored.

  As described above, the pachinko machine 10 is turned on while pressing the RAM erase switch 323 when it is desired to return to the initial state when the power is turned on, for example, when the hall starts business. Therefore, if the RAM erase switch 323 is turned on, the process proceeds to the initialization process of the RAM 503 (step S113 and the like). Similarly, when the information on occurrence of power interruption is not set, or when a backup abnormality is confirmed by the RAM determination value (checksum value or the like), the used RAM area is cleared and the initialization process of the RAM 503 (step S113). That is, in step S113, the CPU 501 of the main control device 261 clears the use area of the RAM 503 to “0” and executes the initialization process of the RAM 503.

  In subsequent step S114, CPU 501 of main controller 261 transmits a payout initialization command. Thus, the payout initialization command is output to the payout control device 311 when the main control device 261 is initialized.

  In step S115, the CPU 501 of the main control device 261 transmits a power-on command to the sub control board 262a. Since the command at the time of power-on includes a command for determining the model of the pachinko machine, the model can be determined based on the contents of the command on the sub-side such as the sub-control board 262a or the display control device 45. .

  In step S116, the CPU 501 of the main control device 261 executes initial setting of a CTC (Counter / Timer Circuit). In step S117, the CPU 501 of the main control device 261 sets interrupt permission, and proceeds to normal processing (see FIG. 8) described later.

  On the other hand, if the RAM erase switch 323 has not been pressed, the power-off occurrence information is set, and the RAM judgment value (checksum value, etc.) is normal. Execute the process (process when power is restored). That is, in step S108, the information on occurrence of power interruption is cleared. In step S109, the CPU 501 of the main control device 261 transmits a payout return command to the payout control device 311 and instructs the payout control device 311 to start payout control. As will be described in detail later, when the payout control device 311 receives a payout return command from the main control device 261, the payout control device 311 returns and starts payout control.

  In step S110, the CPU 501 of the main control device 261 transmits a command for causing the sub-side control device to return to the gaming state when the power is cut off. In step S111, the CPU 501 of the main control device 261 receives the CTC (Counter / Timer Circuit) initial settings. Further, in step S112, the interrupt permission is set, and then the process proceeds to a normal process (see FIG. 8) described later. For example, even if the power interruption occurs during the normal processing, the power is turned off after executing the last step of the normal processing (the “RAM access prohibited” step shown in FIG. 8). Is executed from step S201, which is the first step of normal processing.

  Next, the flow of normal processing will be described with reference to the flowchart of FIG. In this normal process, the main process of the game is executed. As an outline, the processing of steps S201 to S207 is executed as a periodic processing with a period of 4 msec, and the counter update processing of steps S210 and S211 is executed with the remaining time.

  In FIG. 8, first, in step S <b> 201, the CPU 501 of the main control device 261 performs an external output process of transmitting output data such as a command updated in the previous process to each control device on the sub side. Specifically, the presence / absence of winning detection information is determined, and if there is winning detection information, a winning ball payout command corresponding to the number of acquired game balls is transmitted to the payout control device 311. In addition, the decorative design (3rd symbol) is also displayed by the 3rd symbol display device 42 in conjunction with the 1st symbol variation display of the 1st symbol display device 40 (variable display of the first segment display unit 40a). However, when the first symbol display device 40 displays the variation of the first symbol, a variation pattern designation command, a decoration symbol designation command, an all stop command (confirmation command), etc. are transmitted to the sub-control device 262 in the external output process.

  In this pachinko machine 10, external output of normal processing in the order of variation pattern designation command → production command (command for designating change of variation time) → decoration symbol designation command at the start of variation of the first symbol Each time a process is performed, commands are sent at a predetermined number (for example, three) (that is, every three for every 4 msec), and a stop command is sent at the timing of the change time. Further, after the first symbol variation starts, a predetermined number (for example, three) each time the external output processing of the normal processing is performed in the order of variation pattern designation command → effect command → decorative symbol designation command (ie, three every 4 msec). Command), and a stop command may be sent at the timing when the fluctuation time elapses.

  The variation pattern designation command is a command for designating a variation pattern of a decorative symbol (third symbol) that is variably displayed on the third symbol display device 42. The variation pattern designation command is transmitted from the main control device 261 to the sub-control device 262, and is transmitted from the sub-control device 262 to the display control device 45. The display control device 45 controls the third symbol display device 42 to display and execute the decorative symbol variation pattern based on the transmitted variation pattern designation command.

  The decorative symbol designating command is such that the variation display effect of the decorative symbol (the third symbol) on the third symbol display device 42 is the probability variation jackpot (specific hit), the latent probability variation jackpot (latency specific hit), and the normal jackpot (non-specific hit). This is a command for designating whether to be out of the range. The decoration symbol designation command is transmitted from the main control device 261 to the sub-control device 262, and is transmitted from the sub-control device 262 to the display control device 45. The display control device 45 displays the display result of the variation pattern of the decorative symbol as a result according to the transmitted decorative symbol designation command (probability big hit (specific per hit), latent probability big hit (latency specific per hit), normal big hit (non-specific) Display control is performed on the third symbol display device 42 so as to be hit or miss.

  The all stop command is a command for instructing to stop the variation pattern of the decorative symbol (third symbol) displayed in a variable manner on the third symbol display device 42. The all stop command is transmitted from the main control device 261 to the sub control device 262, and is transmitted from the sub control device 262 to the display control device 45. The display control device 45 controls the third symbol display device 42 so as to stop and display the decorative symbol variation pattern based on the transmitted all stop command.

  In addition, the CPU 501 of the main control device 261 sends a change pattern designation command and an effect command (command for designating change of change time) to the sub-control device 262 in the external output process (step S201) of the normal process. May be sent. That is, based on the value of the variation type counter CS3, it is determined which time the variation time addition (addition time due to the above-described decorative design slip effect) is to be used, and such an addition time is appropriately set in the sub-control device 262. An effect command is used to instruct. Therefore, after the first symbol variation starts, a predetermined number (for example, three) each time the external output processing of the normal processing is performed in the order of variation pattern designation command → effect command → decorative symbol designation command (ie, three every 4 msec). Command), and a stop command may be sent when the fluctuation time has elapsed.

  Next, in step S202, the CPU 501 of the main controller 261 updates the variation type counters CS1 to CS3. Specifically, each of the variation type counters CS1 to CS3 is incremented by 1, and each counter value reaches “0” (198, 240, 162 in the present embodiment) and is incremented by “0”. To clear. Then, the update values of the variation type counters CS1 to CS3 are stored in the corresponding buffer area shown in FIG.

  In the subsequent step S203 of FIG. 8, the CPU 501 of the main control device 261 reads the prize ball counting signal, the payout abnormality signal, and the lower dish full signal received from the payout control device 311. Thereafter, in step S204, a first symbol variation process for performing variation display of the first symbol by the first symbol display device 40 is executed. By this first symbol variation process, jackpot determination, variation setting of the first symbol, and the like are performed. The details of the first symbol variation process will be described later.

  Thereafter, in step S205, the CPU 501 of the main control device 261 executes a big prize opening / closing process for opening or closing the big prize opening 32a of the variable prize winning device 32 in the case of the big hit state. That is, the big winning opening 32a is opened for each round of the big hit state, and whether the maximum opening time of the big winning opening 32a has passed for each round, or whether a predetermined number of game balls have won the big winning opening 32a. judge. When any of these conditions is satisfied, the special winning opening 32a is stopped and closed during the round, and when there are remaining rounds, the special winning opening 32a is opened repeatedly for the remaining number of rounds.

  In step S206, the CPU 501 of the main control device 261 executes display control of the second symbol by the second symbol display device 41. Briefly, on the condition that the game ball has passed through the second starting port 34, the second symbol random number counter C4 is acquired and the display units 41a and 41b of the second symbol display device 41 each time. Variation display of the second symbol is performed. Then, when the second symbol lottery is carried out based on the value of the second symbol random number counter C4 and the second symbol wins, the CPU 501 of the main control device 261, as shown at step S207, The opening process of the 2nd starting port 33b which opens the starting port 33b for the predetermined time is performed. Although the explanation is omitted, the second symbol random number counter C4 is also updated by the timer interruption process shown in FIG. 11, like the jackpot random number counter C1, the jackpot symbol counter C2, and the stop pattern selection counter C3. ing.

  In step S208, the CPU 501 of the main control device 261 determines whether or not power-off occurrence information is set in the backup area of the RAM 503 (whether or not a power-off occurrence information flag is set). If the information on occurrence of power interruption is not set, the process proceeds to step S209, and if the occurrence information of power interruption is set, the process proceeds to step S212.

  Thereafter, in step S209, it is determined whether or not the next normal process execution timing has been reached, that is, whether or not a predetermined time (4 msec in the present embodiment) has elapsed since the start of the previous normal process. Then, the update of the initial value random number counter CINI1, the initial value second symbol random number counter CINI2, and the variation type counters CS1 to CS3 is repeatedly executed within the remaining time until the execution timing of the next normal processing (steps S210 and S211). ). That is, in step S210, the initial value random number counter CINI1 and the initial value second symbol random number counter CINI2 are updated. Specifically, the initial value random number counter CINI1 is incremented by 1, and is cleared to “0” at the time of increment of 1 after the counter value reaches the maximum value (“599” in the present embodiment). Then, the updated value of the initial value random number counter CINI1 is stored in the corresponding buffer area of the RAM 503. Similarly, the initial value second symbol random number counter CINI2 is incremented by 1 and cleared to “0” when incremented by 1 after the counter value reaches the maximum value (“250” in the present embodiment). To do. Then, the updated value of the initial value second symbol random number counter CINI2 is stored in the corresponding buffer area of the RAM 503.

  In step S211, the variation type counters CS1 to CS3 are updated (same as step S202). Specifically, the variation type counters CS1 to CS3 are incremented by 1, and the increment value of the increments after reaching the maximum value (“198”, “240”, “162” in the present embodiment) is increased. Each time it is cleared to "0". Then, the updated values of the variation type counters CS1 to CS3 are stored in the corresponding buffer area of the RAM 503.

  Here, since the execution time of each process of steps S201 to S207 changes according to the state of the game, the remaining time until the execution timing of the next normal process is not constant and varies. Therefore, by repeatedly executing the initial value random number counter CINI1 and the initial value second symbol random number counter CINI2 using the remaining time, the initial value random number counter CINI1 (that is, the initial value of the big hit random number counter C1) and the initial value The value second symbol random number counter CINI2 (that is, the initial value of the second symbol random number counter C4) can be updated at random.

  In step S208, if the information on occurrence of power interruption is set, and the process proceeds to step S212, the CPU 501 of the main control device 261 sets interrupt inhibition. Subsequently, in step S213, the CPU 501 of the main control device 261 transmits a power-off notification command indicating that the power has been quickly turned off to another control device. Subsequently, in step S214, the CPU 501 of the main controller 261 stops outputting the control signal. Subsequently, in step S215, the CPU 501 of the main controller 261 calculates a RAM determination value and stores it in the backup area. The RAM determination value is, for example, a checksum value at the work area address of the RAM 503. Subsequently, in step S216, the CPU 501 of the main controller 261 prohibits RAM access. After that, an infinite loop is entered in preparation for the case where the power supply is completely shut down and processing cannot be executed.

  Next, the first symbol variation process of step S205 will be described with reference to the flowchart of FIG.

  In FIG. 9, in step S401, the CPU 501 of the main control device 261 determines whether or not it is currently a big hit. The jackpot includes a special game displayed on the third symbol display device 42 and a predetermined time after the special game is ended. In the subsequent step S402, the CPU 501 of the main control device 261 determines whether or not the first symbol display device 40 is currently displaying the variation of the first symbol. If it is not a big hit and the first symbol variation is not being displayed, the process proceeds to step S403, where the CPU 501 of the main control device 261 determines whether the number N of active suspension balls of the first symbol display device 40 is greater than “0”. Determine whether or not. At this time, if it is a big hit or if the number N of active suspension balls is “0”, the present process is terminated as it is.

  Further, if it is neither a big hit nor a change display of the first symbol, and if the number of operation hold balls N> 0, the process proceeds to step S404. In step S <b> 404, the CPU 501 of the main control device 261 subtracts “1” from the number N of pending operation balls. In step S405, a process for shifting the data stored in the reserved ball storage area is executed. This data shift process is a process of sequentially shifting the data stored in the reserved first to fourth areas of the reserved ball storage area to the execution area side, and the reserved first area → execution area, reserved second area → The data in each area is shifted, such as the hold first area, the hold third area → the hold second urea, the hold fourth area → the hold third area.

  Thereafter, in step S406, the CPU 501 of the main control device 261 executes a change start process. Here, the variation start process will be described in detail with reference to the flowchart of FIG. 10. In step S501, the CPU 501 of the main controller 261 sets the value of the jackpot random number counter C1 stored in the execution area of the reserved ball storage area. Based on this, it is determined whether or not it is a big hit. Specifically, whether or not it is a big hit is determined based on the relationship between the value of the big hit random number counter C1 and the mode at that time (whether it is a probabilistic variation state or a normal state). Of the numerical values “0” to “599” of the jackpot random number counter C1, “150, 450” is a winning value (two), and “50, 150, 350, 450” is a winning value (four) at a high probability. is there.

  If the CPU 501 of the main control device 261 determines that it is a big hit, in step S502, the big hit symbol corresponding to the value of the big hit symbol counter C2 stored in the execution area of the reserved ball storage area, that is, the first symbol display. It is determined whether any of the first to third symbols displayed on the first segment display unit 40a of the device 40 is used. That is, based on a table (not shown) indicating the correspondence between the value of the jackpot symbol counter C2 and the symbol, the jackpot symbol corresponding to the value of the jackpot symbol counter C2 ("specific hit symbol", "latent specific hit symbol" or "Non-specific per symbol").

  Next, in step S503, the CPU 501 of the main control device 261 determines a variation pattern (a jackpot effect pattern) at the time of the jackpot. Specifically, the CPU 501 of the main control device 261 uses the value of the jackpot symbol counter C2 and the values of the variation type counters CS1 and CS2 stored in the counter buffer of the RAM 503 without using the stop pattern selection counter C3. Check in order and determine the variation pattern.

  That is, based on the value of the jackpot symbol counter C2, whether the decorative symbol on the third symbol display device 42 is displayed with the “stop pattern 3” of the normal jackpot (non-specific hit), or on the third symbol display device 42 It is determined whether or not the decorative symbol is displayed with the “stop pattern 4” of the probable big hit (specific hit). The type of “stop pattern 3” or “stop pattern 4” thus determined is further determined based on the value of the first variation type counter CS1. That is, a rough decorative pattern variation pattern group such as a reach type of a decorative symbol (third symbol) such as normal reach, super reach, premium reach, or the like is determined. Subsequently, one variation pattern is determined based on the value of the second variation type counter CS2 from the group of variation patterns of the rough decorative design determined as described above. For example, based on the value of the second variation type counter CS2, a finer decorative pattern such as a predetermined time is set for the elapsed time until the final stop decorative pattern (in this embodiment, the middle decorative pattern) stops after the reach occurs. The variation mode is determined. The following relations in the case of jackpot, that is, the relation between the numerical value of the jackpot symbol counter C2 and the stop pattern, the relation between the numerical value of the first fluctuation type counter CS1 and the fluctuation pattern, the numerical value of the second fluctuation type counter CS2 The relationship with the stop symbol time is defined in advance by a jackpot table or the like.

  On the other hand, if it is determined in step S501 that the game is not a big hit, in step S504, the CPU 501 of the main control device 261 uses the fourth symbol to indicate the out symbol, that is, the first segment display unit 40a of the first symbol display device 40. Set the stop symbol to stop display.

  Next, in step S505, the CPU 501 of the main control device 261 determines a fluctuation pattern (outage effect pattern) at the time of deviation, and sets the deviation fluctuation pattern as a fluctuation pattern designation command. Specifically, the CPU 501 of the main controller 261 checks the values of the stop pattern selection counter C3 and the variation type counters CS1 and CS2 stored in the execution area of the reserved ball storage area of the RAM 503 in that order, and displays the variation pattern. decide.

  That is, based on the value of the stop pattern selection counter C3, after the reach of the decorative symbol on the third symbol display device 42 occurs, the final stop decorative symbol is shifted by one before and after the reach decorative symbol and stops. "Stop pattern 1", which is the same as the "stop pattern 2", which is the "reach other than front-rear disengagement" where the final stop decorative pattern stops other than before and after the reach decorative pattern, "Stop pattern 0" which is "" is determined. For example, when the determined stop pattern is “stop pattern 1” that is, for example, a front / rear out of reach reach, normal reach, super reach from the front / rear out of reach reach variation pattern group based on the value of the first variation type counter CS1. A variation pattern group of rough decorative symbols is determined, for example, a variation pattern in which the reach type of the decorative symbol (third symbol) such as is specified is determined. Here, it is assumed that normal reach is determined. Subsequently, one variation pattern is further determined based on the value of the second variation type counter CS2 from the normal reach variation pattern group of the rough decorative design determined as described above. For example, based on the value of the second variation type counter CS2, a finer decorative pattern such as a predetermined time is set for the elapsed time until the final stop decorative pattern (in this embodiment, the middle decorative pattern) stops after the reach occurs. The variation mode is determined. It should be noted that the following relationships in the case of deviation, that is, the relationship between the numerical value of the stop pattern selection counter C3 and the stop pattern, the relationship between the numerical value of the first variation type counter CS1 and the variation pattern, and the numerical value of the second variation type counter CS2 And the stop symbol time are defined in advance by a table for detachment.

  In the present embodiment, as one of the above-mentioned tables for detachment, for example, at the time of low probability, in the state of the variable time shortening function of the first symbol display device 40, when the first symbol variation starts. Some are used when the number of pending operations of the first symbol is “0”. When the value of the stop pattern selection counter C3 is “0 to 201”, it corresponds to no reach (completely missed), and “ 202-208 "corresponds to the front / rear reach, and" 209-238 "corresponds to the reach other than the front / rear reach.

  Subsequently, in step S506, the CPU 501 of the main control device 261 determines the effect time addition, that is, the effect of adding the effect time of the jackpot variation pattern determined in step S503 or the off-variation pattern determined in step S505. Do. More specifically, on the basis of the value of the variation type counter CS3, an increase in the production time due to the sliding stop of the decorative symbol (third symbol) of the middle decorative symbol sequence on the third symbol display device 42 (the middle ornament) A variation pattern including an increase in time until the decorative symbol of the symbol row slides and is stopped and displayed is determined.

  In step S507, the CPU 501 of the main controller 261 receives a variation pattern designation command corresponding to the jackpot variation pattern determined in step S503 or a variation pattern designation command corresponding to the outlier variation pattern determined in step S505. Set.

  Subsequently, in step S508, if the CPU 501 of the main control device 261 has passed through steps S502 and S503, the jackpot symbol ("specific hit symbol" or "non-specific symbol" of the first symbol display device 40 determined in step S502. If a decorative symbol designation command corresponding to “specific symbol”) is set and steps S504 and S505 are performed, a decorative symbol designation command corresponding to the out symbol of the first symbol display device 40 determined in step S504 is issued. Set.

  Subsequently, in step S509, the CPU 501 of the main control device 261 sets an effect time addition designation command corresponding to the effect time addition determined in step S506, and ends this process.

  Returning to the description of FIG. 9, when step S402 is YES, that is, when the first symbol variation display is being performed, the process proceeds to step S407, and the CPU 501 of the main control device 261 determines whether or not the first symbol variation time has elapsed. Is determined. The variation time of the first symbol is determined based on the variation pattern and the effect time addition determined as described above with reference to FIG. 10, that is, the first symbol according to the variation pattern of the first symbol. The variation time is determined, and when this variation time has elapsed, an affirmative determination is made in step S407. If the variation time has not elapsed, the process proceeds to step S408, and if the variation time has elapsed, the process proceeds to step S409.

  In step S408, the CPU 501 of the main control device 261 updates the first symbol variation display on the first symbol display device 40. That is, the variable display of the first segment display unit 40a of the first symbol display device 40 is continued, and this process is terminated.

  On the other hand, in step S409, the CPU 501 of the main control device 261 stops the first symbol variation display and sets the first symbol stop symbol to the display symbol. In other words, if the jackpot symbol (probable variation jackpot) is determined in step S502 of FIG. 10, the first segment display unit 40a is changed to the first after the variable display of the first segment display unit 40a of the first symbol display device 40. Stop display with a symbol (means probable big hit (specific hit)). When the jackpot symbol (latency probability variation jackpot) is determined in step S502 in FIG. 10, after the first segment display unit 40a of the first symbol display device 40 displays the variation, the first segment display unit 40a is displayed as the second symbol. To stop display (means latent probability change jackpot (latency specific hit)). When the jackpot symbol (ordinary jackpot) is determined in step S502 of FIG. 10, after the variable display of the first segment display unit 40a of the first symbol display device 40, the first segment display unit 40a is indicated by the third symbol. Stop display (usually means big hit (non-specific hit)). If it is determined in step S504 in FIG. 10 that the symbol has been removed, the first segment display unit 40a is stopped and displayed at the fourth symbol after the first segment display unit 40a of the first symbol display device 40 is displayed. Means off).

  Subsequently, in step S410, the CPU 501 of the main control device 261 sets an all stop command for instructing to stop the variation pattern of the decorative symbol (third symbol) that is variably displayed on the third symbol display device 42, Thereafter, this process is terminated.

  Next, payout control executed by the CPU 511 in the payout control device 311 will be described. FIG. 14 is a flowchart showing the main process of the payout control apparatus 311. This main process is started upon reset when the power is turned on.

  First, in step S901, an initial setting process associated with power-on is executed. Specifically, the CPU 511 of the payout control device 311 sets a stack address and an interrupt mode. In step S902, the CPU 511 of the payout control device 311 permits RAM access, and in step S903, the CPU 511 of the payout control device 311 sets an external interrupt vector.

  Thereafter, in step S <b> 904, the CPU 511 of the payout control device 311 determines whether power-off occurrence information is set in the backup area of the RAM 513. In step S905, the CPU 511 of the payout control device 311 calculates a RAM determination value, and in the subsequent step S906, whether or not the RAM determination value matches the RAM determination value stored when the power is turned off, that is, the backup is valid. Determine gender. The RAM determination value is, for example, a checksum value at a work area address in the RAM 513. It should be noted that it is possible to determine the effectiveness of backup based on whether or not the keywords written in a predetermined area of the RAM 513 are correctly stored.

  Subsequently, in step S907, the CPU 511 of the payout control device 311 performs initial setting of the RAM 513 at the time of power recovery. Specifically, when the main control device 261 is initialized, a payout initialization command is transmitted from the main control device 261 to the payout control device 311, and the CPU 511 of the payout control device 311 starts payout from the main control device 261. When the reset command is received, initialization of the RAM 513 at the time of power recovery is performed in step S907. That is, the RAM area is initialized, and the control of game ball payout is started.

  Therefore, when the RAM erase switch 323 is pressed (ON) when the power is turned on, the main controller 261 is initialized and a payout initialization command is transmitted from the main controller 261 to the payout controller 311. Accordingly, the CPU 511 of the payout control device 311 performs initialization processing of the RAM 513 based on the payout initialization command from the main control device 261.

  Subsequently, in step S908, the CPU 511 of the payout control device 311 performs initial setting of peripheral devices of the CPU 511. Specifically, the CPU peripheral device is a timer control device called a CTC (Counter / Timer Circuit). This CTC is set to a predetermined value and a timer interrupt is generated every 2 milliseconds (ms).

  Subsequently, in step S909, the CPU 511 of the payout control apparatus 311 sets an interrupt permission, and proceeds to a payout control process described later.

  On the other hand, when the occurrence information of the power cut-off is not set in step S904, or when a backup abnormality is confirmed by the RAM determination value (checksum value or the like) in step S906, the payout control device 311 is similarly configured. The CPU 511 clears the entire area of the RAM 513 to “0” (step S910), and performs initialization processing (step S911).

  Next, the flow of the payout control process will be described with reference to the flowchart of FIG.

  In FIG. 15, in step S <b> 1001, the CPU 511 of the payout control device 311 acquires and stores a command from the main control device 261. Here, as the commands to be stored, 15 types of prize ball commands (15 types of prize ball commands for instructing 1 to 15 payouts) and the start of payout control to the payout control device 311 are instructed. There are 17 types of commands including a payout return command for payout and a payout initialization command for instructing payout initialization to the payout control device 311.

  In step S1002, the CPU 511 of the payout control device 311 determines whether or not the payout permission has been received. That is, it is determined whether or not a payout return command or a prize ball command is received. In step S1003, the CPU 511 of the payout control device 311 checks the state return switch (not shown) and executes the state return operation when it is determined that the state return operation is started.

  Thereafter, in step S <b> 1004, the CPU 511 of the payout control device 311 executes setting of the lower pan full tank state or the lower pan full tank release state according to the change in the state of the lower pan 15. That is, when the lower pan 15 is detected based on the detection signal of the lower pan full switch, when the lower pan is full, the lower pan full state is set, and when the lower pan full is not reached , Set the lower pan full release state.

  In step S1005, the CPU 511 of the payout control device 311 executes setting of a tank ball absence state or a tank ball absence release state according to a change in the state of the tank ball. In other words, the tank ball no switch state is determined based on the detection signal of the tank ball no switch, and when there is no tank ball, the setting of the tank ball no state is executed. Perform configuration.

  Thereafter, in step S1006, the CPU 511 of the payout control device 311 determines the presence / absence of a notification state, and notifies the 7-segment LED provided in the payout control device 311 if there is a notification state.

  In steps S1007 to S1009, prize ball payout processing is executed. In this case, if the prize ball is not paid out and the total number of prize balls stored in step S1001 is not “0” (both NO in steps S1007 and S1008), the process proceeds to step S1009 and a prize ball control process ( FIG. 16 described later is started. Further, if the prize ball cannot be paid out or the total number of prize balls is 0 (YES in any of steps S1007 and S1008), the process proceeds to a lending payout process.

  Thereafter, in steps S1010 to S1012, a rental ball payout process is executed. In this case, if it is not possible to pay out the rent and if a rent-out request from the card unit has been received (NO in step S1010, YES in S1011), the process proceeds to step S1012 and a renting control process (described later). FIG. 17) is started. Further, if a rental ball cannot be paid out or a rental ball payout request has not been received (YES in step S1010 or NO in S1011), subsequent vibrator motor control (step S1013) is executed.

  In step S1013, the CPU 511 of the payout control device 311 executes control (vibration motor control) of the vibrator 360 (see FIG. 2). Thereafter, in step S1014, the CPU 511 of the payout control device 311 determines whether or not a power failure has occurred. If a power failure has occurred, the process proceeds to step S1015; otherwise, the process returns to step S1001. In step S1015, the CPU 511 of the payout control device 311 sets information on occurrence of power interruption, and creates a RAM determination value in step S1016. After that, an infinite loop is entered in preparation for the case where the power supply is completely shut down and processing cannot be executed.

  Here, in the prize ball control process shown in FIG. 16, in step S1101, the payout motor 358a is driven to execute the prize ball payout. In subsequent step S1102, whether the rotation of the payout motor 358a is normal is determined based on the detection result of the payout rotation sensor. If the rotation of the payout motor 358a is not normal, the process advances to step S1103 to drive the payout motor 358a to execute a retry process and execute a stop process of the payout motor 358a, and then return to the payout control process in FIG.

  If the rotation of the payout motor 358a is normal, the process proceeds to step S1104, and whether or not the game ball is normally counted is determined based on the detection result of the payout count switch. If the game ball count is not normal, the process advances to step S1105 to drive the payout motor 358a to execute a retry process and execute a stop process of the payout motor 358a, and then returns to the payout control process of FIG.

  Further, if the game ball count is normal, the process proceeds to step S1106, and it is determined whether or not the game ball count by the payout count switch has reached the total number of prize balls and the payout has been completed. If the payout has been completed, a stop process of the payout motor 358a is executed in step S1107, and then the process returns to the payout control process of FIG.

  In the ball lending control process shown in FIG. 17, in step S1201, the payout motor 358a is driven to pay out a lending ball. In the subsequent step S1202, it is determined from the detection result of the dispensing rotation sensor whether the rotation of the dispensing motor 358a is normal. If the rotation of the payout motor 358a is not normal, the process advances to step S1203 to drive the payout motor 358a to execute a retry process and stop the payout motor 358a, and then return to the payout control process in FIG.

  If the rotation of the payout motor 358a is normal, the process advances to step S1204 to determine whether or not the game ball is normally counted based on the detection result of the payout count switch. If the game ball count is not normal, the process advances to step S1205 to drive the payout motor 358a to execute a retry process and execute a stop process of the payout motor 358a, and then return to the payout control process of FIG.

  If the game ball count is normal, the process proceeds to step S1206, where it is determined whether or not the game ball count by the payout count switch has reached a predetermined number of rented balls (25) and the payout is completed. If the payout has been completed, a stop process of the payout motor 358a is executed in step S1207, and then the process returns to the payout control process of FIG.

  The NMI interrupt process is similarly executed in the payout control device 311, and the state of the payout control device 311 when the power is cut off due to the occurrence of a power failure or the like is stored in the backup area of the RAM 513 by the NMI interrupt. Similarly, the power is supplied from the power supply unit 541 so that the processing of the payout control device 311 can be executed for a predetermined time after the power failure signal S1 is output. That is, when the power of the pachinko machine 10 is cut off due to the occurrence of a power failure or the like, the power failure signal S1 is output from the power failure monitoring circuit 542 to the NMI terminal of the CPU 511 in the payout control device 311 and the CPU 511 interrupts the control being executed. The NMI interrupt process of FIG. 13 is started. The contents are as described in FIG.

  Next, the main process and the normal process of the sub-control device 262 will be described with reference to FIGS. FIG. 18 is a flowchart showing an example of a main process executed by the CPU 551 of the sub-control device 262, and this main process is started upon reset when the power is turned on. FIG. 19 is a flowchart illustrating an example of normal processing executed by the CPU 551 of the sub-control device 262.

  First, in step S1301, the CPU 551 of the sub-control device 262 executes an initial setting process associated with power-on. Specifically, port setting (port I / O switching and initial value output), timer setting (1 millisecond interval timer, liquid crystal command strobe output timer), and interrupt setting (subcommand strobe interrupt) are performed. .

  In step S1302, the CPU 551 of the sub-control device 262 determines whether the power-off process is incomplete. Specifically, whether or not various lamps (annular illumination unit 102, central illumination unit 103, etc.) of front frame set 14 of pachinko machine 10 are all extinguished and whether speaker 25 is in a mute state or not. Is determined. If the power-off process is not completed, the process proceeds to step S1304. Otherwise, the process proceeds to step S1303.

  Subsequently, in step S1303, the CPU 551 of the sub-control device 262 determines whether or not the RAM of the sub-control device 262 is destroyed. If it is destroyed, the process proceeds to step S1304. Otherwise, the process proceeds to step S1307. . In step S1304, the CPU 551 of the sub control device 262 performs a RAM area read / write check of the sub control device 262. In step S1305, the CPU 551 of the sub control device 262 determines whether or not the RAM of the sub control device 262 is normal. If the RAM of the sub-control device 262 is normal, the process proceeds to step S1306. If the RAM is abnormal, the process proceeds to step S1312. In step S1306, the CPU 551 of the sub-control device 262 writes RAM destruction check data for each area of the RAM 553, and sets RAM destruction check data for determining that there is destruction if there is a reading abnormality.

  In step S1307, the CPU 551 of the sub-control device 262 determines whether the power is turned on after the power is turned off. If the power is turned on after the power is turned off, the process proceeds to step S1308; otherwise, the process proceeds to step S1309.

  In step S1308, the CPU 551 of the sub control device 262 clears the RAM area other than the unprocessed RAM area. Specifically, the unprocessed RAM area is an area for storing information that causes a problem in the system when the data is cleared, and is an area of information that is desired to remain except when the RAM area is destroyed. For example, a subcommand reception buffer and power-on information can be mentioned. When the main control device 261 is turned off and the sub control device 262 is reset (when a power-off notification command is received from the main control device 261), the RAM area other than the unprocessed RAM area is cleared.

  In step S1309, the CPU 551 of the sub-control device 262 sets interrupt permission. In step S1310, the CPU 551 of the sub control device 262 performs initial value setting of the RAM of the sub control device 262. In step S1311, the CPU 551 of the sub-control device 262 sets the effect initialization flag to “1”, and proceeds to the normal process shown in FIG.

  In step S1312, the CPU 551 of the sub-control device 262 notifies the RAM abnormality and enters an infinite loop. For example, notification such as turning on a predetermined lamp unconditionally can be given.

  As shown in FIG. 19, in step S1401, the CPU 551 of the sub-control device 262 determines whether or not 1 ms has elapsed since the start of normal processing. If 1 ms or longer has elapsed, the process proceeds to step S1402, and if not, the process proceeds to step S1410.

  In step S1402, the CPU 551 of the sub control device 262 performs lamp output processing. Specifically, lamp output is performed in accordance with the variation pattern effect of the decorative symbol (third symbol) on the third symbol display device 42.

  In step S1403, the CPU 551 of the sub control device 262 performs power-on notification. Specifically, notification for 30 seconds is performed by a power-on command.

  In step S1404, the CPU 551 of the sub-control device 262 performs a customer waiting effect. Specifically, the title / still image is switched. That is, a so-called demonstration screen display is performed.

  In step S1405, the CPU 551 of the sub-control device 262 performs the number-of-holds display update process for the first symbol variation. Specifically, the number-of-holds display update process is a process for performing the display corresponding to the hold lamp 40 c of the first symbol display device 40 also on the third symbol display device 42, and the hold of the first symbol display device 40 is held. The hold display 90 corresponding to the lamp 40c (up to four as with the hold lamp 40c) is also performed on the display screen 42a of the third symbol display device 42. In the case of a pachinko machine that displays only with the holding lamp 40c of the first symbol display device 40, this processing is unnecessary.

  In step S1406, the CPU 551 of the sub-control device 262 performs frame button input monitoring / effect processing. Specifically, this frame button input monitoring / production process is for performing a model-specific production by pressing a frame button in a pachinko machine provided with a frame button that can be pressed by the player. Therefore, this process is not necessary for a pachinko machine that does not include such a frame button.

  In step S1407, the CPU 551 of the sub-control device 262 performs lamp editing processing. Specifically, a process for editing a lamp lighting pattern corresponding to (synchronized with) the decorative pattern variation pattern effect on the third symbol display device 42 is performed.

  In step S1408, the CPU 551 of the sub-control device 262 issues a sound editing instruction. Specifically, the sound output control device 271 is instructed to sound a sound corresponding to (synchronized with) the decorative pattern variation pattern effect on the third symbol display device 42 (output sound, music, sound effect, etc.). .

  In step S1409, the CPU 551 of the sub-control device 262 performs a liquid crystal effect execution management process. Specifically, time management for synchronizing the lamp, sound, and liquid crystal effect (decorative pattern change pattern effect on the third symbol display device 42) is performed.

  In step S1410, the CPU 551 of the sub-control device 262 performs a process of updating the decorative symbol variation pattern to be performed by the third symbol display device 42, the random value for determining the sound and the lamp effect. Specifically, for example, this random number takes a value of “0” to “32767” and returns to “0” when the upper limit value “37268” is reached.

  In step S1411, when the CPU 551 of the sub control device 262 receives a command from the main control device 261, the CPU 551 performs processing corresponding to each command.

  Specifically, when the CPU 551 of the sub-control device 262 receives a variation pattern designation command from the main control device 261, the CPU 551 transmits a display command obtained by converting the variation pattern designation command to the display control device 45. Note that the variation pattern designation command may be output as it is. Further, when the CPU 551 of the sub-control device 262 receives the decoration symbol designation command from the main control device 261, the CPU 551 transmits a stop display command obtained by converting the decoration symbol designation command to the display control device 45. In addition, in the command conversion of the decorative symbol designation command, when a notice command is generated in addition to the stop display command, the notice command is also transmitted to the display control device 45. The notice command includes, for example, the presence or absence of the appearance of a school of fish as a notice. Further, when the CPU 551 of the sub-control device 262 receives a total stop command (confirmation command) from the main control device 261, the CPU 551 transmits the total stop command to the display control device 45 as it is.

  In step S1412, the CPU 551 of the sub control device 262 performs a command output process for outputting a command to the display control device 45 or the like. The CPU 551 of the sub control device 262 transmits various commands such as the above-described display command and stop display command to the display control device 45, for example.

  In step S1413, the CPU 551 of the sub control device 262 determines whether or not the RAM of the sub control device 262 is destroyed. If the RAM is not destroyed, the process returns to step S1401, and if the RAM is destroyed, an infinite loop is entered.

  In the display control device 45, the decorative symbols to be performed by the third symbol display device 42 based on the commands (variation pattern specifying command, decorative symbol specifying command, notice effect command, all stop command) from the sub-control device 262. The image generation control of the fluctuation pattern is performed. Specifically, the display control device 45 executes image generation processing for the decorative symbol variation pattern in the third symbol display device 42, for example, generates an image at a frame rate of 30 (30 images per second), By storing these generated images in the video RAM 524 (for example, a frame buffer) and displaying them appropriately on the third symbol display device 42, the decorative symbol variation display on the third symbol display device 42 is realized. ing.

<Sound output control>
Next, the structure of the further characteristic part of the pachinko machine 10 of a present Example is demonstrated using FIG. FIG. 20 is a block diagram showing the configuration of the sound output control device 271.

  As described above, the pachinko machine 10 of the present embodiment outputs sound from the speaker 25 in synchronization with the variable display effect on the third symbol display device 42 based on the control signal from the sub-control device 262. A sound output control device 271 for controlling is provided. This sound output control device 271 outputs sound output (sound effect, melody) corresponding to the variable display effect on the third symbol display device 42 from the speaker 25.

  The sound output control device 271 includes a sound control CPU 272 (central processing unit), a sound output LSI 273 (integrated circuit), a sound data ROM 274, an amplifier 275, and a volume level detection unit 276.

  The sound control CPU 272 controls the sound output in the pachinko machine 10, and has a function of controlling the sound output (melody) corresponding to the variable display effect during execution of the variable display effect of the third symbol, for example. ing. The sound control CPU 272 includes a sound control program related to sound control of the pachinko machine 10, a program ROM 281 that stores various data used in the program, and an amplification amount determination unit 282 that determines the amplification amount of the volume. Yes. Various sound output controls are performed by executing the sound control program of the program ROM 281. The sound control CPU 272 designates the music number corresponding to the event input from the sub-control device 262 to the sound output LSI 273, so that the sound output LSI 273, the sound data ROM 274, etc. cooperate to generate a melody corresponding to the music number. Can be played.

  The set value of the volume switch 29 is input to the amplification amount determination unit 282. The amplification amount determination unit 282 outputs an amplification signal corresponding to the set value of the volume switch 29 to the amplifier 275. The correspondence between the set value of the volume switch 29 and the amplified signal will be described with reference to FIG. The set value of the volume switch can be set in 6 levels from “0” to “5”. The set value “0” means mute, and no sound is output from the speaker 25. In this embodiment, it is assumed that the volume switch 29 is set to “5”.

  The set values “1” to “5” of the volume switch 29 correspond to the amplified signals A1 to A5, respectively. When the set value of the volume switch 29 is “1”, an amplification signal A1 is output from the amplification amount determination unit 282 to the amplifier 275, and the amplifier 275 can obtain an amplification amount of 50 dB. When the set value of the volume switch 29 increases by “1”, the amplification amount increases by 10 dB. When the set value of the volume switch 29 is “5”, an amplification amount of 90 dB can be obtained. The relationship between the set value of the volume switch 29 and the corresponding amplified signal is stored in the program ROM 281 as a table. Further, when the count signal is input from the volume level detection unit 276, the amplification amount determination unit 282 lowers the amplification signal output to the amplifier 275 by one step.

  The sound data ROM 274 stores sound data corresponding to the music number. The sound data ROM 274 stores sound data converted into digital data by recording in association with song numbers. For example, a song number “n1” is stored as a first melody, a song number “n2” is stored as a second melody, and a song number “n3” is stored as a third melody in association with a plurality of types. Yes.

  The sound output LSI 273 includes a sound data processing unit 283 that includes a sound source and reproduces digital sound data, and a DAC 284 that converts the reproduced digital sound data into analog sound data. For example, the sound output LSI 273 can simultaneously reproduce eight songs at the same time, but the reproduction can only be performed at the beginning, and cannot be reproduced from the middle. In the case of simultaneous playback, the mixed sound can be output as a single (monaural) or two (stereo) signal. In this embodiment, the mixed sound is output as a monaural signal. .

  The sound data processing unit 283 reads out sound data corresponding to the song number from the sound data ROM 274 based on the song number instruction from the sound control CPU 272. Furthermore, it reproduces based on the read sound data and outputs the reproduced sound signal to the DAC 284.

  The DAC 284 converts the digital sound signal input from the sound data processing unit 283 into an analog sound signal, and outputs the converted analog sound signal to the amplifier 275. The analog sound signal output from the DAC 284 is a waveform voltage signal.

  The amplifier 275 receives the sound signal from the sound output LSI 273 (for example, the sound signal corresponding to the first melody) and the amplified signal from the amplification amount determination unit 282. The amplifier 275 is a programmable amplifier, and in response to the amplified signal from the amplification amount determining unit 282, switching to a built-in resistor is operated to control the amplification amount of the sound signal. In the first embodiment, the amplifier 275 can perform silence and five-stage amplification corresponding to the amplified signal. In other words, the amplifier 275 outputs sounds having five levels of sound for every 10 dB from 50 dB to 90 dB corresponding to the amplified signal. The amplifier 275 outputs the amplified sound signal corresponding to the amplified signal to the speaker 25 and the volume level detector 276.

  A melody (for example, a first melody) is output from the speaker 25, and the player can listen to the melody emitted from the speaker 25. The player can visually enjoy the variable display effect on the 3rd symbol display device 42 and synergistically enjoy the variable display effect by listening to the melody corresponding to the variable display from the speaker 25. Can do.

  The volume level detection unit 276 collects and holds the maximum value of the input analog sound signal and compares the maximum value of the held analog sound signal with a predetermined threshold value. A comparison unit 292 that determines whether or not the held maximum value is larger than a predetermined threshold value, a reset unit 293 that erases the maximum value of the held analog sound signal, and the maximum value that is greater than the threshold value. And a volume counter 294 that counts the number of times determined to be large. A sound signal input from the amplifier 275 to the speaker 25 is branched and input to the volume level detection unit 276. Hereinafter, the volume level detector 276 will be described with reference to FIG. FIG. 22 is a circuit diagram showing an embodiment of the volume level detection unit 276.

  The peak hold unit 291 samples and holds the maximum voltage value of the input analog sound signal. The peak hold unit 291 includes an OP amplifier Am1, a diode D1, and a capacitor Ca1. The analog sound signal output from the amplifier 275 is input to the + input terminal of the OP amplifier Am1. The output terminal of the OP amplifier Am1 is connected to the anode of the diode D1. The cathode of the diode D1 is connected to the node N1. The node N1 is also connected to the negative input terminal of the OP amplifier Am1. Node N1 is also connected to node N2. Node N2 is connected to capacitor Ca1. The capacitor Ca1 holds the maximum voltage value of the analog sound signal input to the peak hold unit 291. A terminal other than the terminal connected to the node N2 of the capacitor Ca1 is grounded. The maximum voltage value output from the peak hold unit 291 is input to the reset unit 293.

  The reset unit 293 includes a relay Ry and resistors R1 and R2. One of the coils CL of the relay Ry is grounded via the resistor R1, and the other is connected to the sound control CPU 272. When a reset signal is input from the sound control CPU 272 to the relay Ry, the internal switch SW is switched to the ON state, and the node N2 is grounded via the resistor R2. When the reset signal from the sound control CPU 272 is canceled, the node N2 is returned to the OFF state, and the negative terminal of the OP amplifier Am2 of the comparison unit 292 is connected. Thus, in the OFF state, the maximum voltage value output from the reset unit 293 is input to the comparison unit 292.

  The comparison unit 292 includes an OP amplifier Am2, resistors R3, R4, R5, and an IC. The negative terminal of the OP amplifier Am2 is connected to the node N2 via the switch SW when the relay Ry is in the OFF state. The + terminal of the OP amplifier Am2 is connected to the node N3. One end of the resistor R3 is connected to the power supply voltage. The magnitude of the power supply voltage is, for example, 5V. The other end of resistor R3 is connected to node N3. Node N3 is also connected to node N4.

  ICs are shunt regulators. A threshold voltage is generated by the ICs and the resistors R3, R4, and R5. By using shunt regulator ICs, the threshold voltage can be kept constant regardless of voltage fluctuations. The cathode of ICs is connected to node N4, the anode of ICs is grounded, and the reference of ICs is connected to node N5. One end of resistor R4 is connected to node N4, and the other end is connected to node N5. One of the resistors R5 is connected to the node N5, and the other is grounded. In Example 1, 2.5 V is generated as the threshold voltage. The reference voltage serving as the threshold can be changed by changing the resistance values of R4 and R5. The generated threshold voltage is input to the + terminal of the OP amplifier Am2.

  When the input value from the peak hold unit 291 to the OP amplifier Am2 is smaller than the set threshold value, a positive voltage signal is output. When the input value to the OP amplifier Am2 is larger than the set threshold value, a voltage signal of 0V is output. These voltage signals are output to the volume counter 294 and the sound control CPU 272. Among these voltage signals, a voltage signal of 0 V is used as a discrimination signal output from the comparison unit 292.

  The volume counter 294 is a loop counter that adds “1” to the previous value each time it is updated, and returns to “0” after reaching the maximum value. The volume counter 294 adds “1” to the count value when a determination signal that is a voltage signal of 0 V is input from the comparison unit 292. When a positive voltage signal is input, it is not counted. The volume counter 294 outputs a count signal to the sound control CPU 272 when a predetermined number of determination signals are input. In this embodiment, the count signal is output when the discrimination signal is input three times. For example, the volume counter 294 can count from “0” to “2”, and outputs a count signal to the sound control CPU 272 when returning from the count value “2” to “0”.

Explanation of Operation Next, in the pachinko machine 10, the volume level control process based on the sound signal output from the amplifier 275 will be described with reference to FIG. FIG. 23 is a flowchart showing sound output processing.

  First, in step S1501, sound data to be reproduced by the sound control unit CPU 272 is designated. That is, the sound control unit CPU 272 designates the melody song number corresponding to the variable display effect on the third symbol display device 42 instructed from the sub-control device 262, and instructs the sound data processing unit 283 of the sound output LSI 273. To do. In step S1502, the amplification amount determination unit 282 determines the amplification amount in the amplifier 275. That is, the amplification amount determination unit 282 reads the set value of the volume switch 29 and outputs an amplified signal corresponding to the set value of the volume switch 29 to the amplifier 275. The amplifier 275 determines the amount of amplification of the input sound signal based on this amplified signal.

  In step S1503, the sound data processing unit 283 reads out and reproduces the sound data corresponding to the music number designated by the sound control CPU 272 from the sound data ROM 274. In step S1504, the DAC 284 converts the reproduced digital sound data into analog sound data. The converted sound data is output from the sound output LSI 273 to the amplifier 275.

  In step S1505, the amplifier 275 amplifies the analog sound signal output from the sound reproduction LSI 273 to the amplifier 275 based on the amplified signal from the amplification amount determination unit 282. In other words, the amplifier 275 performs analog gain on the input sound signal based on one of the amplified signals A1 to A5. The amplifier 275 outputs the amplified analog sound signal from the speaker 25 and also outputs it to the peak hold unit 291 of the volume level detection unit 276.

  In step S1506, the peak hold unit 291 collects (holds) and holds the maximum value of the input analog sound signal. The retained maximum value is output to the comparison unit 292. The operation of the peak hold unit 291 will be described with reference to FIG. FIG. 24 is an explanatory diagram showing sampling of the maximum value of the sound signal. The waveform of the sound signal AS shown in FIG. 24 is a voltage value at the node N2. The sound signal AS at the node N2 is only a voltage value portion of zero or more of the sound signal output from the amplifier 275.

  When the input voltage is larger than the voltage of the capacitor Ca1, since the + input of the OP amplifier Am1 is larger than the − input, the output of the OP amplifier Am1 rises, and the diode D1 is forward biased. As a result, the OP amplifier Am1 becomes a gain buffer, and the capacitor Ca1 is charged to the input voltage. Next, when the input voltage becomes smaller than the voltage of the capacitor Ca1, the + input of the OP amplifier Am1 becomes smaller than the − input, so that the output of the OP amplifier Am1 decreases and reversely biases the diode D1. As a result, the capacitor Ca1 is disconnected from the OP amplifier Am1 and is in an open state. That is, the voltage (maximum value) of the capacitor Ca1 is maintained as it is. When the input voltage becomes higher than the voltage of the capacitor Ca1 again, charging and holding of the capacitor Ca1 are repeated. In this way, every time the maximum value of the sound signal AS is updated, the peak hold unit 291 collects the maximum value (Sp). While the maximum value of the sound signal AS is not updated, the collected maximum value is held (Hd).

  In step S1507, the comparison unit 292 compares the held maximum value with a predetermined threshold value. When the held maximum value is equal to or smaller than a predetermined threshold (No in step S1507), the process returns to step S1506 again to collect the maximum values of the analog sound signals that are sequentially transmitted. If the retained maximum value is larger than a predetermined threshold value (Yes in step S1507), a determination signal is output to the volume counter 294 and the sound control CPU 272. In step S 1508, when the determination signal is input to the volume counter 294, “1” is added to the previous count value of the volume counter 294.

  In step S1509 in parallel with step S1508, when a determination signal is input from the comparison unit 292 to the sound control CPU 272, the sound control CPU 272 transfers to the reset unit 292 so as to erase the maximum value held in the peak hold unit 291. A reset signal is output. In the reset unit 292, the relay Ry performs switching (reset ON period) while the reset signal is input, and the capacitor Ca is grounded. As a result, the voltage stored in the capacitor Ca is erased, so that the retained maximum value can be erased. Note that the collected maximum value is held during a period when the relay Ry is not switching (reset OFF period).

  In step S1510, the process changes depending on whether or not the counter value of the volume counter 294 reaches a predetermined number of times (predetermined number of times). In this embodiment, when the determination signal is input to the volume counter 294 three times, the count signal is output from the volume counter 294 to the amplification amount determination unit 282. For example, when the initial count value is “0” and the count value is changed to “1” by the input of the determination signal, the predetermined number of times has not been reached, so the process returns to step S1506 again. (No in step S1510). Further, even if the determination signal is input and the count value changes to “2”, the predetermined number of times has not been reached, and therefore the process returns to step S1506 again (No in step S1510). Further, when the discrimination signal is input and the count value changes from “2” to “0”, the count signal is output to the amplification amount determination unit 282 because the predetermined number of times has been reached three times. (Yes in step S1510). Thus, every time the count value returns to “0”, the count signal is output from the volume counter 294 to the amplification amount determination unit 282.

  When the count signal is input from the volume counter 294, the amplification amount determination unit 282 reduces the amplification amount of the sound signal. For example, when the amplified signal “5” is transmitted to the amplifier 275, the amplified signal “4” at one stage below is transmitted. Thereby, the amplification amount of the sound data by the amplifier 275 is reduced by one step.

  Note that the volume restriction is released as the game progresses. That is, when the variable display effect on the third symbol display device 42 is changed, the volume restriction is restored. For example, when volume restriction control is performed during a jackpot display effect, the volume restriction is canceled as soon as the jackpot display effect ends. When the next event is input from the sub-control device 262, the increase determination unit 282 returns the amplified signal to the initial value. In addition, a reset signal is output to the reset unit 293. As a result, the amplification amount corresponding to the volume switch setting value is restored.

  According to the first embodiment, the volume level of the analog sound data input to the speaker 25 can be detected, so that the volume level can be detected more accurately. Since the sound output is feedback-controlled based on the accurate volume level detected in this manner, excessive output from the speaker 25 can be reduced. That is, the sound output signal input to the speaker 25 is compared with a predetermined threshold value, and when a sound signal exceeding the threshold value is detected, feedback control is performed to reduce the amplification amount of the sound signal. Thereby, the player does not have to listen to a harsh sound due to excessive amplification, and the occurrence of sound cracking can be prevented, so that clear sound quality can always be maintained.

  Further, since the sound signal input to the speaker 25 is a sound signal in which excessive amplification is suppressed, the speaker 25 can be prevented from being damaged, and deterioration over time can be reduced. Furthermore, the sound signal reproduced by the sound data processing unit 283 can be appropriately amplified even if there is a variation in the recording data reference level stored in the sound data ROM.

  Further, the game machine administrator can set a desired volume level by setting the volume switch 29. When the player does not control the amount of amplification by the sound output control device 271, the player can enjoy the sound comfortably with the amount of amplification set by the volume switch 29.

  Also, if the comparison unit 292 determines that the maximum value of the sound signal is larger than the threshold value, the reset unit 293 deletes the maximum value held in the peak hold unit 291, so that the peak hold unit 291 New maximum values can be collected. Thereby, the maximum value larger than the threshold value can be detected again.

  Note that the volume counter 294 may output the count signal when a predetermined number determination signal is input within a predetermined period. That is, when a predetermined period elapses, the volume counter 294 performs a process of returning the count to “0”. In returning to “0” in this case, the count signal is not output from the volume counter 294. According to this configuration, for example, it is possible to realize a configuration in which the volume level is reduced only when the volume level exceeds the threshold many times in a short period of time. As a result, it is possible to prevent the sound signal from being reduced when the maximum value of the sound signal accidentally exceeds a threshold, such as when noise is mixed.

  In addition, the maximum value held in the peak hold unit 291 is erased by outputting a reset signal from the sound control CPU 272 to the reset unit 293 using a count signal output from the volume counter 294 to the amplification amount determining unit 282 as a trigger. It was. As another configuration, a reset signal may be output to the reset unit 293 at predetermined intervals based on the internal clock of the sound control CPU 272. Even in this configuration, since the maximum value of the sound signal is periodically deleted, the peak hold unit 291 can newly detect the maximum value equal to or greater than the threshold value by newly collecting the maximum value of the sound signal. it can.

  In the first embodiment, the volume level detection unit 276 is provided with the volume counter 294. However, a volume level detection unit 276 'in which the volume counter 294 is omitted may be employed (see FIG. 25). That is, the discrimination signal of the comparison unit 292 may be directly input to the amplification amount determination unit 282. The amplification amount determination unit 282 reduces the amplification signal with the input of the discrimination signal as a trigger. According to the sound output control device 271 ′ having this configuration, the sound volume can be immediately reduced when a sound volume level exceeding the threshold is detected.

  In the first embodiment, the sound output is the speaker 25, but an earphone or a headphone may be used. Moreover, the structure which can select the sound output by the speaker 25 and the sound output by an earphone may be sufficient. In this case, it is preferable that the pachinko machine 10 is provided with an earphone output terminal in addition to the speaker 25. When an earphone or a headphone is used, sound is directly input to the player's ear, so that the volume level particularly affects the player's game. Therefore, it is preferable that excessive sound output is not performed.

  Next, the pachinko machine 10 according to the second embodiment will be described with reference to FIG. FIG. 26 is a block diagram illustrating a configuration of the sound output control device 391 according to the second embodiment. In FIG. 26, since the part shown with the same code | symbol as the code | symbol shown in Example 1 is the structure similar to Example 1, description here is abbreviate | omitted. The configuration of the pachinko machine 10 other than those described below is the same as that of the first embodiment.

  In the first embodiment, the volume level is controlled by the analog amplifier 275 in accordance with the amplified signal from the amplification amount determining unit 282. In the second embodiment, in addition to the control of the volume level by the analog amplifier 275, the sound output LSI 393 is provided with the gain unit 285, and the volume level is controlled even at the stage of the digital sound signal. That is, the feature of the second embodiment is that the volume level is adjusted in two stages, a digital sound signal stage and an analog sound signal stage.

  The sound output control device 391 according to the second embodiment includes a sound control CPU 392, a sound output LSI 393, a sound data ROM 274, an amplifier 275, and a volume level detection unit 276. The sound control CPU 392 is different from the sound control CPU 272 of the first embodiment in that an amplification amount determination unit 396 is provided instead of the amplification amount determination unit 282, and other functions are the same.

  Similarly to the amplification amount determination unit 282 in the first embodiment, the amplification amount determination unit 396 in the second embodiment receives the set value of the volume switch 29 and outputs an amplified signal corresponding to the set value of the volume switch 29 to the amplifier 275. To do. When the count signal is input from the volume counter 294, the amplifier 275 is instructed to reduce the amplified signal or to the gain unit 285 to instruct to decrease the volume level.

  The sound output LSI 393 according to the second embodiment has a configuration in which a gain unit 285 is added to the sound output LSI 273 according to the first embodiment. The sound data reproduced from the sound data processing unit 283 is input to the gain unit 285. The gain unit 285 reduces (minus gain) the value (amplitude amount) of the input digital sound data in accordance with an instruction from the amplification amount determination unit 396. With reference to FIG. 27, the correspondence between the amplified signal sent from the amplification amount determining unit 396 to the gain unit 285 and the amplification amount will be described. In the second embodiment, the negative gain in the gain unit 285 is set in five stages. The amplification amount of the five negative gains is set, for example, every 2 dB from 0 dB to −8 dB, and corresponds to the amplified signals B0 to B4, respectively.

  When the count signal is input from the volume counter 294 to the amplification amount determination unit 396, the amplification signals B0 to B4 to the gain unit 285 are output with priority over the amplification signal to the amplifier 275. The amplified signal output from the amplification amount determining unit 396 to the gain unit 285 is carried up to B4 sequentially from the amplified signal B0 every time the count signal is input. When the amplified signal B4 is output from the amplification amount determination unit 396 to the gain unit 285, when the count signal is input to the amplification amount determination unit 396, the amplification signal B0 is output to the gain unit 285 and the amplifier 275 The amplified signal output to is lowered by one step.

  The operation of the sound output control device 271 according to the second embodiment will be described with reference to FIG. FIG. 28 is a flowchart illustrating sound output processing according to the second embodiment. Since operations from step S1501 to step S1510 are the same as those in the first embodiment, the description thereof is omitted.

  In step S1521, processing differs depending on whether or not the amplification amount determination unit 396 sends an amplification signal with a digital gain of the lowest value to the gain unit 285. When the count signal is input from the volume counter 294, the amplification amount determination unit 396 determines whether or not the digital gain is the lowest value. That is, the amplification amount determination unit 396 confirms whether or not the amplification signal B4 is transmitted to the gain unit 285.

  When the amplification amount determination unit 396 is transmitting the amplified signal B4 to the gain unit 285 (YES in step S1521), the analog gain is reduced and the digital gain is set to zero. That is, the amplification amount determining unit 396 changes the amplified signal transmitted to the amplifier 275 from “5” to “4”, which is one step lower, and the amplified signal transmitted to the gain unit 285 from B4 to B0. change. As a result, the negative gain in the gain unit 285 becomes 0, and the analog gain by the amplifier 275 is reduced by one step. Thereafter, the process returns to step S1506.

  When the amplification amount determining unit 396 does not transmit the amplified signal B4 to the gain unit 285 (No in step S1521), that is, when the amplified signals B0 to B3 are transmitted to the gain unit 285, amplification to the gain unit 285 is performed. By increasing the signal by one step, the digital gain is decreased by one step. Thereby, the digital gain in the gain unit 285 is reduced by one step. For example, when the amplification amount determination unit 396 transmits the amplified signal B2 to the gain unit 285, when the count signal is input, the amplified signal B3 is transmitted to the gain unit 285. In this way, after the digital gain is lowered by one step, the process returns to step S1506.

  According to the control of the volume level in the second embodiment, the volume level is adjusted at the stage of digital sound data in addition to the change of the analog gain in the amplifier 275, so that the volume adjustment range can be made finer. Can be suppressed. This allows the player to concentrate on the game without noticing the change in volume level.

  Next, the pachinko machine 10 according to the third embodiment will be described with reference to FIG. FIG. 29 is a block diagram illustrating a configuration of a sound output control device according to the third embodiment. In FIG. 29, the portions denoted by the same reference numerals as those in the first embodiment or the second embodiment have the same configurations as those in the first or second embodiment, and thus the description thereof is omitted here. Further, the configuration of the pachinko machine 10 other than those described below is the same as that of the first or second embodiment.

  In the first and second embodiments, the amplification amount of the amplifier 275 is determined according to the set value of the volume switch 29, and the amplification amount is reduced when the maximum value of the sound data exceeds the threshold value. In the third embodiment, the amplification amount of the amplifier 275 ′ corresponding to the amplifier 275 is set to a fixed value, and the volume level amplification amount is controlled by digital gain adjustment. Further, as a feature of the third embodiment, the amount of amplification of the volume level can be adjusted in both the plus direction and the minus direction.

  The volume switch 29 in the third embodiment is located at the “f” switching position. In the case of the switching position “f”, the sound control CPU 512 automatically controls the volume level output from the speaker 25.

  The sound output control device 511 according to the third embodiment includes a sound control CPU 512, a sound output LSI 513, a sound data ROM 274, an amplifier 275 ', and a volume level detection unit 276'. The sound control CPU 512 is different from the sound control CPU 272 of the first embodiment in that an amplification amount determination unit 514 is provided instead of the amplification amount determination unit 282, and the other functions are the same.

  The amplification amount determination unit 514 according to the third embodiment outputs the amplified signal to the gain unit of the sound output LSI 513 in response to the count signal input from the volume counter 294 when the set value “f” is input from the volume switch 29. Output to 515. When the count signal is input from the counter 294, the amplification amount determination unit 514 instructs the gain unit 515 to decrease the volume level. When the count signal is not input from the counter 294, the amplification amount determination unit 514 instructs the gain unit 515 to increase the volume level. Do.

  The sound output LSI 513 of the third embodiment has a configuration in which the function of the gain unit 285 of the sound output LSI 393 of the second embodiment is changed. Sound data reproduced by the sound data processing unit 283 is input to the gain unit 515. The gain unit 515 amplifies the value (amplitude amount) of the input digital sound data in accordance with an instruction from the amplification amount determination unit 514. The correspondence between the amplification signal sent from the amplification amount determination unit 514 to the gain unit 285 and the amplification amount will be described with reference to FIG. In the third embodiment, amplification in the gain unit 515 is set to 21 stages. The 21 levels of amplification are set corresponding to the amplified signals C0 to C20 every 2 dB from 0 dB to 40 dB, for example.

  The amplifier 275 'according to the third embodiment is an analog amplifier similarly to the amplifier 275 according to the first embodiment, but may not be a programmable amplifier. That is, the amplification amount of the amplifier 275 'is fixed, for example, 50 dB.

  The volume level detection unit 276 ′ according to the third embodiment includes a peak hold unit 291, a reset unit 293, a comparison unit 292 ′, and a volume counter 294. The volume level detection unit 276 'is different in that a function is newly added to the comparison unit 292 in the volume level detection unit 276 of the first embodiment, and other functions are the same.

  Similar to the comparison unit 292 of the first embodiment, the comparison unit 292 ′ outputs a voltage signal of 0 V to the volume counter 294 ′ as a determination signal when the input value from the peak hold unit 291 is larger than the set threshold value. If the input value from the peak hold unit 291 is equal to or greater than the set threshold value, a positive voltage signal is output to the amplification amount determination unit 514 of the sound control CPU 512 as a gain determination signal.

  When the count signal is input from the volume counter 294, the amplification amount determination unit 514 decrements the amplification signal output to the gain unit 515 by one and outputs the decremented amplification signal to the gain unit 515. Further, the gain value of the lowered amplified signal is set as the maximum gain value, and the lowered amplified signal is stored.

  In addition, when the gain determination signal is input, the amplification amount determination unit 514 determines whether or not the gain value of the amplified signal output to the gain unit 515 is the maximum gain value. If the gain value of the amplified signal output to the gain unit 515 is the set gain maximum value, the amplified signal output to the gain unit 515 is maintained. If the gain value of the amplified signal output to gain unit 515 is not the maximum gain value, the amplified signal output to gain unit 515 is incremented by one, and the amplified signal raised is output to gain unit 515.

  The operation of the sound output control device 511 in the third embodiment will be described with reference to FIG. FIG. 31 is a flowchart illustrating sound output processing according to the third embodiment. Since the operations of Step S1501, Step S1503 to Step S1506, Step S1508, and Step S1509 are the same as those in the first embodiment, description thereof will be omitted.

  In step S1502 ', the amplification amount determination unit 514 reads the setting value of the volume switch 29 and outputs an amplification signal corresponding to the setting value of the volume switch 29 to the gain unit 515. In the third embodiment, since the setting value of the volume switch 29 is “f”, the amplification amount determination unit 514 that has read this setting value outputs a predetermined amplification signal to the gain unit 515 as an initial amplification signal. . For example, the amplified signal C10 is output as an initial amplified signal. When the initial amplification amount is 50 dB of the amplifier 275 ', step S1502' may be omitted.

  In step S1507 ', the comparison unit 292' compares the held maximum value with a predetermined threshold value. When the held maximum value is equal to or smaller than a predetermined threshold value (No in step S1507 '), a gain determination signal is output to the amplification amount determination unit 514. If the retained maximum value is larger than a predetermined threshold value (Yes in step S1507 '), a determination signal is output to the volume counter 294 and the sound control CPU 272. Thereafter, step S1508 and step S1509 are performed as in the first embodiment, and the process proceeds to step S1530.

  In step S1530, as in step S1510 of the first embodiment, the process changes depending on whether or not the counter value of the volume counter 294 reaches a predetermined number of times. In the third embodiment, as in the first embodiment, when the determination signal is input to the volume counter 294 three times, the count signal is output from the volume counter 294 to the amplification amount determination unit 282 (Yes in step S1530). If the predetermined number of times is not reached even when the determination signal is input, the process returns to step S1506 (No in step S1530).

  In step S1531, when the counter value of the volume counter 294 reaches a predetermined number of times, the gain unit 515 performs gain reduction. That is, when the count signal is output from the volume counter 294 to the amplification amount determination unit 514, the amplification amount determination unit 514 lowers the amplification signal output to the gain unit 515 by one, and the reduced amplification signal is output to the gain unit. Output to 515. Thereby, the amount of amplification in the gain unit 515 is reduced.

  In step S1532, the lowered gain value is set to the maximum gain value. That is, the amplification amount determination unit 514 outputs the amplified signal lowered to the gain unit 515 and stores the amplified signal lowered as the maximum amplified signal. Thereafter, the process returns to step S1506.

  When the comparison unit 292 'determines that the retained maximum value is equal to or less than a predetermined threshold value, a gain determination signal is output from the comparison unit 292' to the amplification amount determination unit 514 (No in step S1507 '). In the next step 1533, it is determined whether or not the gain value in the gain unit 515 is the gain maximum value set by the amplification amount determination unit 514. That is, the amplification amount determination unit 514 determines whether or not the amplified signal output to the gain unit 515 is the maximum amplified signal stored.

  When the amplified signal output to the gain unit 515 is the stored maximum amplified signal (Yes in step S1533), the current gain value is maintained in step S1534. That is, the amplification amount determination unit 514 maintains the current amplified signal output to the gain unit 515. This is to prevent the sound volume level from exceeding the threshold value in step S1507 when the gain value is increased from the current level.

  When the amplified signal output to the gain unit 515 is not the stored maximum amplified signal (No in step S1533), the gain value is increased in step S1534. This is because the current gain value is not the maximum gain value, so there is room for raising the volume level. That is, the amplification amount determination unit 514 raises the current amplification signal output to the gain unit 515 by one.

  According to the control of the volume level in the third embodiment, not only the amplification amount can be reduced but also the amplification amount can be increased, so that the volume level can be automatically controlled to the maximum level. Thereby, in addition to the effect in Example 1, the volume level setting of the administrator of the pachinko machine 10 can be saved. Also, the player can comfortably listen to the sound with the automatically set volume level.

  Instead of outputting the gain determination signal from the comparison unit 292 ', the amplification amount determination unit 514 may periodically output the amplification signal output to the gain unit 515. That is, if the count signal is not input, the amplification amount determination unit 514 may periodically raise the amplification signal C0 to the amplification signal C20 in order from the current amplification signal if it is not the maximum amplification signal.

  When the volume switch 29 is located at any position from “0” to “5”, sound control may be performed by the configuration of the first or second embodiment. That is, an amplifier 275 that is a programmable amplifier may be adopted as the amplifier 275 ′, and the amplification amount may be switched corresponding to any position from “0” to “5” of the volume switch 29. Further, when the count signal is input to the amplification amount determination unit 514, negative gain adjustment may be performed on the amplifier 275 ′ or the gain unit 515 as in the first or second embodiment. That is, if the sound output control device is a combination of the first or second embodiment and the third embodiment, it can correspond to the set value of the volume switch 29 set by the administrator, or automatic volume setting can be performed. .

  Next, the pachinko machine 10 according to the fourth embodiment will be described with reference to FIG. FIG. 32 is a block diagram illustrating a configuration of the sound output control device 521 according to the fourth embodiment. In FIG. 32, since the part shown with the code | symbol same as the code | symbol shown in Example 1- Example 3 is the structure similar to Example 1- Example 3, description here is abbreviate | omitted. Moreover, the structure of the pachinko machine 10 other than those described below is the same as that of the first to third embodiments.

  The fourth embodiment is another configuration that realizes the automatic volume control of the third embodiment. That is, in the third embodiment, the amplification amount is adjusted based on the determination result of the comparison unit 292 ′. However, in the fourth embodiment, the amplification amount is adjusted according to the maximum value output from the peak hold unit 291. To do.

  The volume switch 29 in the fourth embodiment is located at the “f” switching position. In the case of the switching position “f”, the sound control CPU 512 automatically controls the volume level output from the speaker 25.

  The sound output control device 521 according to the fourth embodiment includes a sound control CPU 522, a sound output LSI 513, a sound data ROM 274, an amplifier 275 ′, and a volume level detection unit 526. The sound control CPU 522 is different from the sound control CPU 272 of the first embodiment in that it includes an amplification amount determination unit 524 instead of the amplification amount determination unit 282, and further includes an amplification amount calculation unit 525. The function is similar.

  The amplification amount calculation unit 525 calculates the difference between the maximum voltage value output from the peak hold unit 291 of the volume level detection unit 526 and a predetermined threshold value. The predetermined threshold is stored in the program ROM 281 by measuring in advance a preferable value as the maximum voltage value. The amplification amount calculation unit 525 further calculates an appropriate amplification amount based on the calculated difference, and subtracts the amplification amount at the amplifier 275 ′ from the calculated amplification amount to calculate the amplification amount at the gain unit 515. . In the fourth embodiment, the amount of amplification by the amplifier 275 'is 50 dB as in the third embodiment, but the value is not limited to this and may be other values. The amplification amount calculated by the amplification amount calculation unit 525 is output to the amplification amount determination unit 524.

  When the set value “f” is input from the volume switch 29, the amplification amount determination unit 524 outputs an amplification signal corresponding to the amplification amount input from the amplification amount calculation unit 525 to the gain unit 515. In the fourth embodiment, the amplified signals C0 to C20 (FIG. 30) of the third embodiment are used as a correspondence between the amplification amount and the amplified signal. However, the present invention is not limited to this, and an amplified signal that is more finely divided may be used. Amplified signals that are more roughly graded may be used.

  The volume level detection unit 526 according to the fourth embodiment includes a peak hold unit 291 and a reset unit 293. The peak hold unit 291 detects the maximum value of the analog sound signal output from the amplifier 275 ′ and outputs it to the amplification amount calculation unit 525 of the sound control CPU 522. Further, a reset signal is input from the sound control CPU 272 to the reset unit 293 at predetermined intervals based on the internal clock of the sound control CPU 272. The reset unit 293 erases the maximum value held in the peak hold unit 291 according to the reset signal.

  The operation of the sound output control device 521 according to the fourth embodiment will be described with reference to FIG. FIG. 33 is a flowchart illustrating sound output processing according to the fourth embodiment. Since operations from step S1501 to step S1506 are the same as those in the first and third embodiments, the description thereof is omitted.

  In step S1541, the amplification amount calculation unit 525 calculates the difference between the maximum value collected and held and a predetermined threshold value. This threshold value is set for each sound or melody to be reproduced, and a plurality of threshold values are stored. Further, in step S1542, the amplification amount calculation unit 525 calculates an amplification amount to be amplified by the gain unit 515 based on the difference between the maximum value and a predetermined threshold value. The calculated amplification amount is output to the amplification amount determination unit 524. The amplification amount determination unit 524 selects an amplification signal corresponding to the calculated amplification amount, and outputs the selected amplification signal to the gain unit 515. Thereafter, the process returns to step S1506.

  According to the control of the volume level in the fourth embodiment, not only the amount of amplification can be reduced but also the amount of amplification can be increased, so that the volume level can be automatically and appropriately controlled. Thereby, the administrator of the pachinko machine 10 can save labor for setting the volume level. Also, the player can comfortably listen to the sound with the automatically set volume level.

  The configuration of the fourth embodiment may include a microphone 60 that detects sounds around the pachinko machine 10 and adjust the volume level according to the surrounding sound environment. FIG. 34 is a block diagram illustrating a configuration of a sound output control device 531 in which a microphone 60 is added to the configuration of the fourth embodiment.

  The sound control CPU 532 further includes an ambient volume determination unit 535 in addition to the sound control CPU 522 of the fourth embodiment. The ambient sound volume determination unit 535 compares the ambient sound volume level input from the microphone 60 with two predetermined threshold values, and thereby determines the ambient sound environment in three stages of “quiet”, “normal”, and “noisy”. To determine. One threshold is defined as threshold A, and the other threshold is defined as threshold B. The threshold A is smaller than the threshold B. The threshold A is used for “static” or “normal” discrimination. The threshold value B is used to determine “normal” or “noisy”.

  When the detected surrounding sound volume level is smaller than the threshold value A, the surrounding sound volume determination unit 535 determines that the surrounding sound environment is “still”. As a result, the amplification amount determination unit 534 outputs an amplification signal corresponding to the amplification amount calculated by multiplying the amplification amount calculated by the amplification amount calculation unit 525 by an amplification coefficient having a value greater than 1 to the gain unit 515. Instead of multiplying the amplification coefficient, a predetermined amplification amount may be added to the amplification amount calculated by the amplification amount calculation unit 525. In other words, if it is determined that “static”, the amount of amplification is larger than usual, and a larger volume is output from the speaker 25.

  When the detected surrounding sound volume level is not less than the threshold value A and not more than the threshold value B, the surrounding sound volume determination unit 535 determines “normal”. Thereby, the amplification amount determination unit 534 outputs the amplification signal corresponding to the amplification amount calculated by the amplification amount calculation unit 525 to the gain unit 515.

  When the detected surrounding sound volume level is greater than the threshold value B, the surrounding sound volume determination unit 535 determines “noisy”. Thus, the amplification amount determination unit 534 outputs an amplification signal corresponding to the amplification amount calculated by multiplying the amplification amount calculated by the amplification amount calculation unit 525 by an amplification coefficient having a value greater than 0 and less than 1 to the gain unit 515. To do. Instead of multiplying the amplification coefficient, a predetermined amplification amount may be subtracted from the amplification amount calculated by the amplification amount calculation unit 525. That is, when it is determined that the noise is “noisy”, the amount of amplification is smaller than usual, and a smaller volume is output from the speaker 25.

  When the ambient sound environment is “quiet”, a louder sound than usual flows from the speaker 25, so that the player can enjoy a loud sound. In particular, when a big hit, a melody with a volume larger than usual flows, so even if the number of players playing around is small, it is possible to attract the attention of other players, and the player's interest is improved. Further, when the surrounding sound environment is “normal”, a sound and a melody having a normal volume are played.

  When the surrounding sound environment is “noisy”, the volume output from each pachinko machine 10 is reduced even when the hall is crowded with players, so the total volume output from each pachinko machine 10, that is, , The volume of the whole hall is reduced. Thereby, it can reduce that each player hears the sound of the excessive sound volume as the total amount from each pachinko machine 10.

  It should be noted that the ambient sound environment determined by the ambient sound volume determination unit 535 is not limited to three levels, but may be two levels of “static” and “normal”, “normal” and “noisy”, or “still” and “noisy”. Alternatively, it may be determined that there are more stages than three stages. The amplification coefficient may be adjusted according to the stage of each sound environment.

  Next, a pachinko machine 10 according to a fifth embodiment will be described with reference to FIG. FIG. 35 is a block diagram illustrating a configuration of a sound output control device 541 according to the fifth embodiment. 35, since the part shown with the code | symbol same as the code | symbol shown in Examples 1-4 is the structure similar to Examples 1-4, description here is abbreviate | omitted. Moreover, the structure of the pachinko machine 10 other than those described below is the same as in the first to fourth embodiments.

  The sound volume level detection unit 276 in the first to third embodiments includes one comparison unit 292. In the fifth embodiment, the sound volume level detection unit 546 includes two comparison units 292 ′ and 547. Since the two comparison units 292 'and 547 are provided, the volume level can be determined using two threshold values.

  The sound output control device 541 according to the fifth embodiment includes a sound control CPU 542, a sound output LSI 513, a sound data ROM 274, an amplifier 275 ', and a volume level detection unit 546. The sound output control device 541 according to the fifth embodiment has a configuration in which a comparison unit 547 is added to the sound output control device 511 according to the third embodiment.

  The sound control CPU 542 is different from the sound control CPU 272 of the third embodiment in that an amplification amount determination unit 544 is provided instead of the amplification amount determination unit 282, and other functions are the same. In addition to controlling the output of the amplified signal by inputting the count signal, the amplification amount determining unit 544 instructs the gain unit 515 to reduce the amplification amount when the comparison determination signal is input from the second comparison unit 547. To do. That is, the level of the amplified signal output to the gain unit 515 is lowered.

  The volume level detection unit 546 is configured by adding a second comparison unit 547 to the volume level detection unit 276 in the third embodiment.

  The first threshold value that is compared with the maximum value of the sound signal in the first comparison unit 292 ′ is the upper limit value of the volume level at which no sound cracking occurs, and is the same as the threshold value of the comparison unit 292 in the first to third embodiments. In the fifth embodiment, the first threshold value is used as the upper limit value of the volume level in a normal state where no event such as a big hit has occurred.

  The second threshold value that is compared with the maximum value of the sound signal in the other second comparison unit 547 is an upper limit value of a volume level that does not damage the speaker 25, and is a value that is larger than the first threshold value. Therefore, sound cracking occurs slightly at the second threshold value. The second threshold value is used as the upper limit value of the volume level when an event such as a jackpot occurs.

  The operation of the sound output control device 541 in the fifth embodiment will be described with reference to FIG. FIG. 36 is a flowchart illustrating sound output processing according to the fifth embodiment. Since the operations from step S1501 to step S1506 are the same as those in the third embodiment, description thereof will be omitted.

  In step S1551, the retained maximum value is compared with the second threshold value. That is, the second comparison unit 547 compares the retained maximum value with the second threshold value, and if the retained maximum value is greater than the second threshold value (Yes in step S1551), the comparison determination signal is transmitted to the sound control CPU 272. Output to. In step S1552, when the comparison determination signal is input to the amplification amount determination unit 544, the amplification amount of the sound signal is reduced. For example, the amplified signal may be lowered by one step, or two or more steps. Thereafter, the process returns to step S1506. In step S1553 in parallel with step S1552, when the comparison determination signal is input from the second comparison unit 547 to the sound control CPU 542, the sound control CPU 542 resets to delete the maximum value held in the peak hold unit 291. A reset signal is output to the unit 292.

  Returning to step S1551, if the retained maximum value is equal to or smaller than the second threshold value (No in step S1551), the retained maximum value is compared with the first threshold value in step S1554. That is, the first comparison unit 292 ′ compares the maximum value held with the first threshold value. The process of step S1554 is the same as the process of step S1507 'of the third embodiment, and steps S1508 to S1510 are also the same as those of the first to third embodiments, and thus description thereof is omitted here.

  In step S1555, different volume control is performed depending on whether or not an event such as a jackpot has occurred. That is, when an event such as a big hit has occurred (Yes in step S1555), the amplification amount determining unit 544 returns to step S1506 without performing the amplification amount reduction process. If an event such as a big hit has not occurred (No in step S1555), an amplification amount reduction process is performed in step S1556 as in step S1531 of the third embodiment. The event to be discriminated here may be only a jackpot, a super reach may be added, or other events may be targeted.

  As a result, sound cracking to the extent that the player is not harsh can be generated, and sound cracking can be used as an effect of the sound output from the speaker 25. For example, since a loud sound is output from the speaker 25 to such an extent that sound cracking occurs at the time of a big hit, the interest of the player is improved. In spite of the output of a loud sound that causes sound cracking, the second threshold value prevents an excessive sound volume from being output, thereby preventing the speaker 25 from being damaged. be able to. Further, the present invention is not limited to the jackpot event, and may be configured such that sound cracking occurs when a reach or super reach event occurs. As a result, the player's sense of expectation increases, and the game can be played more happily.

  Further, a first threshold value may be prepared for each type of image to be displayed, that is, for each type of sound signal. Since the maximum value of the volume changes according to the displayed image, it is possible to clearly recognize the change in the sound heard from the speaker 25. Thereby, the interest property of a player improves. Further, the amplification amount determination unit 544 may perform control in which the amount of reduction in the amplification amount based on the determination result of the first comparison unit 292 'is smaller than the amount of reduction in the amplification amount based on the determination result of the second comparison unit 547. Since the reduction amount based on the comparison result of the second threshold value having a larger value is larger than the reduction amount based on the comparison result of the first threshold value having a small value, the breakage of the speaker 25 can be avoided promptly.

The present invention is not limited to the above embodiment, and can be modified as follows.
FIG. 37 is a diagram illustrating a sound output control apparatus in which the second embodiment is modified. The sound output control device 391 ′ according to the modification includes a determination unit 276 that determines whether or not the magnitude of the digital sound signal output from the sound data processing unit 283 is appropriate to the sound output control device 391 according to the second embodiment. .

  In the process in which the sound data stored in the sound data ROM 274 is read and reproduced by the sound data processing unit 283, noise is mixed in the data portion of the volume information of the sound signal, and the volume data has an excessively large value. May have. The determination unit 276 receives the sound signal output from the sound data processing unit 283, determines that it is abnormal when it has volume data equal to or greater than a predetermined threshold value, and sends the abnormality determination signal to the amplification amount determination unit 396 ′. Output. When the volume data of the input sound signal is less than a predetermined threshold value, it is determined as normal and no signal is output from the determination unit 276.

  The sound control CPU 392 ′ is configured to include an amplification amount determination unit 396 ′ instead of the amplification amount determination unit 396 in the sound control CPU 392 of the second embodiment. The amplification amount determination unit 396 ′ further has the following function as the amplification amount determination unit 396 in the second embodiment. When the abnormality determination signal is input from the determination unit 276, the amplification amount determination unit 396 'issues a second sound volume reduction instruction to lower the sound volume level to the gain unit 285'.

  The sound output LSI 393 'is configured to include a gain unit 285' instead of the gain unit 285 in the sound output LSI 393 of the second embodiment. The gain unit 285 'further has the following functions in addition to the gain unit 285 in the second embodiment. When the second sound volume reduction instruction is input from the amplification amount determination unit 396 ′, the gain unit 285 ′ selects a predetermined negative gain amplification amount for a certain period of time.

  As a result, when noise or the like is mixed into the volume data and the data value of the volume data is abnormal, a determination signal is output to the amplification amount determination unit 396 ′, and the amplification amount determination unit 396 ′ instructs the gain unit 285 ′ to indicate a negative gain. Can be controlled so that an excessive volume is not generated when the sound signal is a digital signal.

  Conventionally, even if the volume level of the sound data stored in the sound data ROM 274 is appropriate, there is a case where a beeping sound is abruptly generated due to noise mixing. By determining the volume level of the digital sound data by the determination unit 276, the volume level of the sound data can be controlled before amplification of the volume of the sound signal. In addition, noise mixing often occurs accidentally, and the negative gain is performed for a certain time, so that the volume can be limited only when noise is mixed. Thereby, the player can comfortably listen to the melody without excessively reducing the volume. It should be noted that even when noise contamination is constantly occurring, the determination unit 276 continues to determine abnormality of the volume data, so that the volume limit can be maintained. The determination unit 276 may be provided in other embodiments.

<About the invention group extracted from each of the above embodiments>
Hereinafter, the characteristics of the invention group extracted from each of the above-described embodiments will be described while showing effects and the like as necessary. In the following, for easy understanding, the corresponding configuration in each of the above embodiments is shown in parentheses, but is not limited to the specific configuration shown in parentheses.

<Feature A group>
Feature A1. In gaming machines that output sound,
An amplifier for amplifying the sound signal;
A sound control unit for controlling the amplification amount of the amplifier;
A holding unit for holding the maximum value of the amplified sound signal,
The gaming machine, wherein the sound control unit controls the amplification amount based on the held maximum value and a predetermined threshold value.

  According to the feature A1, since the amplification amount is controlled based on the maximum value of the amplified sound signal and a predetermined threshold value, the player can hear the sound by comfortable amplification.

  Feature A2. A comparison unit that compares the held maximum value with a predetermined threshold value, and the sound control unit reduces the amplification amount based on a determination result by the comparison unit that the maximum value is greater than the threshold value. The gaming machine according to Feature A1, wherein:

  According to the feature A2, the maximum value of the amplified sound signal is compared with a predetermined threshold value, and when a sound signal exceeding the threshold value is detected, feedback control is performed to reduce the amplification amount of the sound signal. This eliminates the need for the player to hear annoying sounds due to excessive amplification.

  Feature A3. The gaming machine according to Feature A2, further comprising a reset unit that erases the maximum value, wherein the maximum value is erased based on a determination result by the comparison unit that the maximum value is greater than the threshold value.

  According to the feature A3, when the comparison unit determines that the maximum value of the sound signal is larger than the threshold value, the reset unit deletes the maximum value. Accordingly, the peak hold unit newly holds the maximum value of the sound signal, so that the maximum value larger than the threshold value can be detected again.

  Feature A4. The gaming machine according to Feature A2, further comprising a reset unit that erases the maximum value, wherein the maximum value is erased at predetermined intervals.

  According to the feature A4, since the maximum value of the held sound signal is periodically deleted, the peak hold unit can newly hold the maximum value of the sound signal and detect the maximum value equal to or higher than the threshold value again. be able to.

Feature A5. A counting unit that counts the number of times the maximum value by the comparison unit is greater than the threshold;
Any one of features A2 to A4, wherein the sound control unit reduces the amount of amplification when the number of determinations counted by the counting unit reaches a predetermined number of times within a predetermined period. The gaming machine described in one.

  According to the feature A5, the number of times that the maximum value of the sound signal is determined to be greater than or equal to the threshold value by the comparison unit is counted, and the sound control is triggered by the predetermined number of times being counted within a predetermined period. By reducing the amount of amplification by the unit, it is possible to prevent the sound signal from being reduced when the maximum value of the sound signal accidentally exceeds a threshold, such as noise mixing.

Feature A6. A storage unit storing sound data; and
A gaming machine according to any one of features A2 to A5, further comprising: a sound reproducing unit that reproduces the sound signal based on the sound data.

  According to the feature A6, the sound reproduction unit reproduces the sound signal based on the sound data stored in the storage unit. According to the above-described invention, the reproduced sound signal can be appropriately amplified even if the recording level of the sound data stored in the storage unit varies.

  Feature A7. The gaming machine according to any one of features A2 to A6, further comprising a speaker that outputs the amplified sound signal.

  According to the feature A7, the amplified sound signal is output from the speaker. According to the present invention, since the sound signal input to the speaker is a sound signal in which excessive amplification is suppressed, breakage of the speaker can be prevented and deterioration over time can be reduced.

  Feature A8. The gaming machine according to any one of features A2 to A7, further comprising a volume setting unit that sets the amplification amount.

  According to the feature A8, the gaming machine administrator can set a desired volume level by the volume setting unit. When the player does not control the amplification amount by the sound control unit, the player can enjoy the sound comfortably by the amplification amount set by the volume setting unit.

  Feature A9. The gaming machine according to any one of features A2 to A8, wherein the amplifier is a digital amplifier that amplifies a digital sound signal and an analog amplifier that amplifies an analog sound signal.

  According to the feature A9, the sound signal can be amplified in two stages, that is, a digital signal stage and an analog signal stage. Thereby, the adjustment of the amplification amount of the sound signal can be finely adjusted.

  The inventions of the features A2 to A9 are effective for the following problems.

  In the conventional gaming machine, the sound data stored in the memory is individually created and stored. As a result, the sound volume reference level of each sound data stored in the memory varies. Depending on the sound data, the sound output level may become excessive even with the same amplification amount. If the sound output is excessive, the edge 25b is damaged by the vibration of the cone paper 25a, and the sound cannot be output from the speaker 25.

  Further, as the volume increases, the output voltage level to the speaker 25 increases, and when the limit value of the speaker 25 is exceeded, sound cracking occurs and clear sound quality is lost. Thereby, the player cannot hear a clear melody.

Feature A10. A difference between the retained maximum value and a predetermined threshold value, and an amplification amount calculation unit that calculates an amplification amount based on the difference, and
The game machine according to Feature A1, wherein the sound control unit controls the amplification amount based on the amplification amount calculated by the amplification amount calculation unit.

  According to the feature A10, how much the maximum value of the amplified sound signal is different from a predetermined threshold value is calculated, and the amplification amount is calculated based on the difference. Thereby, the amplification amount is appropriately adjusted with reference to the maximum value of the amplified sound signal, so that the player can comfortably hear the sound. In addition, since the gaming machine automatically adjusts the volume, the burden on the gaming machine administrator is reduced.

  Feature A11. The game machine according to Feature A10, wherein the sound control unit further controls the amplification amount according to a type of the sound signal.

  According to the feature A11, the sound control unit can adjust the amount of amplification according to the type of the sound signal in addition to the difference between the maximum value of the sound signal and the threshold value. You can listen to the sound comfortably.

Feature A12. A microphone for detecting the sound of the ambient environment of the gaming machine;
The game machine according to Feature B1 or B2, wherein the sound control unit further controls the amplification amount according to a volume level of an ambient environment detected by the microphone.

  According to the feature A12, since the sound control unit can further adjust the amount of amplification according to the volume level of the surrounding environment, the player can listen to the sound comfortably according to the sound condition of the surrounding environment. .

  Feature A13. The sound control unit increases the amplification amount calculated by the amplification amount calculation unit, based on a determination result in which the volume level of the surrounding environment detected by the microphone is smaller than a predetermined threshold value. A gaming machine according to Feature B3.

  According to the feature A13, when the surrounding environment is quiet, the sound can be made more conspicuous by increasing the amplification amount. Thereby, since the surrounding attention can be received more, the interest property of a player can be improved more.

  Feature A14. The sound control unit reduces the amplification amount calculated by the amplification amount calculation unit, based on a determination result in which the volume level of the surrounding environment detected by the microphone is greater than a predetermined threshold value. A gaming machine according to Feature B3.

  According to the feature A14, when the surrounding environment is noisy, the volume of each gaming machine can be suppressed by suppressing the amplification amount. As a result, the overall sound volume of the hall can be suppressed, and ear fatigue due to the player staying in the hall can be suppressed.

  The inventions of the features A10 to A14 are effective for the following problems.

  In the conventional gaming machine, the sound data stored in the memory is individually created and stored. As a result, the sound volume reference level of each sound data stored in the memory varies. Depending on the sound data, the sound output level may become excessive even with the same amplification amount. If the sound output is excessive, the edge 25b is damaged by the vibration of the cone paper 25a, and the sound cannot be output from the speaker 25.

  It is difficult for an administrator of a gaming machine to know for each gaming machine how much the volume output from the speaker is excessive. Moreover, it takes a lot of labor for the administrator to set the volume of many gaming machines.

<Feature B group>
Feature B1. In gaming machines that output sound,
An amplifier for amplifying the sound signal;
A sound control unit for controlling the amplification amount of the amplifier;
A holding unit for periodically holding the maximum value of the amplified sound signal;
A first comparison unit that compares the held maximum value with a predetermined first threshold;
A second comparison unit that compares a predetermined second threshold value greater than the first threshold value with the maximum value;
The gaming machine according to claim 1, wherein the sound control unit reduces the amplification amount based on a determination result by the first comparison unit and the second comparison unit.

  According to the feature B1, more accurate volume control can be performed by limiting the volume to two stages. That is, by using two threshold values, for example, it is possible to carry out two-stage control of preventing an excessive load from being applied to the speaker and preventing the occurrence of sound cracking. Further, since minute sound cracking that does not apply an excessive load to the speaker can be generated, it is possible to produce a dramatic effect.

  Feature B2. The game machine according to Feature B1, wherein the sound control unit controls the amplification amount according to a type of the sound signal and a determination result of the first comparison unit or the second comparison unit.

  According to the feature B2, the amount of amplification can be controlled according to the type of sound signal. Thereby, it is possible to control whether or not sound cracking is generated according to the effect. For example, sound cracks can be generated only at the time of a big hit, and an uplifting feeling can be generated for the player.

  Feature B3. In the feature B1 or B2, the sound control unit is characterized in that the reduction amount of the amplification amount based on the discrimination result of the first comparison unit is smaller than the reduction amount of the amplification amount based on the discrimination result of the second comparison unit. The gaming machine described.

  According to the feature B3, since the reduction amount based on the comparison result of the larger threshold value is larger than the reduction amount based on the comparison result of the small threshold value, damage to the speaker or the like can be avoided immediately.

  The invention of the above-mentioned feature B group is effective for the following problems.

  In the conventional gaming machine, the sound data stored in the memory is individually created and stored. As a result, the sound volume reference level of each sound data stored in the memory varies. Depending on the sound data, the sound output level may become excessive even with the same amplification amount. If the sound output is excessive, the edge 25b is damaged by the vibration of the cone paper 25a, and the sound cannot be output from the speaker 25.

  However, a slight effect of sound cracking is a dramatic effect, which may be preferred by game machine managers and players. Therefore, it is desirable to generate sound cracking while avoiding damage to the speaker.

  It should be noted that regarding the various inventions disclosed in this specification, various combinations can be made for all the constituent elements, and the invention can be established independently without any other constituent requirements.

  As described above, the present invention is suitable for gaming machines such as pachinko machines.

10 ... Pachinko machine (game machine)
542 ... Sound control CPU (sound control unit)
275 '… Amplifier (amplifier)
291 ... Peak hold section (holding section)
292 '... 1st comparison part 547 ... 2nd comparison part

Claims (1)

In gaming machines that output sound,
An amplifier for amplifying the sound signal;
A sound control unit for controlling the amplification amount of the amplifier;
A holding unit for periodically holding the maximum value of the amplified sound signal;
A first comparison unit that compares the sampled maximum value with a predetermined first threshold;
A second comparison unit that compares a predetermined second threshold value greater than the first threshold value with the maximum value;
The gaming machine according to claim 1, wherein the sound control unit reduces the amplification amount based on a determination result by the first comparison unit and the second comparison unit.

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