JP2014063842A - Method for manufacturing optical waveguide type semiconductor element, and optical waveguide type semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an optical waveguide type semiconductor element in which the number of disconnections in a metal wiring layer arranged from the top surface of a mesa structure to the outside of the mesa structure can be reduced, and also to provide the optical waveguide type semiconductor element.SOLUTION: By forming an etching mask M1 extending in the optical waveguide direction on a semiconductor lamination part and then by etching the semiconductor lamination part, a mesa structure 25 is formed which has an end surface 25 g including a layer structure of a light receiving element part 6 and a layer structure of an optical waveguide part 5. At this time, the mesa structure 25 is formed so that an angle θ formed by the end surface 25 g and [110]direction of an InP substrate 21 satisfies 0°<θ<90°. After that a semiconductor embedding area which covers the end surface of mesa structure 25 and the side surface of mesa structure 25 is developed.

Description

  The present invention relates to an optical waveguide semiconductor device manufacturing method and an optical waveguide semiconductor device.

  Patent Document 1 describes a semiconductor light receiving device. The semiconductor light-receiving device includes a substrate having a main surface, a light detection unit formed on a partial region of the main surface, and an optical waveguide formed in front of the light detection unit. The semiconductor light receiving device further includes a first semiconductor member formed behind the light detection unit and having the same stacked structure as the optical waveguide, and an insulating or high resistance second semiconductor covering the side surface of the light detection unit. A member, an electrode disposed on the light detection unit, a pad formed further rearward than the first semiconductor member, and a wiring connecting the electrode and the pad are provided.

JP 2001-127333 A

  An optical waveguide type semiconductor element has a structure in which an optical waveguide part including a core layer for confining light and an optical semiconductor element part such as a light receiving element part coupled to the optical waveguide part are monolithically formed on a common semiconductor substrate It has. In such an element, a mesa structure including the semiconductor layer structure of the optical waveguide portion and the semiconductor layer structure of the optical semiconductor element portion is provided on the semiconductor substrate. Furthermore, a metal electrode film is provided on the semiconductor layer structure of the optical semiconductor element portion, and this metal electrode film is connected to a pad electrode provided around the mesa structure via a wiring pattern. And when connecting a metal electrode film and a pad electrode through a wiring pattern, depending on the position of a pad electrode, a wiring pattern may be extended beyond the end surface of the longitudinal direction of a mesa structure (for example, refer patent document 1). ).

  17 and 18 are views showing a part of the manufacturing process of the optical waveguide type semiconductor device. FIG. 17A is a plan view showing a manufacturing process (embedded region forming process) of the optical waveguide type semiconductor device, and FIG. 17B is a side along the line XVII-XVII in FIG. It is sectional drawing. FIG. 18A is a plan view showing a manufacturing process (wiring forming process) of the optical waveguide type semiconductor device, and FIG. 18B is a side along the line XVIII-XVIII in FIG. It is sectional drawing.

  As shown in FIG. 17, the optical waveguide semiconductor device 100 includes an InP substrate 101. The InP substrate 101 has a main surface 101 a along the (100) plane of the InP substrate 101. The optical waveguide semiconductor device 100 further includes a mesa structure 130 formed on the main surface 101 a of the InP substrate 101. The mesa structure 130 extends along a predetermined optical waveguide direction, and has both side surfaces 130a along the predetermined optical waveguide direction and end surfaces 130b in the predetermined optical waveguide direction. Note that since FIG. 17 shows the manufacturing process, the etching mask 150 remains on the mesa structure 130.

  The mesa structure 130 includes an n-type buffer layer 131 provided on the main surface 101a, a core layer 111 and a cladding layer 112 for the optical waveguide unit 110 provided on the n-type buffer layer 131, and an n-type buffer layer. A light absorption layer 121, a hetero barrier relaxation layer 122, a p-type cladding layer 123, a p-type hetero barrier relaxation layer 124, and a p-type contact layer 125 for the light receiving element portion 120 provided on 131 are provided. The core layer 111 for the optical waveguide portion 110 and the light absorption layer 121 for the light receiving element portion 120 are in contact with each other and optically coupled. A semiconductor region 140 having the same semiconductor layer structure as that of the optical waveguide portion 110 is formed on the end surface of the light receiving element portion 120 opposite to the end surface in contact with the optical waveguide portion 110.

  In the step shown in FIG. 17, the semiconductor buried region 160 is formed so as to cover the both side surfaces 130 a and the end surface 130 b of the mesa structure 130. This semiconductor buried region 160 is made of semi-insulating InP, and selectively grows in a region on the main surface 101 a except on the etching mask 150.

  After forming the semiconductor buried region 160, the etching mask 150 is removed. Then, as shown in FIG. 18, after covering the upper surface of the mesa structure 130 and the surface of the semiconductor buried region 160 with the insulating film 162, an opening is formed in the insulating film 162 on the light receiving element portion 120 to form an ohmic electrode layer. 164 is formed in the opening. Thereafter, a metal wiring layer 166 extending from the ohmic electrode layer 164 to the outside of the mesa structure 130 is formed, and a pad electrode 168 is formed on the metal wiring layer 166 outside the mesa structure 130.

  In the manufacturing method shown in FIGS. 17 and 18, the longitudinal direction of the mesa structure 130 may be the [110] direction of the InP substrate. However, in such a case, the following problems arise. FIG. 19A is a cross-sectional view schematically showing the growth process of the semiconductor buried region 160 that grows on the end face 130 b of the mesa structure 130. FIG. 19B is a sectional view schematically showing the growth process of the semiconductor buried region 160 in the vicinity of the side surface 130a of the mesa structure 130 for comparison.

  When the longitudinal direction of the mesa structure 130 is along the [110] direction of the InP substrate 101, the (111) A plane of the InP crystal is located at the position shown in FIG. 19A near the end face 130b of the mesa structure 130. Will exist. The growth rate of InP in the normal direction of the (111) A plane is faster than the growth rate in other directions. Accordingly, as shown in FIG. 19A, the surface of the semiconductor buried region 160 grows like A11, A12, and A13 and protrudes so as to cover the upper surface of the mesa structure 130. The semiconductor buried region 160 requires about 0.3 μm in terms of the growth thickness on the main surface 101a from the viewpoint of ensuring reliability. In this case, the protruding portion of the semiconductor buried region 160 (in FIG. The height of part B) can be as high as 0.6 μm to 0.9 μm. In the vicinity of the end face 130b of the mesa structure 130, as shown in FIG. 19B, the surface of the semiconductor buried region 160 grows in the order of A21, A22, and A23, and exceeds the upper surface of the mesa structure 130. Absent.

  Thus, when the semiconductor buried region 160 protrudes so as to cover the upper surface of the mesa structure 130, the metal wiring layer 166 covers the protruding portion B of the semiconductor buried region 160 as shown in FIG. It will be arranged beyond. Therefore, the metal wiring layer 166 is easily disconnected in the vicinity of the protruding portion B of the semiconductor buried region 160, and the reliability of the optical waveguide semiconductor device is lowered.

  The present invention has been made in view of such problems, and manufacture of an optical waveguide semiconductor device capable of reducing disconnection of a metal wiring layer disposed from the upper surface of the mesa structure to the outside of the mesa structure. It is an object to provide a method and an optical waveguide type semiconductor device.

  In order to solve the above-described problems, an optical waveguide semiconductor device manufacturing method according to the present invention includes a common optical waveguide portion including a core layer that confines light, and an optical semiconductor element portion coupled to the optical waveguide portion. A method of manufacturing an optical waveguide type semiconductor device having an InP substrate, wherein the second of the first, second, and third regions arranged in order in the optical waveguide direction of the optical waveguide portion on the main surface of the InP substrate. A first semiconductor laminated portion having a layer structure for the optical semiconductor element portion is formed on the region, and a second semiconductor laminated portion having a layer structure for the optical waveguide portion on the first and third regions. And forming an etching mask extending from the first region to the third region on the first and second semiconductor stacked portions, and forming the etching mask on the first and second semiconductor stacked portions. First and second semiconductors using Etching the layer portion to form a mesa structure including the layer structure of the optical semiconductor element portion and the layer structure of the optical waveguide portion and having an end face on the third region, the end face of the mesa structure, and the second A buried layer forming step for growing a semiconductor buried region covering the side surface of the mesa structure extending from the first region to the third region, and from the optical semiconductor element portion of the mesa structure to the outside of the mesa structure through the end face. A wiring layer forming step of forming a metal wiring layer, wherein the optical waveguide direction is along the [110] direction of the InP substrate, and in the etching step, the end surface in the plane along the main surface and the [ 110] direction, the mesa structure is formed so that the angle θ satisfies 0 ° <θ <90 °.

  An optical waveguide semiconductor device according to the present invention includes an InP substrate having a main surface including first, second, and third regions arranged in order in a predetermined optical waveguide direction. A layer structure for an optical waveguide portion including a core layer for confining light is included on the first and third regions, and a layer structure for an optical semiconductor element portion coupled to the optical waveguide portion is provided on the second region. A mesa structure having an optical waveguide direction as a longitudinal direction on the main surface and having an end surface on the third region, an end surface of the mesa structure, and a mesa structure extending from the second region to the third region And a metal wiring layer extending from the mesa structure of the optical semiconductor element portion to the outside of the mesa structure, and the optical waveguide direction is along the [110] direction of the InP substrate. And [11] the end face in the plane along the main surface and the InP substrate. ] Angle theta is 0 ° formed by the direction <theta and satisfies the <90 °.

  In the optical waveguide semiconductor device manufacturing method and the optical waveguide semiconductor device described above, the angle θ between the end face of the mesa structure and the [110] direction of the InP substrate in the plane along the main surface of the InP substrate is 0. ° <θ <90 ° is satisfied. In other words, when viewed from the normal direction of the main surface of the InP substrate, the end surface of the mesa structure is inclined with respect to the (110) plane of the InP substrate. By inclining the end face of the mesa structure in this way, the position of the (111) A plane of the semiconductor buried region with respect to the end face of the mesa structure is changed, and the semiconductor buried region grows so as to cover the upper surface of the mesa structure. (See FIG. 19A) The phenomenon can be suppressed. Therefore, according to the method for manufacturing an optical waveguide semiconductor device and the optical waveguide semiconductor device described above, it is possible to reduce disconnection of the metal wiring layer disposed outside the mesa structure from the upper surface of the mesa structure to the end surface. it can.

Further, in the manufacturing method of the optical waveguide type semiconductor element, the angle θ is θ ≦ (1/2) · [arcsin {d2 / (n · d1) −1}] + 45 °.
The mesa structure may be formed so as to satisfy (where d1 is the growth thickness of the semiconductor buried region on the main surface, d2 is the thickness of the etching mask, and n is a constant not less than 2 and not more than 3). . Thereby, since the height of the protruding portion of the semiconductor buried region is lower than the height of the etching mask, disconnection of the metal wiring layer can be more effectively reduced.

  Further, in the method of manufacturing an optical waveguide semiconductor device, methyl chloride may be added when growing a semiconductor buried region in order to planarize the semiconductor buried region. Since methyl chloride promotes the growth of a semiconductor buried region covering the upper surface of the mesa structure, the above-described method for manufacturing an optical waveguide semiconductor device is useful in such a case.

  In addition, the optical waveguide semiconductor element has a plurality of mesa structures including a layer structure for the optical waveguide part and a layer structure for the optical semiconductor element part formed on the InP substrate. The metal wiring layers may be arranged side by side in a direction perpendicular to the optical waveguide direction, and the metal wiring layer may be provided extending in the optical waveguide direction. With such a configuration, each electrode pad of the plurality of optical semiconductor element portions can be disposed along the edge of the optical waveguide semiconductor element. Therefore, bonding wires that electrically connect each electrode pad of the plurality of optical semiconductor element portions and the other electrode pads, along the edge of the optical waveguide type semiconductor element, in a direction perpendicular to the optical waveguide direction, It is possible to arrange them at approximately the same length and at a short distance. As a result, it is possible to avoid deterioration of frequency response characteristics due to a large lead inductance component and variations in frequency response characteristics between signals.

  According to the method for manufacturing an optical waveguide semiconductor device and the optical waveguide semiconductor device according to the present invention, it is possible to reduce the disconnection of the metal wiring layer disposed from the upper surface of the mesa structure to the outside of the mesa structure.

FIG. 1 is a plan view showing a configuration of a light receiving device including an optical waveguide semiconductor device according to the first embodiment of the present invention. 2A shows a cross section along the line IIa-IIa in FIG. 1, FIG. 2B shows a cross section along the line IIb-IIb in FIG. 1, and FIG. 2 shows a cross section taken along line IIc-IIc in FIG. 1, and FIG. 2D shows a cross section taken along line IId-IId in FIG. FIG. 3 is a cross-sectional view showing in detail the configuration of the semiconductor portion and its periphery, and shows a cross section taken along line III-III in FIG. FIG. 4 is a perspective view showing a semiconductor laminated portion forming step. FIG. 5 is a perspective view showing an etching process. FIG. 6 is a perspective view showing an etching process. FIG. 7 is a cross-sectional view showing a buried layer forming step. FIG. 8 is a cross-sectional view showing a buried layer forming step. FIG. 9A is a plan view showing the vicinity of the end face of the mesa structure after the growth of the semiconductor buried region. FIG. 9B is a cross-sectional view taken along line IXb-IXb shown in FIG. FIG. 10 is a graph showing the relationship between the angle θ formed between the end face of the mesa structure and the [110] direction and the growth height of the semiconductor buried region based on the top face of the mesa structure. FIG. 11A to FIG. 11C schematically show the cross-sectional shapes of the semiconductor buried region when the angle θ is 0 °, 45 °, and 90 °, respectively. FIG. 12 is a cross-sectional view showing the mask removing process. FIG. 13 is a cross-sectional view showing the element isolation step. FIG. 14 is a cross-sectional view showing a process of forming an insulating film and an ohmic electrode. FIG. 15 is a cross-sectional view showing the wiring layer forming step. FIG. 16 is a plan view showing a configuration of a multi-channel optical waveguide light-receiving device including an optical waveguide semiconductor element as a second embodiment of the present invention. FIG. 17 is a diagram showing a part of the manufacturing process of the optical waveguide type semiconductor device. FIG. 18 is a diagram showing a part of the manufacturing process of the optical waveguide type semiconductor device. FIG. 19A is a cross-sectional view schematically showing a growth process of a semiconductor buried region grown on the end face of the mesa structure. FIG. 19B is a sectional view schematically showing the growth process of the semiconductor buried region in the vicinity of the side surface of the mesa structure for comparison.

  Hereinafter, embodiments of a method for manufacturing an optical waveguide semiconductor device and an optical waveguide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
FIG. 1 is a plan view showing a configuration of a light receiving device 1A including an optical waveguide type semiconductor element according to the first embodiment of the present invention. 2A shows a cross section taken along line IIa-IIa in FIG. 1, and FIG. 2B shows a cross section taken along line IIb-IIb in FIG. ) Shows a cross section taken along the line IIc-IIc in FIG. 1, and FIG. 2D shows a cross section taken along the line IId-IId in FIG.

  As shown in FIG. 1, the light receiving device 1 </ b> A according to the present embodiment includes an optical waveguide semiconductor element 2, a signal amplifier 3, and a capacitor 4. The optical waveguide type semiconductor element 2 has a planar shape such as a substantially rectangular shape, and includes an optical waveguide part 5, a light receiving element part 6, metal wiring layers 7a and 7b, and electrode pads 8a and 8b formed on an InP substrate. It has. The optical waveguide portion 5 extends along a predetermined optical waveguide direction A. The optical waveguide portion 5 is preferably configured by a core made of a material having a relatively high refractive index (for example, InGaAsP) and a clad made of a material having a refractive index smaller than that of the core (for example, InP) and covering the core.

  The light receiving element portion 6 is an optical semiconductor element portion in the present embodiment. The light receiving element portion 6 has a configuration as a PIN photodiode, and is optically coupled to one end of the optical waveguide portion 5 in the optical waveguide direction A. A constant bias voltage is supplied to the cathode of the light receiving element section 6. The light receiving element unit 6 receives an optical signal through the optical waveguide unit 5 and generates an electric signal (photocurrent) corresponding to the light intensity of the optical signal. On the optical waveguide type semiconductor element 2, a signal output electrode pad 8 a electrically connected to the anode of the light receiving element portion 6 is provided. The signal output electrode pad 8 a is disposed between the edge 2 b of the optical waveguide semiconductor element 2 and the light receiving element portion 6. The signal output electrode pad 8a is electrically connected to a signal input electrode pad 3a of the signal amplifying unit 3 described later via a bonding wire 27a.

  The capacitor 4 is arranged side by side on the optical waveguide semiconductor element 2. The capacitor 4 is electrically connected between the cathode of the light receiving element portion 6 to which a bias voltage is supplied and a reference potential line (GND line). That is, one of the pair of electrodes constituting the capacitor 4 is connected to the cathode of the light receiving element portion 6 and the bias power supply, and the other is connected to the reference potential line (GND line). A bias voltage side electrode pad 8 b electrically connected to the cathode of the light receiving element portion 6 is provided on the optical waveguide type semiconductor element 2. One electrode of the capacitor 4 is electrically connected to the bias voltage side electrode pad 8b via the bonding wire 27b, and is electrically connected to the bias power source via the bonding wire 27c.

  The signal amplifying unit 3 is an amplifier (preamplifier) that amplifies the electric signal (photocurrent) output from the light receiving element unit 6. The signal amplifying unit 3 includes a signal input electrode pad 3a, and generates a single voltage signal by performing differential amplification of the electric signal input to the signal input electrode pad 3a. As described above, the signal input electrode pad 3a is electrically connected to the signal output electrode pad 8a through the bonding wire 27a.

  Here, the cross-sectional structure of the optical waveguide semiconductor device 2 will be described in detail with reference to FIGS. As shown in FIGS. 2A to 2D, the optical waveguide semiconductor device 2 of the present embodiment includes an InP substrate 21. The InP substrate 21 has a main surface 21a along (100) of the InP crystal. As shown in FIG. 2C, the main surface 21a includes a first region 21b, a second region 21c, and a third region 21d arranged in order along the optical waveguide direction A (see FIG. 1). Contains. In addition, the optical waveguide type semiconductor element 2 includes a mesa structure 25 whose longitudinal direction is the optical waveguide direction A (see FIG. 1). The optical waveguide direction A is along the [110] direction of the InP substrate 21. The mesa structure 25 includes a layer structure for the optical waveguide portion 5 on the region 21b and the region 21d, and includes a layer structure for the light receiving element portion 6 on the region 21c. The mesa structure 25 has an end face 25g (see FIG. 2C) in the optical waveguide direction A on the region 21d.

With reference to FIG. 2B and FIG. 2C, a cross-sectional structure of the optical waveguide portion 5 will be described. The optical waveguide unit 5 includes a buffer layer 22 provided on the region 21 b of the InP substrate 21, an optical waveguide core layer 23 provided on the buffer layer 22, and a cladding layer 24 provided on the optical waveguide core layer 23. It is comprised including. The InP substrate 21 is made of semi-insulating InP, and the buffer layer 22 is made of n-type InP. The optical waveguide core layer 23 is made of a material (for example, InGaAsP) having a refractive index larger than that of the buffer layer 22 and capable of lattice matching with the buffer layer 22, and confines light propagating through the optical waveguide unit 5. In one example, the band gap wavelength of InGaAsP in the optical waveguide core layer 23 is 1.05 μm. The cladding layer 24 is made of a material (for example, undoped InP) having a refractive index smaller than that of the optical waveguide core layer 23 and capable of lattice matching with the optical waveguide core layer 23. A part of the buffer layer 22, the optical waveguide core layer 23, and the cladding layer 24 are included in a mesa structure 25 extending in a predetermined optical waveguide direction. With this mesa structure 25, an optical signal can propagate in the optical waveguide core layer 23 in the optical waveguide unit 5. Note that the pair of side surfaces 25 a and 25 b and the upper surface 25 c of the mesa structure 25 in the optical waveguide portion 5 are protected by being covered with the insulating film 26. The insulating film 26 is made of, for example, an insulating silicon compound (SiN, SiON, or SiO ₂ ).

  Next, a cross-sectional structure of the light receiving element portion 6 will be described with reference to FIGS. 2 (a) and 2 (c). The light receiving element portion 6 includes an n-type buffer layer 22, a light absorption layer 34, an i-type or p-type hetero barrier relaxation layer 35, a p-type cladding layer 36, and a p-layer, which are sequentially stacked on the main surface 21 a of the InP substrate 21. A type hetero barrier relaxation layer 37 and a p type contact layer 38 are provided. The n-type buffer layer 22 is a layer common to the optical waveguide unit 5 described above. The light absorption layer 34 is made of undoped InGaAs, for example. The i-type or p-type hetero barrier relaxation layer 35 is made of, for example, two layers of undoped or Zn-doped InGaAsP, and the band gap wavelengths of the two layers are, for example, 1.3 μm and 1.1 μm. The p-type cladding layer 36 is made of, for example, Zn-doped InP. The p-type hetero barrier relaxation layer 37 is made of, for example, two layers of Zn-doped InGaAsP, and the band gap wavelengths of the two layers are, for example, 1.1 μm and 1.3 μm. The p-type contact layer 38 is made of, for example, Zn-doped InGaAs.

  As shown in FIG. 2A, a part of the n-type buffer layer 22, an n-type hetero barrier relaxation layer 33, a light absorption layer 34, an i-type or p-type hetero barrier relaxation layer 35, a p-type cladding layer 36, The p-type hetero barrier relaxation layer 37 and the p-type contact layer 38 are included in the mesa structure 25 extending in a predetermined optical waveguide direction. One end of the light absorption layer 34 and the hetero barrier relaxation layer 35 in the optical waveguide direction is optically coupled to the optical waveguide core layer 23 by contacting the optical waveguide core layer 23 of the optical waveguide portion 5 described above. . In addition, the pair of side surfaces 25d and 25e of the mesa structure 25 in the light receiving element portion 6 are buried with a semiconductor buried region 41 made of a semi-insulating material such as Fe-doped InP.

  The light receiving element portion 6 further includes an insulating film 26. The insulating film 26 is common to the optical waveguide portion 5 described above, and is provided from the upper surface 25f of the mesa structure 25 to the semiconductor buried region 41, and covers and protects them. Further, the insulating film 26 has an opening on the upper surface 25f of the mesa structure 25 in the light receiving element portion 6, and a p-type ohmic electrode is formed on the p-type contact layer 38 exposed from the insulating film 26 through the opening. 39 is provided. The p-type ohmic electrode 39 is made of, for example, an alloy of AuZn or Pt and the contact layer 38. A metal wiring layer 7 a is provided on the p-type ohmic electrode 39. As shown in FIG. 2 (c), the metal wiring layer 7a extends in the optical waveguide direction, exceeds the end face 25g of the mesa structure 25 in this direction, and the p-type ohmic electrode 39 and the signal output electrode pad 8a. And electrically connect. The metal wiring layer 7a has a laminated structure such as TiW / Au or Ti / Pt / Au, and the signal output electrode pad 8a is formed by Au plating, for example.

  Further, as shown in FIG. 2A, the insulating film 26 has another opening also on the n-type buffer layer 22 away from the mesa structure 25 of the light receiving element portion 6. An n-type ohmic electrode 43 is provided on the n-type buffer layer 22 exposed from the insulating film 26 through the opening. The n-type ohmic electrode 43 is made of, for example, an alloy of AuGe or AuGeNi and the n-type buffer layer 22. A metal wiring layer 7 b is provided on the n-type ohmic electrode 43. The metal wiring layer 7b electrically connects the n-type ohmic electrode 43 and the bias voltage side electrode pad 8b. The metal wiring layer 7b has a laminated structure such as TiW / Au or Ti / Pt / Au, and the bias electrode side electrode pad 8b is formed by Au plating, for example.

  As shown in FIG. 2C, the mesa structure 25 further includes a semiconductor portion 9 having the same layer structure as that of the optical waveguide portion 5 described above on the region 21 d of the InP substrate 21. That is, the semiconductor portion 9 has a buffer layer 22, an optical waveguide core layer 23, and a cladding layer 24. Further, the end face 25 g of the mesa structure 25 described above is constituted by the semiconductor portion 9. Both side surfaces and the end surface 25g of the mesa structure 25 on the region 21d are embedded by a semiconductor embedded region 41 common to the light receiving element portion 6. That is, the semiconductor buried region 41 covers the end face 25g of the mesa structure 25 and the side surface of the mesa structure 25 extending from the region 21c to the region 21d. The insulating film 26 is common to the light receiving element portion 6, is provided from the upper surface of the semiconductor portion 9 to the semiconductor buried region 41, and covers and protects them.

  Here, FIG. 3 is a cross-sectional view showing in detail the configuration of the semiconductor portion 9 and its periphery, and is a cross-section along the line III-III in FIG. 2C (the mesa structure 25 along the main surface 21a). Cross section). FIG. 3 also shows the [110] direction and (110) plane of the InP substrate 21. As shown in FIG. 3, the end face 25g of the mesa structure 25 is inclined with respect to the (110) plane of the InP substrate 21 when viewed from the normal direction of the main surface 21a. In other words, the angle θ formed by the end face 25g of the mesa structure 25 and the [110] direction of the InP substrate 21 in the plane along the main surface 21a satisfies 0 ° <θ <90 °.

  A method for manufacturing the optical waveguide semiconductor device 2 having the above configuration will be described below.

<Semiconductor laminated part formation process>
FIG. 4 is a perspective view showing a semiconductor laminated portion forming step. In this step, first, an InP substrate 21 having regions 21b to 21d arranged in a predetermined optical waveguide direction (arrow A in the drawing) on the main surface 21a is prepared. Next, as shown in FIG. 4, a first semiconductor laminated portion 60 having a layer structure for the light receiving element portion 6 is grown on the region 21 c of the InP substrate 21, and the optical waveguide portion 5 A second semiconductor stacked portion 70 having a layer structure is grown on the region 21b and the region 21d of the InP substrate 21.

  Specifically, first, a semiconductor layer 58 for the n-type buffer layer 22, a semiconductor layer 61 for the light absorption layer 34, a semiconductor layer 62 for the hetero barrier relaxation layer 35, and a p-type cladding layer 36. A semiconductor layer 63, a semiconductor layer 64 for the p-type hetero barrier relaxation layer 37, and a semiconductor layer 65 for the p-type contact layer 38 are grown on the entire surface of the InP substrate 21. Then, an etching mask that covers a portion of the semiconductor layers 61 to 65 on the region 21c is formed on the semiconductor layer 65, and the semiconductor layers 61 to 65 are etched using the etching mask. Thereafter, a semiconductor layer 71 for the optical waveguide core layer 23 and a semiconductor layer 72 for the cladding layer 24 are selectively grown in regions on the substrate 21 that are not covered with the etching mask (ie, regions 21b and 21d). Let Through the above steps, the first semiconductor laminated portion 60 including the semiconductor layers 58 and 61 to 65 for the light receiving element portion 6 and the second semiconductor including the semiconductor layers 58, 71 and 72 for the optical waveguide portion 5. The stacked portion 70 is suitably formed.

<Etching process>
5 and 6 are perspective views showing the etching process. In this step, first, as shown in FIG. 5, an etching mask M1 extending in the optical waveguide direction (arrow A in the drawing) is formed on the first and second semiconductor stacked portions 60 and 70 from above the region 21b. It is formed over the region 21d. The etching mask M1 is made of a silicon compound (SiN, SiON, or SiO ₂ ), and the planar shape thereof matches the planar shape of the mesa structure 25 (see FIG. 2). That is, a part of the etching mask M <b> 1 covers a region to be the optical waveguide portion 5 and the semiconductor portion 9 in the semiconductor stacked portion 70. Further, the other part of the etching mask M <b> 1 covers a region to be the light receiving element part 6 in the semiconductor stacked part 60. The etching mask M1 has a linear edge M1a on the region 21d, and the edge M1a is relative to the (110) plane of the InP substrate 21 when viewed from the normal direction of the main surface 21a. Inclined. In other words, the angle θ formed by the edge M1a and the [110] direction of the InP substrate 21 (that is, the optical waveguide direction A) satisfies 0 ° <θ <90 °.

  Thereafter, as shown in FIG. 6, dry etching is performed on the semiconductor stacked portions 60 and 70 using the etching mask M <b> 1. This etching may be stopped in the middle of the semiconductor layer 58. By this etching, the mesa structure 25 having the end face 25g is formed on the region 21d, and the n-type buffer layer 22, the light absorption layer 34, the hetero barrier relaxation layer 35, the p-type cladding layer 36, p of the light receiving element portion 6 are formed. A type hetero barrier relaxation layer 37 and a p type contact layer 38 are formed. Further, the n-type buffer layer 22, the optical waveguide core layer 23, and the cladding layer 24 of the optical waveguide portion 5 and the semiconductor portion 9 are formed by this etching. Further, as a result of the etching mask M1 having the edge M1a inclined with respect to the [110] direction of the InP substrate 21, the angle formed between the end face 25g of the mesa structure 25 in the optical waveguide direction and the [110] direction of the InP substrate 21 θ satisfies 0 ° <θ <90 °.

<Built-in layer formation process>
7 and 8 are cross-sectional views showing a buried layer forming step. Each of FIGS. 7 and 8 (a) to (d) represents a cross section corresponding to each of FIGS. 2 (a) to 2 (d) in this step. In this step, a semiconductor buried region 41 is grown that covers the end face 25g of the mesa structure 25 and the side surface of the mesa structure 25 extending from the region 21c to the region 21d.

Specifically, first, as shown in FIGS. 7B and 7C, a mask M2 that covers the upper surface and both side surfaces of the optical waveguide portion 5 is formed. At this time, as shown in FIG. 7A, a mask M3 is formed on a partial region of the exposed surface of the n-type buffer layer 22. The masks M2 and M3 are made of a silicon compound (SiN, SiON, or SiO ₂ ). As a result of forming the masks M2 and M3, the light receiving element portion 6 and the semiconductor portion 9 are exposed from the mask M2, and further, a region of the n-type buffer layer 22 excluding the portion covered with the mask M3 is exposed. Then, wet etching for removing damage is performed on the surfaces of these exposed portions.

  Subsequently, as shown in FIGS. 8A to 8D, a semiconductor buried region 41 made of semi-insulating InP such as Fe-doped InP is grown on the portions exposed from the masks M2 and M3. Let In this step, the semiconductor buried region 41 is grown so as to bury both side surfaces of the light receiving element portion 6 and the semiconductor portion 9 in the mesa structure 25 and the end face 25g of the mesa structure 25. Further, the semiconductor buried region 41 grows so as to bury the exposed surface of the n-type buffer layer 22. In order to improve the flatness of the surface of the semiconductor buried region 41, it is desirable to add methyl chloride when the semiconductor buried region 41 is grown.

  Here, FIG. 9A is a plan view showing the vicinity of the end face 25g of the mesa structure 25 after the semiconductor buried region 41 is grown. FIG. 9B is a cross-sectional view taken along the line IXb-IXb shown in FIG. FIG. 9A shows the [110] direction and the (110) plane of the InP substrate 21, and FIG. 9B shows the (111) A plane of the semiconductor buried region 41.

  As described above, in the present embodiment, the angle θ between the end surface 25g of the mesa structure 25 and the [110] direction of the InP substrate 21 in the plane along the main surface 21a is larger than 0 ° and larger than 90 °. small. Therefore, as shown in FIG. 17, the end face 25g of the mesa structure 25 and the (111) A face of the semiconductor buried region are compared with the case where the end face of the mesa structure is perpendicular to the [110] direction. The relative position and angle relationship changes. Accordingly, it is possible to effectively suppress the phenomenon that the semiconductor buried region grows so as to cover the upper surface of the mesa structure as shown in FIG.

  FIG. 10 shows the relationship between the angle θ formed by the end face 25g and the [110] direction and the growth height h of the semiconductor buried region 41 with reference to the upper surface of the mesa structure 25 (see FIG. 9B). It is a graph to show. 11A to 11C schematically show the cross-sectional shape of the semiconductor buried region 41 when the angle θ is 0 °, 45 °, and 90 °, respectively.

In this graph, as a trial, a cylindrical mesa structure is fabricated on a (100) plane InP substrate, and the periphery of the mesa structure is filled with methyl chloride-added Fe-doped InP, and then the crystal orientation and mesa structure of the InP substrate are shown. It was obtained by investigating the relationship with the growth height of Fe-doped InP on the upper surface. The relationship shown in FIG. 10 is obtained by the following approximate expression (1), where d1 is a growth thickness of the semiconductor buried region 41 on the main surface 21a (see FIG. 9B).
h≈n · d1 · [sin {2 (θ−45 °)} + 1] (1)
(Where n is a constant between 2 and 3)

  As shown in FIGS. 10 and 11, when θ = 90 ° (that is, when the end face 25g is perpendicular to the [110] direction, in other words, parallel to the [1-10] direction) ), The growth height h is the highest, and the growth height h is the lowest when θ = 0 ° (that is, when the end face 25g is parallel to the [110] direction). Then, as θ approaches 90 ° from 90 °, the growth height h gradually decreases.

Further, considering that the metal wiring layer 7a is drawn beyond the semiconductor buried region 41 in a later step, the growth height h of the semiconductor buried region 41 is equal to the thickness d2 of the etching mask M1 (FIG. 9B). Smaller than that). That is, the growth height h is expressed by the following relational expression (2)
h = n · d1 · [sin {2 (θ−45 °)} + 1] ≦ d2 (2)
It is desirable to satisfy. Rewriting the above relational expression (2), the angle θ is θ ≦ (1/2) · [arcsin {d2 / (n · d1) −1}] + 45 ° (3)
It is desirable to satisfy.

<Mask removal process>
FIG. 12 is a cross-sectional view showing the mask removing process. Each of FIG. 12A to FIG. 12D represents a cross section corresponding to each of FIG. 2A to FIG. 2D in this step. After the semiconductor buried region 41 is grown in the above-described buried layer forming step, the masks M1 to M3 are removed. By this step, the upper surface and both side surfaces of the optical waveguide portion 5 and the upper surfaces of the light receiving element portion 6 and the semiconductor portion 9 are exposed, and a part of the n-type buffer layer 22 covered with the mask M3 is exposed.

<Element isolation process>
FIG. 13 is a cross-sectional view showing the element isolation step. Each of FIGS. 13A to 13D represents a cross-section corresponding to FIGS. 2A to 2D in this step. In this step, in order to electrically isolate the mesa structure 25 from other regions on the substrate 21, the semiconductor buried region 41 and the buffer layer 22 around the mesa structure 25 are etched to expose the substrate 21.

<Insulating film and ohmic electrode formation process>
FIG. 14 is a cross-sectional view showing a process of forming an insulating film and an ohmic electrode. Each of FIG. 14A to FIG. 14D represents a cross section corresponding to each of FIG. 2A to FIG. 2D in this step. In this step, the insulating film 26 is formed on the entire surface of the substrate 21. Thereby, the upper surface and both side surfaces of the optical waveguide portion 5 and the upper surfaces of the light receiving element portion 6 and the semiconductor portion 9 are covered with the insulating film 26. Thereafter, an opening is formed in the insulating film 26 on the n-type buffer layer 22 exposed from the semiconductor buried region 41 to expose the n-type buffer layer 22, and the opening is formed in the insulating film 26 on the light receiving element portion 6 And the p-type contact layer 38 is exposed.

  Thereafter, an n-type ohmic electrode 43 is formed on the n-type buffer layer 22 exposed from the insulating film 26. A p-type ohmic electrode 39 is formed on the p-type contact layer 38 exposed from the insulating film 26.

<Wiring layer formation process>
FIG. 15 is a cross-sectional view showing the wiring layer forming step. Each of FIG. 15A to FIG. 15D represents a cross section corresponding to each of FIG. 2A to FIG. 2D in this step. In this step, a metal wiring layer 7 a is formed from the p-type ohmic electrode 39 to the outside of the mesa structure 25 through the end face 25 g of the mesa structure 25. At the same time, a metal wiring layer 7 b extending from the n-type ohmic electrode 43 to the side of the mesa structure 25 is formed. Thereafter, a signal output electrode pad 8a is formed on the metal wiring layer 7a, and a bias voltage side electrode pad 8b is formed on the metal wiring layer 7b.

  Through the above steps, the optical waveguide type semiconductor device 2 shown in FIGS. 1 and 2 is completed.

  The effects obtained by the optical waveguide semiconductor device 2 and the manufacturing method thereof according to this embodiment will be described. In the optical waveguide semiconductor device 2 and the manufacturing method thereof described above, the angle θ between the end face 25g of the mesa structure 25 and the [110] direction of the InP substrate 21 in the plane along the main surface 21a of the InP substrate 21 is 0 ° <θ <90 ° is satisfied. By inclining the end face 25g in this way, as shown in FIGS. 10 and 11, the growth height h of the semiconductor buried region 41 is suppressed to be small, and the semiconductor buried region 41 is formed on the upper surface of the mesa structure 25. It is possible to suppress the phenomenon of growing so as to cover it. Accordingly, disconnection of the metal wiring layer 7a disposed from the upper surface of the mesa structure 25 to the outside of the mesa structure 25 through the end surface 25g can be reduced.

  In the present embodiment, it is more preferable to form the mesa structure 25 so that the angle θ satisfies the relational expression (3) described above. Thereby, since the height of the protruding portion of the semiconductor buried region 41 is lower than the height of the surface of the etching mask M1, disconnection of the metal wiring layer 7a can be more effectively reduced.

  Further, as in this embodiment, in order to planarize the semiconductor buried region 41, methyl chloride may be added when the semiconductor buried region 41 is grown. Methyl chloride has a function of promoting the growth of the semiconductor buried region 41 that covers the upper surface of the mesa structure 25 (that is, the growth of the (111) A plane of InP in the normal direction). According to the optical waveguide semiconductor device 2 and the manufacturing method thereof of the present embodiment, even in such a case, the growth height h of the semiconductor buried region 41 is sufficiently suppressed, and the disconnection of the metal wiring layer 7a is prevented. Can be reduced.

(Second Embodiment)
FIG. 16 is a plan view showing a configuration of a multi-channel optical waveguide light receiving device (hereinafter simply referred to as a light receiving device) including an optical waveguide semiconductor element as a second embodiment of the present invention.

  As shown in FIG. 16, the light receiving device 1 </ b> B of this embodiment includes an optical waveguide semiconductor element 10 and signal amplification units 50 </ b> A and 50 </ b> B. The optical waveguide semiconductor element 10 has a planar shape such as a substantially rectangular shape, and is formed by forming optical waveguide portions 15a to 15f on an InP substrate. The optical waveguide type semiconductor device 10 has two input ports 11 a and 11 b and an optical branching unit (optical coupler) 12. The optical waveguide semiconductor device 10 further includes first to fourth light receiving element portions 13a to 13d formed on the InP substrate and first to fourth capacitors 14a to 14d.

  The two input ports 11 a and 11 b are provided on one end edge 10 a of the optical waveguide semiconductor element 10. One input port 11a receives an optical signal La including four signal components modulated by the QPSK method from the outside of the light receiving device 1B. Further, the local oscillation light Lb is input to the other input port 11b. Each of the input ports 11a and 11b is optically coupled to the optical branching section 12 through the optical waveguide sections 15a and 15b. The optical waveguide portions 15a and 15b have the same configuration as the optical waveguide portion 5 of the first embodiment.

  The optical branching unit 12 constitutes a 90 ° optical hybrid. That is, the optical branching unit 12 is configured by an MMI coupler, and causes the optical signal La and the local oscillation light Lb to interfere with each other, whereby the optical signal La is converted into four signal components Lc1 to Lc1 modulated by the QPSK system. Branches to each Lc4. Of these four signal components Lc1 to Lc4, the signal components Lc1 and Lc2 have the same polarization state and have an in-phase relationship. The polarization states of the signal components Lc3 and Lc4 are equal to each other and different from the polarization states of the signal components Lc1 and Lc2. The signal components Lc3 and Lc4 have a quadrature relationship.

  Each of the light receiving element portions 13a to 13d is optically coupled to the four output ends of the light branching portion 12 via the optical waveguide portions 15c to 15f. The optical waveguide portions 15c to 15f have the same configuration as the optical waveguide portion 5 of the first embodiment, and the light receiving element portions 13a to 13d have the same configuration as the light receiving element portion 6 of the first embodiment. doing. That is, the optical waveguide type semiconductor device 10 has four mesa structures having the same configuration as the mesa structure 25 of the first embodiment. These mesa structures include optical waveguide portions 15c to 15f and light receiving element portions 13a to 13d, respectively, and further include a semiconductor portion corresponding to the semiconductor portion 9 of the first embodiment. The longitudinal direction (optical waveguide direction) of these mesa structures is along the [110] direction of the InP substrate, and the end faces in the longitudinal direction of these mesa structures are in-plane along the main surface of the InP substrate. In FIG. 1, the angle is inclined by an angle θ (0 ° <θ <90 °) with respect to the [110] direction of the InP substrate. Further, both side surfaces of the light receiving element portions 13a to 13d and the end surface in the longitudinal direction of the mesa structure are buried with a semiconductor buried region having the same configuration as the semiconductor buried region 41 of the first embodiment.

  The light receiving element portions 13 a to 13 d are arranged in this order along the edge 10 b of the optical waveguide semiconductor element 10. A constant bias voltage is supplied to the cathodes of the light receiving element portions 13a to 13d. Each of the light receiving element portions 13a to 13d receives the four signal components Lc1 to Lc4 from the optical branching portion 12, and generates an electric signal (photocurrent) corresponding to the light intensity of each of the signal components Lc1 to Lc4. On the optical waveguide semiconductor element 10, signal output electrode pads 16a to 16d electrically connected to anodes of the light receiving element portions 13a to 13d are provided. Similarly to the signal output electrode pad 8a of the first embodiment, the signal output electrode pads 16a to 16d are metal wiring layers (first electrodes) disposed on the end face of the ridge structure including the light receiving element portions 13a to 13d. (Corresponding to the metal wiring layer 7a of the embodiment) and electrically connected to the anodes of the light receiving element portions 13a to 13d. The signal output electrode pads 16a to 16d are electrically connected to signal input electrode pads 51a to 51d of signal amplifiers 50A and 50B, which will be described later, via bonding wires 20a to 20d, respectively.

  The capacitors 14a to 14d are preferably, for example, MIM (Metal Insulation Metal) capacitors having two metal layers stacked on the optical waveguide semiconductor element 10 and an insulating layer sandwiched between the two metal layers. Configured. Each of the capacitors 14a to 14d is electrically connected between the cathode of each of the light receiving element portions 13a to 13d to which a bias voltage is supplied and a reference potential line (GND line). That is, one of the two metal layers is connected to the cathodes of the light receiving element portions 13a to 13d, and the other metal layer is connected to the reference potential line (GND line).

  Each of the capacitors 14a to 14d has a bias voltage side electrode pad 17a to 17d connected to the one metal layer and a reference potential side electrode pad 18a to 18d connected to the other metal layer. Yes. One end of each of the bonding wires 20i to 20m is connected to each of the bias voltage side electrode pads 17a to 17d. The other end of each of the bonding wires 20i to 20m is electrically connected to a bias voltage source (not shown).

  One end of each of the bonding wires 20e to 20h is connected to each of the reference potential side electrode pads 18a to 18d. The bonding wires 20e to 20h are provided along the bonding wires 20a to 20d, and the other ends of the bonding wires 20e to 20h are the reference potential electrode pads 52a, 52c, 52d, and 52f of the signal amplification units 50A and 50B. Connected to each.

  The signal amplification units 50A and 50B are amplifiers (preamplifiers) that amplify the electric signals (photocurrents) output from the light receiving element units 13a to 13d. The signal amplifier 50A has two signal input electrode pads 51a and 51b, and generates a single voltage signal by performing differential amplification of the electric signals input to the signal input electrode pads 51a and 51b. . The signal amplifying unit 50B includes two signal input electrode pads 51c and 51d, and performs differential amplification of the electric signal input to the signal input electrode pads 51c and 51d to generate one voltage signal. Generate. As described above, each of the signal input electrode pads 51a to 51d is electrically connected to each of the signal output electrode pads 16a to 16d via the bonding wires 20a to 20d.

  The signal amplification unit 50A further includes three reference potential electrode pads 52a to 52c. The signal input electrode pad 51a is disposed between the reference potential electrode pads 52a and 52b, and the signal input electrode pad 51b is disposed between the reference potential electrode pads 52b and 52c. Similarly, the signal amplifying unit 50B further includes three reference potential electrode pads 52d to 52f. The signal input electrode pad 51c is disposed between the reference potential electrode pads 52d and 52e, and the signal input electrode pad 51d is disposed between the reference potential electrode pads 52e and 52f. As described above, the reference potential electrode pads 52a, 52c, 52d, and 52f of the signal amplifiers 50A and 50B are electrically connected to the reference potential side electrode pads 18a to 18d via the bonding wires 20e to 20h, respectively. Has been.

  The effects obtained by the light receiving device 1B of the present embodiment described above will be described. The light receiving device 1 </ b> B described above includes the optical waveguide semiconductor element 10. In the optical waveguide semiconductor device 10, as in the optical waveguide semiconductor device 2 of the first embodiment, the angle θ formed by the end face of the mesa structure and the [110] direction of the InP substrate satisfies 0 ° <θ <90 °. Satisfies. Thereby, the growth height of the semiconductor buried region can be suppressed to be small, and the phenomenon that the semiconductor buried region grows so as to cover the upper surface of the mesa structure can be suppressed. Therefore, disconnection of the metal wiring layer disposed on the signal output electrode pads 16a to 16d from the upper surface of the mesa structure to the end surface can be reduced.

  The optical waveguide semiconductor element 10 includes a plurality of light receiving element portions 13a to 13d and optical waveguide portions 15c to 15f optically connected to the plurality of light receiving element portions, respectively. 13 a to 13 d are arranged along the edge 10 b of the optical waveguide semiconductor element 10 in a direction perpendicular to the optical waveguide direction. Thereby, the signal output electrode pads 16 a to 16 d of the plurality of light receiving element portions 13 a to 13 d can be arranged along the edge 10 b of the optical waveguide type semiconductor element 10. By adopting such an arrangement, the signal input electrode pads 51a to 51d of the signal amplifiers 50A and 50B are also optical waveguide type with respect to the signal output electrode pads 16a to 16d of the plurality of light receiving element portions 13a to 13d. The semiconductor element 10 can be disposed along the edge 10b. Bonding wires 20 a to 20 d that electrically connect each of the signal output electrode pads 16 a to 16 d and each of the signal input electrode pads 51 a to 51 d extend along the edge 10 b of the optical waveguide semiconductor element 10. Thus, they can be arranged in the direction perpendicular to the direction of the optical waveguide and at substantially the same length and at a short distance. As a result, it is possible to avoid deterioration of frequency response characteristics due to a large lead inductance component and variations in frequency response characteristics between signals. Such an effect is more remarkable when the optical waveguide semiconductor element 10 includes a plurality of light receiving element portions optically connected to the plurality of optical waveguide portions.

  Further, when the optical waveguide semiconductor device 10 includes the MIM capacitors 14a to 14d as in the present embodiment, the MIM capacitors 14a to 14d are formed by the same process as the element isolation process (see FIG. 13) of the first embodiment. It may be formed on the surface of the exposed InP substrate. Then, in order to make the breakdown voltage distribution of the MIM capacitors 14a to 14d close to uniform within the surface of the InP wafer, it is desirable that the surface of the InP substrate on which the MIM capacitors 14a to 14d are formed has high flatness. However, when the InP substrate is exposed in the element isolation step, irregularities on the surface of the semiconductor buried region are transferred to the surface of the InP substrate, and the flatness of the surface of the InP substrate may be impaired. In particular, when dichloroethylene is added when growing a semiconductor buried region, a large number of hillocks are generated on the growth surface of the semiconductor buried region, and these hillocks are transferred to the surface of the InP substrate in the element isolation process. Therefore, the flatness of the surface of the InP substrate is greatly impaired.

  Such a problem can be solved by using methyl chloride as an additive when the semiconductor buried region is grown. This is because methyl chloride has a function of suppressing the generation of hillocks on the growth surface of the semiconductor buried region and flattening the growth surface. However, when methyl chloride is added to the semiconductor buried region, the growth rate in the normal direction of the (111) A plane becomes faster. Therefore, in the conventional optical waveguide semiconductor device, the semiconductor buried region on the upper surface of the mesa structure is increased. There arises a problem that the covering (see FIG. 19) becomes large.

  With respect to this problem, in the optical waveguide semiconductor device of this embodiment, as described above, the angle θ formed by the end face of the mesa structure and the [110] direction of the InP substrate satisfies 0 ° <θ <90 °. Therefore, it is possible to effectively suppress the semiconductor buried region from being covered on the upper surface of the mesa structure. Further, the addition of methyl chloride can improve the flatness of the surface of the semiconductor buried region, and the breakdown voltage distribution of the MIM capacitors 14a to 14d can be made closer to uniform.

  The method for manufacturing an optical waveguide semiconductor device and the optical waveguide semiconductor device according to the present invention are not limited to the above-described embodiments, and various other modifications are possible. For example, in each of the above embodiments, the light receiving element portion is exemplified as the optical semiconductor element portion, but the optical semiconductor element portion in the present invention includes a semiconductor structure that performs light incidence or emission with the optical waveguide portion, As long as it has an electrode on the semiconductor structure, it is not limited to the light receiving element portion.

  In each of the above embodiments, InGaAsP is exemplified as the composition of the optical waveguide core layer and the light absorption layer. However, the composition of the optical waveguide core layer and the light absorption layer is not limited to the InGaAsP system, and other examples such as an AlGaInAs system are available. The composition may also be

  In each of the above embodiments, the buffer layer on the InP substrate is n-type, and the cladding layer on the optical waveguide core layer and the light absorption layer is p-type. However, the conductivity type of each semiconductor layer is the opposite. Also good.

  In addition to the optical waveguide portion and the optical semiconductor element portion, an InP-based electronic device (for example, a heterojunction bipolar transistor), a capacitor, and a resistor are further provided on the InP substrate of each of the above embodiments, and these are photoelectric conversion circuits. May be configured.

DESCRIPTION OF SYMBOLS 1A, 1B ... Light receiving device, 2 ... Optical waveguide type semiconductor element, 3 ... Signal amplification part, 4 ... Capacitor, 5 ... Optical waveguide part, 6 ... Light receiving element part, 7a, 7b ... Metal wiring layer, 8a ... For signal output Electrode pad, 8b ... Bias voltage side electrode pad, 9 ... Semiconductor portion, 10 ... Optical waveguide semiconductor element, 21 ... InP substrate, 21a ... Main surface, 21b ... First region, 21c ... Second region, 21d ... 3rd area | region, 22 ... n-type buffer layer, 23 ... Optical waveguide core layer, 24 ... Cladding layer, 25 ... Mesa structure, 25g ... End face, 26 ... Insulating film, 27a-27c ... Bonding wire, 33 ... N-type hetero Barrier relaxation layer, 34 ... light absorption layer, 35 ... hetero barrier relaxation layer, 36 ... p-type cladding layer, 37 ... p-type hetero barrier relaxation layer, 38 ... p-type contact layer, 39 ... p-type ohmic electrode, 41 ... semiconductor Buried region, 3 ... n-type ohmic electrode, A ... optical waveguide direction, B ... projecting portion, M1 ... mask.

Claims (5)

A method of manufacturing an optical waveguide semiconductor device having an optical waveguide portion including a core layer for confining light and an optical semiconductor element portion coupled to the optical waveguide portion on a common InP substrate,
On the main surface of the InP substrate, a layer structure for the optical semiconductor element portion is formed on the second region of the first, second and third regions arranged in order in the optical waveguide direction of the optical waveguide portion. Forming a first semiconductor multilayer portion, and forming a second semiconductor multilayer portion having a layer structure for the optical waveguide portion on the first and third regions; and
An etching mask extending in the optical waveguide direction is formed on the first and second semiconductor stacked portions from the first region to the third region, and the first and second semiconductor masks are formed using the etching mask. An etching step of forming a mesa structure including an end surface on the third region, including the layer structure of the optical semiconductor element portion and the layer structure of the optical waveguide portion, by etching the second semiconductor stacked portion;
A buried layer forming step of growing a semiconductor buried region covering the end face of the mesa structure and a side surface of the mesa structure extending from the second region to the third region;
A wiring layer forming step of forming a metal wiring layer from the optical semiconductor element portion of the mesa structure to the outside of the mesa structure through the end face;
The optical waveguide direction is along the [110] direction of the InP substrate, and the angle θ formed by the end face in the plane along the main surface and the [110] direction of the InP substrate during the etching process. The mesa structure is formed so as to satisfy 0 ° <θ <90 °. A method for manufacturing an optical waveguide semiconductor device, comprising: The angle θ is θ ≦ (1/2) · [arcsin {d2 / (n · d1) −1}] + 45 °.
(Where d1 is the growth thickness of the semiconductor buried region on the main surface, d2 is the thickness of the etching mask, and n is a constant not less than 2 and not more than 3). The method for manufacturing an optical waveguide type semiconductor device according to claim 1, wherein the method is characterized in that:   3. The method for manufacturing an optical waveguide semiconductor device according to claim 1, wherein the semiconductor buried region is grown while adding methyl chloride. An InP substrate having a main surface including first, second and third regions arranged in order in a predetermined optical waveguide direction;
A layer structure for an optical waveguide portion including a core layer for confining light is included on the first and third regions, and a layer structure for an optical semiconductor element portion coupled to the optical waveguide portion is the second structure. A mesa structure included on a region, provided on the main surface with the optical waveguide direction as a longitudinal direction, and having an end surface on the third region;
A semiconductor buried region covering the end surface of the mesa structure and a side surface of the mesa structure extending from the second region to the third region;
A metal wiring layer extending from the optical semiconductor element portion of the mesa structure to the outside of the mesa structure through the end face;
The optical waveguide direction is along the [110] direction of the InP substrate, and the angle θ formed by the end surface in the plane along the main surface and the [110] direction of the InP substrate is 0 ° <θ <90. An optical waveguide type semiconductor device characterized by satisfying the angle. A plurality of mesa structures including a layer structure for the optical waveguide portion and a layer structure for the optical semiconductor element portion are formed on the InP substrate,
The plurality of mesa structures are arranged side by side in a direction perpendicular to the optical waveguide direction,
5. The optical waveguide semiconductor device according to claim 4, wherein the metal wiring layer is provided extending in the optical waveguide direction.

Images