JP2014060579A - Image processing apparatus and image processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent logical operation different from the original intent from being carried out, while allowing high speed processing, when performing RMW.SOLUTION: A generation unit generates drawing information including the information indicating at least a drawing pattern, a drawing address showing an address on the memory of drawing pattern, and a logical operation being applied to the drawing pattern. When the information indicating a logical operation included in the drawing information generated in the generation unit indicates a logical operation on the memory using read modify write, a determination is made whether or not a drawing address included in the drawing information matches a drawing address included in the drawing information that is held in at least one of a plurality of holding parts for holding the drawing information. When a determination is made that they match each other, read processing by read modify write is stopped temporally for a memory based on the drawing information generated in the generation unit.

Description

  The present invention relates to an image processing apparatus and an image processing method suitable for use when performing memory access using read-modify-write.

  Conventionally, in page printers and the like, there has been a demand for higher printing resolution and higher printing speed, but the CPU (Central Processing Unit) that controls the operation of the printer alone can meet these requirements. It has become difficult to meet.

  Here, the flow of processing in the printer according to the prior art will be schematically described. For example, PDL (Page Description Language) data created by a personal computer or the like is transferred to a printer via a predetermined interface such as a network or a cable. The printer analyzes the transferred PDL data and creates an intermediate language that can be executed by the drawing unit of the printer. The drawing unit analyzes the created intermediate language to generate image data, and performs gradation processing on the generated image data to obtain binary image data. The binarized image data is drawn on the band memory and written to the band memory. Image drawing is performed for each color of C, M, Y, and K.

  The printer encodes the image data of each color drawn in the band memory by a binary image compression algorithm such as JBIG (Joint Bi-level Image Coding Expert Group), and writes the generated codes to the memory. When printing, the printer reads the code from the memory with a delay for each of the C, M, Y, and K plates, decodes the code, and transfers the decoded data to the printer engine corresponding to each of the C, M, Y, and K plates. To print.

  With respect to memory access control in such a printer apparatus, Patent Document 1 discloses a technique in which an image processing unit performs drawing processing (logical operation processing) by sharing a memory with a CPU via a memory arbiter that performs memory access arbitration. Has been. Since the read processing of the memory via this memory arbiter competes with the processing of other components connected to the memory arbiter such as a CPU (Central Processing Unit), generally, after a read request is issued It may take a relatively long time for the data read in response to the read request to arrive.

  On the other hand, in recent years, LSI (Large Scale Integration) with a built-in CPU and system bus has been developed. In recent years, the AXI (Advanced eXtensible Interface) bus has attracted attention as a standard protocol for buses in SOC (System-on-a-chip).

  In the configuration using the AXI bus in the SOC, arbitration among the CPU, the image processing unit, and the band memory can be performed more efficiently than in the case where the memory arbiter is used. Therefore, the data reading side can issue read requests issued as commands one after another without waiting for the arrival of read data according to the read request, and can efficiently process access to the band memory.

  By the way, in the configuration using the AXI bus described above, memory access can be performed efficiently, but in the case of read-modify-write (hereinafter abbreviated as RMW) for the same address on the band memory, incorrect drawing / logic Arithmetic processing may be performed.

  An incorrect logical operation process in the RMW will be schematically described with reference to FIG. FIG. 20A shows an example of correct access, that is, originally intended access and logical operation processing. In this example, RMW of the horizontally long rectangular image 200 shown in the left diagram of FIG. 20A is performed, and the vertically long image 201 intersecting the image 200 shown in the right diagram of FIG. Perform RMW. At this time, in the originally intended logical operation processing, a predetermined operation is performed between the image 200 and the image 201 at the intersection between the image 200 and the image 201, and the changed image is drawn at the intersection.

  FIG. 20B shows an example in which an incorrect access, that is, an unintended access and logical operation processing are performed. In this example, as described above, the RMW of the horizontally long image 200 shown in the left diagram of FIG. 20B is performed, and the RMW of the vertically long image 201 intersecting with the image 200 is performed. The intersection with the image 201 has been overwritten with the image 201. This is different from the result of the originally intended logical operation processing described with reference to FIG.

  As described above, the reason why the logical operation result is different from the originally intended one is that the data reading side (the drawing processing unit side) reads one after another without waiting for the arrival of data corresponding to the read request. Occurs to issue a request. That is, the logical operation processing of the intersection between the image 200 and the image 201 needs to be executed after the RMW of the intersection in the image 200 is completed.

  However, since a memory controller that controls memory access handles RMW as access information that is divided into read information and write information, it is difficult to guarantee read and write data in the RMW. Therefore, when the read request is issued one after another without waiting for the arrival of the read data, the read is performed on the address where the write by RMW has not been completed, and the read is performed on the address where the write has been completed and the modification is performed. There is a possibility that the written data will be written. The phenomenon described with reference to FIG. 20B occurs for this reason.

  The present invention has been made in view of the above, and in performing RMW, it is possible to perform high-speed processing and to prevent a logical operation different from the original intention from being performed. Objective.

  In order to solve the above-described problems and achieve the object, the present invention provides drawing information including at least a drawing pattern, a drawing address indicating an address of the drawing pattern in a memory, and information indicating a logical operation performed on the drawing pattern. A generation unit that generates the drawing information, a plurality of holding units that hold the drawing information, and information indicating the logical operation included in the drawing information generated by the generation unit indicates a logical operation using the read-modify-write on the memory. In this case, the determination unit that determines whether or not the drawing address included in the drawing information matches the drawing address included in the drawing information held in at least one of the plurality of holding units is matched by the determination unit. Control to temporarily stop the read processing by read-modify-write to the memory based on the drawing information generated by the generation unit when it is determined that Characterized in that it has and.

  According to the present invention, when RMW is performed, it is possible to perform high-speed processing, and it is possible to prevent a logical operation different from the original intention from being performed.

FIG. 1 is a block diagram illustrating a configuration of an example of an image forming apparatus according to an embodiment. FIG. 2 is a diagram illustrating a format of an example of a band storage area in the main memory applicable to the embodiment. FIG. 3 is a diagram schematically illustrating an example of an intermediate language processed by the drawing unit, which can be applied to the embodiment. FIG. 4 is a diagram illustrating an example of a command in an intermediate language that can be applied to the embodiment. FIG. 5 is a diagram illustrating examples of logical operation types applicable to the embodiment. FIG. 6 is a block diagram illustrating a configuration of an example of a drawing unit according to the embodiment. FIG. 7 is a block diagram illustrating a configuration of an example of a drawing pattern generation unit according to the embodiment. FIG. 8 is a block diagram illustrating a configuration example of the logical operation processing unit according to the embodiment. FIG. 9 is a flowchart illustrating processing of an example of a controller according to the embodiment. FIG. 10 is a flowchart illustrating an example of processing in the RMW of the read control unit according to the embodiment. FIG. 11 is a flowchart illustrating an example of a write address check process according to the embodiment. FIG. 12 is a flowchart illustrating an example of a read address check process according to the embodiment. FIG. 13 is a diagram for explaining the effect of the processing according to the embodiment. FIG. 14 is a diagram for explaining the effect of the processing according to the embodiment. FIG. 15A is a diagram for explaining an example when the embodiment is not applied. FIG. 15-2 is a diagram for explaining an example when the embodiment is not applied. FIG. 15C is a diagram for explaining an example when the embodiment is not applied. FIG. 16 is a diagram for explaining another example when the embodiment is not applied. FIG. 17A is a diagram for explaining another example when the embodiment is not applied. FIG. 17-2 is a diagram for explaining another example when the embodiment is not applied. FIG. 17C is a diagram for explaining another example when the embodiment is not applied. FIG. 18 is a diagram for explaining yet another example to which the embodiment is not applied. FIG. 19 is a diagram for explaining yet another example to which the embodiment is not applied. FIG. 20 is a diagram for schematically explaining an incorrect logical operation process in the RMW according to the conventional technique.

  Embodiments of an image processing apparatus and an image processing method will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram illustrating an exemplary configuration of an image forming apparatus 1 according to the embodiment. In the image forming apparatus 1, a CPU (Central Processing Unit) 10 is connected via a CPU I / F 11 to a bus 13 (hereinafter referred to as an AXI bus 13) according to an AXI (Advanced eXtensible Interface) bus. A ROM (Read Only Memory) 22 and a panel controller 23 are connected via the local I / F 21.

  The AXI bus 13 is connected to the main memory 14 via the memory controller 25. At the same time, the drawing unit 15, the encoding unit 16, the decoding unit 17, and the communication controller 20 are connected to the AXI bus 13. The output of the decoding unit 17 is connected to an engine controller 18 that controls the printer engine 19.

  The AXI bus 13 controls data transfer between the connected units. The CPU I / F 11 is an interface between the CPU 10 and the AXI bus 13, and the CPU 10 is connected to each part of the image forming apparatus 1 via the CPU I / F 11 and the AXI bus 13. The panel controller 23 is connected to a panel 24 provided with an operator and a display unit for performing user operations.

  The ROM 22 stores font information such as various programs and characters in advance. The CPU 10 controls the operation of the image forming apparatus 1 using a RAM (Random Access Memory) (not shown) as a work memory according to a program stored in advance in the ROM 22. The CPU 10 can also use the main memory 14 as a work memory. Further, the CPU 10 issues a command for controlling the printer engine 19 to the engine controller 18. The communication controller 20 controls communication with an external device such as a personal computer (PC) connected via a network.

  Control of access to the main memory 14 via the AXI bus 13 is performed by the memory controller 25. The main memory 14 includes, for example, a program area, a PDL data area, a CMYK band image data area, a CMYK page code data area, and other areas.

  The program area stores a program for the CPU 10 to operate. In the PDL data area, for example, PDL (Page Description Language) data transferred from a personal computer via the communication controller 20 is stored. An intermediate language generated by the CPU 10 based on the PDL data may be stored in this PDL data area. In the CMYK band image data area, band image data based on C, M, Y, and K color plates generated based on the PDL data is stored. The CMYK band code data area stores encoded band image data (referred to as band code data) of each version of CMYK. The other area is an area for storing data other than those described above, and can be used as a work memory when the CPU 10 executes a program, for example.

  The drawing unit 15 reads and analyzes the intermediate language generated by the CPU 10 based on the PDL data, and performs a drawing process of writing a band image in the band storage area of the main memory 14 according to the analysis result. In addition, the drawing unit 15 includes a logical operation processing unit 30. When a logical operation instruction is included in the analysis result of the intermediate language, the drawing unit 15 performs a logical operation on the band image according to the logical operation instruction.

  The band image drawn by the drawing unit 15 is read from the main memory 14 and subjected to encoding and decoding processing by the encoding unit 16 and the decoding unit 17 via the AXI bus 13. Supplied. The engine controller 18 controls the printer engine 19 according to the supplied band image, whereby an image is formed on the print medium and printing is performed.

  In such a configuration, for example, PDL data generated by a personal computer is received by the communication controller 20 via the network and stored in the PDL data area of the main memory 14. The CPU 10 reads and analyzes the PDL data from the PDL data area of the main memory 14, generates an intermediate language based on the analysis result, and stores it in the main memory 14. The drawing unit 15 performs drawing processing according to the intermediate language read from the main memory 14, and generates image data for each version of CMYK. The generated image data of each CMYK plate is written in the CMYK band image data area of the main memory 14.

  The encoding unit 16 compresses the CMYK band image data read from the CMYK band image data area of the main memory 14 using MTF (Move To Front) control, Huffman encoding, and the like. Thus, compression encoding processing is performed. Code data obtained by compression-coding band image data is stored in the CMYK page code data area of the main memory 14. The decoding unit 17 decodes the CMYK version code data read from the CMYK page code data area of the main memory 14, outputs the CMYK version image data, and sends the image data to the engine controller 18. The engine controller 18 controls the printer engine 19 based on the CMYK image data received from the decoding unit 17 to perform printout.

  FIG. 2 shows an exemplary format of a band storage area in the main memory 14. In the example of FIG. 2, the bandwidth is, for example, the width of one page, that is, the length of one horizontal line drawn by horizontal scanning (main scanning), and the band height is divided into one page in the vertical scanning direction. It is assumed that the height of the region 1 is. The drawing word width indicates a unit for accessing the band storage area in the drawing unit 15.

  FIG. 2 shows an example of writing (writing) a horizontal line from the start point of the horizontal line X to the end point of the horizontal line X with respect to the horizontal line Y as an example of writing image data to the band storage area. As described above, the drawing unit 15 performs drawing by writing the image data subjected to the image processing to the band storage area for each horizontal line. It is assumed that the direction along the horizontal line is the X direction, the direction perpendicular to the horizontal line, that is, the sub-scanning direction is the Y direction, and for example, the print area in one page is represented by X and Y coordinates.

  FIG. 3 schematically shows an example of an intermediate language processed by the drawing unit 15. In the example of FIG. 3, the intermediate language sequentially describes a band initialization command, a logical operation type setting command, a rectangle drawing command, a triangle drawing command, a logic operation type setting command, a rectangle drawing command, a rectangle drawing command, and a band end command. Has been. Actually, there are intermediate languages for C, M, Y, and K colors.

  FIG. 4 shows an example of the command in the above intermediate language. In the example of FIG. 4, each command has a data width of 32 bits. The first 32 bits are used as a command header, followed by each parameter of the command. Each command can be specified for each color of C, M, Y, and K. The NOP immediately after the command header is for adjusting the data width of the command header to the 32-bit width, and hereinafter, this NOP is included and referred to as a command header.

  FIG. 4A shows an example of a band initialization command. In the band initialization command, following the command header, setting parameters for the head address of the band, the band height, and the bandwidth are designated. When receiving the command, the drawing command analysis unit 41 to be described later with reference to FIG. 7 stores the band head address, the band height, and the width in the parameter storage unit 40 of FIG.

  FIG. 4B shows an example of a rectangle drawing command for instructing drawing of a rectangle. Following the command header, the drawing parameters of the X and Y coordinates of the upper left corner and the X and Y coordinates of the lower right corner of the rectangle are designated, respectively. Upon receiving this command, the drawing command analysis unit 41, which will be described later with reference to FIG. 7, receives the X and Y coordinates of the upper left corner of the rectangle, the X and Y coordinates of the lower right corner, and the rectangular command name with the horizontal line conversion unit 42 to be described later with reference to FIG. And draw processing.

  FIG. 4C shows an example of a triangle drawing command for instructing triangle drawing. Each drawing parameter of the X and Y coordinates of the three end points # 0, # 1, and # 2 of the triangle is designated. Upon receiving this command, the drawing command analysis unit 41, which will be described later with reference to FIG. 7, transfers the coordinates of the end points of the triangle and the triangle command name to the horizontal line conversion unit 42, which will be described later with reference to FIG. 7, and performs drawing processing.

  FIG. 4D shows an example of a logical operation type setting command that defines a logical operation type. Following the command head, the logical operation type is specified. FIG. 5 shows examples of logical operation types. In the example of FIG. 5, 16 types of logical operations respectively defined by logical operation types “ROP_00” to “ROP_FF” are defined. In the logical operation, “0x0000 — 0000” indicates black painting, and “0xFFFF_FFFF” indicates white painting. Symbols “S” and “D” indicate images (drawing patterns) to be calculated, and a logical operation is defined for one or two images.

  In FIG. 5, a memory access type used in each logical operation is associated with each logical operation type. Memory access “WRITE” indicates a logical operation using only writing. Memory access “RMW” indicates a logical operation using read-modify-write. The read modify write is a process of reading (reading) data from a certain area on the memory, changing (modifying) the data, and writing (writing) the changed data in the original area.

  Hereinafter, the read modify write is abbreviated as RMW. Further, hereinafter, the logical operation is described as “ROP” as appropriate.

  FIG. 4E shows an example of a band end command for instructing the end of drawing of the defined band. This band end command has only a command header. When receiving the command, the drawing command analysis unit 41 described later with reference to FIG. 7 ends the processing of the band.

  FIG. 6 shows an exemplary configuration of the drawing unit 15. The drawing unit 15 includes a logical operation processing unit 30, a drawing pattern generation unit 31, an AXI bus input unit 32, and an AXI bus output unit 33. The AXI bus input unit 32 and the AXI bus output unit 33 are an input interface and an output interface with the AXI bus 13 shown in FIG. 1, respectively.

  The drawing pattern generation unit 31 reads the drawing command described with reference to FIG. 4 from the intermediate language storage memory area of the main memory 14, analyzes the drawing command, and generates a drawing pattern for drawing in the band memory area of the main memory 14. It generates and transfers drawing information including a drawing pattern, a drawing unit for each word to be drawn, a mask pattern, and an address to the logical operation processing unit 30.

  The logical operation processing unit 30 is a part that characterizes the embodiment, and receives drawing information including a drawing pattern, a mask pattern, an address, and a logical operation type from the drawing pattern generation unit 31. The logical operation processing unit 30 performs a logical operation or the like according to the drawing information received from the drawing pattern generation unit 31, communicates with the memory controller 25 via the AXI bus input unit 32 and the AXI bus output unit 33, and outputs the operation result as the main. Drawing in the band memory area of the memory 14.

  FIG. 7 shows an exemplary configuration of the drawing pattern generation unit 31. The drawing pattern generation unit 31 includes a drawing command analysis unit 41, a horizontal line conversion unit 42, and a horizontal line drawing unit 43. The drawing command analysis unit 41 reads the drawing command from the AXI bus input unit 32, analyzes the drawing command, transfers the parameter value to the parameter storage unit 40 if it is a parameter setting command, and if it is a drawing command, The drawing command is transferred to the horizontal line converter 42.

  The horizontal line conversion unit 42 receives a drawing command from the drawing command analysis unit 41, converts it into a horizontal line, and transfers it to the horizontal line drawing unit 43. The horizontal line drawing unit 43 generates a drawing unit, a mask pattern, an address, and the like for drawing a horizontal line based on the horizontal line data from the horizontal line conversion unit 42, and transfers the drawing pattern to the logical operation processing unit 30.

  FIG. 8 shows an exemplary configuration of the logical operation processing unit 30. The drawing pattern generation unit I / F 50 is an interface with the drawing pattern generation unit 31 in FIG. 6 and receives a drawing unit, a logical operation type, a mask pattern, an address, and the like for drawing. The RMW determination unit 51 has, for example, the logical operation type information of FIG. 5 as a table, and determines whether the received logical operation type performs a logical operation using RMW or performs a logical operation using only write (W). to decide.

  The RMW drawing address registers 52A and 52B each store a drawing address at the time of RMW. In this example, the RMW drawing address registers 52A and 52B have two registers in order to throw off two leads first, and these RMW drawing address registers 52A and 52B are switched by the MUX (multiplexer) 60, and the read control unit 67 and the write are performed. The data is transferred to the control unit 68.

  The RMW drawing length storage registers 53A and 53B are registers for storing drawing lengths during RMW, respectively. In this example, in order to throw two leads ahead, the RMW drawing length registers 53A and 53B have two registers, and these RMW drawing length registers 53A and 53B are switched by the MUX 61 to the read control unit 67 and the write control unit 68. Forwarding.

  The RMW_ROPTYPE registers 54A and 54B are registers for storing logical operation types during RMW. In this example, two registers, RMW_ROPTYPE registers 54A and 54B, are provided in order to presend two leads, and are transferred to the RMW_ROPT processing unit 64 that performs a logical operation for RMW by switching with the MUX 62.

  The RMW light drawing pattern buffers 55A and 55B each store a drawing pattern (light drawing pattern) at the time of RMW. In this example, two RMW write drawing pattern buffers 55A and 55B are provided in order to throw two leads ahead, and the data is transferred to the RMW_ROPT processing unit 64 which performs a logical operation for RMW by switching with the MUX 63.

  As described above, the RMW process according to the embodiment has two pieces of drawing information (drawing address, drawing length, logical operation type, and drawing pattern), because the first throw process is required at the time of reading. Hereinafter, one of these two pieces of drawing information will be referred to as a lead A and the other as a lead B as appropriate. The reason for having two (a plurality of) values of the leads A and B is that they are required at different timings of the read processing and the write processing of the RMW processing. This is because when the read data returns according to B, the write processing is sequentially performed in the order of read A and read B.

  The RMW_ROPT processing unit 64 performs a logical operation for RMW. The RMW_ROPT processing unit 64 reads the lead drawing pattern from the lead drawing pattern buffer 65 and also reads the logical operation type and the write drawing pattern from the MUXs 62 and 63. Then, the RMW_ROPT processing unit 64 performs the logical operation indicated by the logical operation type on the read lead drawing pattern and write drawing pattern, and writes the drawing pattern of the calculation result in the RMW write buffer 66.

  The lead drawing pattern buffer 65 stores the band memory data read from the read control unit 67 as a lead drawing pattern. The RMW write buffer 66 stores the drawing pattern logically processed by the RMW_ROPT processing unit 64.

  The read control unit 67 reads read data from the AXI bus input unit 32. The write control 68 writes the write data to the AXI bus output unit 33.

  The write drawing address register 56 stores a drawing address at the time of writing, and transfers the stored drawing address at the time of writing to the write address check unit 69. The write length register 57 is a register for storing the drawing length at the time of writing, and transfers the stored drawing length at the time of writing to the write address check unit 69. The write ROPTYPE register 58 is a register for storing a logical operation type at the time of writing, and transfers the stored logical operation type at the time of writing to the write ROPT processing unit 70. The light drawing pattern buffer 59 is a register for storing a drawing pattern at the time of writing, and transfers the stored drawing pattern at the time of writing to the write ROPT processing unit 70.

  As described above, according to the embodiment, the write process does not perform the first throw process, and thus does not have a plurality of drawing information.

  The write ROPT processing unit 70 performs a write logical operation indicated by the logical operation type. The drawing pattern resulting from the logical operation is written into the write buffer 71 for writing.

  The write address check unit 69 checks the presence / absence of a read / write address collision from the RMW address / length and the write address / length. If there is no conflict, the write address check unit 69 requests the write control unit 68 to write. If there is a collision, the controller 73 is notified accordingly. The read address check unit 72 checks the presence / absence of an address collision based on the address and length of the lead A and the lead B, and notifies the controller 73 if there is a collision. The controller 73 controls logical operation processing described later based on the check results of the write address check unit 69 and the read address check unit 72.

  FIG. 9 is a flowchart illustrating an example of processing of the controller 73. In step S100, the controller 73 determines whether data enable from the drawing pattern generation unit 31 is active. If it is determined that it is inactive, the process of step S100 is performed again. If it is determined to be active, the process proceeds to step S101, and the controller 73 determines whether or not the logical operation indicated by the logical operation type is a logical operation using only writing (write).

  If it is determined in step S101 that the logical operation uses only a write, the process proceeds to step S102 and instructs the write address check unit 69 to perform a write address check. Details of the write address check process will be described later. In the next step S103, the controller 73 determines whether or not the write address matches the read address based on the result of the write address check. If it is determined that they match, the process returns to step S102 to instruct the write address check unit 69 to perform the write address check again. As a result, the write process is temporarily stopped.

  On the other hand, if it is determined in step S103 that the write address does not match the read address, the controller 73 shifts the processing to step S104, and uses the drawing address, drawing length, and drawing pattern received from the drawing pattern generation unit 31. The data is transferred to the write ROPT processing unit 70. The write ROPT processing unit 70 performs a logical operation according to the logical operation type based on the transferred drawing address, drawing length, and drawing pattern. The logical operation result is transferred to the write control unit 68 via the write buffer 71 for writing. The controller 73 requests the write control unit 68 to perform a write process. Thereafter, the process returns to step S100.

  When it is determined in step S101 described above that the logical operation uses RMW, the process proceeds to step S105, and it is determined whether or not the lead A is free. Specifically, it is determined whether or not the RMW drawing address register 52A, the RMW length register 53A, the RMW_ROPTYPE register 54A, and the RMW write drawing pattern buffer 55A are empty.

  If it is determined that it is free, the process proceeds to step S106, and the drawing address, drawing length, and drawing pattern received from the drawing pattern generation unit 31 are set to the read A side (RMW drawing address register 52A, RMW length register 53A). And the RMW write drawing pattern buffer 55A), and requests the read control unit 67 to perform read processing. Thereafter, the process returns to step S100.

  If it is determined in step S105 that the lead B is not available, the process proceeds to step S107, and it is determined whether the lead B is available. Specifically, it is determined whether the RMW drawing address register 52B, the RMW length register 53B, the RMW_ROPTYPE register 54B, and the RMW write drawing pattern buffer 55B are empty. If it is determined that it is not available, the process returns to step S105.

  If it is determined that it is free, the process proceeds to step S108 to instruct the read address check unit 72 to perform a read address check. Details of the read address check process will be described later. In the next step S109, the controller 73 determines whether or not the read address matches the read address of the read A based on the result of the read address check. If it is determined that they match, the process returns to step S108 to instruct the read address check unit 72 to perform the read address check again. As a result, the read processing by the RMW is temporarily stopped.

  If it is determined in step S109 that the read addresses do not match, the process proceeds to step S110, and the drawing address, drawing length, and drawing pattern received from the drawing pattern generation unit 31 are set to the read B side (RMW drawing address register 52B, The data is transferred to the RMW length register 53B and the RMW write drawing pattern buffer 55B), and a read process is requested to the read control unit 67. Thereafter, the process returns to step S100.

  FIG. 10 is a flowchart showing an example of processing in the RMW of the read control unit 67. In step S120, the read control unit 67 determines whether the read enable is active. If it is determined that it is inactive, the process of step S120 is performed again. If it is determined that it is active, the process proceeds to step S121, and it is determined whether or not the read flag (read FLAG) is zero.

  If it is determined that the read FLAG = 0, the process proceeds to step S122, and the read control unit 67 determines whether the write process is being performed. If it is determined that the write process is being performed, the process of step S122 is performed again.

  If it is determined in step S122 that the write process is not in progress, the read control unit 67 sets the value of the read FLAG to 1 in the next step S123, and shifts the process to step S124. In step S124, the RMW_ROPT processing unit 64 performs a logical operation on the read pattern received from the read drawing pattern buffer 65 and the drawing pattern received from the write drawing pattern buffer 55A according to the logical operation type received from the RMW_ROPTYPE register 54A. A write request for the drawing length stored in the RMW length register 53A is made to the write control unit 68 with respect to the drawing address stored in the RMW drawing address register 52A of the drawing pattern resulting from the logical operation.

  If it is determined in step S121 that read FLAG = 1 (not read FLAG = 0), the process proceeds to step S125, and the read control unit 67 determines whether write processing is in progress. . If it is determined that the write process is being performed, the process of step S125 is performed again.

  If it is determined in step S125 that the write process is not in progress, the read control unit 67 sets the value of the read FLAG to 0 in the next step S126, and shifts the process to step S127. In step S127, the RMW_ROPT processing unit 64 performs a logical operation on the read pattern received from the read drawing pattern buffer 65 and the drawing pattern received from the write drawing pattern buffer 55B according to the logical operation type received from the RMW_ROPTYPE register 54B. A write request for the drawing length stored in the RMW length register 53B is made to the write control unit 68 for the drawing address stored in the RMW drawing address register 52B of the drawing pattern resulting from the logical operation.

  FIG. 11 is a flowchart showing an example of the write address check process described in step S102 of FIG. In step S130, the write address check unit 64 obtains the end address of the read A from the drawing address and the drawing length of the read A stored in the RMW drawing address register 52A and the RMW length register 53A. Similarly, the write address check unit 64 obtains the end address of the read B from the drawing address and the drawing length of the read B stored in the RMW drawing address register 52B and the RMW length register 53B in step S131. Further, the write address check unit 64 obtains the end address of the write based on the write drawing address stored in the write drawing address register 56 and the write drawing length stored in the write length register 57 in step S132.

  In step S133 and step S134, the write address check unit 64 checks whether there is a read A start point or end address between the write start point address and the end address. Next, in step S135 and step S136, the write address check unit 64 checks whether there is a write start point or end address between the start point address and the end address of the read A. This checks for the presence or absence of an address collision between read A and write.

  In the next step S137 and step S138, it is checked whether or not there is a read B start point or end address between the write start point address and the end address. Next, in step S139 and step S140, the write address check unit 64 checks whether there is a write start point or end address between the start point address and the end address of the read B. As a result, the presence or absence of an address collision between the read B and the write is checked.

  As a result of the above determination, when it is determined that the write address does not collide with the read address (when all the determination results in the determinations in steps S133 to S140 are “No”), the process proceeds to step S141. It is assumed that the write address and the read address do not match. On the other hand, when it is determined that the write address and the read address collide (when at least one of the determination results obtained in the determinations in steps S133 to S140 is “Yes”), the process proceeds to step S142 and the write is performed. It is assumed that the address matches the read address.

  FIG. 12 is a flowchart showing an example of the read address check process described in step S108 of FIG. In step S150, the read address check unit 72 obtains the end address of the lead A from the drawing address and the drawing length of the lead A stored in the RMW drawing address register 52A and the RMW length register 53A. Similarly, the read address check unit 72 obtains the end address of the read B from the drawing address and the drawing length of the lead B stored in the RMW drawing address register 52B and the RMW length register 53B in step S151.

  In step S152 and step S153, the read address check unit 72 checks the presence or absence of the start point or the end address of the lead B between the start point and the end address of the lead A. In step S154 and step S155, the read address check unit 72 checks the presence or absence of the start point or the end address of the lead A between the start point and the end address of the lead B. Thereby, the presence or absence of an address collision between the lead A and the lead B is checked.

  As a result of the above determination, when it is determined that the addresses do not collide between lead A and lead B (when all the determination results in the determinations in steps S152 to S155 are “No”), the process proceeds to step S156. Thus, it is assumed that the address of the lead A and the address of the lead B do not match. On the other hand, when it is determined that the addresses of the lead A and the lead B collide (when at least one of the determination results of the determinations in steps S152 to S155 is “Yes”), the process proceeds to step S157. The address of the lead A and the address of the lead B are assumed to match.

  The effect of the processing according to the embodiment will be described with reference to FIGS. 13 and 14. FIG. 13 shows an example of processing in the order of memory access. A plurality of pieces of drawing information for performing logical operations using RMW are stored, and by checking whether or not there is a collision between the read address and the write address by RMW, the write processing of data # 0 to # 3 by the write address #A and the read address The read processing of data # 4 to # 7 by #B can be executed in parallel.

  As described above, in the embodiment, a plurality of pieces of drawing information for performing a logical operation using the RMW are stored, and at the time of the write request, it is confirmed whether or not the drawing addresses match among the drawing information of the plurality of RMWs. If they do not match, RMW read processing and write processing are performed in parallel. As a result, the processing can be executed at high speed.

  FIG. 14 shows an example in which it is checked that there is no address collision in the RMW, and the write processing of data # 8 to # 11 by the write address #C is performed before the write processing by the write address #A. . In this case, the processing can be further speeded up with respect to the example of FIG.

  An example in which the present embodiment is not applied will be described with reference to FIGS. Consider a case where an image (drawing pattern) 300 and an image (drawing pattern) 301 intersect as shown in FIG. 15A, and a predetermined logical operation is performed at the intersection. Here, as shown in FIG. 15-1 (b), reference numerals of the areas a to e are given to the respective parts. In this case, the first RMW (referred to as RMW # 1) is performed in the order of the regions a, b, and c, and the next RMW (referred to as RMW # 2) is performed in the order of the regions d, b, and e. That is, in the area b, RMW # 2 should be read with respect to data that has been modified by RMW # 1 and written.

  When a read command can be issued one after another without waiting for a read response as in the AXI bus, the areas a, b, c, and d are sequentially read and then the area b, as illustrated in FIG. There is a possibility that the area b is read by RMW # 2 before the write by RMW # 1. In this case, since the originally intended processing procedure is not executed, a correct logical operation result cannot be obtained.

  In order to avoid this, as illustrated in FIG. 15C, after the reading of the areas a, b, c, and d is completed, the writing of these areas a, b, c, and d must be completed. Wait, and then start reading the areas b and e by RMW # 2. This method has a drawback in that while a correct logical operation result can be obtained, the processing is delayed by the amount of waiting time.

  Another example when this embodiment is not applied will be described with reference to FIGS. 16 and 17-1 to 17-3. In this other example, a logical operation is performed in units of memory words or less for a memory accessed in units of memory words. That is, as illustrated in FIG. 16A, the left memory word and the central memory word are read for the RMW in the areas 310 and 311 and the central memory word is modified and written. At this time, the areas 311 and 312 are modified and written. Thereafter, the right memory word is read, and the region 313 is modified and written.

  On the other hand, if a read command can be issued one after another without waiting for a read response, the central area is read for the RMW in areas 310 and 311 and then written in the RMW in areas 312 and 313 before being written. This can lead to a situation that leads. In this case, the modified region 311 cannot be obtained, and a correct logical operation result cannot be obtained as illustrated in FIG.

  Another example when the present embodiment is not applied will be described more specifically with reference to FIGS. As shown in FIG. 17A, symbols of the memory words p, q, and r are attached to the image of FIG. In this case, RMW # 1 is performed on memory words p and q, and RMW # 2 is performed on memory words q and r.

  When a read command can be issued one after another without waiting for a read response as in the AXI bus, the memory words p and q are read by RMW # 1 and then RMW # as illustrated in FIG. 17-2. 2 reads the memory words q and r. Then, a situation may occur in which the memory word q is read by RMW # 2 before writing by RMW # 1. In this case, since the originally intended processing procedure is not executed, a correct logical operation result cannot be obtained.

  In order to avoid this, as illustrated in FIG. 17C, RMW # 2 is started after RMW # 1 completely completes RMW of memory words p and q. With this method, a correct logical operation result can be obtained, but the processing is slowed down by the amount of waiting time.

  Still another example to which the present embodiment is not applied will be described with reference to FIGS. 18 and 19. FIG. 18 shows an example in which a correct logical operation by RMW is not performed. In this example, data by read address #A by the first RMW # 1 is data # 0 to # 3, data by read address #B by the next RMW # 2 is data # 4 to # 7, and RMW # 1 and RMW # 2 have overlapping data # 3. In this case, data # 3 needs to be read by RMW # 2 after being written by RMW # 1.

  However, in the example of FIG. 18, since the presence or absence of an address conflict is not checked, it is impossible to detect that an address conflict occurs in data # 3 that overlaps between RMW # 1 and RMW # 2. Therefore, data # 3 is first read as read data 100 by RMW # 1, and the data # 3 is read as read data 101 by RMW # 2 before being written by RMW # 1, and then the write data 102 is written. Therefore, the write data 102 does not reflect the write by RMW # 2, and a correct logical operation result cannot be obtained. In this case, the subsequent write data 103 by the same data # 3 is also incorrect.

  In order to avoid this, as illustrated in FIG. 19, an address collision is recognized at the read addresses #A and #B, and the write processing of the data # 0 to # 3 by the RMW # 1 of the read address #A is completed. After that, it is considered that data # 3 to # 7 are read by RMW # 1 of the read address #B. Even in this case, while a correct logical operation result can be obtained, the processing is delayed by the amount of waiting time.

  In the embodiment, as described with reference to FIGS. 13 and 14, a plurality of pieces of drawing information for performing logical operations using RMW are stored, and a drawing address is set between drawing information of a plurality of RMWs at the time of a write request. It is confirmed whether or not they match, and if they do not match, the RMW read processing and write processing are performed in parallel. As a result, the processing can be executed at high speed.

  As a method of avoiding address collision by RMW, information (address information, logical operation type, drawing mask, drawing pattern to be written, etc.) for accessing the memory is sequentially stored in a FIFO (First In, First Out) memory, A method may be considered in which the presence or absence of a write / read address collision is monitored in the FIFO memory, and if there is no collision, the memory access information is sequentially read from the FIFO to access the memory.

  However, in this method, in order to store memory access information in the FIFO memory in accordance with the memory, the FIFO memory becomes enormous and a large gate scale is required. Further, when the FIFO memory is full, it is necessary to wait until the FIFO memory becomes empty at that time, and it is difficult to increase the speed. Further, when accessing the memory, it is necessary to sequentially compare the addresses in the FIFO memory, which hinders the speeding up of processing.

  For example, if the burst length is 8 accesses with 16 bits, it is necessary to store 128 pieces of memory access information in the FIFO memory, and the FIFO memory requires a large or large capacity, and at least 128 for speeding up. One address comparison device is required, and the gate scale becomes large.

  In the embodiment, since the address collision check is performed by checking whether or not there is an address match based on the start address and length (drawing length) for each memory access unit, the gate scale is small and high-speed processing is possible. is there. Further, since the gate scale is small, more memory accesses can be handled.

  The above-described embodiment is a preferred embodiment of the present invention, but is not limited thereto, and various modifications can be made without departing from the gist of the present invention.

DESCRIPTION OF SYMBOLS 1 Image processing apparatus 13 AXI bus 14 Main memory 15 Drawing part 30 Logical operation part 31 Drawing pattern generation part 52A, 52B RMW drawing address register 53A, 53B RMW drawing length register 54A, 54B RMW_ROPTYPE register 55A, 55B RMW write drawing pattern buffer 56 Write drawing address register 57 Write length register 58 Write ROPTYPE register 59 Write drawing pattern buffer 64 RMW_ROPT processing unit 67 Read control unit 68 Write control unit 69 Write address check unit 70 Write ROPT processing unit 72 Read address check unit 73 Controller

JP 2004-230742 A

Claims (7)

A generating unit that generates drawing information including at least a drawing pattern, a drawing address indicating an address on the memory of the drawing pattern, and information indicating a logical operation performed on the drawing pattern;
A plurality of holding units for holding the drawing information;
When the information indicating the logical operation included in the drawing information generated by the generating unit indicates a logical operation using read-modify-write on the memory, the drawing address included in the drawing information, and the plurality of A determination unit that determines whether or not a drawing address included in drawing information held in at least one of the holding units matches;
A control unit that temporarily stops read processing by the read-modify-write on the memory based on the drawing information generated by the generation unit when the determination unit determines that they match. An image processing apparatus. The controller is
The image processing apparatus according to claim 1, wherein a read request to the memory based on the drawing information held in the plurality of holding units is sequentially executed regardless of presence or absence of a read response. The controller is
3. The image according to claim 1, wherein when the determination unit determines that they match, the read process and the write process by the read-modify-write to the memory are serially executed. Processing equipment. The controller is
The write processing with respect to the memory is preferentially executed when the information indicates a logical operation using only the write with respect to the memory and the determination unit determines that they do not match. The image processing apparatus according to any one of claims 1 to 3. An arithmetic unit that performs a logical operation on the drawing pattern according to the information indicating the logical operation;
The computing unit is
When the information indicating the logical operation included in the drawing information generated by the generation unit indicates the logical operation using the read-modify-write on the memory, the information is held in one of the plurality of holding units. Perform logical operations according to the drawing information,
When the information indicates a logical operation using only writing to the memory, the logical operation is executed according to the drawing information generated by the generation unit,
The controller is
The result of the logical operation by the arithmetic unit is written to the memory according to drawing information including the information indicating the logical operation. Image processing apparatus. When information indicating a logical operation included in the drawing information generated by the generation unit indicates a logical operation using a read-modify-write on the memory, a logical operation is performed on the drawing pattern according to the information. 1 calculation unit,
A second operation unit for performing a logical operation on a drawing pattern according to the information when the information indicates a logical operation using only writing to the memory;
The controller is
When it is determined by the determination unit that they do not match, the logical operation by the second operation unit is executed with priority over the logical operation by the first operation unit, and the result of the logical operation is The image processing apparatus according to claim 1, wherein a write process is performed on the memory in accordance with drawing information including the information indicating an operation. A generation step of generating drawing information including at least a drawing pattern, a drawing address indicating an address of the drawing pattern on a memory, and information indicating a logical operation performed on the drawing pattern;
A holding step for holding the drawing information in a plurality of holding units;
When the information indicating the logical operation included in the drawing information generated by the generating step indicates a logical operation using read-modify-write on the memory, the drawing address included in the drawing information, and the plurality of A determination step of determining whether or not a drawing address included in drawing information held in at least one of the holding units matches;
And a control step of temporarily stopping the read processing by the read-modify-write on the memory based on the drawing information generated by the generation step when it is determined by the determination step that they match. An image processing method.

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